JP6073825B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device using a group III-V compound semiconductor and a method for manufacturing the same.

  Nitride semiconductors such as gallium nitride (GaN) are semiconductors having a larger band gap than silicon (Si), and have a higher breakdown field strength than Si and are expected to be applied in the field of power electronics. It is. A useful application destination is a transistor using a channel layer made of GaN. For example, there is a high electron mobility transistor (HEMT) formed in the vicinity of the interface between GaN and AlGaN using a so-called two-dimensional electron gas (2DEG) having a high concentration and high mobility as a c-plane. This HEMT is used as a transistor having low on-resistance and high withstand voltage.

  However, the HEMT is a so-called normally-on transistor in which current flows when the gate voltage is turned off because electrons as carriers always exist at the AlGaN / GaN interface unless a gate electric field is applied. From the viewpoint of fail-safe, a normally-off type transistor in which a current flows only when the gate voltage is on is preferable, and a normally-off type transistor utilizing GaN is being developed.

  As a typical normally-off type GaN transistor, there is a recess structure in which a gate portion is dug by dry etching. In order to fabricate the recess structure, there are problems such as difficult processing due to the need for precise control of the dry etching depth and the need to suppress damage due to dry etching. There is a field effect transistor (MISFET) using a MIS (Metal-Insulator-Semiconductor) structure as a normally-off transistor that is relatively easy to manufacture.

In the MIS structure, an insulating layer made of SiO ₂ , Al ₂ O ₃ or the like is formed on the GaN surface serving as a channel between the source and drain by using, for example, a plasma assisted chemical vapor deposition (P-CVD) apparatus or the like. It is formed by forming a metal electrode. In the MISFET using GaN as a channel using such an insulating layer, the interface state existing at the interface between the insulating layer and GaN has a problem that the device characteristics are deteriorated. The same applies to MISFETs using other III-V group compounds such as GaAs and InP, as well as nitride semiconductors.

  For example, when carriers are trapped at the interface state, problems such as a change in threshold voltage, operational instability due to hysteresis, and a decrease in drain voltage occur. As the origin of the interface state, in addition to the film quality of the insulating layer, a natural oxide film in the exposed GaN surface state before forming the insulating layer can be cited. Non-Patent Document 1 reports that an interface state is formed by a natural oxide film formed on the GaN surface.

R. Nakasakia et al., "Insulator-GaN interface structures formed by plasma-assisted chemical vapor deposition", Physica E, vol.7, pp.953-957, 2000. Hiroaki Okakawa et al., “Development of GaN-based optical semiconductors”, Mitsubishi Cable Industrial Time Report, No. 96, pp. 59-63, 2000.

  As described above, conventionally, in the method of forming an insulating layer directly on the channel region like GaN-MISFET, the natural oxide film formed on the surface of the channel region becomes the origin of the interface state, and the transistor characteristics are deteriorated. There was a problem of bringing about.

  The present invention has been made to solve the above-described problems, and an object thereof is to suppress deterioration of transistor characteristics in a MISFET using a III-V group compound semiconductor.

  The method of manufacturing a semiconductor device according to the present invention includes an insulating layer forming step of forming an insulating layer on a first semiconductor layer made of a nitride semiconductor with a part of the surface of the first semiconductor layer exposed, and an insulating layer Forming a second semiconductor layer serving as a channel on the insulating layer by epitaxially growing a nitride semiconductor from a region where the surface of a part of the first semiconductor layer is exposed by selective lateral growth using a selective growth mask And a gate electrode forming step for forming a gate electrode disposed under the insulating layer, and a source / drain electrode forming step for forming a source electrode and a drain electrode on the second semiconductor layer.

  In the semiconductor device manufacturing method, the first semiconductor layer is formed of an n-type nitride semiconductor, the second semiconductor layer is formed of a p-type nitride semiconductor, and is formed in a region serving as a channel of the second semiconductor layer. , A source / drain region forming step of forming a source region and a drain region into which n-type impurities are introduced at a predetermined distance, and in the insulating layer forming step, a part of the insulating layer is removed and a part of the first In the channel formation process, the second semiconductor layer is formed so as to cover the insulating layer, the second semiconductor layer other than the channel region is removed, and in the source / drain electrode formation process, the surface of the semiconductor layer is exposed. Forming an ohmic electrode in each of the source region and the drain region to form a source electrode and a drain electrode, and in the gate electrode forming step, the ohmic electrode connected to the first semiconductor layer To form a line, the first semiconductor layer below the region to be a channel may be a gate electrode.

  In the semiconductor device manufacturing method, the first semiconductor layer is made of an insulating nitride semiconductor, and in the gate electrode formation step, an n-type impurity is added to a part of the first semiconductor layer in the region serving as a channel. Introducing the gate electrode, in the insulating layer forming step, a part of the insulating layer is removed to expose a part of the surface of the first semiconductor layer, and in the channel forming step, the insulating layer is covered. The second semiconductor layer is formed, the second semiconductor layer other than the channel region is removed, and the channel region of the second semiconductor layer is separated by a predetermined distance with the gate electrode formation region interposed therebetween. A source / drain region forming step for forming a source region and a drain region into which is introduced, and in the source / drain electrode forming step, an ohmic electrode is formed in each of the source region and the drain region. It may be a source electrode and a drain electrode.

  The method for manufacturing a semiconductor device includes a source / drain region forming step of forming a source region and a drain region into which an n-type impurity is introduced, spaced apart from each other by a predetermined distance in a region to be a channel of the second semiconductor layer, The two semiconductor layers are made of a p-type nitride semiconductor. In the insulating layer forming step, a part of the insulating layer is removed to expose a part of the first semiconductor layer surface. In the channel forming step, the insulating layer is insulated. The second semiconductor layer is formed so as to cover the layer, the second semiconductor layer other than the channel region is removed, and in the source / drain electrode formation step, an ohmic electrode is formed in each of the source region and the drain region. The source and drain electrodes are formed, and in the gate electrode formation step, the insulating layer is formed in the region between the source and drain regions in the channel region. A gate electrode made of a metal on the first semiconductor layer is formed prior to, the insulating layer forming step may be planarized surface irregularities of the insulating layer formed by the presence of the gate electrode.

  In the method for manufacturing a semiconductor device, the first semiconductor layer is made of an n-type nitride semiconductor, the second semiconductor layer is made of an undoped nitride semiconductor, and a part of the insulating layer is formed in the insulating layer forming step. In the channel forming step, the second semiconductor layer is formed so as to cover the insulating layer, and the second semiconductor layer is formed on the second semiconductor layer. Forming a third semiconductor layer composed of a nitride semiconductor for generating a two-dimensional electron gas, and then removing the second and third semiconductor layers other than the channel region, In the electrode forming step, an ohmic electrode is formed in each of the source region and the drain region of the third semiconductor layer in the channel region to form the source electrode and the drain electrode, and the gate electrode forming step Is an ohmic electrode wiring connected to the first semiconductor layer is formed, the first semiconductor layer below the region to be a channel may be a gate electrode.

  In the semiconductor device manufacturing method, the first semiconductor layer is made of an insulating nitride semiconductor, the second semiconductor layer is made of an undoped nitride semiconductor, and a channel region is formed in the gate electrode forming step. A gate electrode is formed by introducing an n-type impurity into a part of the first semiconductor layer, and a part of the first semiconductor layer surface is exposed in the insulating layer forming step by removing a part of the insulating layer. In the channel forming step, the second semiconductor layer is formed so as to cover the insulating layer, and a nitride semiconductor for generating a two-dimensional electron gas in the second semiconductor layer is formed on the second semiconductor layer. After forming the third semiconductor layer, the second semiconductor layer and the third semiconductor layer other than the channel region are removed, and in the source / drain electrode formation step, the third semiconductor in the channel region is formed. Over, it is sufficient to form a source electrode and a drain electrode to form an ohmic electrode on each of the source region and a drain region by a predetermined distance apart across the gate electrode formation region.

  In the semiconductor device manufacturing method, the second semiconductor layer is made of an undoped nitride semiconductor, and in the insulating layer forming step, a part of the insulating layer is removed and a part of the first semiconductor layer surface is exposed. In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and the second semiconductor layer is formed of a nitride semiconductor for generating a two-dimensional electron gas on the second semiconductor layer. Then, the second semiconductor layer and the third semiconductor layer other than the channel region are removed, and in the source / drain electrode formation step, the third semiconductor layer is formed on the third semiconductor layer in the channel region. In addition, an ohmic electrode is formed in each of the source region and the drain region separated by a predetermined distance to form the source electrode and the drain electrode, and the channel is formed in the gate electrode forming step. In the region sandwiched between the source region and the drain region in the region, a gate electrode made of metal is formed on the first semiconductor layer before forming the insulating layer. In the insulating layer forming step, the presence of the gate electrode What is necessary is just to planarize the unevenness | corrugation of the surface of the insulating layer formed.

  In the semiconductor device manufacturing method, the first semiconductor layer and the second semiconductor layer may be made of the same nitride semiconductor.

  In addition, a semiconductor device according to the present invention includes a first semiconductor layer made of a nitride semiconductor, an insulating layer formed on the first semiconductor layer in a state where a part of the surface of the first semiconductor layer is exposed, and an insulating layer A channel formed on the insulating layer, comprising a second semiconductor layer made of a nitride semiconductor epitaxially grown from a region in which a part of the surface of the first semiconductor layer is exposed by selective lateral growth using the layer as a selective growth mask; A gate electrode disposed under the insulating layer, and a source electrode and a drain electrode formed on the channel.

  In the semiconductor device, the first semiconductor layer is made of an n-type nitride semiconductor, and the second semiconductor layer is made of a p-type nitride semiconductor, and is formed in a channel and arranged at a predetermined distance apart. A source region and a drain region into which an n-type impurity is introduced, and an ohmic electrode wiring connected to the first semiconductor layer, the source electrode and the drain electrode being connected to each of the source region and the drain region The first semiconductor layer that is an electrode and under the channel may be a gate electrode.

  In the semiconductor device, the first semiconductor layer is made of an insulating nitride semiconductor, and the gate electrode is formed by introducing an n-type impurity into a part of the first semiconductor layer in the channel region. And a source region and a drain region which are formed in a channel and are spaced apart from each other by a predetermined distance and into which an n-type impurity is introduced. The source electrode and the drain electrode are connected to each of the source region and the drain region. Any electrode may be used.

  In the semiconductor device, the second semiconductor layer is made of a p-type nitride semiconductor, includes a source region and a drain region which are formed in a channel and are spaced apart from each other by a predetermined distance and into which an n-type impurity is introduced. The source electrode and the drain electrode are ohmic electrodes connected to each of the source region and the drain region, and the gate electrode is below the insulating layer in a region sandwiched between the source region and the drain region in the channel region. The surface of the insulating layer only needs to be planarized by the presence of the gate electrode. The metal pattern is formed on the first semiconductor layer.

  In the semiconductor device, the first semiconductor layer is composed of an n-type nitride semiconductor, the second semiconductor layer is composed of an undoped nitride semiconductor, and generates a two-dimensional electron gas in the channel on the channel. And a ohmic electrode wiring connected to the first semiconductor layer, wherein the source electrode and the drain electrode are a source region and a drain of the third semiconductor layer in the channel region, respectively. It is an ohmic electrode formed in each of the regions, and the first semiconductor layer under the channel may be a gate electrode.

  In the semiconductor device, the first semiconductor layer is made of an insulating nitride semiconductor, the second semiconductor layer is made of an undoped nitride semiconductor, and the gate electrode is a first part of a channel region. A third semiconductor layer is formed by introducing an n-type impurity into the semiconductor layer, and is formed on the channel and made of a nitride semiconductor for generating a two-dimensional electron gas in the channel. May be any ohmic electrode formed in each of the source region and the drain region of the third semiconductor layer in the channel region.

  In the semiconductor device, the second semiconductor layer is made of an undoped nitride semiconductor, and has a third semiconductor layer made of a nitride semiconductor for generating a two-dimensional electron gas in the channel on the channel. The source electrode and the drain electrode are ohmic electrodes formed in each of the source region and the drain region of the third semiconductor layer in the channel region, and the gate electrode is sandwiched between the source region and the drain region in the channel region. In this region, the pattern of the metal formed on the first semiconductor layer below the insulating layer is formed, and the surface of the insulating layer is flattened by the surface unevenness formed by the presence of the gate electrode. That's fine.

In the semiconductor device, the third semiconductor layer is made of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Just do it. The first semiconductor layer and the second semiconductor layer are made of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It only has to be done.

  As described above, according to the present invention, it is possible to obtain an excellent effect that deterioration of transistor characteristics in a MISFET using a III-V group compound semiconductor can be suppressed.

FIG. 1A is a cross-sectional view showing a state of a process in the middle of explaining the method for manufacturing a semiconductor device in the first embodiment of the present invention. 1B is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the method for manufacturing a semiconductor device in the first embodiment of the present invention. FIG. 1C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the first embodiment of the present invention. FIG. 1D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the method for manufacturing a semiconductor device in the first embodiment of the present invention. FIG. 1E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the first embodiment of the present invention. FIG. 1F is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the first embodiment of the present invention. FIG. 2 is a band diagram schematically showing the state of the energy band from the source region 104 to the drain region 105 in the channel portion of the semiconductor device in the first embodiment. FIG. 3A is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3B is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3F is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3G is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. FIG. 3H is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the second embodiment of the present invention. 4A is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining a method for manufacturing a semiconductor device in the third embodiment of the present invention. FIG. 4B is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4F is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4G is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 4H is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention. FIG. 5A is a cross-sectional view showing a state in the middle of the process for explaining the method of manufacturing a semiconductor device in the fourth embodiment of the present invention. FIG. 5B is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fourth embodiment of the present invention. FIG. 5C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fourth embodiment of the present invention. FIG. 5D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fourth embodiment of the present invention. FIG. 5E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fourth embodiment of the present invention. FIG. 6A is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining a manufacturing method of a semiconductor device in Embodiment 5 of the present invention. FIG. 6B is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention. FIG. 6C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention. FIG. 6D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention. FIG. 6E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention. FIG. 6F is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the method for manufacturing the semiconductor device in the fifth embodiment of the present invention. FIG. 6G is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention. FIG. 7A is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining a manufacturing method of a semiconductor device in Embodiment 6 of the present invention. FIG. 7B is a cross-sectional view (a) and a plan view (b) showing the state of a process in the middle of explaining the manufacturing method of the semiconductor device in the sixth embodiment of the present invention. FIG. 7C is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the sixth embodiment of the present invention. FIG. 7D is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in Embodiment 6 of the present invention. FIG. 7E is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the sixth embodiment of the present invention. FIG. 7F is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the sixth embodiment of the present invention. FIG. 7G is a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the sixth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIGS. 1A to 1F. 1A to 1F are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining a method for manufacturing a semiconductor device in the first embodiment of the present invention.

First, as shown in FIG. 1A, an insulating layer 102 is formed on a first semiconductor layer 101 made of a nitride semiconductor. The first semiconductor layer 101 may be made of, for example, GaN (n-type nitride semiconductor) into which an n-type impurity is introduced at a high concentration. For example, the first semiconductor layer 101 may be grown on a crystal substrate such as corundum (sapphire), silicon (Si), and GaN, or a SiC substrate. This layer becomes a buffer layer. For example, the insulating layer 102 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by a chemical vapor deposition (CVD) method using plasma assist.

  Next, a part of the insulating layer 102 is removed, and as shown in FIG. 1B, the surface of a part of the first semiconductor layer 101 is exposed to form an insulating layer 102a (insulating layer forming step). For example, the insulating layer 102 may be patterned by a known lithography technique and dry etching technique to form an opening region so that a part of the first semiconductor layer 101 is exposed to form the insulating layer 102a.

  Next, as shown in FIG. 1C, a nitride semiconductor is formed from a region where the surface of a part of the first semiconductor layer 101 is exposed by selective lateral growth (ELO) using the insulating layer 102a as a selective growth mask. Epitaxial growth is performed to form the second semiconductor layer 103 serving as a channel on the insulating layer 102a (channel forming step).

  For example, GaN (p-type nitride semiconductor) doped with p-type impurities is grown by ELO by metal organic chemical vapor deposition (MOCVD), and the second semiconductor layer 103 is formed so as to cover the insulating layer 102a. . Here, in the first embodiment, as will be described later, the first semiconductor layer 101 is used as a gate electrode. Therefore, it can be seen that the first semiconductor layer 101 / insulating layer 102a / second semiconductor layer 103 plays the same role as the MIS structure at the stage of forming the second semiconductor layer 103. FIG. 1C shows a joint 103a where GaN grown ELO from left to right on the paper surface and GaN grown ELO from right to left are joined on the surface of the insulating layer 102a.

Next, as shown in FIG. 1D, a source region 104 and a drain region 105 into which an n-type impurity has been introduced are formed in a region to be a channel of the second semiconductor layer 103 and separated by a predetermined distance (source / drain regions). Forming step). For example, the source region 104 and the drain region 105 to be n ⁺ regions may be formed by introducing an n-type impurity at a higher concentration by a well-known ion implantation method. Here, since there is a possibility that dislocation occurs in the junction 103a, the source region 104 and the drain region 105 are preferably formed so as to avoid the junction 103a.

  Next, as shown in FIG. 1E, the second semiconductor layer 103 other than the channel region is removed. For example, the second semiconductor layer 103 is patterned by a known lithography technique and dry etching technique. In particular, the second semiconductor layer 103 is patterned so that the second semiconductor layer 103 exists only on the insulating layer 102a so as to be separated from the first semiconductor layer 101 to be a gate electrode.

  Next, as shown in FIG. 1F, an ohmic electrode wiring 106 connected to the first semiconductor layer 101 is formed, and the first semiconductor layer 101 under the channel region is used as a gate electrode (gate electrode forming step). . Further, an ohmic electrode is formed in each of the source region 104 and the drain region 105 to form the source electrode 107 and the drain electrode 108.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. Thereafter, the ohmic electrode wiring 106, the source electrode 107, and the drain electrode 108 are formed by patterning so that the electrode metal material is left in the electrode formation region by removing (lifting off) the resist mask pattern. Good.

  In the first embodiment, as described above, the first semiconductor layer 101 is used as a gate electrode, and the gate electrode is disposed under the insulating layer 102a when viewed from the channel. Further, according to Embodiment 1, immediately before the second semiconductor layer 103 is grown, the insulating layer 102 is heat-treated as a nitrogen atmosphere inside the growth furnace in which the metal organic vapor phase epitaxy method is performed. The film quality of the layer 102 (insulating layer 102a) can also be improved.

  Further, as described in Non-Patent Document 2, since the upward propagation of threading dislocations existing in the first semiconductor layer 101 is blocked by the insulating layer 102a by using ELO, an insulating layer is formed from an inner region of the insulating layer 102a. Since the second semiconductor layer 103 grown laterally on 102a has fewer threading dislocations, a high-quality second semiconductor layer 103 can be obtained on the insulating layer 102a.

  Next, operation of the semiconductor device (transistor) in Embodiment 1 is described with reference to FIGS. FIG. 2 is a band diagram schematically showing the state of the energy band from the source region 104 to the drain region 105 in the channel portion of the semiconductor device in the first embodiment.

  The source region 104 and the drain region 105 are connected via a channel (p-GaN), and when the gate voltage is 0 V, as shown in FIG. Acts as a barrier to block current and no current flows. On the other hand, when a positive gate voltage is applied to the insulating layer 102a as a gate insulating layer and the first semiconductor layer 101 as a gate electrode, the channel potential is decreased and the barrier is lowered as shown in FIG. A current flows between the source and the drain through the channel. As described above, the semiconductor device in Embodiment 1 exhibits normally-off transistor characteristics.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIGS. 3A to 3H. 3A to 3H are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the method for manufacturing the semiconductor device in the second embodiment of the present invention.

  First, as shown in FIG. 3A, an n-type impurity is introduced into a predetermined location on the first semiconductor layer 201 made of a nitride semiconductor to form a gate electrode 206 (gate electrode forming step). The first semiconductor layer 201 may be made of, for example, semi-insulating GaN (an insulating nitride semiconductor). The second embodiment is characterized in that the gate electrode 206 is formed in the initial stage. The gate electrode 206 is formed in a strip shape extending in a predetermined direction, as shown in FIG. 3A (b). In the plane of the first semiconductor layer 201, the direction perpendicular to the predetermined direction is the gate length direction.

For example, the first semiconductor layer 201 may be grown on a crystal substrate such as sapphire, Si, and GaN, or a SiC substrate. This layer becomes a buffer layer. Also, a mask pattern having an opening in the gate electrode formation region is formed, and an n-type impurity is ion-implanted from above to form a gate electrode 206 that is an n ⁺ region.

Next, as illustrated in FIG. 3B, the insulating layer 202 is formed on the first semiconductor layer 201. For example, the insulating layer 202 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by plasma-assisted chemical vapor deposition (CVD).

  Next, a part of the insulating layer 202 is removed to form an insulating layer 202a where the surface of a part of the first semiconductor layer 201 is exposed as shown in FIG. 3C (insulating layer forming step). For example, the insulating layer 202 may be formed by patterning the insulating layer 202 by a known lithography technique and dry etching technique so as to expose a part of the first semiconductor layer 201 to form the insulating layer 202a.

  Next, as shown in FIG. 3D, by selective lateral growth ELO using the insulating layer 202a as a selective growth mask, a nitride semiconductor is epitaxially grown from a region where the surface of a part of the first semiconductor layer 201 is exposed, and the insulating layer 202a A second semiconductor layer 103 serving as a channel is formed on the substrate (channel forming step).

  For example, GaN (p-type nitride semiconductor) doped with p-type impurities is grown by ELO by MOCVD, and the second semiconductor layer 203 is formed so as to cover the insulating layer 202a. Here, in the second embodiment, as described above, a part of the first semiconductor layer 201 into which the n-type impurity is introduced becomes the gate electrode 206. Therefore, when the second semiconductor layer 203 is formed, the MIS structure is formed by the gate electrode 206 / the insulating layer 202a / the second semiconductor layer 203. FIG. 3D shows a joint 203a where GaN grown ELO from left to right on the paper surface and GaN grown ELO from right to left are joined on the surface of the insulating layer 202a.

Next, as shown in FIG. 3E, a source region 204 and a drain region 205 into which an n-type impurity has been introduced are formed in a region to be a channel of the second semiconductor layer 203 and separated by a predetermined distance (source / drain regions). Forming step). For example, the source region 204 and the drain region 205 to be n ⁺ regions may be formed by introducing an n-type impurity at a higher concentration by a well-known ion implantation method. Here, since there is a possibility that dislocation may occur in the joint portion 203a, the source region 204 and the drain region 205 are preferably formed so as to avoid the joint portion 203a.

  Next, as illustrated in FIG. 3F, the second semiconductor layer 203 other than the region serving as a channel is removed in order to separate the elements from each other. For example, the second semiconductor layer 203 is patterned by a known lithography technique and dry etching technique. Note that the second semiconductor layer 203 may be patterned so that the second semiconductor layer 203 exists only over the insulating layer 202a in order to separate from the gate electrode 206 formed in the first semiconductor layer 201.

  Next, as shown in FIG. 3G (b), a contact hole 202b for connecting to the gate electrode 206 is formed in the insulating layer 202a outside the channel region. For example, the contact hole 202b may be formed by selectively etching and patterning the insulating layer 202a by a known lithography technique and dry etching technique.

  Next, as shown in FIG. 3H, an ohmic electrode wiring 206a connected to the gate electrode 206 is formed. Further, an ohmic electrode is formed in each of the source region 204 and the drain region 205 to form the source electrode 207 and the drain electrode 208.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. Thereafter, by removing (lifting off) the resist mask pattern, patterning is performed so that the electrode metal material remains in the electrode formation region, thereby forming the ohmic electrode wiring 206a, the source electrode 207, and the drain electrode 208. Good.

  Also in the second embodiment, as described above, impurities are introduced into part of the semi-insulating first semiconductor layer 201 to form the gate electrode 206, and the gate electrode 206 is below the insulating layer 202a when viewed from the channel. It will be in the state where it is arranged. In the second embodiment as well, the insulating layer 202 is heat-treated as a nitrogen atmosphere in the growth furnace in which the metal organic chemical vapor deposition method is performed immediately before the second semiconductor layer 203 is grown. The film quality of 202 (insulating layer 202a) can also be improved.

  In the second embodiment as well, as described in Non-Patent Document 2, by using ELO, upward propagation of threading dislocations existing in the first semiconductor layer 201 is prevented by the insulating layer 202a. The second semiconductor layer 203 grown laterally on the insulating layer 202a from the inner region of 202a has fewer threading dislocations, and as a result, a high-quality second semiconductor layer 203 can be obtained on the insulating layer 202a. it can.

[Embodiment 3]
Next, Embodiment 3 of the present invention will be described with reference to FIGS. 4A to 4H. 4A to 4H are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the third embodiment of the present invention.

  First, as shown in FIG. 4A, a gate electrode 306 made of metal is formed at a predetermined location on the first semiconductor layer 301 made of a nitride semiconductor (gate electrode forming step). The first semiconductor layer 301 may be made of, for example, semi-insulating GaN (an insulating nitride semiconductor). The third embodiment is characterized in that the gate electrode 306 is formed in the initial stage. Note that the gate electrode 306 is formed in a strip shape extending in a predetermined direction, as shown in FIG. 4A (b). In the plane of the first semiconductor layer 301, the direction perpendicular to the predetermined direction is the gate length direction.

  For example, the first semiconductor layer 301 may be grown on a crystal substrate such as sapphire, Si, and GaN, or a SiC substrate. This layer becomes a buffer layer. Further, a resist mask pattern having an opening in the gate electrode formation region is formed, and a gate metal material is deposited thereon by, for example, vapor deposition, and then the resist mask pattern is removed (lifted off), whereby the gate electrode 306 is formed. Form.

Next, as illustrated in FIG. 4B, the insulating layer 302 is formed on the first semiconductor layer 301. For example, the insulating layer 302 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by a chemical vapor deposition (CVD) method using plasma assist. Here, since the gate electrode 306 is formed, a step is formed on the surface of the insulating layer 302 where the gate electrode 306 is formed.

  Next, the step of the insulating layer 302 described above is planarized, and in addition, a part of the insulating layer 302 is removed, and as shown in FIG. 4C, the insulating layer 302a in which the surface of the part of the first semiconductor layer 301 is exposed. (Insulating layer forming step). For example, the insulating layer 302 at the stepped portion is selectively removed by a known lithography technique and dry etching technique, and the first insulating layer 302 is patterned to form an opening region, thereby forming a part of the first region. The insulating layer 302a may be formed by exposing the semiconductor layer 301. Note that the insulating layer 302a over the gate electrode 306 is thinner than the surroundings. For this reason, an electric field is intensively generated between the gate electrode 306 and the channel by application of the gate voltage regardless of the resistivity of the first semiconductor layer 301. Therefore, the first semiconductor layer 301 is not limited to insulation, and may have an arbitrary resistivity.

  Next, as shown in FIG. 4D, by selective lateral growth ELO using the insulating layer 302a as a selective growth mask, a nitride semiconductor is epitaxially grown from a region where the surface of a part of the first semiconductor layer 301 is exposed, and the insulating layer 302a. A second semiconductor layer 303 serving as a channel is formed on the substrate (channel forming step).

  For example, GaN (p-type nitride semiconductor) doped with p-type impurities is grown by MOLO by MOCVD, and the second semiconductor layer 303 is formed so as to cover the insulating layer 302a. Here, in Embodiment Mode 3, as described above, the gate electrode 306 is provided before the formation of the insulating layer 302a. Therefore, when the second semiconductor layer 303 is formed, the MIS structure is formed by the gate electrode 306 / the insulating layer 302a / the second semiconductor layer 303. FIG. 4D shows a bonding portion 303a where GaN grown ELO from the left to the right on the paper surface and GaN grown ELO from the right to the left are joined on the surface of the insulating layer 302a.

Next, as shown in FIG. 4E, a source region 304 and a drain region 305 into which an n-type impurity has been introduced are formed in a region to be a channel of the second semiconductor layer 303 and separated by a predetermined distance (source / drain regions). Forming step). For example, the source region 304 and the drain region 305 to be n ⁺ regions may be formed by introducing an n-type impurity at a higher concentration by a well-known ion implantation method. Here, since there is a possibility that dislocation occurs in the junction portion 303a, the source region 304 and the drain region 305 are preferably formed so as to avoid the junction portion 303a.

  Next, as illustrated in FIG. 4F, the second semiconductor layer 303 other than the channel region is removed in order to separate the elements from each other. For example, the second semiconductor layer 303 is patterned by a known lithography technique and dry etching technique. Note that in order to separate from the gate electrode 306 formed over the first semiconductor layer 301, the second semiconductor layer 303 may be patterned so that the second semiconductor layer 303 exists only over the insulating layer 302a.

  Next, as illustrated in FIG. 4B, a contact hole 302b for connecting to the gate electrode 306 is formed in the insulating layer 302a in a region other than the channel region. For example, the contact hole 302b may be formed by selectively etching and patterning the insulating layer 302a by a known lithography technique and dry etching technique.

  Next, as shown in FIG. 4H, an ohmic electrode wiring 306a connected to the gate electrode 306 is formed. Further, an ohmic electrode is formed in each of the source region 304 and the drain region 305 to form the source electrode 307 and the drain electrode 308. The source electrode 307 and the drain electrode 308 are formed so as not to be connected to the gate electrode 306, the ohmic electrode wiring 306a, and the like.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. Thereafter, by removing (lifting off) the resist mask pattern and patterning so that the electrode metal material remains in the electrode formation region, the ohmic electrode wiring 306a, the source electrode 307, and the drain electrode 308 are formed. Good.

  Also in Embodiment 3, as described above, impurities are introduced into part of the semi-insulating first semiconductor layer 301 to form the gate electrode 306, and the gate electrode 306 is below the insulating layer 302a when viewed from the channel. It will be in the state where it is arranged. Also in Embodiment 3, immediately before the second semiconductor layer 303 is grown, the insulating layer 302 is heat-treated as a nitrogen atmosphere inside the growth furnace in which the metal organic chemical vapor deposition method is performed. The film quality of 302 (insulating layer 302a) can also be improved.

  Also in Embodiment 3, as described in Non-Patent Document 2, by using ELO, upward propagation of threading dislocations existing in the first semiconductor layer 301 is prevented by the insulating layer 302a. The second semiconductor layer 303 grown laterally on the insulating layer 302a from the inner region of the 302a has fewer threading dislocations. As a result, a high-quality second semiconductor layer 303 can be obtained on the insulating layer 302a. it can.

[Embodiment 4]
Next, Embodiment 4 of the present invention will be described with reference to FIGS. 5A to 5E. 5A to 5E are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fourth embodiment of the present invention.

First, as shown in FIG. 5A, the insulating layer 402 is formed on the first semiconductor layer 401 made of a nitride semiconductor. The first semiconductor layer 401 may be made of, for example, GaN (n-type nitride semiconductor) into which an n-type impurity is introduced at a high concentration. For example, the first semiconductor layer 401 may be grown on a crystal substrate such as sapphire, Si, and GaN, or a SiC substrate. This layer becomes a buffer layer. Further, for example, the insulating layer 402 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by a plasma-assisted chemical vapor deposition (CVD) method.

  Next, a part of the insulating layer 402 is removed, and as shown in FIG. 5B, the surface of a part of the first semiconductor layer 401 is exposed to form an insulating layer 402a (insulating layer forming step). For example, by patterning the insulating layer 402 by a known lithography technique and dry etching technique to form an opening region, a part of the first semiconductor layer 401 may be exposed to form the insulating layer 402a.

  Next, as shown in FIG. 5C, a nitride semiconductor is epitaxially grown from a region where the surface of a part of the first semiconductor layer 401 is exposed by ELO using the insulating layer 402a as a selective growth mask, and a channel is formed on the insulating layer 402a. The second semiconductor layer 403 is formed (channel formation step). Subsequently, a third semiconductor layer 404 is formed on the second semiconductor layer 403. The third semiconductor layer 404 serves as a carrier generation layer for causing the second semiconductor layer 403 to generate a two-dimensional electron gas.

  For example, in the heterostructure of the second semiconductor layer 403 and the third semiconductor layer 404, as is well known, if the first semiconductor layer 401 is crystal-grown in the C-axis direction and the main surface is c-plane, Even if impurities are not doped, high-concentration carriers are generated at the heterointerface due to spontaneous polarization and piezoelectric polarization, and a two-dimensional electron gas serving as a channel is formed.

  For example, undoped GaN (undoped nitride semiconductor) is grown by ELO by MOCVD, and the second semiconductor layer 403 is formed so as to cover the insulating layer 402a. Next, undoped AlGaN is epitaxially grown to form the third semiconductor layer 404.

  Here, in the fourth embodiment, as will be described later, the first semiconductor layer 401 is used as a gate electrode. Therefore, it can be seen that the first semiconductor layer 401 / the insulating layer 402a / the second semiconductor layer 403 play the same role as the MIS structure at the stage where the second semiconductor layer 403 is formed. FIG. 5C shows a junction 403a where GaN grown ELO from left to right on the surface of the insulating layer 402a and GaN grown ELO from right to left are joined.

  Next, as shown in FIG. 5D, the second semiconductor layer 403 and the third semiconductor layer 404 other than the region to be the channel are removed. For example, the second semiconductor layer 403 and the third semiconductor layer 404 are patterned by a known lithography technique and dry etching technique. In particular, the second semiconductor layer 403 and the third semiconductor are separated so that the second semiconductor layer 403 and the third semiconductor layer 404 exist only on the insulating layer 402a in order to separate from the first semiconductor layer 401 serving as the gate electrode. Layer 404 is patterned.

  Next, as shown in FIG. 5E, an ohmic electrode wiring 406 to be connected to the first semiconductor layer 401 is formed, and the first semiconductor layer 401 under the channel region is used as a gate electrode (gate electrode forming step). . In addition, an ohmic electrode is formed in a region to be a channel of the second semiconductor layer 403 at a predetermined distance, and a source electrode 407 and a drain electrode 408 are formed.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. Thereafter, the ohmic electrode wiring 406, the source electrode 407, and the drain electrode 408 are formed by patterning so as to leave the electrode metal material in the electrode formation region by removing (lifting off) the resist mask pattern. Good. Here, since there is a possibility that dislocation occurs in the junction portion 403a, the source electrode 407 and the drain electrode 408 are preferably formed so as to avoid the junction portion 403a.

  In the fourth embodiment, as described above, the first semiconductor layer 401 is used as a gate electrode, and the gate electrode is disposed under the insulating layer 402a when viewed from the channel. In addition, according to Embodiment 4, immediately before the second semiconductor layer 403 is grown, the insulating layer 402 is heat-treated as a nitrogen atmosphere inside the growth furnace in which the metal organic chemical vapor deposition method is performed, so that the insulating layer 402 is insulated. The film quality of the layer 402 (insulating layer 402a) can also be improved.

  Further, as described in Non-Patent Document 2, by using ELO, upward propagation of threading dislocations existing in the first semiconductor layer 401 is blocked by the insulating layer 402a. Since the second semiconductor layer 403 grown laterally on 402a has fewer threading dislocations, a high-quality second semiconductor layer 403 can be obtained on the insulating layer 402a.

  In the fourth embodiment, a two-dimensional electron gas formed by a built-in potential in a heterostructure of a nitride semiconductor is used as a channel, and a so-called normally-on transistor is obtained.

[Embodiment 5]
Next, Embodiment 5 of the present invention will be described with reference to FIGS. 6A to 6G. 6A to 6G are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the manufacturing method of the semiconductor device in the fifth embodiment of the present invention.

  First, as shown in FIG. 6A, an n-type impurity is introduced into a predetermined location on the first semiconductor layer 501 made of a nitride semiconductor to form a gate electrode 506 (gate electrode forming step). The first semiconductor layer 501 may be made of, for example, semi-insulating GaN (an insulating nitride semiconductor). As shown in FIG. 6A (b), the gate electrode 506 includes a strip-shaped portion extending in the vertical direction on the paper surface and a triangular (end-spread) portion in plan view that widens toward one side (the lower side of the paper surface). With. A gate length that does not overlap the source / drain region is set in a portion sandwiched between the source / drain described later, and an electrode wiring described later is connected in a divergent portion.

For example, the first semiconductor layer 501 may be grown on a crystal substrate such as corundum (sapphire), silicon (Si), and GaN, or a SiC substrate. This layer becomes a buffer layer. Further, a mask pattern having an opening in the gate electrode formation region is formed, and an n-type impurity is ion-implanted from above to form a gate electrode 506 that is an n ⁺ region.

Next, as illustrated in FIG. 6B, the insulating layer 502 is formed on the first semiconductor layer 501. For example, the insulating layer 502 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by a plasma-assisted chemical vapor deposition (CVD) method.

  Next, as shown in FIG. 6C, a part of the insulating layer 502 is removed to form an insulating layer 502a in which the surface of the part of the first semiconductor layer 501 is exposed (insulating layer forming step). For example, the insulating layer 502 a may be formed by exposing the part of the first semiconductor layer 501 by patterning the insulating layer 502 by a known lithography technique and dry etching technique to form an opening region.

  Next, as shown in FIG. 6D, a nitride semiconductor is epitaxially grown from a region where the surface of a part of the first semiconductor layer 501 is exposed by selective lateral growth ELO using the insulating layer 502a as a selective growth mask. A second semiconductor layer 103 serving as a channel is formed on the substrate (channel forming step). Subsequently, a third semiconductor layer 504 is formed on the second semiconductor layer 503. The third semiconductor layer 504 serves as a carrier generation layer for causing the second semiconductor layer 503 to generate a two-dimensional electron gas.

  For example, in the heterostructure of the second semiconductor layer 503 and the third semiconductor layer 504, as is well known, if the first semiconductor layer 501 is crystal-grown in the C-axis direction and the main surface is c-plane, Even if impurities are not doped, high-concentration carriers are generated at the heterointerface due to spontaneous polarization and piezoelectric polarization, and a two-dimensional electron gas serving as a channel is formed.

  For example, undoped GaN (undoped nitride semiconductor) is grown by ELO by MOCVD, and the second semiconductor layer 503 is formed so as to cover the insulating layer 502a. Next, undoped AlGaN is epitaxially grown to form the third semiconductor layer 504.

  Here, in the fifth embodiment, as described above, a part of the first semiconductor layer 501 into which the n-type impurity is introduced becomes the gate electrode 506. Therefore, at the stage of forming the second semiconductor layer 503, the MIS structure is formed by the gate electrode 506 / insulating layer 502a / second semiconductor layer 503. FIG. 6D shows a junction 503a where GaN grown ELO from left to right and GaN grown ELO from right to left are joined on the surface of the insulating layer 502a.

  Next, as illustrated in FIG. 6E, the second semiconductor layer 503 and the third semiconductor layer 504 other than the channel region are removed in order to separate the elements from each other. For example, the second semiconductor layer 503 and the third semiconductor layer 504 are patterned by a known lithography technique and dry etching technique. Note that in order to separate from the gate electrode 506 formed in the first semiconductor layer 501, the second semiconductor layer 503 may be patterned so that the second semiconductor layer 503 exists only on the insulating layer 502a.

  Next, as illustrated in FIG. 6F, a contact hole 502b for connecting to the gate electrode 506 is formed in the insulating layer 502a in a region other than the channel region. For example, the contact hole 502b may be formed by selectively etching and patterning the insulating layer 502a by a known lithography technique and dry etching technique.

  Next, as shown in FIG. 6G, ohmic electrode wiring 506a connected to the gate electrode 506 is formed. Further, an ohmic electrode is formed in each of the source region 504 and the drain region 505 to form the source electrode 507 and the drain electrode 508.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. After that, the ohmic electrode wiring 506a, the source electrode 507, and the drain electrode 508 are formed by patterning so as to leave the electrode metal material in the electrode formation region by removing (lifting off) the resist mask pattern. Good.

  In Embodiment Mode 5 as well, as described above, impurities are introduced into part of the semi-insulating first semiconductor layer 501 to form the gate electrode 506, and the gate electrode 506 is below the insulating layer 502a when viewed from the channel. It will be in the state to be arranged. Also in Embodiment 5, immediately before the second semiconductor layer 503 is grown, the insulating layer 502 is heat-treated as a nitrogen atmosphere inside the growth furnace in which the metal organic chemical vapor deposition method is performed. The film quality of 502 (insulating layer 502a) can also be improved.

  Also in Embodiment 5, as described in Non-Patent Document 2, by using ELO, upward propagation of threading dislocations existing in the first semiconductor layer 501 is prevented by the insulating layer 502a. Since the second semiconductor layer 503 grown laterally on the insulating layer 502a from the inner region of 502a has fewer threading dislocations, a high-quality second semiconductor layer 503 can be obtained on the insulating layer 502a. it can.

  In the fifth embodiment, a two-dimensional electron gas formed by a built-in potential in a heterostructure of a nitride semiconductor is used as a channel, so that a so-called normally-on transistor is obtained. Here, in the fifth embodiment, the gate electrode 506 is not formed in the source / drain regions. With this configuration, the carrier concentration of the two-dimensional electron gas existing in the source / drain region is not modulated by the gate voltage, and the access resistance to the source / drain channel is changed by the application of the gate voltage. There is nothing. In addition, the gate length can be shortened within the range of the patterning system, which is advantageous for high-frequency operation.

[Embodiment 6]
Next, Embodiment 6 of the present invention will be described with reference to FIGS. 7A to 7G. 7A to 7G are a cross-sectional view (a) and a plan view (b) showing a state of a process in the middle of explaining the method for manufacturing the semiconductor device in the sixth embodiment of the present invention.

  First, as shown in FIG. 7A, a gate electrode 606 made of metal is formed at a predetermined location on the first semiconductor layer 601 made of a nitride semiconductor (gate electrode forming step). The first semiconductor layer 601 may be made of, for example, semi-insulating GaN (an insulating nitride semiconductor). As shown in FIG. 7A (b), the gate electrode 606 has a strip-shaped portion extending in the vertical direction on the paper surface and a triangular (end-spreading) portion in plan view that widens toward one side (the lower side of the paper surface). With. A gate length that does not overlap the source / drain region is set in a portion sandwiched between the source / drain described later, and an electrode wiring described later is connected in a divergent portion.

  For example, the first semiconductor layer 601 may be grown on a crystal substrate such as corundum (sapphire), silicon (Si), and GaN, or a SiC substrate. This layer becomes a buffer layer. Further, a resist mask pattern having an opening in the gate electrode formation region is formed, and a gate metal material is deposited thereon by, for example, vapor deposition, and then the resist mask pattern is removed (lifted off), whereby the gate electrode 606 is formed. Form.

Next, as illustrated in FIG. 7B, the insulating layer 602 is formed over the first semiconductor layer 601. For example, the insulating layer 602 may be formed by depositing an insulating material such as SiO ₂ , Al ₂ O ₃ , or SiN by a chemical vapor deposition (CVD) method using plasma assist. Here, since the gate electrode 606 is formed, a step is formed on the surface of the insulating layer 602 where the gate electrode 606 is formed.

  Next, the above-described step of the insulating layer 602 is flattened, and in addition, a part of the insulating layer 602 is removed, and as shown in FIG. 7C, the insulating layer 602a in which the surface of the part of the first semiconductor layer 601 is exposed. (Insulating layer forming step). For example, the insulating layer 602 at the step portion is selectively removed by a known lithography technique and dry etching technique, and the first insulating layer 602 is patterned to form an opening region. The insulating layer 602a may be formed by exposing the semiconductor layer 601.

  Note that the insulating layer 602a over the gate electrode 606 is thinner than the surroundings. For this reason, an electric field is intensively generated between the gate electrode 606 and the channel by application of the gate voltage regardless of the resistivity of the first semiconductor layer 601. Therefore, the first semiconductor layer 601 is not limited to an insulating property and may have an arbitrary resistivity.

  Next, as shown in FIG. 7D, a nitride semiconductor is epitaxially grown from a region where the surface of a part of the first semiconductor layer 601 is exposed by selective lateral growth ELO using the insulating layer 602a as a selective growth mask. A second semiconductor layer 103 serving as a channel is formed on the substrate (channel forming step). Subsequently, a third semiconductor layer 604 is formed on the second semiconductor layer 603. The third semiconductor layer 604 serves as a carrier generation layer for causing the second semiconductor layer 603 to generate a two-dimensional electron gas.

  For example, in the heterostructure of the second semiconductor layer 603 and the third semiconductor layer 604, as is well known, if the first semiconductor layer 601 is crystal-grown in the C-axis direction and the main surface is the c-plane, Even if impurities are not doped, high-concentration carriers are generated at the heterointerface due to spontaneous polarization and piezoelectric polarization, and a two-dimensional electron gas serving as a channel is formed.

  For example, undoped GaN (undoped nitride semiconductor) is grown by ELO by MOCVD, and the second semiconductor layer 603 is formed so as to cover the insulating layer 602a. Next, undoped AlGaN is epitaxially grown to form the third semiconductor layer 604.

  Here, in Embodiment 6, as described above, the gate electrode 606 is provided before the formation of the insulating layer 602a. Therefore, when the second semiconductor layer 603 is formed, the MIS structure is formed by the gate electrode 606 / the insulating layer 602a / the second semiconductor layer 603. FIG. 7D shows a junction 603a where GaN grown ELO from left to right and GaN grown ELO from right to left are joined on the surface of the insulating layer 602a.

  Next, as illustrated in FIG. 7E, the second semiconductor layer 603 and the third semiconductor layer 604 other than the channel region are removed in order to separate the elements from each other. For example, the second semiconductor layer 603 and the third semiconductor layer 604 are patterned by a known lithography technique and dry etching technique. Note that the second semiconductor layer 603 may be patterned so that the second semiconductor layer 603 exists only over the insulating layer 602a in order to separate from the gate electrode 606 formed in the first semiconductor layer 601.

  Next, as illustrated in FIG. 7F, a contact hole 602b for connecting to the gate electrode 606 is formed in the insulating layer 602a in a region other than the channel region. For example, the contact hole 602b may be formed by selectively etching and patterning the insulating layer 602a by a known lithography technique and dry etching technique.

  Next, as shown in FIG. 7G, an ohmic electrode wiring 606a connected to the gate electrode 606 is formed. Further, an ohmic electrode is formed in each of the source region 604 and the drain region 605 to form the source electrode 607 and the drain electrode 608.

  For example, a resist mask pattern having openings is formed in the electrode formation region, and an electrode metal material is deposited thereon by vapor deposition or the like. After that, the ohmic electrode wiring 606a, the source electrode 607, and the drain electrode 608 are formed by patterning so as to leave the electrode metal material in the electrode formation region by removing (lifting off) the resist mask pattern. Good.

  Also in Embodiment 6, as described above, impurities are introduced into part of the semi-insulating first semiconductor layer 601 to form the gate electrode 606, and the gate electrode 606 is located below the insulating layer 602a when viewed from the channel. It will be in the state to be arranged. Also in Embodiment 6, immediately before the second semiconductor layer 603 is grown, the insulating layer 602 is heat-treated as a nitrogen atmosphere inside the growth furnace in which the metal organic chemical vapor deposition method is performed, whereby the insulating layer The film quality of 602 (insulating layer 602a) can also be improved.

  Also in Embodiment 6, as described in Non-Patent Document 2, by using ELO, upward propagation of threading dislocations existing in the first semiconductor layer 601 is prevented by the insulating layer 602a. Since the second semiconductor layer 603 grown laterally on the insulating layer 602a from the inner region of the layer 602a has fewer threading dislocations, a high-quality second semiconductor layer 603 can be obtained on the insulating layer 602a as a result. it can.

  In the sixth embodiment, a two-dimensional electron gas formed by a built-in potential in a heterostructure of a nitride semiconductor is used as a channel, so that a so-called normally-on transistor is obtained. Here, in the sixth embodiment, the gate electrode 606 is not formed in the source / drain regions. With this configuration, the carrier concentration of the two-dimensional electron gas existing in the source / drain region is not modulated by the gate voltage, and the access resistance to the source / drain channel is changed by the application of the gate voltage. There is nothing. In addition, the gate length can be shortened within the range of the patterning system, which is advantageous for high-frequency operation.

  As described above, the present invention has a significant feature in that the second semiconductor layer serving as the channel is formed after the insulating layer is formed.

  Conventionally, since an insulating layer is formed on a semiconductor layer that becomes a channel, a natural oxide film that is formed on the surface of the channel is a source of interface states, resulting in deterioration of transistor characteristics.

  In order to solve the above problems, in the present invention, an insulating layer forming step of forming an insulating layer on a first semiconductor layer made of a nitride semiconductor with a part of the surface of the first semiconductor layer exposed, Channel formation for forming a second semiconductor layer serving as a channel on an insulating layer by epitaxially growing a nitride semiconductor from a region where the surface of a part of the first semiconductor layer is exposed by selective lateral growth using the layer as a selective growth mask And a source electrode / drain electrode forming step for forming a source electrode and a drain electrode on the second semiconductor layer, and a gate electrode forming step for forming a gate electrode disposed under the insulating layer. There is.

  As a result, according to the present invention, a natural oxide film of a nitride semiconductor is not formed on the interface of the insulating layer on the semiconductor layer serving as a channel, and a III-V group compound semiconductor is used. It is possible to suppress deterioration of transistor characteristics in the MISFET.

The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, the first semiconductor layer and the second semiconductor layer are composed of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It only has to be done. The third semiconductor layer only needs to be made of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). . In addition, for example, in the above description, the two-dimensional electron gas is formed using the built-in potential of the nitride semiconductor crystal grown in the C-axis direction. However, the present invention is not limited to this. (Carrier injection layer) may be used.

  The present invention can be applied not only to nitride semiconductors containing GaN but also to materials capable of ELO such as other III-V group compound semiconductors such as GaAs and InP. In MISFETs using GaAs, InP, or the like, the same problem as described above occurs. Therefore, according to the present invention, deterioration of transistor characteristics in MISFETs using III-V group compound semiconductors can be suppressed.

  DESCRIPTION OF SYMBOLS 101 ... 1st semiconductor layer, 102 ... Insulating layer, 102a ... Insulating layer, 103 ... 2nd semiconductor layer, 103a ... Junction part, 104 ... Source region, 105 ... Drain region, 106 ... Ohmic electrode wiring, 107 ... Source electrode 108: Drain electrode.

Claims (17)

An insulating layer forming step of forming an insulating layer on a first semiconductor layer made of a nitride semiconductor with a part of the surface of the first semiconductor layer exposed;
By selective lateral growth using the insulating layer as a selective growth mask, a nitride semiconductor is epitaxially grown from a region where a part of the surface of the first semiconductor layer is exposed, and a second semiconductor layer serving as a channel is formed on the insulating layer. A channel forming step to be formed;
Forming a gate electrode disposed under the insulating layer; and
And a source / drain electrode forming step of forming a source electrode and a drain electrode on the second semiconductor layer. In the manufacturing method of the semiconductor device according to claim 1,
The first semiconductor layer is composed of an n-type nitride semiconductor,
The second semiconductor layer is composed of a p-type nitride semiconductor,
A source / drain region forming step of forming a source region and a drain region into which an n-type impurity is introduced, separated from the region to be the channel of the second semiconductor layer by a predetermined distance;
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and the second semiconductor layer other than the region to be the channel is removed,
In the source / drain electrode formation step, an ohmic electrode is formed in each of the source region and the drain region to form the source electrode and the drain electrode,
In the gate electrode forming step, an ohmic electrode wiring connected to the first semiconductor layer is formed, and the first semiconductor layer under the channel region is used as a gate electrode. Method. In the manufacturing method of the semiconductor device according to claim 1,
The first semiconductor layer is made of an insulating nitride semiconductor,
In the gate electrode forming step, the gate electrode is formed by introducing an n-type impurity into a part of the first semiconductor layer in a region to be a channel,
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and the second semiconductor layer other than the region to be the channel is removed,
A source / drain region forming step of forming a source region and a drain region into which an n-type impurity is introduced, spaced apart from the region of the second semiconductor layer by a predetermined distance across a gate electrode formation region;
In the source / drain electrode formation step, an ohmic electrode is formed in each of the source region and the drain region to form the source electrode and the drain electrode. In the manufacturing method of the semiconductor device according to claim 1,
A source / drain region forming step of forming a source region and a drain region into which an n-type impurity is introduced, separated from the region to be the channel of the second semiconductor layer by a predetermined distance;
The second semiconductor layer is composed of a p-type nitride semiconductor,
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and the second semiconductor layer other than the region to be the channel is removed,
In the source / drain electrode formation step, an ohmic electrode is formed in each of the source region and the drain region to form the source electrode and the drain electrode,
In the gate electrode forming step, in the region sandwiched between the source region and the drain region in the channel region, the gate electrode made of metal is formed on the first semiconductor layer before forming the insulating layer. Forming,
In the insulating layer forming step, unevenness on the surface of the insulating layer formed by the presence of the gate electrode is planarized. In the manufacturing method of the semiconductor device according to claim 1,
The first semiconductor layer is composed of an n-type nitride semiconductor,
The second semiconductor layer is composed of an undoped nitride semiconductor,
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and a nitride semiconductor for generating a two-dimensional electron gas in the second semiconductor layer on the second semiconductor layer Forming a third semiconductor layer comprising: and then removing the second semiconductor layer and the third semiconductor layer other than the region to be the channel;
In the source / drain electrode formation step, an ohmic electrode is formed in each of the source region and the drain region of the third semiconductor layer in the region to be the channel to form the source electrode and the drain electrode,
In the gate electrode forming step, an ohmic electrode wiring connected to the first semiconductor layer is formed, and the first semiconductor layer under the channel region is used as a gate electrode. Method. In the manufacturing method of the semiconductor device according to claim 1,
The first semiconductor layer is made of an insulating nitride semiconductor,
The second semiconductor layer is composed of an undoped nitride semiconductor,
In the gate electrode forming step, the gate electrode is formed by introducing an n-type impurity into a part of the first semiconductor layer in a region to be a channel,
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and a nitride semiconductor for generating a two-dimensional electron gas in the second semiconductor layer on the second semiconductor layer Forming a third semiconductor layer comprising: and then removing the second semiconductor layer and the third semiconductor layer other than the region to be the channel;
In the source / drain electrode formation step, an ohmic electrode is formed on each of the source region and the drain region spaced apart from each other by a predetermined distance on the third semiconductor layer in the channel region. Then, the source electrode and the drain electrode are formed. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The second semiconductor layer is composed of an undoped nitride semiconductor,
In the insulating layer forming step, a part of the insulating layer is removed and a part of the surface of the first semiconductor layer is exposed,
In the channel formation step, the second semiconductor layer is formed so as to cover the insulating layer, and a nitride semiconductor for generating a two-dimensional electron gas in the second semiconductor layer on the second semiconductor layer Forming a third semiconductor layer comprising: and then removing the second semiconductor layer and the third semiconductor layer other than the region to be the channel;
In the source / drain electrode formation step, an ohmic electrode is formed on each of the source region and the drain region separated by a predetermined distance on the third semiconductor layer in the channel region, and the source electrode and the Forming a drain electrode,
In the gate electrode forming step, in the region sandwiched between the source region and the drain region in the channel region, the gate electrode made of metal is formed on the first semiconductor layer before forming the insulating layer. Forming,
In the insulating layer forming step, unevenness on the surface of the insulating layer formed by the presence of the gate electrode is planarized. In the manufacturing method of the semiconductor device according to any one of claims 1 to 7,
The method for manufacturing a semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are made of the same nitride semiconductor. A first semiconductor layer made of a nitride semiconductor;
An insulating layer formed on the first semiconductor layer with a portion of the surface of the first semiconductor layer exposed;
A second semiconductor layer made of a nitride semiconductor epitaxially grown from a region where a part of the surface of the first semiconductor layer is exposed by selective lateral growth using the insulating layer as a selective growth mask is formed on the insulating layer. Channel,
A gate electrode disposed under the insulating layer;
A semiconductor device comprising: a source electrode and a drain electrode formed on the channel. The semiconductor device according to claim 9.
The first semiconductor layer is composed of an n-type nitride semiconductor,
The second semiconductor layer is composed of a p-type nitride semiconductor,
A source region and a drain region which are formed in the channel and are spaced apart from each other by a predetermined distance and into which an n-type impurity is introduced;
An ohmic electrode wiring connected to the first semiconductor layer,
The source electrode and the drain electrode are ohmic electrodes connected to each of the source region and the drain region,
A semiconductor device, wherein the first semiconductor layer under the channel is a gate electrode. The semiconductor device according to claim 9.
The first semiconductor layer is made of an insulating nitride semiconductor,
The gate electrode is formed by introducing an n-type impurity into a part of the first semiconductor layer in a channel region,
A source region and a drain region formed in the channel and spaced apart from each other by a predetermined distance, into which an n-type impurity is introduced;
The semiconductor device, wherein the source electrode and the drain electrode are ohmic electrodes connected to each of the source region and the drain region. The semiconductor device according to claim 9.
The second semiconductor layer is composed of a p-type nitride semiconductor,
A source region and a drain region formed in the channel and spaced apart from each other by a predetermined distance, into which an n-type impurity is introduced;
The source electrode and the drain electrode are ohmic electrodes connected to each of the source region and the drain region,
The gate electrode is composed of a metal pattern formed on the first semiconductor layer below the insulating layer in a region sandwiched between a source region and a drain region in a region to be a channel,
The semiconductor device is characterized in that the surface of the insulating layer has flattened surface irregularities formed by the presence of the gate electrode. The semiconductor device according to claim 9.
The first semiconductor layer is composed of an n-type nitride semiconductor,
The second semiconductor layer is composed of an undoped nitride semiconductor,
A third semiconductor layer made of a nitride semiconductor for generating a two-dimensional electron gas in the channel;
An ohmic electrode wiring connected to the first semiconductor layer,
The source electrode and the drain electrode are ohmic electrodes formed in each of the source region and the drain region of the third semiconductor layer in the channel region,
A semiconductor device, wherein the first semiconductor layer under the channel is a gate electrode. The semiconductor device according to claim 9.
The first semiconductor layer is made of an insulating nitride semiconductor,
The second semiconductor layer is composed of an undoped nitride semiconductor,
The gate electrode is formed by introducing an n-type impurity into the first semiconductor layer in a part of the channel region,
A third semiconductor layer made of a nitride semiconductor for generating a two-dimensional electron gas in the channel is provided on the channel,
The source device and the drain electrode are ohmic electrodes formed in each of a source region and a drain region of the third semiconductor layer in the channel region. The semiconductor device according to claim 9.
The second semiconductor layer is composed of an undoped nitride semiconductor,
A third semiconductor layer made of a nitride semiconductor for generating a two-dimensional electron gas in the channel is provided on the channel,
The source electrode and the drain electrode are ohmic electrodes formed in each of the source region and the drain region of the third semiconductor layer in the channel region,
The gate electrode is composed of a metal pattern formed on the first semiconductor layer below the insulating layer in a region sandwiched between a source region and a drain region in a region to be a channel,
The semiconductor device is characterized in that the surface of the insulating layer has flattened surface irregularities formed by the presence of the gate electrode. The semiconductor device according to any one of claims 13 to 15,
The third semiconductor layer is made of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A semiconductor device. The semiconductor device according to any one of claims 9 to 16,
The first semiconductor layer and the second semiconductor layer are made of a nitride semiconductor represented by In _1-xy Al _x Ga _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A semiconductor device which is characterized by being made.

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