JP6073707B2 - Programmable controller - Google Patents

Description

  The present invention relates to a programmable controller.

  Conventionally, there has been known a programmable controller that includes a control unit and a connection connector, and can connect multiple types of function expansion cassettes that extend different functions by inputting / outputting signals to / from the control unit to the connection connector. (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 2003-22150

  By the way, if the type of the function expansion cassette connected to the programmable controller is different, the signals input / output between the function expansion cassette and the programmable controller are different, so in order to support all signals, there are many in the connector. It is necessary to provide a pin. On the other hand, from the viewpoint of reducing the size and weight of the function expansion cassette and saving the space of the connector portion in the programmable controller, it is required to reduce the number of pins provided in the connector.

  The technology disclosed in this specification has been created in view of the above problems. An object of the technology disclosed in the present specification is to provide a programmable controller that can reduce the number of connector pins while allowing attachment of a plurality of types of function expansion cassettes.

  The technology disclosed in this specification can selectively attach a control unit having a plurality of control unit ports to / from which signals are input and a plurality of types of function expansion cassettes having status information according to the type. A connector portion, a plurality of connector side selector portion ports connected to the connector portion, and a plurality of control portion side selector portion ports that correspond one-to-one with the plurality of control portion ports, and the connector side selector A selector unit that outputs a signal input to the unit port to the corresponding selector unit port of the control unit, a storage unit that stores discrimination information according to the type of the function expansion cassette, and an input via the connector unit The function expansion cassette attached to the connector unit based on the status information of the function expansion cassette to be performed and the determination information stored in the storage unit. A discriminating unit for discriminating the type of the slot, and the selector unit corresponds to a signal output to the connector-side selector unit port according to the type of the function expansion cassette discriminated by the discriminating unit. The present invention relates to a programmable controller characterized by being distributed to a side selector port and outputting.

  In the above programmable controller, when a function expansion cassette is attached to the connector portion, the attachment is performed based on the status information of the function expansion cassette input from the function expansion cassette side through the connector portion and the discrimination information stored in the storage portion. The type of the function expansion cassette received is discriminated. Then, signals input from the function expansion cassette through the connector unit are distributed and output to the corresponding control unit side selector ports depending on the determined type of the function expansion cassette. For this reason, when pins for inputting and outputting signals are provided in the connector portion, some of these pins can be shared between different types of function expansion cassettes as pins for inputting and outputting different signals. . Accordingly, in order to make a one-to-one correspondence with all signals output from each of the different types of function expansion cassettes, the number of connector-side selector ports, in other words, the shape corresponding to each port of the connector-side selector port. Thus, the number of pins provided in the connector part can be made smaller than the number of control part side selector part ports. As described above, in the above programmable controller, it is possible to reduce the number of pins provided in the connector portion while allowing a plurality of types of function expansion cassettes to be attached.

  According to the technology disclosed in the present specification, it is possible to realize a programmable controller that can reduce the number of connector pins while allowing attachment of a plurality of types of function expansion cassettes.

The perspective view which shows the external appearance structure of the programmable controller which concerns on Embodiment 1. FIG. The perspective view which shows typically the external appearance structure of CPU unit to which the cassette was attached. The perspective view which shows the attachment aspect of the cassette with respect to CPU unit of a front attachment type Schematic showing the mounting direction of the cassette to the front mounting type CPU unit The perspective view which shows the attachment aspect of the cassette with respect to the CPU unit of a side attachment type Schematic showing the mounting direction of the cassette to the side-mounting type CPU unit Simplified diagram of each configuration of CPU unit Diagram showing each component on the main board Circuit diagram showing internal configuration of communication cassette and input / output cassette Circuit diagram showing internal configuration of FPGA The figure which shows the table of discrimination information Diagram showing the flow from the start of the programmable controller to the start of operation

<Embodiment 1>
Embodiment 1 will be described with reference to the drawings. As shown in FIG. 1, the programmable controller PLC according to the present embodiment includes a power supply unit PU, a CPU unit CU, and a plurality of input / output units IU, and is a so-called unit expansion type. Each unit PU, CU, IU has a box shape and is a vertical type. Moreover, the connection part 2 is provided in the side of each unit PU, CU, IU, and it becomes possible to connect an adjacent unit by connecting with the connection part 2 of another unit. The power supply unit PU supplies power to other connected units. The CPU unit CU is a unit in which a CPU (an example of a control unit) 15 described later is incorporated. The input / output unit IU is a unit for connection with input and output devices.

  Next, the configuration of the CPU unit CU will be described. Various switches and the like are provided on the outer surface of the CPU unit CU as shown in FIG. 1, but simplified ones are shown in FIGS. 2, 3, and 5. As shown in FIG. 2, a cassette interface 11 to which a plurality of types of function expansion cassettes (hereinafter referred to as cassettes) CT can be selectively attached is provided on the front surface of the CPU unit CU. The cassette CT extends the functions of the CPU unit by inputting and outputting signals to and from the CPU unit CU while being attached to the CPU unit CU. In the CPU unit CU, different functions are expanded by selectively attaching a plurality of types of cassettes CT.

  As shown in FIG. 2, a main body substrate 12 is built in the CPU unit CU in a posture perpendicular to the installation surface of the CPU unit CU. A connector (an example of a connector portion) 13 is provided at a portion of the main body substrate 12 facing the cassette interface 11 so as to be exposed to the outside. The connector 13 has a plurality of pins (not shown). On the other hand, a cassette substrate 22 is built in the cassette CT attached to the CPU unit CU. A cassette-side connector 23 is provided on one end edge of the cassette substrate 22 so as to be exposed to the outside. By connecting the cassette-side connector 23 of the cassette CT to the connector 13 of the CPU unit CU, the cassette CT is attached to the CPU unit CU, and both are electrically connected.

  Next, the manner in which the cassette CT is attached to the CPU unit CU will be described. The CPU unit CU has a front mounting type (see FIG. 3) in which the cassette CT can be mounted straight from the front side of the CPU unit CU, and a side mounting type in which the cassette CT can be mounted straight from the side of the CPU unit CU ( 5)). Note that the CPU unit CU in the present embodiment may be any of the front mounting type and the side mounting type.

  In the front-mounted type CPU unit CU, as shown in FIG. 4, the cassette CT is attached to the CPU unit CU by inserting the terminals of the cassette-side connector 23 into the connector 13 from the front of the CPU unit CU. On the other hand, in the side-mounted type CPU unit CU, as shown in FIG. 6, the cassette CT is attached to the CPU unit CU by inserting the cassette-side connector 23 into the connector 13 from the side of the CPU unit CU. .

  Next, the configuration of the main body substrate 12 will be described. As shown in FIG. 7, at least an FPGA (Field-Programmable Gate Array) 14 and a CPU 15 are arranged on the main body substrate 12. The FPGA 14 is electrically connected to each of the connector 13 and the CPU 15 and is interposed between the two. The CPU 15 controls various circuits on the main body substrate 12. FIG. 7 shows a simplified configuration of the main body substrate 12. Therefore, the numbers of pins PN and CPU ports (an example of a control unit port) 32 of the connector 13 are different from those illustrated in FIGS.

  Next, the configuration of the connector 13 will be described. In FIG. 7, the connector 13 is illustrated as having 20 pins PN. Of the pins PN, six pins PN are variable buses CB. Each signal input from each pin PN of the variable bus CB is distributed to each port of a CPU side selector port (an example of a control unit side selector unit port) 34A by a selector 52 described later. Of the 14 pins PN excluding the variable bus CB, 8 pins PN are used as the data bus DB.

  In FIG. 7, among the pins PN of the connector 13, “A0” and “A1” indicate address signals, and “D7” indicates signals input / output from each pin PN excluding the variable bus CB. “D0” indicates data signals, “RD” and “WR” indicate data read / write signals, and “VCC” and “GND” indicate power supply signals.

  Here, in the present embodiment, among the plurality of types of cassettes CT, any of the input / output cassette CT1 (see FIG. 9), the communication cassette CT2 (see FIG. 9), and the pulse input / output cassette (not shown). It is assumed that such a cassette CT is attached to the CPU unit CU. Each cassette CT stores unique status information for each type of cassette CT.

  In the present embodiment, signals input / output between the programmable controller PLC and the cassette CT include an interface signal, a parallel data address signal, and an access control signal. Of these, the interface signals include communication signals such as TXD and RXD, special I / O signals such as a pulse control signal and analog input / output, a serial bus, and an address addition signal. The parallel data address signal includes status information and input / output information. The access control signal includes data read / write.

  Reference numeral CB1 in FIG. 7 indicates each signal input from the input / output cassette CT1 to each pin PN of the variable bus CB when the input / output cassette CT1 is attached to the CPU unit CU. Reference CB2 indicates each signal input from the communication cassette CT2 to each pin PN of the variable bus CB when the communication cassette CT2 is attached to the CPU unit CU. Reference numeral CB3 indicates each signal input from the pulse input / output cassette to each pin PN of the variable bus CB when the pulse input / output cassette is attached to the CPU unit CU.

  The CPU 15 is provided with a plurality of CPU ports 32 through which signals are input / output. As shown in FIG. 7, in the programmable controller PLC according to the present embodiment, each signal input from the cassette CT attached to the CPU unit CU through the pin PN of the connector 13 is sent to each CPU port 32 in the CPU 15 via the FPGA 14. It is configured to be input to the port.

  Next, detailed configurations of the connector 13 and the FPGA 14 and the CPU 15 arranged on the main body substrate 12 will be described with reference to FIG. As shown in FIG. 8, each port provided in the CPU 15 corresponds to three integrated circuits UART0, UART1, and UART2, an SPI interface, a general-purpose bus, and a port for a “WAIT” signal. Among these, each port corresponding to UART 1, UART 2, SPI interface, general-purpose bus, and “WAIT” signal is included in the CPU port 32. The integrated circuit UART0 is directly connected to the communication driver 16 and serves as a COM0 communication port of the CPU unit CU.

  Integrated circuits UART1 and UART2 each use three ports. The integrated circuits UART1 and UART2 correspond to COM1 and COM2 of the communication cassette CT2 (see FIG. 9), respectively. The SPI interface uses four ports. The general-purpose bus uses 48 ports. A port corresponding to the “WAIT” signal is added to this, and the CPU port 32 is composed of a total of 59 ports. Each port of the CPU port 32 is electrically connected to the FPGA 14 so that input / output is possible.

  A CPU-side FPGA port 34 is provided on the CPU 15 side of the FPGA 14 (see FIG. 8). Each port of the CPU side FPGA port 34 is connected to each port of the CPU port 32 in a one-to-one correspondence. The signals input / output at each port of the CPU port 32 correspond to the signals input / output at each port of the CPU-side FPGA port 34, respectively. Therefore, the CPU side FPGA port 34 is composed of 59 ports.

  On the other hand, a connector-side FPGA port 36 is provided on the connector 14 side of the FPGA 14. The connector-side FPGA port 36 includes eight ports corresponding to the signals “FS0” to “FS7”, three ports corresponding to the signals “CA0”, “CWE”, and “C0E”, and “CD0”. To 8 ports corresponding to the signal of “CD7”, and is composed of a total of 19 ports.

  The connector 13 has 21 pins PN as shown in FIG. Of these, the 19 pins PN excluding the power supply signal pin PN are electrically connected to each port of the connector-side FPGA port 36. The signals input / output at these 19 pins PN correspond to the signals input / output at each port of the connector-side FPGA port 36, respectively.

  Of the 21 pins PN in the connector 13, the eight pins PN that input and output the signals "FS0" to "FS7" are the variable bus CB described in FIG. Further, the eight pins PN for inputting / outputting the signals “CD0” to “CD7” are the data bus DB described with reference to FIG. A signal indicating status information of the cassette CT is input from the cassette CT attached to the CPU unit CU to the pin PN of the data bus DB.

  Next, the configuration of the input / output cassette CT1 and the communication cassette CT2 among the cassettes CT attached to the CPU unit CU in the present embodiment will be described. As shown in FIG. 9, the input / output cassette CT1 incorporates an output circuit for connection to an analog device. The cassette-side connector 23 of the input / output cassette CT1 is composed of 21 cassette-side pins CPN and is connected to each pin PN of the connector 13 on a one-to-one basis. The input / output cassette CT1 includes a status information storage unit CT1A in which 32-bit status information is stored. Even in the same input / output cassette, there are different types (input / output signals are different).

  As shown in FIG. 9, the communication cassette CT2 incorporates two types of communication drivers for communicating with external devices. The cassette-side connector 23 of the communication cassette CT2 is composed of 21 cassette-side pins CPN and is connected to each pin PN of the connector 13 on a one-to-one basis. In addition, the communication cassette CT2 stores 8-bit status information and incorporates a status information storage unit CT2A. Even in the same communication cassette, there are different types (different input / output signals). The input / output cassette CT1 and the communication cassette CT2 have different signals output to the pin PN of the variable bus CB.

  Next, the internal configuration of the FPGA 14 will be described with reference to FIG. As shown in FIG. 10, the FPGA 14 includes a selector (an example of a selector unit) 52, three flip-flops 54, a cassette status read unit (hereinafter referred to as a read unit) 56, and an address decode bus arbitration unit. 58.

  The selector 52 is provided with a connector-side selector port 36A on the connector 13 side, and a CPU-side selector port 34A is provided on the CPU 15 side. The connector-side selector port 36A is a signal port corresponding to a signal input / output at the pin PN of the variable bus CB in the connector 13 of the connector-side FPGA port 36. That is, the connector-side selector port 36A is composed of eight ports that input and output signals “FS0” to “FS7”. The CPU side selector port 34 </ b> A is composed of 16 ports among the CPU side FPGA ports 34. The CPU-side FPGA port 34 corresponds to the CPU port 32 on a one-to-one basis.

  The selector 52 has a function of distributing and outputting each signal (8-bit signal) input to the connector side selector port 36A to each port of the CPU side selector port 34A. Therefore, the signals respectively input to the eight ports in the connector side selector port 36A are distributed to any of the 16 ports in the CPU side selector port 34A by the selector 52 and output. The signal output from the CPU side selector port 34A is input to each port of the CPU port 32 corresponding to the signal.

  The selector 52 includes a discrimination information storage unit (an example of a storage unit) 52A in which discrimination information is stored. The discrimination information is information for discriminating the type of the attached cassette CT based on the binary signal output from the flip-flop 54 when the cassette CT is attached to the CPU unit CU. This discrimination information will be described in detail later.

  Further, the selector 52 includes a determination unit 52B. The determination unit 52B determines the type of the cassette CT attached to the connector 13 based on the status information of the cassette CT input via the connector 13 and the determination information stored in the determination information storage unit 52A. . A specific method for determining the type of cassette CT will be described in detail later.

  Each flip-flop 54 is electrically connected to the selector 52. Each flip-flop 54 reads a signal flowing through a signal line connecting the pin PN and the connector-side FPGA port 36, and holds a binary signal based on the read signal. Specifically, in the present embodiment, among the signal lines of the signal input from the pin PN of the data bus DB in the connector 13, the “CD0”, “CD1”, and “CD2” signals are input / output. Each flip-flop 54 is connected to the signal line (see FIG. 10). Each flip-flop 54 reads each signal of “CD0”, “CD1”, “CD2”, that is, 3-bit information.

  When each of the flip-flops 54 reads the signals “CD0”, “CD1”, and “CD2”, the flip-flops 54 temporarily hold these signals in a “0” or “1” state (as a binary signal). Thereafter, each flip-flop 54 outputs the held information “0” or “1” to the selector 52. The combinations of the binary signals output from the three flip-flops 54 are 2 to the third power, that is, eight ways.

  The lead part 56 is electrically connected to each flip-flop 54. When the cassette CT is attached to the CPU unit CU, the lead unit 56 displays the status of the cassette CT attached through signals (8-bit signals “CD0” to “CD7”) input from the pin PN of the data bus DB. To lead. Then, a signal instructing each flip-flop 54 to read the signals “CD0”, “CD1”, and “CD2” is output.

  The address decode bus arbitration unit 58 performs arbitration between the CPU 15 and other devices (such as an internal memory) inside and outside the programmable controller PLC.

  In the present embodiment, the discrimination information stored in the discrimination information storage unit 52A includes a table T as shown in FIG. As shown in the table T of FIG. 11, the discrimination information includes 3-bit signals (“CD0”, “CD1”, and “CD2” signals) input from the pin PN of a part DB1 of the data bus DB. Based on the combination of the binary signals held in the flip-flop 54, the modes “MODE1” to “MODE5” are included. Table T shows combinations of signals corresponding to signals input from the pin PN of the variable bus CB in the respective modes “MODE1” to “MODE5”, and these combinations differ depending on the modes. Each of these different signals corresponds to each signal suitable for the type of cassette CT attached to the CPU unit CU.

  The above is the configuration of the programmable controller PLC according to the first embodiment, and the operation thereof will be described. First, the flow from when the cassette CT is attached to the CPU unit CU to when the operation is started will be schematically described with reference to FIG.

  When the programmable controller PLC is activated, the lead unit 56 outputs signals (“CD0” to “CD0” to “CD0”) that are input from the pin PN of the data bus DB in the connector 13 among signals input from the cassette CT attached to the CPU unit CU. The status information of the attached cassette CT is read through the “CD7” 8-bit signal), and it is detected that the cassette CT is attached to the CPU unit CU.

  Next, the read unit 56 outputs to each flip-flop 54 a signal instructing reading of the signals “CD0”, “CD1”, and “CD2” among the signals indicating the status information. Receiving the read instruction, each flip-flop 54 reads the signals “CD0”, “CD1”, and “CD2”, and temporarily holds these signals as binary signals. Thereafter, each flip-flop 54 outputs the held binary signal, that is, information of “0” or “1” to the selector 52.

  Upon receiving the binary signal from each flip-flop 54, the selector 52 reads the discrimination information table T from the discrimination information storage unit 52A. Then, the determination unit 52B determines the mode on the table T corresponding to the received binary signal combination. That is, the type of the cassette CT attached to the CPU unit CU is determined from the status information and the determination information of the cassette CT.

  When the selector 52B determines the mode on the table T corresponding to the received binary signal combination, the selector 52 reads a signal corresponding to the signal input from the pin PN of the variable bus CB in the determined mode. Then, each signal that is input from the pin PN of the variable bus CB and reaches the connector-side selector port 36A is distributed and output to each port of the CPU-side selector port 34A corresponding to the corresponding signal (read signal).

  As described above, the signal input from the pin PN of the variable bus CB is distributed to a signal port suitable for each type of the communication cassette CT2, the pulse input / output cassette, and the input / output cassette CT1. Thereafter, the operation of the programmable controller PLC is started.

  Next, a binary signal output mode by the flip-flop 54 and a distribution mode by the selector 52 will be specifically described. First, a case where a communication cassette CT2 of the type shown in the present embodiment is attached to the CPU unit CU will be exemplified. Of the status information signals input from the type of communication cassette CT2 shown in the present embodiment, the signals corresponding to “CD0”, “CD1”, and “CD2” of the data bus DB are sent to the flip-flops 54, respectively. “1”, “0”, and “1” are held respectively. Therefore, each signal input from the pin PN of the variable bus CB in the communication cassette CT2 corresponds to mode 2 in the discrimination information table T (see column DB1 in FIG. 11).

  When the communication cassette CT2 is attached and the programmable controller PLC is activated, when each flip-flop 54 receives an instruction to read the signals “CD0”, “CD1”, and “CD2”, the signal “CD0” is read. The flip-flop 54 outputs a signal “1”, the flip-flop 54 that has read the signal “CD1” outputs a signal “0”, and the flip-flop 54 that has read the signal “CD2” is “1”. Output a signal.

  In the determination unit 52B, the selector 52 compares the signals “1”, “0”, and “1” received from the respective flip-flops 54 with the determination information table T read from the determination information storage unit 52A, and determines the CPU unit CU. It is determined that the cassette CT attached to is a cassette CT corresponding to mode 2. That is, it is determined that the cassette CT attached to the CPU unit CU is the type of communication cassette CT2 shown in the present embodiment.

  When the determination unit 52B determines that the cassette CT attached to the CPU unit CU is the type of communication cassette CT2 shown in the present embodiment, the selector 52 inputs from the pin PN of the variable bus CB to which the communication cassette CT2 is connected. Then, each signal that has arrived at the connector side selector port 36A is converted into a signal corresponding to the communication cassette CT2 (a signal corresponding to the signals "FS0" to "FS7" in mode 2) and each port of the CPU side selector port 34A. To output.

  That is, the selector 52 connects each port corresponding to “RXD1”, “TXD1”, “DE1 / RE1”, “DE2 / RE2”, “RXD2”, “TXD2” among the CPU side selector ports 34A to the connector side. The selector port 36A is switched so as to be connected to each port corresponding to “FS0”, “FS1”, “FS2”, “FS3”, “FS4”, and “FS5”. As a result, of the connector side selector port 36A, the signals that have arrived at the ports corresponding to “FS0”, “FS1”, “FS2”, “FS3”, “FS4”, “FS5” are sent to the CPU side selector port. It is assigned to each corresponding port of 34A. As a result, a signal suitable for the type of communication cassette CT2 shown in the present embodiment is output to the CPU port 32.

  Next, the case where the input / output cassette CT1 of the type shown in the present embodiment is attached to the CPU unit CU will be exemplified. Of the status information signals input from the input / output cassette CT1 of the type shown in this embodiment, the signals corresponding to “CD0”, “CD1”, and “CD2” of the data bus DB are the respective flip-flops 54. In FIG. 1, “1”, “1”, and “0” are held respectively. Accordingly, each signal input from the pin PN of the variable bus CB in the input / output cassette CT1 corresponds to mode 4 in the discrimination information table T (see column DB1 in FIG. 11).

  When the input / output cassette CT1 is attached and the programmable controller PLC is activated, when each flip-flop 54 receives an instruction to read the signals “CD0”, “CD1”, and “CD2”, the signal “CD0” is read. The flip-flop 54 outputs a signal “1”, the flip-flop 54 that has read the signal “CD1” outputs a signal “1”, and the flip-flop 54 that has read the signal “CD2” is “0”. The signal is output.

  In the determination unit 52B, the selector 52 compares the signals “1”, “1”, and “0” received from the flip-flops 54 with the determination information table T read from the determination information storage unit 52A, and determines the CPU unit CU. It is determined that the cassette CT attached to is a cassette CT corresponding to mode 4. That is, it is determined that the cassette CT attached to the CPU unit CU is the input / output cassette CT1 of the type shown in the present embodiment.

  When the determination unit 52B determines that the cassette CT attached to the CPU unit CU is the input / output cassette CT1 of the type shown in the present embodiment, the selector 52 determines the pin PN of the variable bus CB to which the input / output cassette CT1 is connected. From the CPU side selector port 34A corresponding to the signal suitable for the communication cassette CT2 (the signal corresponding to the signals "FS0" to "FS7" in mode 4). Output to each port.

  That is, the selector 52 corresponds to “RXD1”, “TXD1”, “CLR”, “S / IO”, “CA3”, “CA2”, “CA1”, “RDY” in the CPU-side selector port 34A. Each port is connected to each port corresponding to “FS0”, “FS1”, “FS2”, “FS3”, “FS4”, “FS5”, “FS6”, “FS7” in the connector side selector port 36A. Switch to be. As a result, in the connector-side selector port 36A, each signal that has reached “FS0”, “FS1”, “FS2”, “FS3”, “FS4”, “FS5”, “FS6”, “FS7” It is assigned to each corresponding port of the side selector port 34A. As a result, a signal suitable for the input / output cassette CT1 of the type shown in the present embodiment is output to the CPU port 32.

  As described above, in the programmable controller PLC according to this embodiment, when the cassette CT is attached to the CPU unit, the signal input from the cassette CT side through the pin PN of the connector 13 is input through the pin PN of the data bus DB. A part of the signal, that is, a signal indicating the status information of the cassette CT, a 3-bit signal is read by each flip-flop 54 and stored in the discrimination information storage unit 52A and a binary signal based on the signal. The type of cassette CT attached is determined based on the determination information table T. Then, a signal input from the cassette CT through the pin PN of the variable bus CB in the connector 13 and reaches the connector-side selector port 36A is distributed to the corresponding CPU-side selector port 34A according to the determined type of the cassette CT and output. Is done. Therefore, when the pins PN are provided in the connector 13 as in the present embodiment, a part of those pins PN, specifically, the pin PN of the variable bus CB is used as a pin PN for inputting and outputting different signals. It can be shared between different types of cassettes CT. Accordingly, in order to make a one-to-one correspondence with all signals output from each of the different types of cassettes CT, the number of connector-side selector ports 36A, in other words, in a form corresponding to each port of the connector-side selector port 36A. The number of pins provided on the variable bus CB of the connector 13 can be made smaller than the number of CPU side selector ports 34A. As described above, in the programmable controller PLC of the present embodiment, the number of pins PN provided on the connector 13 can be reduced while a plurality of types of cassettes CT can be attached.

  The programmable controller PLC according to this embodiment includes three flip-flops 54. Each of the three flip-flops 54 holds three binary signals based on the three signals input from the cassette CT attached to the connector 13 through the pin PN, and outputs these signals to the selector 52. Further, the selector 52 is based on the status information input from the cassette CT, that is, the combination of the three input binary signals, and the discrimination information table T read from the discrimination information storage unit 52A. The type of the cassette CT attached to the PC is determined. In this way, by combining a plurality of binary signals, it is possible to discriminate between three or more types of cassette CT. In the present embodiment, since the programmable controller PLC includes the three flip-flops 54, a maximum of 2 to the third power, that is, eight modes can be stored in the table T of the discrimination information.

  In the programmable controller PLC according to the present embodiment, the number of pins PN provided in the connector 13 can be reduced, so that the connector 13 (cassette side connector CPN) can be reduced in size. Thereby, the manufacturing cost can be reduced. Furthermore, since the number of pins PN provided on the connector 13 can be reduced, the degree of freedom in manufacturing the connector PN (cassette side connector CPN) can be increased, and thus a cassette CT excellent in workability, mechanical mounting strength, and the like is manufactured. be able to.

  Here, if the types of cassettes CT to be attached are different, the same signal among the signals output through the pin PN of the variable bus CB may be assigned to another pin PN of the variable bus CB. In this case, it has been difficult to cope with the conventional programmable controller. On the other hand, in the programmable controller PLC of the present embodiment, the signal output through the pin PN of the variable bus CB is distributed to a suitable port according to the type of the cassette CT to which the signal is attached. Is possible.

  In the conventional programmable controller, it is necessary to provide about 50 pins on the connector in order to correspond to a plurality of types of cassettes. On the other hand, in the programmable controller PLC according to the present embodiment, it is possible to cope with a plurality of types of cassettes only by providing about 20 pins on the connector, so the number of pins provided on the connector is greatly reduced compared to the conventional case. can do.

<Embodiment 2>
Next, the programmable controller according to the second embodiment will be described. In the programmable controller according to the second embodiment, the CPU unit includes a determination information storage unit and a determination unit built in the CPU. Since other configurations are the same as those of the programmable controller PLC according to the first embodiment, description thereof is omitted.

  In the programmable controller of this embodiment, the discrimination information storage unit and the discrimination unit are built in the CPU, respectively, and the binary signal held by the flip-flop is output to the CPU. When the CPU receives the binary signal from the flip-flop, the CPU reads the discrimination information table from the discrimination information storage unit. Then, the type of the cassette attached to the CPU unit is determined by the determination unit from the received binary signal combination and the read determination information table. That is, in this embodiment, the CPU determines the type of cassette attached to the CPU unit.

  When the CPU determines the type of the cassette, the CPU outputs information on each port of the CPU-side selector port corresponding to the matching signal based on the determined information from the determined type to the selector. Based on the information, the selector distributes each signal inputted from the pin of the variable bus and reaching the connector-side selector port to each port of the CPU-side selector port corresponding to the corresponding signal.

  As described above, even when the CPU determines the type of cassette, the pin of the variable bus in the connector can be used as a pin for inputting and outputting different signals between different types of cassettes. Can be shared. For this reason, the number of pins provided in the connector can be reduced while a plurality of types of cassettes can be attached.

<Other embodiments>
The present invention is not limited to the embodiments described above and with reference to the drawings. For example, the following embodiments are also included in the technical scope of the present invention.
(1) In each of the above-described embodiments, a configuration is illustrated in which signals that are input from the pins of the variable bus and reach the connector-side selector port among the signals input through the pins are distributed to the ports of the CPU-side selector port. However, it is not limited to this. Any part of the signal input through the pin may be distributed to each port of the CPU side selector port.

(2) In each of the above embodiments, the configuration in which the selector is arranged in the FPGA is illustrated, but the present invention is not limited to this. For example, the selector may be arranged in the multiplexer.

(3) In each of the above embodiments, the case where one of the input / output cassette, the communication cassette, and the pulse input / output cassette among the plurality of types of cassettes is attached to the CPU unit is exemplified. There may be a case where different types of cassettes are attached to the CPU unit. For example, communication cassettes of different communication types may be attached to the CPU unit.

(4) In each of the above embodiments, the configuration in which the discrimination information storage unit is built in the selector or the CPU is exemplified, but the present invention is not limited to this. For example, the discrimination information storage unit may be provided outside the selector and the CPU.

(5) In each of the above embodiments, the configuration in which the determination unit is built in the selector or the CPU is exemplified, but the present invention is not limited thereto. For example, the determination unit may be provided outside the selector and the CPU.

(6) In each of the above embodiments, the configuration in which the discrimination information is stored in the storage unit in a table format is illustrated, but the manner in which the discrimination information is stored is not limited.

  As mentioned above, although each embodiment of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

2 ... Connecting part 11 ... Cassette interface 12 ... Main board 13 ... Connector 14 ... FPGA
15 ... CPU
DESCRIPTION OF SYMBOLS 22 ... Cassette board 23 ... Cassette side connector 32 ... CPU port 34 ... CPU side FPGA port 34A ... CPU side selector port 36 ... Connector side FPGA port 36A ... Connector side selector port 52 ... Selector 52A ... Discrimination information storage part 52B ... Discrimination part 54 ... flip-flop 56 ... cassette status read unit 58 ... address decode bus arbitration unit CB ... variable bus CPN ... cassette side pin CT ... cassette CT1 ... input / output cassette CT1A, CT2A ... status information storage unit CT2 ... communication cassette CU ... CPU unit DB ... Data bus IU ... I / O unit PLC ... Programmable controller PN ... Pin PU ... Power supply unit T ... Table

Claims (1)

A control unit having a plurality of control unit ports through which signals are input and output;
A connector unit that can selectively mount a plurality of types of function expansion cassettes having status information according to the type; and
A plurality of connector side selector unit ports connected to the connector unit, and a plurality of control unit side selector unit ports corresponding to the plurality of control unit ports on a one-to-one basis, and input to the connector side selector unit port; A selector unit that outputs a corresponding signal to the corresponding selector unit port,
A storage unit storing discrimination information according to the type of the function expansion cassette;
Based on the status information of the function expansion cassette input through the connector unit and the determination information stored in the storage unit, the type of the function expansion cassette attached to the connector unit is determined. And a discriminator for
The selector unit distributes and outputs a signal output to the connector side selector unit port to the corresponding control unit side selector unit port according to the type of the function expansion cassette determined by the determination unit. Programmable controller.

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