JP6066737B2 - Timing reproduction apparatus and timing reproduction method - Google Patents

Description

  The present invention relates to a timing reproduction device and a timing reproduction method that constitute a communication device (reception device) on a reception side of a wireless communication system.

  In wireless communication, there are many diversity techniques for improving communication quality. STBC (Space Time Block Coding) and DSTBC (Differential Space Time Coding) are one of transmission diversity technologies, and a transmitter uses space-time coding (STBC coding) and differential time using a plurality of transmission antennas. This is a technique for obtaining a diversity effect by transmitting a signal subjected to spatial coding (DSTBC coding). As an example, STBC and DSTBC when two transmission antennas are used perform STBC coding and DSTBC coding on a block basis with two symbols as one block. Only one block is used for STBC encoding. In the case of DSTBC encoding, encoding is performed using the immediately preceding block and the next two blocks to be transmitted. The receiving apparatus performs STBC decoding and DSTBC decoding for each block generated by the transmitting apparatus. STBC decoding obtains a transmission path estimation value, and DSTBC decoding extracts an original symbol by processing between a certain block and the block immediately before it by processing within the block (see Non-Patent Document 1). As for the sensitivity characteristics, STBC has better characteristics than DSTBC, but DSTBC can be decoded without estimating the transmission path from the received signal in the decoding process, which corresponds to transmission path estimation performed by the STBC receiver. No processing is required. Therefore, there is an advantage that the DSTBC receiving apparatus is easier to configure than the STBC receiving apparatus.

  In the receiving apparatus, it is necessary to extract the timing (hereinafter referred to as symbol timing) at which the modulated signal is generated when demodulating the received signal. When filtering by the Nyquist filter is performed in the transmission / reception apparatus, the adjacent modulation signal is not interfered at the symbol timing, but is affected by intersymbol interference at other timings. When the clocks of the transmission device and the reception device are synchronized, symbol timing extraction processing is not necessary, but the clocks of the transmission device and the reception device cannot be synchronized in wireless communication. For this reason, a method of reproducing the symbol timing by synchronizing the phase of the clock of the transmitting device with the receiving device (hereinafter referred to as BTR (Bit Timing Recovery) method) is required. There is a multiplying tank system described in Non-Patent Document 2 as a BTR system. In the multiplication tank method, the I-phase component and the Q-phase component after quadrature detection of the received signal are squared and added to calculate a power value, and the power value is used as a clock waveform as a DFT (Discrete Fourier Transform) (discrete Fourier transform). Timing extraction is performed by calculating the phase component of the waveform by conversion. The multiplying tank method does not require a known signal such as a preamble or SW (also referred to as a sync word) and can perform processing on the entire received signal, so that timing reproduction can be performed at high speed. Further, even when the signal point of the known signal is not constant for each frame by differential encoding as in DSTBC, the timing recovery by the multiplying tank method is effective.

V. Tarokh, H .; Jafarkhani, “A Differential Detection Scheme for Transmit Diversity,” IEEE Journal on Selected Areas in Communications, Vol. 18, pp 1169-1174, July 2000. Yoichi Matsumoto, Masahiro Morikura, Shuzo Kato, “A study on an all-digital high-speed clock recovery circuit, storage clock recovery method,” IEICE technical report, SAT90 29-40, pp13-18, September 1990.

  The conventional multiplying tank method is based on the influence of noise after calculating the phase by performing DFT processing on the clock waveform using the power value obtained by squaring and adding the I-phase component and Q-phase component of the received signal as the clock waveform. The phase is averaged to reduce the variation. Even when the power of the symbol is not constant, the clock waveform is distorted and the result of the phase calculation varies, so that the accuracy of timing recovery by the multiplying tank method is higher when the modulation method with less power variation is used. Therefore, symbol timing can be estimated with high accuracy when the multiplying tank method is used as a modulation method BTR method in which the power of the modulation signal is constant, such as QPSK (Quadrature Phase Shift Keying) and DQPSK (Differential QPSK). However, when differential encoding by DSTBC is performed, the power of the signal after differential encoding is not constant even if the modulation method is QPSK. is there.

  The present invention has been made in view of the above, and in a receiving device that receives a signal differentially encoded by DSTBC, a timing reproducing device and timing that perform symbol timing estimation using a multiplying tank method with high accuracy The purpose is to obtain a reproduction method.

  In order to solve the above-described problems and achieve the object, the present invention provides symbol timing in a receiving apparatus that receives a DSTBC-coded signal in units of blocks with N symbols (N is an integer of 2 or more) as one block. A timing reproducing apparatus for reproducing, a power calculating means for calculating a power value of each sample value obtained by oversampling a received signal by K times, an adding means for adding the power values over N symbols, and the addition Timing estimation means for estimating symbol timing based on the addition result by the means.

  According to the present invention, there is an effect that it is possible to realize a timing reproducing apparatus capable of estimating the symbol timing of a received signal with high accuracy.

FIG. 1 is a diagram illustrating a configuration example of a receiving device including a timing reproducing device. FIG. 2 is a diagram illustrating a configuration example of a BTR unit which is a timing reproduction device. FIG. 3 is a diagram showing spectra before and after adding power values for two symbols. FIG. 4 is a diagram illustrating a configuration example of the BTR unit according to the second embodiment. FIG. 5 is a diagram illustrating a configuration example of a receiving apparatus according to the third embodiment. FIG. 6 is a diagram illustrating a configuration example of the BTR unit according to the third embodiment. FIG. 7 is a diagram illustrating a configuration example of the BTR unit according to the fourth embodiment.

  Embodiments of a timing reproduction apparatus and a timing reproduction method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a first embodiment of a receiving device including a timing reproducing device according to the present invention.

  As shown in the figure, the receiving apparatus includes a receiving antenna 1 that receives a DSTBC transmission signal, an A / D converter 2 that converts the received signal from an analog value to a digital value, and converts a high-frequency band signal into a baseband signal. An orthogonal detector 3 that performs orthogonal transform, a shaping filter 4 that blocks a signal other than the desired band, a BTR unit 5 that estimates a symbol timing from the received signal, and an oversampled signal using the timing estimated by the BTR unit 5 A timing extraction unit 6 that extracts a timing at which a transmission signal is modulated from a reception signal, a DSTBC decoding unit 7 that decodes differential encoding of DSTBC, and a determination unit 8 that determines a demodulation sequence from the modulation signal are provided.

  Next, the flow of processing from reception of a transmission signal to acquisition of a demodulated sequence in the receiving apparatus of FIG. 1 which is a DSTBC receiver will be described. In DSTBC, it is possible to use N symbols as one block, and any integer greater than or equal to 2 can be used for N. In the following description, N is 2. First, a DSTBC received signal obtained by the receiving antenna 1 is converted into a digital value by the A / D converter 2 to obtain an oversampled received signal. The received signal is converted into a baseband complex signal by the quadrature detector 3 and then input to the shaping filter. The shaping filter 4 blocks signals other than the desired band of the input signal.

  The BTR unit 5 corresponding to the timing reproduction device according to the present invention estimates the symbol timing using the K-overreceived received signal output from the shaping filter 4. The detailed configuration and operation of the BTR unit 5 will be described later. The estimation result of the symbol timing in the BTR unit 5 is output with a resolution of L times. The timing extraction unit 6 extracts a symbol timing reception signal from a reception signal (a signal output from the shaping filter 4) that has been oversampled K times in accordance with the symbol timing estimation result. Here, since L> K when the symbol timing is estimated with high accuracy, the timing extraction unit 6 takes out the received signal at the symbol timing after interpolating the sample points by the filter. For example, a cosine roll-off filter may be used as a filter for performing interpolation of sample points.

  The DSTBC decoding unit 7 decodes the differential encoding of the Nyquist rate reception signal extracted at the symbol timing, which is the signal output from the timing extraction unit 6, and decodes it. The determination unit 8 performs a hard decision or a soft decision on the modulation signal output from the DSTBC decoding unit 7 to obtain a demodulated sequence.

  Next, the BTR unit 5 that performs the timing reproduction of the symbol timing will be described in detail. FIG. 2 is a diagram illustrating a configuration example of the BTR unit 5. The BTR unit 5 includes square units 9 and 10 that calculate the squares of the I-phase component (in-phase component) and Q-phase component (orthogonal component) of the received signal, and values obtained by squaring the I-phase component and the Q-phase component. And an adder 11 that calculates the power value of the received signal, a 1-symbol delay unit 12 that performs a delay of one symbol length (K-sample delay), and the power of the sample delayed by one symbol for each sample An adder 13 that adds values, a sine wave generation unit 14 that generates a sine wave of a symbol rate, a 90 ° rotation unit 15 that converts the generated sine wave into a cosine wave, and a signal output from the adder 13 A multiplier 16 that multiplies the cosine wave output from the 90 ° rotation unit 15 and a multiplier 17 that multiplies the signal output from the adder 13 by the sine wave output from the sine wave generation unit 14; 1 symbol length for each symbol Output from the adders 18 and 19 that calculate the sum of the power values of the received signals, the averaging processors 20 and 21 that average the sum of the power values calculated for each symbol, and the average processor 20 The phase calculation unit 22 calculates a phase from the I phase component and the Q phase component output from the averaging processing unit 21. The sine wave generation unit 14, the 90 ° rotation unit 15, the multipliers 16 and 17, and the addition units 18 and 19 form a DFT processing unit 50.

  In the BTR unit 5 having such a configuration, a clock waveform is first generated from the filtered received signal (the signal output from the shaping filter 4).

  Specifically, the sum of the square values of the I-phase component and the Q-phase component is calculated by the processes of the square units 9 and 10 and the adder 11, and the power value of the received signal is obtained. Here, it is not essential to use the above-described method for obtaining the power value. For example, the power value may be obtained by squaring the amplitude value of the received signal before performing quadrature detection.

  When the power value of the received waveform is obtained, a clock waveform is generated according to the following procedure. When normal QPSK without DSTBC is used as a transmission signal, the power value of the modulation signal is constant, so the power value of the received waveform is determined by the periodic delta function of the symbol period and the tap coefficient of the shaping filter of the transmission / reception device. Determined by convolution of the squared filter, the power value is minimized at the symbol timing, and the power value is maximized at the middle of the symbol timing. Since the power value of the received waveform repeats the same value in the symbol period, it can be handled as a clock waveform at the symbol rate. On the other hand, when transmitting a QPSK modulated signal using DSTBC, the power value is not constant, and the generated clock waveform is distorted depending on the power value of the received signal. Therefore, in this embodiment, in order to suppress the distortion of the clock waveform, the sum of the power value of the sample and the power value of the sample in the past of one symbol is used for each sample using the one symbol delay unit 12 and the adder 13. Generate a clock waveform.

  For the operation of adding the power values of the samples delayed by one symbol, two series of reception signals filtered by the shaping filter 4 are prepared, one symbol delay is performed on one series, and the two series of power values are added. If the formulas are the same, the process of adding the power values for two symbols may be performed at an arbitrary position.

The effect obtained by calculating the sum of power values for two symbols will be described below. When performing differential encoding of DSTBC, first, information symbols s _2k-1 and s _2k to be transmitted are prepared for the k-th block. For example, a QPSK modulation signal is used as the information symbol. Assuming that the coded symbols obtained by performing differential coding of the k-th block are c _2k-1 and c _2k , c _2k-1 and c _2k are coded symbols c _{2 (k-1) −} of the k−1 block. ₁ and c2 _(k-1) are calculated according to the following equations (1) and (2) using _s2k-1 and _s2k .

In the formulas (1) and (2), ^* represents a complex conjugate. At this time, in the DSTBC, in order to prevent the divergence of the amplitude value due to the differential encoding, the encoded symbols c _2k−1 and c _{2k in} the k block need to satisfy the condition of the following expression (3).

When transmitting a DSTBC encoded symbol using two transmission antennas, the first transmission antenna is c _2K−1 , −c ^* _2k , and the second transmission antenna is c _2k , c ^* _2k−1. Transmit as the coded symbol of the block. When receiving with one receiving antenna, the received signals r _2k-1 and r _2k of the k-th block are the transmission path information between the first transmitting antenna and the receiving antenna, h ₁ , and the second transmitting antenna. When the transmission path information between the receiving antennas is h ₂ and the thermal noise added to the received signal of the k-th block is w ₁ and w ₂ , they are expressed by the following equations (4) and (5).

  When the sum of the power values of the received signal of the k-th block is calculated, it is expressed as the following equation (6).

  In Equation (6), w ′ represents a noise term. As can be seen from the equations (3) and (6), in the DSTBC, it is possible to normalize the power value by adding the power values of the two symbols constituting the block with respect to the received signal. When one block of DSTBC is used with two symbols, the power value normalization effect can be obtained for every two symbols by taking the sum of the sample power value and the power value of the past sample for each symbol. . FIG. 3 is a diagram in which a spectrum is displayed by DFT of the output waveform of the adder 11 before adding the power values of two symbols and the output waveform of the adder 13 after adding the power values of two symbols. . A portion where the normalized frequency of the spectrum is 0 is a signal component, and the other frequency components are noise components. If the signal component is larger than the sum of the noise components, the accuracy when extracting the phase component of the clock waveform is increased. As shown in FIG. 3, the spectrum of the waveform after adding the power values for two symbols has a smaller noise component than the spectrum of the waveform where the power values are not added, and constitutes a DSTBC block. The effect of normalizing the power of the symbol is obtained. When DSTBC is N symbols and one block, the sum of power values of N symbols constituting the block is normalized. Therefore, in a DSTBC receiver with one block of N symbols, N−1 1-symbol delay units 12 and adders 13 are prepared, and the power values of samples delayed by 1, 2,..., N symbols are added for each sample. With this configuration, the power value is normalized every N symbols.

  After generating the clock waveform by adding the power values of the samples for two symbols as described above, the BTR unit 5 extracts the phase component of the clock waveform by DFT.

  Specifically, first, the sine wave generation unit 14 generates a symbol rate sine wave having the same frequency as the clock waveform. Since the sine wave has the same value in the symbol period, the value may be stored in advance in a memory and read out. Since it is necessary to use a cosine wave and a sine wave for the DFT processing, the phase of the sine wave generated by the sine wave generation unit 14 is rotated by 90 ° by the 90 ° rotation unit 15 to convert the sine wave into a cosine wave. . The multiplier 16 multiplies the clock waveform output from the adder 13 and the cosine wave to obtain an I-phase component power value. On the other hand, the multiplier 17 multiplies the clock waveform and the sine wave to obtain the power value of the Q phase component. Here, the same effect can be obtained even if the processing for calculating the sum of the power values of two symbols for each sample performed by the one symbol delay unit 12 and the adder 13 is performed after the multipliers 16 and 17. .

  Adders 18 and 19 add the power values of K samples corresponding to the symbol length for the I-phase component and Q-phase component, respectively, and output the result. The adders 18 and 19 may calculate an output value for each sample and then extract a value for each K sample, or may calculate the output value for each K sample. Averaging processing units 20 and 21 output the symbol rate power values output from the adding units 18 and 19 respectively after the DFT processing on the clock waveform, in order to suppress variations due to fading, noise, etc. Averaging is performed for each phase component and Q-phase component. For the averaging, an FIR filter, an IIR filter or the like may be used. In addition, the averaging processing units 20 and 21 may integrate functions into the adding units 18 and 19. In the adding units 18 and 19, for example, if the sum of power values of M × K samples is calculated and output, M Symbols can be averaged.

  The phase calculation unit 22 calculates a phase (symbol timing) using the averaged I-phase component power value and Q-phase component power value output from each of the averaging processing units 20 and 21. When the phase calculation is performed with a resolution of L times the symbol rate, 360 ° is divided into L sections, and the index of the section corresponding to the calculated phase value is output. Regarding the phase, 0 ° is the symbol timing, and 360 ° is the next symbol timing.

  As described above, in the receiving apparatus of the present embodiment, the timing recovery apparatus (BTR unit 5) calculates and calculates the power value of each of N symbols forming a DSTBC coding unit (one block). The calculated power values are added, and the symbol timing is estimated using the addition result. For example, if one encoding unit (one block) is formed by two symbols, as shown in FIG. 2, a one-symbol delay unit 12 and an addition are added to the conventional multi-tank type timing recovery circuit. A device 13 may be added. According to the timing reproduction apparatus of the present embodiment, the accuracy of timing reproduction can be improved with almost no change in circuit scale.

Embodiment 2. FIG.
In the present embodiment, a timing reproducing apparatus having a configuration different from that of the first embodiment will be described. The overall configuration of the receiving apparatus is the same as that of the first embodiment (see FIG. 1). The timing reproduction device of the present embodiment is expressed as a timing reproduction device 5a. Since the configuration and operation other than the BTR unit 5a are the same as those in the first embodiment, the description of the common part is omitted, and the BTR unit 5a will be described below.

  FIG. 4 is a diagram illustrating a configuration example of the BTR unit 5a. The BTR unit 5a deletes the 1-symbol delay unit 12 and the adder 13 from the BTR unit 5 (FIG. 2) of the first embodiment, and between the adder unit 18 and the averaging processing unit 20, An adder 25 is added, and a 1-symbol delay unit 24 and an adder 26 are added between the adder 19 and the averaging processor 21.

  The 1-symbol delay units 23 and 24 add a delay corresponding to a 1-symbol length to the signal (power value) input from the previous addition unit 18 or 19 and output the result. The adders 25 and 26 add the power value directly input from the preceding adding unit 18 or 19 and the power value input via the 1 symbol delay unit 23 or 24.

  Details of the BTR unit 5a will be described below. Note that description of portions common to the BTR unit 5 is omitted.

  The multiplier 16 multiplies the power value output from the adder 11 by the cosine wave output from the 90 ° rotation unit 15 and outputs the result to the adder 18. On the other hand, the multiplier 17 multiplies the power value output from the adder 11 by the cosine wave output from the sine wave generation unit 14 and outputs the result to the adder 19. Adders 18 and 19 calculate the sum of power values of K samples corresponding to one symbol length, and complete the DFT processing.

  The 1-symbol delay unit 23 gives a delay of 1 symbol length to the clock waveform that is the output signal from the adder 18, and the adder 25 receives the clock waveform output from the adder 18 and the 1-symbol delay unit 23. Add the output clock waveforms (clock waveforms with delay). The 1-symbol delay unit 24 gives a delay of 1 symbol length to the clock waveform that is the output signal from the adder unit 19, and the adder 26 receives the clock waveform output from the adder unit 19 and the 1-symbol delay unit 23. Add the output clock waveforms (clock waveforms with delay). The averaging processing units 20 and 21 average the clock waveforms output from the adders 25 and 26, respectively.

  In the BTR unit 5 of the first embodiment, the power value delayed by one symbol is added before the DFT process. However, since the DFT is a linear process, the DTR process is performed after the DFT process as in the BTR unit 5a of the present embodiment. A configuration in which the same operation is performed can be employed, and the signal power value can be normalized when the DSTBC is used as in the first embodiment. Note that the power values of the averaging processing units 20 and 21 are averaged at the position (the position of the 1-symbol delay units 23 and 24 and the adders 25 and 26) where the sum of the power values of two symbols after DFT processing is calculated. In the case where a linear filter is used, the processing may be performed after the averaging processing units 20 and 21.

  As described above, the timing recovery apparatus (BTR unit 5a) of the present embodiment forms a DSTBC coding unit (one block) from a clock waveform signal obtained by DFT of the power value of the received signal. The symbol timing is estimated using the added N symbols. Thereby, the accuracy of timing generation can be improved as in the timing reproduction apparatus of the first embodiment. Compared to the timing recovery apparatus of the first embodiment that performs 1-symbol delay processing and addition processing on K times oversampled received signals before DFT processing, the same operation is performed by Nyquist rate after DFT processing. Since this is performed on the received signal, the calculation amount of circuit processing can be reduced.

Embodiment 3 FIG.
In the present embodiment, a timing recovery apparatus according to the present invention when antenna diversity is performed using a plurality of receiving antennas will be described. Note that although P antennas (P is an integer of 2 or more) can be used for antenna diversity, P is 2 in the following description. An example of the overall configuration of the receiving apparatus according to this embodiment is shown in FIG.

  As shown in the figure, the receiving apparatus includes receiving antennas 1 and 27 that receive a DSTBC transmission signal, A / D conversion units 2 and 28 that convert the received signal from an analog value to a digital value, and a high-frequency band signal as a base. Quadrature detection units 3 and 29 that perform quadrature conversion to band signals, shaping filters 4 and 30 that block signals other than the desired band, a BTR unit (multiple antennas) 31 that estimates symbol timing from a received signal, and a BTR unit ( Timing extraction units 6 and 32 that extract the timing at which the transmission signal is modulated from the reception signal oversampled using the timing estimated by the multiple antennas 31, the DSTBC decoding unit 7 that decodes the differential encoding of DSTBC, and 33 and a determination unit (multiple antennas) 34 for determining a demodulated sequence from the modulated signal.

  Next, the flow of processing from reception of a transmission signal to acquisition of a demodulated sequence in the receiving apparatus of FIG. 5 which is a DSTBC receiver will be described. Up to the shaping filters 4 and 30, the received signals received by the two receiving antennas are processed in the same manner as the receiving apparatus of FIG. 1 used in the first and second embodiments, and the received signals are oversampled by K times. Get. The BTR unit (multiple antennas) 31 estimates symbol timing using two received signals. The detailed configuration and operation of the BTR unit (multiple antennas) 31 will be described later. A symbol timing estimation result is output from the BTR unit (multiple antennas) 31 with a resolution L times as with the BTR unit 5 of the receiving apparatus of FIG. The timing extraction units 6 and 32 extract a symbol timing reception signal from the reception signal oversampled K times based on the output result of the BTR unit (multiple antennas) 31. The DSTBC decoding units 7 and 32 decode the Nyquist rate received signal by performing differential encoding. The decision unit (multiple antennas) 34 performs diversity combining on two received signals to obtain one received signal, and then performs hard decision or soft decision to obtain a demodulated sequence. For diversity combining, any of selective combining, equal gain combining, and maximum ratio combining may be used. Diversity combining may be performed before DSTBC decoding.

  Next, the BTR unit (multiple antennas) 31 that performs symbol timing timing reproduction will be described in detail. FIG. 6 is a diagram illustrating a configuration example of the BTR unit (multiple antennas) 31. The BTR unit (multiple antennas) 31 includes square units 9, 10, 35, and 36 that calculate the squares of the I-phase component (in-phase component) and Q-phase component (orthogonal component) of the received signal, Adders 11 and 37 that calculate the power value of the received signal by taking the sum of values obtained by squaring the Q-phase component, and 1-symbol delay units 12 and 38 that perform a delay of one symbol length (K-sample delay) Adders 13 and 39 for adding the power values of samples delayed by one symbol for each sample, sine wave generators 14 and 40 for generating a sine wave at a symbol rate, and converting the generated sine wave into a cosine wave 90 ° rotators 15 and 41, multipliers 16 and 42 for multiplying signals output from adders 13 and 39 by cosine waves output from 90 ° rotators 15 and 41, adders 13 and 39 out Multipliers 17 and 43 for multiplying the received signal by the sine wave output from the sine wave generators 14 and 40, and addition for calculating the sum of the power values of the received signal for one symbol length for each symbol Units 18, 19, 44, 45, an adder 46 that sums the outputs of the adder 18 and the adder 44, an adder 47 that sums the outputs of the adder 19 and the adder 45, and for each symbol. The phase is calculated from the averaging processing units 20 and 21 that average the sum of the calculated power values, the I-phase component output from the averaging processing unit 20, and the Q-phase component output from the averaging processing unit 21. And a phase calculation unit 22. The sine wave generation unit 14, the 90 ° rotation unit 15, the multipliers 16 and 17, and the addition units 18 and 19 include the DFT processing unit 50, the sine wave generation unit 40, the 90 ° rotation unit 41, the multipliers 42 and 43, and the addition unit. 44 and 45 form a DFT processing unit 60.

  The operation of the BTR unit (multiple antennas) 31 will be described below. Performing the DFT processing on the clock waveform in the processing up to the adders 18, 19, 44, and 45 provides the same processing as that of the BTR unit 5 (see FIG. 1) of the first embodiment with two receiving antennas. Since this means that it is performed for each received signal, the description is omitted. The adder 46 and the adder 47 perform diversity combining by taking the sum of the outputs of the DFT processing for the respective clock waveforms obtained from the two received signals. The adders 46 and 47 may be configured to select one received signal. Further, the position where the processing of the adders 46 and 47 is performed may be anywhere after the adders 11 and 37 and before the averaging processing units 20 and 21, and the same result can be obtained mathematically. The processing of the averaging processing units 20 and 21 and the phase calculation unit 22 is the same as that of the BTR unit 5 of the first embodiment, in order to suppress the influence of fading and noise on the power values output from the adders 46 and 47. After averaging each of the I-phase and Q-phase components, the phase (symbol timing) is calculated.

  As described above, the timing recovery apparatus (BTR unit (multiple antennas) 31) of the present embodiment converts a clock waveform signal obtained by DFT of the power value of a received signal into a DSTBC coding unit (1 block). ) To form the symbol timing using the addition result. In this embodiment, the above addition result is generated for each of P received signals obtained by P receiving antennas, and diversity combining is performed using all the addition results. Thereby, it is possible to improve the accuracy of timing generation when performing antenna diversity using a plurality of receiving antennas.

Embodiment 4 FIG.
In the present embodiment, a timing reproducing apparatus having a configuration different from that of the third embodiment will be described. The overall configuration of the receiving apparatus is the same as that in Embodiment 3 (see FIG. 5). The timing reproducing device of the present embodiment is expressed as a timing reproducing device 31a. Since the configuration and operation other than the BTR section (multiple antennas) 31a are the same as those in the third embodiment, the description of the common parts is omitted, and the BTR section (multiple antennas) 31a will be described below.

  FIG. 7 is a diagram illustrating a configuration example of the BTR unit (multiple antennas) 31a. The BTR unit 31a includes the 1-symbol delay unit 38, the adder 39, the elements constituting the DFT processing unit 60, and the adders 46 and 47 from the BTR unit (multiple antennas) 31 (FIG. 6) of the third embodiment. While being deleted, an adder 48 for adding the outputs of the adder 11 and the adder 37 is added.

  Details of the BTR unit (multiple antennas) 31a will be described below. Note that description of portions common to the BTR unit (multiple antennas) 31 is omitted.

  The power values of the two received signals obtained by the two receiving antennas by the adders 11 and 37 are summed by the adder 48, and diversity combining is performed.

  In the BTR unit (multiple antennas) 31 of Embodiment 3, diversity combining performed on the power values of two received signals is performed after the DFT processing. However, the processing of adding the DFT and the power values for two symbols is linear processing. Therefore, it is possible to adopt a configuration in which a similar operation is performed before the process of adding the DFT and the power values for two symbols, as in the BTR unit (multiple antennas) 31a of the present embodiment.

  As described above, the timing recovery apparatus (BTR unit (multiple antennas) 31a) of the present embodiment converts the clock waveform signal obtained by DFT of the power value of the received signal into a DSTBC coding unit (1 block). Are added over N symbols, and the addition result is used to estimate the symbol timing. Also, in this embodiment, diversity combining is performed by calculating the power value for each of P received signals obtained by P receiving antennas and then summing the power values using all received signals. Thereby, it is possible to improve the accuracy of timing generation when performing antenna diversity using a plurality of receiving antennas. Compared to the timing recovery apparatus of the third embodiment that performs diversity combining after DFT processing, the same operation may be performed by performing diversity combining before DFT processing, so that only one DFT processing circuit is provided. There is an effect that the scale can be reduced.

  As described above, the present invention is useful as a timing reproduction device that estimates the symbol timing of a received signal in a receiving device (receiving-side communication device) of a wireless communication system.

1,27 antenna, 2,28 A / D conversion unit, 3,29 quadrature detection unit, 4,30 shaping filter, 5 BTR unit, 6,32 timing extraction unit, 7,33 DSTBC decoding unit, 8 determination unit, 9 , 10, 35, 36 square part, 11, 13, 25, 26, 37, 39, 46, 47, 48 adder, 12, 23, 24, 38 1 symbol delay part, 14, 40 sine wave generation part, 15, 41 90 ° rotation unit, 16, 17, 42, 43 multiplier, 18, 19, 44, 45 addition unit, 20, 21 averaging processing unit, 22 phase calculation unit, 31 BTR unit (multiple antennas), 34 Determination unit (multiple antennas), 50, 60 DFT processing unit.

Claims (8)

A timing reproduction device that reproduces symbol timing in a reception device that receives a signal that is DSTBC-coded in units of N symbols (N is an integer of 2 or more) as one block,
Power calculating means for calculating the power value of each sample value obtained by oversampling the received signal K times;
Adding means for adding the power values over N symbols;
And timing estimation means for extracting a frequency component of the Nyquist rate, estimates the symbol timing based on the frequency components the extracted for each in-phase and quadrature components running DFT for the addition result by the adding means,
A timing reproduction apparatus comprising:   When the receiving apparatus has P receiving antennas (P is an integer of 2 or more), the power value is calculated for the received signals obtained by the respective receiving antennas, and the power value of each received signal is added or selected. The timing reproduction apparatus according to claim 1, wherein the symbol timing is estimated later.   3. The timing recovery apparatus according to claim 1, wherein the adding means adds the power value every K samples when adding the power value over N symbols. A timing reproduction device that reproduces symbol timing in a reception device that receives a signal that is DSTBC-coded in units of N symbols (N is an integer of 2 or more) as one block,
Power calculating means for calculating the power value of each sample value obtained by oversampling the received signal K times;
Frequency component extraction means for performing DFT on the power value to extract Nyquist rate frequency components for each of the in-phase and quadrature components;
Adding means for adding the frequency components over N symbols;
Timing estimation means for estimating a symbol timing based on the addition result of the frequency components by the addition means;
A timing reproduction apparatus comprising: When the receiving apparatus has P receiving antennas (P is an integer of 2 or more), the power value is calculated for the received signals obtained by the respective receiving antennas, and the power value of each received signal is added or selected. 5. The timing reproduction apparatus according to claim 4 , wherein the symbol timing is estimated later. The said power calculation means calculates the square value of each of an in-phase component and a quadrature component, and also adds the square value of each component, and obtains the said power value, The one of Claims 1-5 characterized by the above-mentioned. The timing reproduction apparatus according to one. A timing reproduction method for reproducing symbol timing in a receiving apparatus that receives a signal that is DSTBC-encoded in units of N symbols (N is an integer of 2 or more) as one block,
A power calculation step of calculating a power value of each sample value obtained by oversampling the received signal by K times;
An adding step of adding the power values over N symbols;
And timing estimation step of extracting frequency components of the Nyquist rate, estimates the symbol timing based on the frequency components the extracted for each in-phase and quadrature components running DFT for the addition result of the adding step,
Including a timing reproduction method. A timing reproduction method for reproducing symbol timing in a receiving apparatus that receives a signal that is DSTBC-encoded in units of N symbols (N is an integer of 2 or more) as one block,
A power calculation step of calculating a power value of each sample value obtained by oversampling the received signal by K times;
A frequency component extracting step of performing DFT on the power value to extract a Nyquist rate frequency component for each of the in-phase component and the quadrature component;
An adding step of adding the frequency components over N symbols;
A timing estimation step for estimating a symbol timing based on the addition result of the frequency components in the addition step;
Including a timing reproduction method.

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