JP6056072B2 - Display device - Google Patents

Description

  The present invention relates to a display device and, more particularly, to an active matrix display device.

  An active matrix display device (display panel) such as a liquid crystal display device or an organic EL (electroluminescence) display device has a display region in which a plurality of pixels are arranged in a matrix in the row direction and the column direction. Each pixel includes a driving circuit including a switching element, a driving element, and a capacitor element including a thin film transistor (TFT), and a display element such as a liquid crystal element and an organic EL element.

  In an active matrix organic EL display device, in general, for each pixel row composed of a plurality of pixels in the same row, a power supply wiring for supplying a power supply voltage to each pixel included in the pixel row is provided. . The power supply wiring is disposed, for example, between a pixel row that supplies a voltage and a pixel row adjacent to the pixel row.

  2. Description of the Related Art In recent years, a configuration in which auxiliary wiring (auxiliary electrode) is provided in order to prevent a voltage drop at a central portion in a display panel surface is known as the display panel becomes larger. The auxiliary wiring is provided for each pixel row, for example, and is arranged so as to overlap the above-described power supply wiring in the stacking direction between a pixel row for supplying a voltage and a pixel row adjacent to the pixel row.

  In the case of a display device in which two wirings are arranged in the stacking direction as described above, if a conductive foreign matter is mixed in the manufacturing process, the two wirings may be short-circuited by the foreign matter. Therefore, conventionally, a technique for preventing such a short circuit between wirings due to foreign substances has been proposed (see Patent Document 1).

  FIG. 7 is a layout diagram showing a configuration of a conventional display device described in Patent Document 1. In FIG.

  As shown in FIG. 7, in the conventional display device 1000, the auxiliary wiring 1054 is shifted so as to detour to the pixel side at a position where the power supply wiring 1051 and the auxiliary wiring 1054 overlap in the stacking direction.

JP 2009-128374 A

  However, in the conventional display device 1000 shown in FIG. 7, since the auxiliary wiring 1054 is shifted in the horizontal direction, the area of the detour portion of the auxiliary wiring 1054, that is, the pixel capacity of each pixel (capacitance of the capacitor 1033 constituting the pixel). Get smaller. When the pixel capacity is reduced, there is a problem that pixel characteristics such as peak luminance and uniformity of in-plane luminance are deteriorated.

  In particular, when the display panel is enlarged, the width of the auxiliary wiring may be increased. In this case, if the auxiliary wiring is detoured, the reduction rate of the pixel capacity increases, and the above problem becomes more remarkable.

  The present invention has been made to solve the above problem, and an object of the present invention is to provide a display device capable of suppressing a decrease in yield due to a short circuit between wirings without reducing a pixel capacity.

  In order to achieve the above object, one embodiment of a display device according to the present invention is a display device including a display region in which a plurality of pixels are arranged in a matrix, and includes a first wiring and a second wiring. Including a lower wiring layer, an interlayer insulating layer (planarization layer) provided above the lower wiring layer, and an upper wiring provided above the interlayer insulating layer and including a third wiring and a fourth wiring Each of the first wiring and the third wiring includes a plurality of pixel lines configured by pixels arranged in the same row or the same column in the display region. Are arranged along the pixel line rows belonging to the first group, and are arranged at positions overlapping in the stacking direction via the interlayer insulating layer, and the second wiring and the fourth wiring Respectively, before In the display area, among the plurality of pixel lines, arranged along the pixel line rows belonging to the second group excluding the pixel line rows belonging to the first group from the rows constituting the matrix, The first wiring and the third wiring are set at a first potential, and the first potential is applied to the plurality of pixels. And the second wiring and the fourth wiring are set to a second potential different from the first potential, and the second potential is applied to the plurality of pixels. Configured to supply.

  According to the present invention, it is possible to obtain a display device that can suppress a decrease in yield due to a short circuit between wirings without reducing a pixel capacitance.

FIG. 1 is a partially cutaway perspective view showing one configuration example of a display panel constituting a display device according to the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of sub-pixels constituting the pixels of the display panel. FIG. 3A is a layout diagram illustrating a configuration example of the display device in the first embodiment. FIG. 3B is a cross-sectional view showing the configuration of the AA ′ cross section of FIG. 3A. FIG. 3C is a cross-sectional view showing the configuration of the BB ′ cross section of FIG. 3A. FIG. 4A is a layout diagram illustrating a configuration example of a display device in Embodiment 2. FIG. 4B is a cross-sectional view showing the configuration of the AA ′ cross section of FIG. 4A. FIG. 5A is a layout diagram illustrating a configuration example of the display device in Embodiment 3. FIG. 5B is a cross-sectional view showing the configuration of the AA ′ cross-section of FIG. 5A. FIG. 6A is a layout diagram illustrating a configuration example of a display device in Embodiment 4. FIG. 6B is a cross-sectional view showing the configuration of the AA ′ cross section of FIG. 6A. FIG. 7 is a layout diagram showing one configuration example of an active matrix substrate constituting a conventional display panel. FIG. 8A is a cross-sectional view showing a configuration example of a conventional display panel. FIG. 8B is a cross-sectional view illustrating a configuration example of a conventional display panel. FIG. 9 is a layout diagram showing a configuration example of an active matrix substrate constituting a conventional display panel.

  Prior to the description of the embodiments of the present invention, problems to be solved by the present invention will be described more specifically.

  Here, a specific example in the case where a short due to the foreign matter 60 occurs will be described with reference to FIGS. 8A and 8B. 8A and 8B are cross-sectional views of an organic EL display panel which is an example of a display device.

  As shown in FIGS. 8A and 8B, the organic EL display panel includes, for example, an organic EL element that is a self-luminous display element, an active matrix substrate on which a thin film transistor and various wirings are formed (a thin film semiconductor array device for a display device). ).

  As shown in FIGS. 8A and 8B, the active matrix substrate includes a semiconductor layer 101, a gate insulating layer 102, a GM layer 103 (gate electrode), a passivation layer 104, an SD metal layer 105 (source electrode, drain) on the substrate 100. Electrode) and the planarizing layer 106 are laminated. The active matrix substrate includes a pixel portion in which a plurality of pixels are arranged in a matrix (matrix shape), a plurality of gate wirings extending in the row direction, a plurality of source wirings extending in the column direction, and a column direction. And a plurality of power supply wirings.

  As shown in FIGS. 8A and 8B, the organic EL element has an AM layer 111 (anode electrode, auxiliary electrode) and an EL layer 112 including a light emitting layer (blue EL layer 112B and red EL layer 112R) on an active matrix substrate. The transparent electrode layer 113 (cathode electrode) and the sealing material layer 114 are laminated. Although not shown, the EL layer 112 is formed by stacking a hole transport layer, a light emitting layer, an electron transport layer, and the like, and is formed separately for each sub-pixel described later by the bank 115.

  A counter glass substrate 50 on which a color filter (not shown) is formed is attached on the organic EL element.

  Each pixel corresponds to one of the three primary colors RGB. The pixel includes a pixel circuit composed of a thin film transistor or the like and an organic EL element corresponding to the pixel circuit. 8A and 8B show two pixels, a blue display pixel PB and a red display pixel PR. The three pixels of the blue display pixel PB, the red display pixel PR, and the green display pixel (not shown) constitute one pixel.

  In the organic EL display panel configured as described above, as shown in FIGS. 8A and 8B, the power supply wiring PL and the source wiring SL are formed in the SD metal layer 105, and the auxiliary wiring AL is formed in the AM layer 111. ing. For this reason, the power supply wiring PL and the auxiliary wiring AL are arranged so as to overlap in the stacking direction. For example, when the organic EL display panel is viewed in plan, the power supply wiring PL and the auxiliary wiring AL are arranged so as to overlap as shown in FIG. FIG. 9 is a layout diagram illustrating an example of an organic EL display panel.

  In such a display panel in which two wirings are arranged in the stacking direction, if conductive foreign matter is mixed during the manufacturing process, the two wires may be short-circuited by the foreign matter. For example, in the step of forming the planarization film, if conductive foreign matter enters the planarization film, two wirings arranged so as to overlap in the stacking direction may be short-circuited. In addition, in the process of attaching a counter glass substrate to an active matrix substrate on which an organic EL element or the like is formed, if conductive foreign matter enters between the active matrix substrate and the counter glass substrate, the foreign matter is pushed into the active matrix substrate side. In some cases, two wirings arranged so as to overlap in the stacking direction are short-circuited.

  FIG. 8A shows a case where conductive foreign matter 60 is mixed during the formation of the planarizing layer 106. In FIG. 8B, after forming the sealing material layer 114, conductive foreign matter 60 is mixed between the sealing material layer 114 and the counter glass substrate 50, and the conductive glass 60 is bonded when the counter glass substrate 50 is attached. The case where the foreign material 60 is pushed into the active matrix substrate is shown. As shown in FIGS. 8A and 8B, in both cases, the auxiliary wiring AL and the power supply wiring PL having different potentials are short-circuited.

  As described above, when a wiring having a different potential from the wiring formed in the AM layer 111 is formed in the SD metal layer 105, a short circuit may occur due to the mixing of the conductive foreign matter 60. In other words, there is a possibility that a short circuit occurs due to the conductive foreign material 60 between two layers formed adjacent to the planarization layer 106. That is, although not shown in FIGS. 8A and 8B, in the region where the SD metal layer 105 is not formed between the planarization layer 106 and the GM layer 103, there is a conductive foreign matter between the AM layer 111 and the GM layer 103. There is a possibility that a short circuit occurs due to mixing of 60. When a short circuit between the wirings occurs due to the mixing of the conductive foreign matter 60, there arises a problem that the organic EL element does not emit light.

  A display device according to one embodiment of the present invention is a display device having a display region in which a plurality of pixels are arranged in a matrix, a first wiring, a lower wiring layer including a second wiring, and the lower part An interlayer insulating layer (planarization layer) provided above the wiring layer; and an upper wiring layer provided above the interlayer insulating layer and including a third wiring and a fourth wiring; One wiring and the third wiring are respectively a plurality of pixel lines composed of pixels arranged in the same row or the same column in the display region. Arranged along the pixel line row belonging to the group, and arranged in a position overlapping in the stacking direction via the interlayer insulating layer, and the second wiring and the fourth wiring are respectively in the display region. In the above Among the plurality of pixel lines, the pixel lines are arranged along the pixel line rows belonging to the second group excluding the pixel line rows belonging to the first group from the rows constituting the matrix, and the interlayer insulating layer is interposed therebetween. And the first wiring and the third wiring are set to a first potential and configured to supply the first potential to the plurality of pixels. And the second wiring and the fourth wiring are set to a second potential different from the first potential, and the second potential is supplied to the plurality of pixels. Is done.

  According to the display device having the above configuration, the first wiring and the third wiring having the same potential are arranged so as to overlap each other in the stacking direction. Even in this case, the wirings having the same potential are short-circuited, so that it does not become defective. Similarly, according to the display device having the above configuration, since the second wiring and the fourth wiring having the same potential are arranged so as to overlap in the stacking direction, foreign matter is mixed and the second wiring and the fourth wiring are mixed. Even if the wiring is short-circuited, the wirings having the same potential are short-circuited, so that it does not become a defect.

  In other words, because the auxiliary wirings are arranged so that they overlap each other in the stacking direction and the power supply wirings overlap each other in the stacking direction, even if a short circuit occurs due to the mixing of foreign matter, it does not become a defect and the yield Reduction can be suppressed.

  For example, the pixel line belonging to the first group is one of an odd-numbered pixel line and an even-numbered pixel line among the plurality of pixel lines, and the pixel line belonging to the second group May be the other of the pixel lines of the odd lines and the pixel lines of the even lines.

  In addition, for example, the first wiring and the third wiring are electrically connected via a contact hole provided in the interlayer insulating layer, and the second wiring and the fourth wiring are These may be electrically connected through contact holes provided in the interlayer insulating layer.

  Further, for example, the plurality of pixels are formed in an organic light emitting element including an organic light emitting layer having an organic material sandwiched between two electrodes, and a layer positioned on the substrate side from a layer constituting the organic light emitting element, A driving circuit layer in which a driving transistor for current driving the organic light emitting element is formed, and a source / drain electrode of the driving transistor is connected to the first wiring and the third wiring, and the organic light emitting One of the two electrodes of the element may be connected to the second wiring and the fourth wiring.

  In addition, for example, the first wiring and the third wiring are power supply wirings that supply power of the first potential to the pixels constituting the pixel lines belonging to the first group, and the second wiring The fourth wiring and the fourth wiring may be power wirings that supply power of the second potential to the pixels constituting the pixel lines belonging to the second group.

  According to the display device having the above-described configuration, it is possible to reduce a short circuit caused by foreign matter between the power supply wires. In addition, if the short circuit between the normal wirings, there is a high possibility that only the pixel related to the location where the failure occurred does not emit light, and the location where the short occurs may be identified. Can handle shorts. However, in the case of a short circuit due to foreign matter between the power supply wirings, since all the pixels constituting the display panel do not emit light, the location where the short circuit occurs cannot be specified, and the short circuit cannot be dealt with. Therefore, the display device having the above configuration can reduce short-circuit due to foreign matter between the power supply wirings, and thus can more effectively suppress a decrease in yield.

  Further, for example, the lower wiring layer is formed in the same layer as a gate electrode layer where a gate electrode of the driving transistor is formed or a source / drain layer where a source / drain electrode of the driving transistor is formed, The upper wiring layer may be formed in the same layer as the layer on which the electrode of the organic light emitting element located on the substrate side is formed.

  Further, for example, the first potential is a high potential side potential applied to a pixel circuit configured to include the driving circuit formed for each pixel, and the second potential is the pixel circuit. It may be a potential on the low potential side applied to.

  Hereinafter, embodiments of a display device according to the present invention will be described with reference to the drawings. Each figure is a schematic diagram for explanation, and the film thickness, the ratio of the sizes of the respective parts, and the like are not necessarily expressed strictly. Moreover, in each figure, the same code | symbol is attached | subjected about the substantially same component.

  Furthermore, in the following embodiments and drawings, the row direction and the column direction are directions set for explanation, and can be arbitrarily set in two different directions. In the following description, the row direction and the column direction are described as an example where they are orthogonal to each other, but they are not necessarily orthogonal.

  Each of the embodiments described below shows a desirable specific example of the present invention. Constituent elements, arrangement positions and connection forms of constituent elements, processing, processing order, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements that constitute a more desirable form.

(Embodiment 1)
First, the display device according to Embodiment 1 of the present invention will be described with reference to FIGS. Note that the display device (display panel) according to this embodiment is an active matrix organic EL display device (organic EL display panel), and includes a plurality of pixels arranged in a matrix in the row direction and the column direction. Part (display area).

[1. Display panel configuration]
The structure of the display panel 1 in this Embodiment is demonstrated based on FIG. FIG. 1 is a partially cutaway perspective view showing a configuration example of a display panel 1 according to the present embodiment.

  As shown in FIG. 1, a display panel 1 includes an active matrix substrate (a thin film semiconductor array device for a display device) on which an organic EL element 10 which is a self-luminous display element and a pixel circuit 30 including a thin film transistor and various wirings are formed. ) 20.

  The organic EL element 10 includes a lower electrode layer 12 (anode), an organic light emitting layer 13 (EL layer), and an upper electrode layer 14 (cathode), and is formed on the active matrix substrate 20 in this order. Yes. Although not shown, the lower electrode layer 12 and the organic light emitting layer 13 are configured by stacking a hole transport layer, a light emitting layer, an electron transport layer, and the like, and are separated for each sub-pixel described later by a bank 115 (not shown). Is formed.

  The active matrix substrate 20 includes a pixel portion in which a plurality of pixels P are arranged in a matrix (matrix shape), a plurality of gate lines GL extending in the pixel row direction, and a plurality of source lines SL extending in the pixel column direction. It has. The plurality of source lines SL and the plurality of gate lines GL are configured to be orthogonal to each other.

  Each pixel P includes a pixel circuit 30 made of a thin film transistor and the like, and an organic EL element 10 corresponding to the pixel circuit 30. In the present embodiment, each pixel P corresponds to the three primary colors RGB. In the present embodiment, one pixel PG is constituted by three pixels P of RGB. The pixels P of the same color are arranged adjacent to each other in the row direction.

  Each of the plurality of gate lines GL is provided for each pixel row composed of a plurality of pixels P in the same row. All the pixels P belonging to the pixel row corresponding to each gate line GL are connected to the control circuit (scanning line driving circuit) by the gate line GL.

  Each of the plurality of source lines SL is provided for each pixel column composed of a plurality of pixels P in the same column. All the pixels P belonging to the pixel column corresponding to each source line SL are connected to the control circuit (data line driving circuit) by the source line SL.

  Thus, the display panel 1 according to the present embodiment employs an active matrix system that performs display control for each pixel P partitioned by the gate line GL and the source line SL.

  Although not shown in FIG. 1, the display panel 1 according to the present embodiment includes a plurality of power supply lines PL extending in the pixel row direction and auxiliary lines AL extending in the pixel row direction.

[2. Sub-pixel circuit configuration]
Next, the circuit configuration of each pixel P will be described with reference to FIG. FIG. 2 is a circuit diagram illustrating a circuit configuration example of the pixel P in the display device according to the present embodiment.

  As shown in FIG. 2, the pixel P includes a pixel circuit 30 including a first thin film transistor 31 that is a p-channel TFT, a second thin film transistor 32 that is a p-channel TFT, and a capacitor 33, and the organic EL element 10. With.

  The first thin film transistor 31 is a switching transistor that selectively switches the organic EL element 10 to be driven (writes a video signal voltage), and selects a pixel P that emits light (writes a video signal voltage) from a plurality of pixels P. . The first thin film transistor 31 has a drain electrode connected to one end of the capacitor 33 and the gate electrode of the second thin film transistor, a source electrode connected to the source line SL, and a gate electrode connected to the gate line GL.

  The second thin film transistor 32 is a drive transistor for driving the organic EL element 10. The second thin film transistor 32 has a drain electrode on the anode (anode) of the organic EL element 10, a source electrode on the other end of the capacitor 33 and the power supply line PL, and a gate electrode on the drain electrode of the first thin film transistor 31 and one end of the capacitor 33. , Each connected.

  The capacitor 33 has one end connected to the drain electrode of the first thin film transistor 31 and the gate electrode of the second thin film transistor 32, and the other end connected to the source electrode of the second thin film transistor 32 and the power supply line PL.

  The organic EL element 10 has an anode connected to the drain electrode of the second thin film transistor 32 and a cathode connected to the auxiliary wiring AL via a transparent electrode.

  In the pixel P configured as described above, when a gate signal is input to the gate line GL and the first thin film transistor 31 is turned on, the video signal voltage supplied via the source line SL is written into the capacitor 33. The video signal voltage written in the capacitor 33 is held throughout one frame period. Due to the held video signal voltage, the conductance of the second thin film transistor 32 changes in an analog manner, and a drive current corresponding to the light emission gradation flows from the anode to the cathode of the organic EL element 10 so that the organic EL element 10 emits light. To do. Thereby, a predetermined image can be displayed.

[3. Configuration of power supply wiring and auxiliary wiring]
Next, the layout configuration of the display device according to this embodiment will be described with reference to FIGS. 3A and 3B.

FIG. 3A is a diagram showing a layout configuration of the display device in the present embodiment, and shows a configuration when viewed from the side to which the counter glass substrate 50 is attached. 3B is a cross-sectional view showing a cross section of the display device corresponding to the line AA ′ in FIG. 3A, and FIG. 3C is a cross-sectional view showing a cross section of the display device corresponding to the line BB ′ in FIG. 3A. In FIG. 3A, for the sake of explanation, six pixels P _ij to pixels P _{(i + 1) (j + 1)} are illustrated.

  As shown in FIGS. 3B and 3C, the display device in this embodiment includes a substrate 100, a semiconductor layer 101 (not shown in FIGS. 3B and 3C), and a gate insulating layer 102, which are sequentially stacked from the substrate 100 side. , GM layer 103 (gate electrode, gate wiring), passivation layer 104, SD metal layer 105 (source electrode, drain electrode, source wiring, power supply wiring), planarization layer 106, AM layers 111A, 111P (anode, auxiliary wiring) And a laminated structure composed of an EL layer 112 (not shown in FIGS. 3B and 3C), a transparent electrode layer 113 (cathode) and a sealing material layer 114, and a counter glass substrate 50 bonded to the laminated structure. In this embodiment, the display device is described as an example of a top emission type, but may be a bottom emission type.

  An EL layer 112 (not shown) that is a light emitting unit is surrounded by a bank 115. The bank 115 has an opening for separating and partitioning the EL layer 112 for each pixel P. The bank 115 includes a convex portion extending between adjacent pixels P in a direction parallel to the source line SL. In other words, the lower electrode layer 12 (anode) and the organic light emitting layer 13 of each pixel P shown in FIG. 1 are formed between the adjacent protrusions (that is, the opening of the bank 115).

In FIG. 3A to FIG. 3C, six pixels P _ij to pixels P _{(i + 1) (j + 1)} , source lines SL _j and SL _{(j + 1)} , and power supply lines PL _{i to} PL _{(i + 3)} are shown as components of the display device. Auxiliary wirings AL _i and AL _{(i + 1)} are illustrated.

The six pixels P _ij to P _{(i + 1) (j + 1)} are arranged in a matrix (in a matrix) on a plane parallel to the active matrix substrate, and are formed in the semiconductor layer 101 to the SD metal layer 105 and the like. .

In FIG. 3A, the pixels P _ij to P _{(i + 1) (j + 1)} are respectively arranged in a portion indicated by a rectangular broken line, the first thin film transistor 31 on the upper left side of the drawing, and the second thin film transistor 32 on the upper right side of the drawing. However, the capacitor 33 is disposed so as to partially overlap the second thin film transistor 32 in the stacking direction. Further, the drain terminals of the second thin film transistors 32 of the pixel P _ij and the pixel P _{(i + 1) j} are connected to the connection wiring 40 connected to the power supply wiring.

The source lines SL _j and SL _{(j + 1)} are formed in the SD metal layer 105 so as to extend in the column direction on a plane parallel to the active matrix substrate. The source line SL _j is connected to the first thin film transistor 31 on the left side of the pixels P _ij , P _{(i + 1) j} , P _{(i + 2) j in} the drawing (so as to overlap in the stacking direction), and the pixels P _ij , P It is formed through the formation region of _{(i + 1) j} , P _{(i + 2) j} .

As shown in FIGS. 3A to 3C, the power supply lines PL _i and PL _{(i + 1)} are arranged along the pixel row including the pixel P _ij and the pixel row including the pixel P _{(i + 1) j} in the present embodiment. Has been. The power supply wiring PL _i is formed in the GM layer 103P (GM layer 103), and the power supply wiring PL _{(i + 1)} is formed in the AM layer 111P (AM layer 111) and is arranged so as to overlap in the stacking direction. . Note that the power supply wiring PL _i and the power supply wiring PL _{(i + 1)} may be arranged so as to overlap the pixel rows to be supplied with power as shown in FIG. 3A, or may be arranged between the pixel rows.

Similarly, as shown in FIGS. 3A to 3C, the power supply wirings PL _{(i + 2)} and PL _{(i + 3)} are arranged along the pixel row including the pixel P _{(i + 2) j} in the present embodiment. The power supply wiring PL _{(i + 2)} is formed in the GM layer 103P (GM layer 103), and the power supply wiring PL _{(i + 3)} is formed in the AM layer 111P (AM layer 111), and is arranged so as to overlap in the stacking direction. . Note that the power supply wiring PL _{(i + 2)} and the power supply wiring PL _{(i + 3)} may be arranged so as to overlap the pixel rows to be supplied with power as shown in FIG. 3A, or may be arranged between the pixel rows. Good.

As shown in FIGS. 3A to 3C, the auxiliary wirings AL _i and AL _{(i + 1)} are arranged in a pixel row including the pixel P _{(i + 1) j} and a pixel row including the pixel P _{(i + 2) j} in the present embodiment. Are arranged along. The auxiliary wiring AL _{(i + 1)} is formed in the GM layer 103A (GM layer 103), and the auxiliary wiring AL _i is formed in the AM layer 111A (AM layer 111), and is arranged so as to overlap in the stacking direction. As shown in FIG. 3A, the auxiliary wiring AL _{(i + 1)} and the auxiliary wiring AL _i may be arranged so as to overlap with the pixel row to be supplied with power, or may be arranged between the pixel rows.

[4. Comparison etc.]
Here, in the display device in the conventional comparative example shown in FIGS. 8A and 8B, the power supply wiring PL _i is formed in the GM layer 103 between the pixel P _ij and the pixel P _{(i + 1) j} , and the auxiliary wiring AL _i is formed on the AM layer 111. Therefore, the power supply wiring PL _i and the auxiliary wiring AL _i are arranged so as to overlap in the stacking direction. In such a display panel in which two wirings are arranged in the stacking direction, a short circuit between wirings may occur due to the mixing of the conductive foreign matter 60 during the manufacturing process.

On the other hand, in the present embodiment, as shown in FIGS. 3B and 3C, in the cross section along the line AA ′, the power supply line PL _i is arranged in the GM layer 103 and the power supply line PL _{(i + 1)} is arranged in the AM layer 111P. Yes. In the cross section taken along line BB ′, the auxiliary wiring AL _{(i + 1)} is arranged in the GM layer 103 and the auxiliary wiring AL _i is arranged in the AM layer 111A. Therefore, the power supply wiring PL _{(i + 1)} and the power supply wiring PL _i are arranged in the stacking direction, and the auxiliary wiring AL _{(i + 1)} and the auxiliary wiring AL _i are arranged in the stacking direction. That is, the wiring formed in the GM layer 103P and the wiring formed in the AM layer 111P have the same potential, and the wiring formed in the GM layer 103A and the wiring formed in the AM layer 111A have the same potential. Even if a short circuit occurs due to the foreign matter 60, the potential is the same, so there is no problem.

  Therefore, in the display device of the present embodiment, it is possible to suppress a decrease in yield due to a short due to the foreign matter 60. Further, since the auxiliary wiring is not detoured, the pixel capacity does not decrease.

  Note that in this embodiment mode, two wirings having the same potential are formed so as to overlap in the stacking direction. Therefore, the power supply wiring PL is formed only in the GM layer 103P or the AM layer 111P without forming the same potential wiring in the two layers, or the auxiliary wiring AL is formed only in the GM layer 103A or the AM layer 111A. It is also considered good. However, in this case, since the number of wirings is halved, the wiring resistance increases. Therefore, if the power supply wiring PL having the same potential is formed in both the AM layer 111P and the GM layer 103P and the auxiliary wiring AL having the same potential is formed in both the AM layer 111A and the GM layer 103A as in the present embodiment, the wiring Increase in resistance can be suppressed. The power supply wiring PL formed in the AM layer 111P and the auxiliary wiring AL formed in the AM layer 111A are compared with the power supply wiring GL formed in the GM layer 103P and the auxiliary wiring AL formed in the GM layer 103A. The wiring width is narrow. For this reason, although the total wiring width of the power supply wiring PL is reduced as compared with the conventional case, this reduction width is very small and does not affect the circuit operation. In addition, the total wiring width of the auxiliary wiring AL is increased as compared with the conventional case, but there is no problem when the wiring width is increased.

(Embodiment 2)
A display device according to Embodiment 2 of the present invention will be described with reference to FIGS. 4A and 4B. Note that the display device (display panel) according to the present embodiment is an active matrix organic EL display device (organic EL display panel) as in the first embodiment, and a plurality of pixels P are arranged in the row direction and the column. Pixel portions (display regions) arranged in a matrix in the direction are provided.

  Note that the display device of this embodiment is different from the display device of Embodiment 1 in that the power supply wiring PL and the auxiliary wiring AL are arranged not only in the row direction but also in the column direction.

  As in the first embodiment, the display panel 1 in the present embodiment includes an organic EL element 10 that is a self-luminous display element, and an active matrix substrate 20 on which a pixel circuit 30 including a thin film transistor and various wirings is formed. Prepare. The configuration of the organic EL element 10 is the same as that in FIG. The configuration of the active matrix substrate 20 is the same except for the arrangement configuration of the power supply wiring PL and the auxiliary wiring AL.

4A is a diagram showing a layout configuration of the display device in the present embodiment, and FIG. 4B is a cross-sectional view corresponding to the line AA ′ in FIG. 4A. 4A illustrates nine pixels P _ij to P _{(i + 2) (j + 2)} for the sake of explanation.

  As shown in FIG. 4B, the display device is the same as the display device in this embodiment, in which a semiconductor layer 101 (not shown in FIG. 4B), a gate insulating layer 102, and a GM are stacked in this order from the substrate 100 side. Layer 103A (gate electrode, gate wiring), passivation layer 104, SD metal layer 105 (source electrode, drain electrode, source wiring, power supply wiring), planarization layer 106, AM layer 111A (anode, auxiliary wiring), EL layer 112 (Not shown in FIG. 4B), a laminated structure including a transparent electrode layer 113 (cathode) and a sealing material layer 114, and a counter glass substrate 50 bonded to the laminated structure. In this embodiment, the display device is described as an example of a top emission type, but may be a bottom emission type.

  An EL layer 112 (not shown) that is a light emitting unit is surrounded by a bank 115. The bank 115 has an opening for separating and partitioning the EL layer 112 for each pixel P. The bank 115 includes a convex portion extending between adjacent pixels P in a direction parallel to the source line SL. In other words, the lower electrode layer 12 (anode) and the organic light emitting layer 13 of each pixel P shown in FIG. 1 are formed between the adjacent protrusions (that is, the opening of the bank 115).

4A and 4B, as components of the display device, nine pixels P _ij to pixels P _{(i + 2) (j + 2)} , source lines SL _{j to} SL _{(j + 2),} and power supply lines PL _i extending in the row direction are used. ˜PL _{(i + 3)} , power supply wiring PL _j extending in the column direction, auxiliary wirings AL _i and AL _{(i + 1)} extending in the row direction, and auxiliary wiring AL _j extending in the column direction are illustrated.

The nine pixels P _ij to P _{(i + 2) (j + 2)} are arranged in a matrix (in a matrix) on a plane parallel to the active matrix substrate, and are formed in the semiconductor layer 101 to the SD metal layer 105 and the like. .

In FIG. 4A, the pixel P _ij to the pixel P _{(i + 2) (j + 2)} are each arranged in a portion indicated by a rectangular broken line.

Similarly to the first embodiment, the pixel P _ij to the pixel P _{(i + 2) j} are a first thin film transistor 31 on the upper left side of the drawing, a second thin film transistor 32 on the upper right side of the drawing, and a part of the second thin film transistor 32 in the stacking direction. A capacitor 33 is arranged so as to overlap with the capacitor. Further, the drain terminals of the second thin film transistors 32 of the pixels P _ij to P _{(i + 2) j} are connected to the power supply wiring PL _j extending in the column direction, and the source terminals of the first thin film transistors 31 are connected to the source wiring SL _j . Has been.

The pixel P _{i (j + 1)} to the pixel P _{(i + 2) (j + 1)} are different from the above-described pixel P _ij to the pixel P _{(i + 2) j in} that components such as the first thin film transistor 31, the second thin film transistor 32, and the capacitor 33 are It is formed symmetrically. Further, the drain terminals of the second thin film transistors 32 of the pixels P _{i (j + 1)} to P _{(i + 2) (j + 1)} are connected to the power supply wiring PL _j extending in the column direction, and the source terminals of the first thin film transistors 31 are the source It is connected to the wiring SL _{(j + 1)} .

Similarly to the first embodiment, the pixel P _{i (j + 2)} to the pixel P _{(i + 2) (j + 2)} have the first thin film transistor 31 on the upper left side of the drawing, the second thin film transistor 32 on the upper right side of the drawing, and the second thin film transistor 32. Capacitor 33 is arranged so that a part thereof overlaps in the stacking direction. The source terminals of the first thin film transistors 31 of the pixels P _{i (j + 2)} to P _{(i + 2) (j + 2)} are connected to the source line SL _{(j + 2)} .

Source wirings SL _{j to} SL _{(j + 2)} are formed in SD metal layer 105 so as to extend in the column direction on a plane parallel to the active matrix substrate. Source lines SL _j is the left side of the drawing of the pixel _{P ij ~P (i + 2)} j, ( so as to overlap in the stacking direction) so as to be connected to the first TFT 31, the formation of the pixel _{P ij ~P (i + 2)} j Formed through the area. Similarly, the source wiring SL _{(j + 1)} is connected to the first thin film transistor 31 on the right side of the pixel P _{i (j + 1) to} P _{(i + 2) (j + 1) in} the drawing (so as to overlap in the stacking direction). P _{i (j + 1) to} P _{(i + 2) (j + 1)} are formed through the formation region. Source lines _{SL (j + 2)} is the left side of the drawing of the pixel _{P i (j + 2) ~P} (i + 2) (j + 2), ( so as to overlap in the stacking direction) so as to be connected to the first TFT 31, the pixel _{P i ( j + 2) to} P _{(i + 2) (j + 2)} .

As shown in FIGS. 4A and 4B, power supply lines PL _i and PL _{(i + 1)} are arranged along a pixel row including pixel P _ij and a pixel row including pixel P _{(i + 1) j} in the present embodiment. Has been. The power supply wiring PL _i is formed in the GM layer (same hierarchy as the GM layer 103P in FIG. 3B), and the power supply wiring PL _{(i + 1)} is formed in the AM layer (same hierarchy as the AM layer 111P in FIG. 3B). It arrange | positions so that it may overlap with the lamination direction. Note that the power supply wiring PL _i and the power supply wiring PL _{(i + 1)} may be arranged so as to overlap with the pixel rows to be supplied with power as shown in FIG. 4A, or may be arranged between the pixel rows.

Similarly, the power supply wirings PL _{(i + 2)} and PL _{(i + 3)} are arranged along the pixel row including the pixel P _{(i + 2) j} in the present embodiment, as shown in FIGS. 4A and 4B. The power supply wiring PL _{(i + 2)} is formed in the GM layer (same hierarchy as the GM layer 103P in FIG. 3B), and the power supply wiring PL _{(i + 3)} is formed in the AM layer (same hierarchy as the AM layer 111P in FIG. 3B). And are arranged so as to overlap in the stacking direction. Note that the power supply wiring PL _{(i + 2)} and the power supply wiring PL _{(i + 3)} may be arranged so as to overlap the pixel rows to be supplied with power as shown in FIG. 4A, or may be arranged between the pixel rows. Good.

As shown in FIGS. 4A and 4B, the auxiliary wirings AL _i and AL _{(i + 1)} are arranged in a pixel row including the pixel P _{(i + 1) j} and a pixel row including the pixel P _{(i + 2) j} in the present embodiment. Are arranged along. The auxiliary wiring AL _{(i + 1)} is formed in the GM layer 103A, and the auxiliary wiring AL _i is formed in the AM layer 111A, and is arranged so as to overlap in the stacking direction. As shown in FIG. 4A, the auxiliary wiring AL _{(i + 1)} and the auxiliary wiring AL _i may be arranged so as to overlap with the pixel row to be supplied with power, or may be arranged between the pixel rows.

In the present embodiment, the auxiliary wiring ALj surrounded by the alternate long and short dash line overlaps with the power supply wiring PL _i and the power supply wiring PL _{(i + 1)} , the auxiliary wiring ALj enclosed with the alternate long and short dash line, the power supply wiring PL _{(i + 2),} and the power supply. For a portion where the wiring PL _{(i + 3)} overlaps, and a portion where the power supply wiring PLj surrounded by a two-dot chain line, the auxiliary wiring AL _i, and the auxiliary wiring AL _{(i + 1)} overlap, wirings having different potentials are connected to the upper wiring layer, Although the lower wiring layer and the SD metal layer 105 overlap in the stacking direction, the area of the portion is very limited as compared with the conventional case, so that a decrease in yield due to a short due to the foreign matter 60 can be effectively suppressed. . Further, since the auxiliary wiring AL is not detoured, the pixel capacity does not decrease.

(Embodiment 3)
A display device according to Embodiment 3 of the present invention will be described with reference to FIGS. 5A and 5B. Note that the display device (display panel) according to the present embodiment is an active matrix organic EL display device (organic EL display panel) as in the first embodiment, and a plurality of pixels are arranged in the row direction and the column direction. Are provided with pixel portions (display areas) arranged in a matrix.

  Note that the display device of this embodiment is different from the display device of Embodiment 2 in that the wiring is switched at the intersection of the power supply wiring PL and the auxiliary wiring AL.

  As in the first embodiment, the display panel 1 in the present embodiment includes an organic EL element 10 that is a self-luminous display element, and an active matrix substrate 20 on which a pixel circuit 30 including a thin film transistor and various wirings is formed. Prepare. The configuration of the organic EL element 10 is the same as that in FIG. The configuration of the active matrix substrate 20 is the same except for the arrangement configuration of the power supply wiring PL and the auxiliary wiring AL.

FIG. 5A is a diagram showing a layout configuration of the display device in this embodiment, and FIG. 5B is a cross-sectional view corresponding to the line AA ′ in FIG. 5A. In FIG. 5A, nine pixels P _ij to P _{(i + 2) (j + 2)} are illustrated for explanation.

  As shown in FIG. 5B, the display device is the same as the display device in this embodiment, in which a semiconductor layer 101 (not shown in FIG. 5B), a gate insulating layer 102, and a GM are stacked in this order from the substrate 100 side. Layer 103A (gate electrode, gate wiring), passivation layer 104, SD metal layer 105 (source electrode, drain electrode, source wiring, power supply wiring), planarization layer 106, AM layer 111A (anode, auxiliary wiring), EL layer 112 (Not shown in FIG. 5B), a laminated structure including a transparent electrode layer 113 (cathode) and a sealing material layer 114, and a counter glass substrate 50 bonded to the laminated structure. In this embodiment, the display device is described as an example of a top emission type, but may be a bottom emission type.

  An EL layer 112 (not shown) that is a light emitting unit is surrounded by a bank 115. The bank 115 has an opening for separating and partitioning the EL layer 112 for each pixel P. The bank 115 includes a convex portion extending between adjacent pixels P in a direction parallel to the source line SL. In other words, the lower electrode layer 12 (anode) and the organic light emitting layer 13 of each pixel P shown in FIG. 1 are formed between the adjacent protrusions (that is, the opening of the bank 115).

In FIG. 5A and FIG. 5B, as the constituent elements of the display device, nine pixels P _ij to pixels P _{(i + 2) (j + 2)} , source wirings SL _{j to} SL _{(j + 2)} , and rows, as in the _second embodiment. Power supply lines PL _{i to} PL _{(i + 3)} extending in the direction, power supply lines PL _j extending in the column direction, auxiliary lines AL _i and AL _{(i + 1)} extending in the row direction, and auxiliary lines AL extending in the column direction _j .

Note that the configurations of the nine pixels P _ij to pixels P _{(i + 2) (j + 2)} and the source lines SL _{j to} SL _{(j + 2)} are the same as those in the second embodiment.

As shown in FIGS. 5A and 5B, the power supply lines PL _i and PL _{(i + 1)} are arranged along the pixel P _ij and the pixel P _{(i + 1) j} in the present embodiment.

The power supply line PL _{(i + 1)} is formed in the AM layer as in the second embodiment. In the present embodiment, power supply line PL _i is formed in the GM layer except for a portion surrounded by a one-dot chain line (hereinafter referred to as a first intersection), and is formed in the AM layer at the first intersection. ing. More specifically, the power supply wiring PL _i is connected to the power supply wiring PL _{(i + 1) through} contacts on the left and right sides of the first intersection, and the power supply wiring formed in the AM layer at the first intersection. Integrated with PL _{(i + 1)} . The first crossing portion where the auxiliary wiring AL formed in the column direction and the power supply wiring PL formed in the row direction overlap has the same configuration. Further, as shown in FIG. 5A, the power supply wiring PL _i and the power supply wiring PL _{(i + 1)} may be arranged so as to overlap with the pixel rows to be supplied with power, or may be arranged between the pixel rows.

The auxiliary wiring AL _j extending in the column direction is formed in the SD metal layer 105 in a portion excluding the first intersection, and is formed in the GM layer 103A in the first intersection. The SD metal layer 105 is connected to the GM layer 103A by contacts on both the upper and lower sides of the crossing portion in the drawing.

As shown in FIGS. 5A and 5B, the auxiliary wirings AL _i and AL _{(i + 1)} are arranged along the pixel P _{(i + 1) j} and the pixel P _{(i + 2) j} in this embodiment.

The auxiliary wiring AL _i is formed in the AM layer 111A as in the second embodiment. In the present embodiment, the auxiliary wiring AL _{(i + 1)} is formed with a GM layer 103A except for a portion surrounded by a two-dot chain line (hereinafter referred to as a second intersecting portion), and at the second intersecting portion, an AM layer is formed. 111A. More specifically, the auxiliary wiring AL _{(i + 1)} is connected to the auxiliary wiring AL _{i by} a contact on both the left and right sides of the second intersection, and the auxiliary wiring AL _{(i + 1)} is formed in the AM layer 111A at the second intersection. Integrated with wiring AL _i . Note that the second crossing portion where the power supply wiring PL formed in the column direction and the auxiliary wiring AL formed in the row direction overlap has the same configuration. Further, as shown in FIG. 5A, the auxiliary wiring AL _{(i + 1)} and the auxiliary wiring AL _i may be arranged so as to overlap with the pixel row to be supplied with power, or may be arranged between the pixel rows.

Further, the power supply wiring PL _j extending in the column direction is formed in the SD metal layer 105 in a portion excluding the second intersecting portion, and is formed in the GM layer in the second intersecting portion. The SD metal layer 105 is connected to the GM layer by contacts on both upper and lower sides of the drawing.

  In the present embodiment, at the first intersection and the second intersection, one of the power supply wiring PL and the auxiliary wiring AL is arranged in the GM layer, and the other is arranged in the AM layer. Compared to the configuration in which one of the auxiliary wirings AL is sandwiched between the other, the possibility of short-circuiting by the foreign matter 61 and the foreign matter 62 can be reduced. Further, since the auxiliary wiring is not detoured, the pixel capacity does not decrease.

(Embodiment 4)
A display device according to Embodiment 4 of the present invention will be described with reference to FIGS. 6A and 6B. Note that the display device (display panel) according to the present embodiment is an active matrix organic EL display device (organic EL display panel) as in the first embodiment, and a plurality of pixels P are arranged in the row direction and the column. Pixel portions (display regions) arranged in a matrix in the direction are provided.

  Note that the display device of this embodiment is different from the display device of Embodiment 3 in that the method of changing the wiring is different at the intersection of the power supply wiring PL and the auxiliary wiring AL.

  As in the first embodiment, the display panel 1 in the present embodiment includes an organic EL element 10 that is a self-luminous display element, and an active matrix substrate 20 on which a pixel circuit 30 including a thin film transistor and various wirings is formed. Prepare. The configuration of the organic EL element 10 is the same as that in FIG. The configuration of the active matrix substrate 20 is the same except for the arrangement configuration of the power supply wiring PL and the auxiliary wiring AL.

6A is a diagram showing a layout configuration of the display device in the present embodiment, and FIG. 6B is a cross-sectional view corresponding to the line AA ′ in FIG. 6A. In FIG. 6A, nine pixels P _ij to P _{(i + 2) (j + 2)} are illustrated for explanation.

  As shown in FIG. 6B, the display device is the same as the display device in this embodiment, in which a semiconductor layer 101 (not shown in FIG. 6B), a gate insulating layer 102, and a GM are stacked in this order from the substrate 100 side. Layer 103A (gate electrode, gate wiring), passivation layer 104, SD metal layer 105 (source electrode, drain electrode, source wiring, power supply wiring), planarization layer 106, AM layer 111A (anode, auxiliary wiring), EL layer 112 (Not shown in FIG. 6B), a laminated structure including a transparent electrode layer 113 (cathode) and a sealing material layer 114, and a counter glass substrate 50 bonded to the laminated structure. In this embodiment, the display device is described as an example of a top emission type, but may be a bottom emission type.

  An EL layer 112 (not shown) that is a light emitting unit is surrounded by a bank 115. The bank 115 has an opening for separating and partitioning the EL layer 112 for each pixel P. The bank 115 includes a convex portion extending between adjacent pixels P in a direction parallel to the source line SL. In other words, the lower electrode layer 12 (anode) and the organic light emitting layer 13 of each pixel P shown in FIG. 1 are formed between the adjacent protrusions (that is, the opening of the bank 115).

6A and 6B, as in the second embodiment, as the constituent elements of the display device, nine pixels P _ij to pixel P _{(i + 2) (j + 2)} , source wirings SL _{j to} SL _{(j + 2)} , rows Power supply lines PL _{i to} PL _{(i + 3)} extending in the direction, power supply lines PL _j extending in the column direction, auxiliary lines AL _i and AL _{(i + 1)} extending in the row direction, and auxiliary lines AL extending in the column direction _j .

The configuration of nine pixels P _ij to pixels P _{(i + 2) (j + 2)} , source lines SL _{j to} SL _{(j + 2),} power supply lines PL _j extending in the column direction, and auxiliary lines AL _j extending in the column direction Is the same as in the second embodiment.

As shown in FIGS. 6A and 6B, the power supply lines PL _i and PL _{(i + 1)} are arranged along the pixel P _ij and the pixel P _{(i + 1) j} in the present embodiment.

The power supply wiring PL _i is formed in the GM layer (same hierarchy as the GM layer 103P in FIG. 3B), as in the second embodiment. In the present embodiment, power supply wiring PL _{(i + 1)} is formed in the AM layer (the same layer as AM layer 111P in FIG. 3B) except for the first intersection, and is formed in the GM layer at the first intersection. Has been. More specifically, in the present embodiment, the power supply wiring PL _{(i + 1)} is connected to the power supply wiring PL _{i through} a contact on both the left and right sides of the first intersection in the drawing, and the GM layer at the first intersection. Are integrated with the power supply wiring PL _i formed in the above. The first crossing portion where the auxiliary wiring AL formed in the column direction and the power supply wiring PL formed in the row direction overlap has the same configuration. Further, as shown in FIG. 6A, the power supply wiring PL _i and the power supply wiring PL _{(i + 1)} may be arranged so as to overlap with the pixel rows to be supplied with power, or may be arranged between the pixel rows.

As shown in FIGS. 6A and 6B, the auxiliary wirings AL _i and AL _{(i + 1)} are arranged along the pixel P _{(i + 1) j} and the pixel P _{(i + 2) j} in this embodiment.

The auxiliary wiring AL _{(i + 1)} is formed in the GM layer 103A as in the second embodiment. In the present embodiment, the auxiliary wiring AL _i is formed in the AM layer 111A except for the second intersection, and is formed in the GM layer 103A at the second intersection. More specifically, in the present embodiment, the auxiliary wiring AL _i is connected to the auxiliary wiring AL _{(i + 1) by} a contact on both the left and right sides of the second intersection in the drawing, and at the second intersection, the GM layer It is integrated with the auxiliary wiring AL _{(i + 1)} formed in 103A. Note that the second crossing portion where the power supply wiring PL formed in the column direction and the auxiliary wiring AL formed in the row direction overlap has the same configuration. Further, as shown in FIG. 6A, the auxiliary wiring AL _{(i + 1)} and the auxiliary wiring AL _i may be arranged so as to overlap with the pixel row to be supplied with power, or may be arranged between the pixel rows.

  Furthermore, in this embodiment, a bank 115 is formed on the second intersection.

  In the present embodiment, since the power supply wiring PL and the auxiliary wiring AL having different potentials are formed in the SD metal layer 105 and the GM layer 103A at the first intersection and the second intersection, Even when the foreign matter 60 is mixed, the possibility of a short circuit can be reduced. As described with reference to FIGS. 8A and 8B, the foreign matter 60 mixed during the formation of the planarizing layer 106 is typically between the AM layer 111A and the SD metal layer 105, or between the AM layer 111A and the GM layer. This is because a short circuit is generated with 103. Moreover, since the bank 115 is formed on the second intersection, it is possible to prevent the foreign matter 60 from being pushed in when the counter glass substrate 50 is attached.

  Therefore, when the contamination path of the foreign matter 60 can be estimated to some extent, the reconnection of the present embodiment is useful.

  Further, as in the first to third embodiments, the auxiliary wiring is not detoured, so that the pixel capacitance is not reduced.

(Another embodiment)
(1) In the first to fourth embodiments, the case where the one pixel PG is the pixel P of the three primary colors of RGB has been described as an example. However, the present invention is not limited to this. For example, four primary colors such as RGBW and RGBY, and further primary colors may be added and configured corresponding to each. Further, for example, it may be configured by pixels of a pen tile arrangement in which RG and BG are combined and arranged in a matrix as one unit cell.

  (2) In the first to fourth embodiments, the first thin film transistor 31 and the second thin film transistor 32 are described as p-channel TFTs, but they may be n-channel TFTs.

  (3) In the first to fourth embodiments, the display device can be used as, for example, a television set, a mobile phone, a personal computer, or a flat panel display of another device.

  While the display device according to the present invention has been described based on the embodiments and examples, the present invention is not limited to these embodiments and examples.

  In this embodiment, the display device according to the present invention is applied to an organic EL display device. However, the display device can be applied to other active matrix display devices.

  In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and example, and arbitrarily combining the components and functions in each embodiment and example without departing from the spirit of the present invention The embodiment realized by the above is also included in the present invention.

  The display device according to the present invention can be widely used in display devices such as television sets, personal computers, and mobile phones.

DESCRIPTION OF SYMBOLS 1 Display panel 10 Organic EL element 12 Lower electrode layer 13 Organic light emitting layer 14 Upper electrode layer 20 Active matrix substrate 30 Pixel circuit 31 First thin film transistor 32 Second thin film transistor 33 Capacitor 40 Connection wiring 50 Opposite glass substrates 60, 61, 62 100 Substrate 101 Semiconductor layer 102 Gate insulating layer 103, 103A, 103P GM layer 104 Passivation layer 105 SD metal layer 106 Planarization layer 111, 111A, 111P AM layer 112 EL layer 112B EL layer 112R EL layer 113 Transparent electrode layer 114 Sealing Material layer 115 Bank 1000 Active matrix display device 1010 Organic EL element 1031 First thin film transistor 1032 Second thin film transistor 1033 Capacitor 1051 Power supply wiring 1052 Scan line 1053 Electricity Line 1054 auxiliary wiring PG pixel P subpixels GL gate line SL source lines PL power wiring AL auxiliary lines PB blue display pixel PR red display pixel

Claims (8)

A display device having a display area in which a plurality of pixels are arranged in a matrix,
In the display region, source wiring extended along a plurality of pixels arranged in the same column,
A lower wiring layer including a first wiring and a second wiring;
An interlayer insulating layer provided above the lower wiring layer;
An upper wiring layer provided above the interlayer insulating layer and including a third wiring and a fourth wiring; and
The first wiring and the third wiring, respectively, in the display region, among the plurality of pixel lines formed by pixels arranged in the same row along the pixel lines belonging to the first group It extends over the plurality of pixels and is disposed at a position overlapping in the stacking direction via the interlayer insulating layer,
Each of the second wiring and the fourth wiring is a pixel line belonging to the first group among the plurality of pixel lines composed of pixels arranged in the same row in the display area. Extending across the plurality of pixels along the pixel line belonging to the second group excluding, and disposed in a position overlapping in the stacking direction via the interlayer insulating layer,
The first wiring and the third wiring are set to a first potential and configured to supply the first potential to the plurality of pixels, and the second wiring and the second wiring The four wirings are set to a second potential different from the first potential, and are configured to supply the second potential to the plurality of pixels. The pixel line belonging to the first group is one of an odd-numbered pixel line and an even-numbered pixel line among the plurality of pixel lines, and the pixel line belonging to the second group is the odd-numbered pixel line. The display device according to claim 1, wherein the display device is the other of a pixel line of a line and a pixel line of the even line. The first wiring and the third wiring are electrically connected through a contact hole provided in the interlayer insulating layer,
The display device according to claim 1, wherein the second wiring and the fourth wiring are electrically connected via a contact hole provided in the interlayer insulating layer. The plurality of pixels are:
An organic light emitting device including an organic light emitting layer having an organic material sandwiched between two electrodes;
A driving circuit layer on which a driving transistor for current driving the organic light emitting element is formed in a layer located on a substrate side from a layer constituting the organic light emitting element;
A source / drain electrode of the driving transistor is connected to the first wiring and the third wiring;
The display device according to claim 1, wherein one of the two electrodes of the organic light emitting element is connected to the second wiring and the fourth wiring. The first wiring and the third wiring are power supply wirings that supply power of the first potential to the pixels constituting the pixel lines belonging to the first group,
5. The display device according to claim 4, wherein the second wiring and the fourth wiring are power supply wirings that supply power of the second potential to pixels that form pixel lines belonging to the second group. . The lower wiring layer is formed in the same layer as a gate electrode layer where a gate electrode of the driving transistor is formed or a source / drain layer where a source / drain electrode of the driving transistor is formed,
The display device according to claim 4, wherein the upper wiring layer is formed in the same layer as a layer on which an electrode of the organic light emitting element located on the substrate side is formed.   And a bank for partitioning the plurality of pixels for each pixel,
  One of the third wiring and the fourth wiring is not connected to the electrode of the organic light emitting element by being covered by the bank, and the other is connected to the electrode of the organic light emitting element by being exposed from the bank. Be done
  The display device according to claim 6. The first potential is a high potential side potential applied to a pixel circuit configured to include the driving circuit formed for each pixel,
It said second potential is a display device according to any one of claims 4-7 which is the potential on the low potential side is applied to the pixel circuit.

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