JP6038955B2 - 高時間的参照局所性のデータフィルバッファの排除防止 - Google Patents

高時間的参照局所性のデータフィルバッファの排除防止 Download PDF

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JP6038955B2
JP6038955B2 JP2014553535A JP2014553535A JP6038955B2 JP 6038955 B2 JP6038955 B2 JP 6038955B2 JP 2014553535 A JP2014553535 A JP 2014553535A JP 2014553535 A JP2014553535 A JP 2014553535A JP 6038955 B2 JP6038955 B2 JP 6038955B2
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data buffer
high temporal
temporal reference
cache
counter
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JP2015508192A5 (enExample
JP2015508192A (ja
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ロバート・ディー・クランシー
トーマス・フィリップ・スパイアー
ジェームズ・ノリス・ディーフェンダッファー
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2014553535A 2012-01-23 2013-01-23 高時間的参照局所性のデータフィルバッファの排除防止 Expired - Fee Related JP6038955B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261589577P 2012-01-23 2012-01-23
US61/589,577 2012-01-23
US13/451,010 US10114750B2 (en) 2012-01-23 2012-04-19 Preventing the displacement of high temporal locality of reference data fill buffers
US13/451,010 2012-04-19
PCT/US2013/022775 WO2013112607A1 (en) 2012-01-23 2013-01-23 Preventing the displacement of high temporal locality of reference data fill buffers

Publications (3)

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JP2015508192A JP2015508192A (ja) 2015-03-16
JP2015508192A5 JP2015508192A5 (enExample) 2016-02-18
JP6038955B2 true JP6038955B2 (ja) 2016-12-07

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JP2014553535A Expired - Fee Related JP6038955B2 (ja) 2012-01-23 2013-01-23 高時間的参照局所性のデータフィルバッファの排除防止

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US (1) US10114750B2 (enExample)
EP (1) EP2807566A1 (enExample)
JP (1) JP6038955B2 (enExample)
KR (1) KR20140116943A (enExample)
CN (1) CN104067244B (enExample)
WO (1) WO2013112607A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9507725B2 (en) * 2012-12-28 2016-11-29 Intel Corporation Store forwarding for data caches
US9946646B2 (en) * 2016-09-06 2018-04-17 Advanced Micro Devices, Inc. Systems and method for delayed cache utilization

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EP0457403B1 (en) 1990-05-18 1998-01-21 Koninklijke Philips Electronics N.V. Multilevel instruction cache and method for using said cache
DE69224084T2 (de) 1991-01-15 1998-07-23 Koninkl Philips Electronics Nv Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür
US6192449B1 (en) 1996-04-12 2001-02-20 Motorola, Inc. Apparatus and method for optimizing performance of a cache memory in a data processing system
JP2976909B2 (ja) 1996-12-25 1999-11-10 日本電気株式会社 キャッシュ・データの掃き出し制御方法
JPH1145180A (ja) 1997-07-25 1999-02-16 Nec Corp キャッシュ制御方式
DE19961499A1 (de) * 1999-12-20 2001-07-05 Ericsson Telefon Ab L M Caching von Objekten in Platten-gestützten Datenbanken
JP3498673B2 (ja) 2000-04-05 2004-02-16 日本電気株式会社 記憶装置
US20030110357A1 (en) 2001-11-14 2003-06-12 Nguyen Phillip V. Weight based disk cache replacement method
US7278136B2 (en) * 2002-07-09 2007-10-02 University Of Massachusetts Reducing processor energy consumption using compile-time information
US7451271B2 (en) 2004-04-05 2008-11-11 Marvell International Ltd. Physically-tagged cache with virtually-tagged fill buffers
JP2006185335A (ja) 2004-12-28 2006-07-13 Toshiba Corp 情報処理装置及びこの情報処理装置の制御方法
KR101257848B1 (ko) * 2005-07-13 2013-04-24 삼성전자주식회사 복합 메모리를 구비하는 데이터 저장 시스템 및 그 동작방법
DE102006017768A1 (de) * 2006-04-15 2007-10-18 Infineon Technologies Ag Integrierter Speicherbaustein sowie Verfahren zum Betrieb eines integrierten Speicherbausteins
US7757034B1 (en) * 2006-06-29 2010-07-13 Parallels Software International, Inc. Expansion of virtualized physical memory of virtual machine
KR101128234B1 (ko) 2006-08-23 2012-03-23 엘지전자 주식회사 메모리 접근 제어 장치 및 방법
JP5137002B2 (ja) 2007-01-25 2013-02-06 株式会社メガチップス メモリコントローラ
US8726248B2 (en) 2008-06-12 2014-05-13 Oracle America, Inc. Method and apparatus for enregistering memory locations
US8271732B2 (en) 2008-12-04 2012-09-18 Intel Corporation System and method to reduce power consumption by partially disabling cache memory
US8452946B2 (en) 2009-12-17 2013-05-28 Intel Corporation Methods and apparatuses for efficient load processing using buffers
US8402232B2 (en) * 2009-12-23 2013-03-19 Oracle America, Inc. Memory utilization tracking
US9015441B2 (en) * 2010-04-30 2015-04-21 Microsoft Technology Licensing, Llc Memory usage scanning
US20120017039A1 (en) * 2010-07-16 2012-01-19 Plx Technology, Inc. Caching using virtual memory
US8386717B1 (en) * 2010-09-08 2013-02-26 Symantec Corporation Method and apparatus to free up cache memory space with a pseudo least recently used scheme
US8595463B2 (en) * 2010-09-15 2013-11-26 International Business Machines Corporation Memory architecture with policy based data storage
US8990538B2 (en) * 2010-11-05 2015-03-24 Microsoft Corporation Managing memory with limited write cycles in heterogeneous memory systems
CN102073596B (zh) 2011-01-14 2012-07-25 东南大学 针对指令的可重构片上统一存储器管理方法
US8683243B2 (en) * 2011-03-11 2014-03-25 Intel Corporation Dynamic core selection for heterogeneous multi-core systems

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Publication number Publication date
EP2807566A1 (en) 2014-12-03
WO2013112607A1 (en) 2013-08-01
US20130191559A1 (en) 2013-07-25
US10114750B2 (en) 2018-10-30
KR20140116943A (ko) 2014-10-06
CN104067244A (zh) 2014-09-24
CN104067244B (zh) 2017-10-31
JP2015508192A (ja) 2015-03-16

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