CN104067244B - 防止参考数据填充缓冲器的高时间局部性的移位 - Google Patents

防止参考数据填充缓冲器的高时间局部性的移位 Download PDF

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Publication number
CN104067244B
CN104067244B CN201380006129.7A CN201380006129A CN104067244B CN 104067244 B CN104067244 B CN 104067244B CN 201380006129 A CN201380006129 A CN 201380006129A CN 104067244 B CN104067244 B CN 104067244B
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China
Prior art keywords
data buffer
counter
memory
memory content
logic
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Expired - Fee Related
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CN201380006129.7A
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English (en)
Chinese (zh)
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CN104067244A (zh
Inventor
罗伯特·D·克兰西
托马斯·菲利普·施派尔
詹姆斯·诺里斯·迪芬德尔费尔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201380006129.7A 2012-01-23 2013-01-23 防止参考数据填充缓冲器的高时间局部性的移位 Expired - Fee Related CN104067244B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261589577P 2012-01-23 2012-01-23
US61/589,577 2012-01-23
US13/451,010 US10114750B2 (en) 2012-01-23 2012-04-19 Preventing the displacement of high temporal locality of reference data fill buffers
US13/451,010 2012-04-19
PCT/US2013/022775 WO2013112607A1 (en) 2012-01-23 2013-01-23 Preventing the displacement of high temporal locality of reference data fill buffers

Publications (2)

Publication Number Publication Date
CN104067244A CN104067244A (zh) 2014-09-24
CN104067244B true CN104067244B (zh) 2017-10-31

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CN201380006129.7A Expired - Fee Related CN104067244B (zh) 2012-01-23 2013-01-23 防止参考数据填充缓冲器的高时间局部性的移位

Country Status (6)

Country Link
US (1) US10114750B2 (enExample)
EP (1) EP2807566A1 (enExample)
JP (1) JP6038955B2 (enExample)
KR (1) KR20140116943A (enExample)
CN (1) CN104067244B (enExample)
WO (1) WO2013112607A1 (enExample)

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US9507725B2 (en) * 2012-12-28 2016-11-29 Intel Corporation Store forwarding for data caches
US9946646B2 (en) * 2016-09-06 2018-04-17 Advanced Micro Devices, Inc. Systems and method for delayed cache utilization

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CN102073596A (zh) * 2011-01-14 2011-05-25 东南大学 针对指令的可重构片上统一存储器管理方法
CN102103488A (zh) * 2009-12-17 2011-06-22 英特尔公司 利用缓冲器进行高效加载处理的方法和设备

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JP2976909B2 (ja) 1996-12-25 1999-11-10 日本電気株式会社 キャッシュ・データの掃き出し制御方法
JPH1145180A (ja) 1997-07-25 1999-02-16 Nec Corp キャッシュ制御方式
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JP2006185335A (ja) 2004-12-28 2006-07-13 Toshiba Corp 情報処理装置及びこの情報処理装置の制御方法
KR101257848B1 (ko) * 2005-07-13 2013-04-24 삼성전자주식회사 복합 메모리를 구비하는 데이터 저장 시스템 및 그 동작방법
DE102006017768A1 (de) * 2006-04-15 2007-10-18 Infineon Technologies Ag Integrierter Speicherbaustein sowie Verfahren zum Betrieb eines integrierten Speicherbausteins
US7757034B1 (en) * 2006-06-29 2010-07-13 Parallels Software International, Inc. Expansion of virtualized physical memory of virtual machine
KR101128234B1 (ko) 2006-08-23 2012-03-23 엘지전자 주식회사 메모리 접근 제어 장치 및 방법
JP5137002B2 (ja) 2007-01-25 2013-02-06 株式会社メガチップス メモリコントローラ
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US8683243B2 (en) * 2011-03-11 2014-03-25 Intel Corporation Dynamic core selection for heterogeneous multi-core systems

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US6192449B1 (en) * 1996-04-12 2001-02-20 Motorola, Inc. Apparatus and method for optimizing performance of a cache memory in a data processing system
CN102103488A (zh) * 2009-12-17 2011-06-22 英特尔公司 利用缓冲器进行高效加载处理的方法和设备
CN102073596A (zh) * 2011-01-14 2011-05-25 东南大学 针对指令的可重构片上统一存储器管理方法

Also Published As

Publication number Publication date
JP6038955B2 (ja) 2016-12-07
EP2807566A1 (en) 2014-12-03
WO2013112607A1 (en) 2013-08-01
US20130191559A1 (en) 2013-07-25
US10114750B2 (en) 2018-10-30
KR20140116943A (ko) 2014-10-06
CN104067244A (zh) 2014-09-24
JP2015508192A (ja) 2015-03-16

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