JP6003970B2 - Uninterruptible power supply controller - Google Patents

Description

  The present invention is particularly effective in a three-level converter that combines a converter and an inverter having a three-level main circuit configuration to suppress a voltage imbalance formed by a voltage dividing capacitor in a direct current section and to enable a stable operation. The present invention relates to a control device for a power failure power supply (UPS).

  There is a PWM converter / inverter system as a system for supplying an AC voltage having an arbitrary amplitude and frequency to a load. In this system, an AC voltage of a system power supply is converted into a DC voltage by a PWM converter, and the DC voltage is converted into an AC voltage having a desired amplitude and frequency by a PWM inverter. Such a system is widely applied in applications such as an inverter for driving a motor and an uninterruptible power supply.

In recent years, attention has been focused on three levels of the main circuit of the PWM converter / inverter system from the viewpoint of reducing harmonics and loss.
Here, FIG. 8 shows a main circuit configuration example of a three-phase full-bridge type three-level inverter. The three-level inverter includes four semiconductor switching elements per phase (for example, switching elements S _1U , S _2U , S _3U , S _4U for the U phase), and the DC part of the inverter includes capacitors C _D1 , C _D2 is connected in series, and the DC input voltage E _D is divided into two.

As an example, the operation of the U phase in FIG. 8 will be described. When the switching elements S _1U and S _2U are turned on, the U-phase output terminal generates a positive voltage (+ E _D1 ) with reference to the direct current midpoint N _D that is a connection point between the capacitors C _D1 and C _D2. When the switching elements S _2U and S _3U are turned on, a zero voltage is output, and when the switching elements S _3U and S _4U are turned on, a negative voltage (−E _D2 ) is output.
That is, by combining the three states of the switching elements S _{1U to} S _4U , the voltage of the U-phase output terminal can be changed to three levels, and the time ratio of each level can be changed to output any voltage. . Such three-level operation has advantages such as fewer output voltage harmonics, lower switching loss, and easier high-voltage and larger capacity. Is progressing.

As one of the problems of the three-level converter, there is control of voltage sharing imbalance (hereinafter referred to as DC voltage imbalance) of the two divided capacitors.
For example, in FIG. 8, the voltages E _D1 and E _D2 of the capacitors C _D1 and C _D2 should be equal to each other. However, when to output the zero voltage by turning on the switching element S _2U, the S _3U will become a current flows through the DC midpoint N _D, this means that the potential of the DC midpoint N _D is changed, i.e. , The voltages E _D1 and E _D2 are imbalanced.

  The above DC voltage imbalance becomes prominent particularly when a load through which a positive / negative asymmetric current flows is connected, such as a half-wave rectification load. Even if a linear load through which positive and negative symmetric currents flow is connected, it may occur when there are variations in characteristics of the semiconductor elements of the main circuit or errors in the detection circuit.

  When the DC voltage imbalance becomes remarkable, not only the inverter cannot output a voltage as commanded, but a voltage exceeding the withstand voltage is applied to the main circuit element, and in the worst case, the device may be destroyed. Therefore, in the three-level converter, some means for suppressing the DC voltage imbalance is essential.

Under the background as described above, Patent Document 1 discloses a method of suppressing DC voltage imbalance by controlling an inverter.
FIG. 9 shows a control circuit 100 of a three-level inverter described in Patent Document 1, wherein 101 is a 6-fold frequency so that the deviation S ₁ between the voltages E _D1 and E _D2 of two capacitors is zero. regulator for calculating the amplitude _{S 2} of the sine wave, 102 theta _R ^* each phase of the phase angle, theta _S ^*, is sin (6θ) table for outputting the value of sin (6θ) corresponding to theta _T ^* .

In this prior art, a final output phase voltage command V _R ^** , V _{S is} obtained by adding a sine wave of 6 times the frequency to the inverter output phase voltage commands V _R ^* , V _S ^* , V _T ^* . ^** and V _T ^** are generated and PWM control is performed using these output phase voltage commands V _R ^** , V _S ^** and V _T ^** to generate a desired AC voltage. This is an operation of changing the time for which the inverter outputs 0 voltage. As a result, the current flowing through the DC midpoint can be changed to suppress the DC voltage imbalance.
In this prior art, a sine wave is added to the output phase voltage commands V _R ^* , V _S ^* , and V _T ^{*. Since} the frequency of the sine wave is six times the output frequency, this operation is performed. As a result, the output line voltage of the inverter does not change and the load is not affected.

Patent Document 2 discloses another method for suppressing DC voltage imbalance.
FIG. 10 shows the prior art described in Patent Document 2. In this prior art, a switching arm composed of semiconductor switching elements DB ₁ and DB ₂ and a reactor L ₁ are added to the main circuit 150 of the three-level inverter to control on / off of the switching elements DB ₁ and DB _2. This suppresses DC voltage imbalance.

However, regardless of which DC voltage imbalance suppression means shown in FIG. 9 or FIG. 10 is applied, the unbalance suppression capability has a certain limit.
For example, as shown in FIG. 10, when a dedicated switching arm including the switching elements DB ₁ and DB ₂ and the reactor L ₁ are added, the DC voltage imbalance suppression capability is determined by the capacity of the reactor L ₁ . Therefore, if an attempt to improve the imbalance suppressing capability, reactor L ₁ is large, there is a limit for the cost is increased and the volume increase of the apparatus.
Further, as shown in FIG. 9, the same applies to the case where the DC voltage imbalance is suppressed by the control of the converter.

In view of the above points, Patent Document 3 discloses that in an uninterruptible power supply using a three-level converter, even when a DC voltage imbalance exceeding the suppression capability of the apparatus occurs, the apparatus can be operated continuously. Technology is disclosed.
FIG. 11 is a block diagram of a control device described in Patent Document 3, and is for controlling a converter in a three-level converter / inverter system.

In FIG. 11, reference numeral 161 denotes a voltage command value V _un for each phase based on the sum of the system voltage V _cnv , the system current I _cnv , the DC voltage command value V _dcREF , and the positive side and negative side capacitor voltages V _dcP and V _dcN. , V _vn , V _wn computing means, 162 is a judgment means for judging the power failure of the system voltage V _cnv and outputs the signal SG ₁ , 163 is a voltage command at the time of the power failure from the deviation of the capacitor voltages V _dcP , V _dcN Calculation means for calculating the values V _un ', V _vn ', V _wn ', 164 is an absolute value calculator for calculating the absolute value of the deviation of the capacitor voltages V _dcP and V _dcN , and 165 compares the absolute value with a threshold value. judging means for outputting a signal SG ₂ Te, respectively 166 and 167 pulse calculator for calculating a PWM pulse _{P c1, P cc2,} 168 is based on the signal SG ₂ P Judging means for outputting the M pulse _{P cc2} or zero pulse as _{P c2,} 169 is a switch for switching the PWM pulse _{P c} to be supplied to the converter between the _{P c1, P c2.}

In this prior art, when the power supply is normal, the converter is controlled to supply power to the inverter, and at the same time, the DC voltage imbalance is suppressed by the operation of the arithmetic means 161.
When the power supply fails and voltage imbalance occurs in the two capacitors in the DC section, the operation of the converter is temporarily stopped and power is supplied from the storage battery to the inverter. Thereafter, the operation of the converter is resumed, and the voltage of the capacitor is balanced by controlling the converter so as to discharge the load of the capacitor having a high voltage. That is, the control block of FIG. 11 allows the converter to operate only to suppress DC voltage imbalance, thereby improving the ability to suppress DC voltage imbalance and enabling operation of the apparatus to continue even after an imbalance has occurred. .

JP-A-7-79574 (paragraphs [0037] to [0039], FIG. 1 etc.) Japanese Unexamined Patent Publication No. 2000-199738 (paragraphs [0008] to [0010], FIG. 1, FIG. 2, etc.) JP 2013-247724 A (paragraphs [0026] to [0039], FIGS. 1 to 3 etc.)

In the uninterruptible power supply, when any abnormality occurs in the input voltage, such as when a power failure occurs, power is supplied from the inverter to the load using the power of the storage battery by backup operation. However, if the amount of charge of the storage battery is insufficient, power is not supplied from the storage battery to the inverter, and power supply to the load is adversely affected. In the worst case, power may not be supplied.
For this reason, in the case where the DC voltage imbalance suppression operation is frequently performed using the conventional technology of Patent Document 3, there is a risk that the amount of charge of the storage battery may be insufficient, and continuation of the backup operation using the power of the storage battery during a power failure There may be a problem that the time is shortened or the power supply to the load cannot be normally performed.

  Therefore, a problem to be solved by the present invention is to provide a control device capable of continuing operation without adversely affecting power feeding to a load even when a DC voltage imbalance occurs in an uninterruptible power supply using a three-level converter. It is to provide.

In order to solve the above-mentioned problem, the invention according to claim 1 is a converter for converting an AC input voltage into a DC voltage and outputting the DC voltage, wherein a plurality of capacitors are connected in series between positive and negative circuits of a DC unit, and the capacitor A three-level converter that generates a positive potential and a negative potential with reference to the midpoint potential of the series circuit of
A three-level inverter connected to the converter via the DC unit and outputting any one of the positive potential, negative potential, and midpoint potential for each phase and supplying an AC voltage having an arbitrary amplitude and frequency to a load When,
A bypass circuit for supplying an alternating voltage to the load instead of the inverter;
In a control device for controlling an uninterruptible power supply comprising
When the deviation between the magnitude of the positive potential with respect to the midpoint potential and the magnitude of the negative potential exceeds a reference value, switching from feeding to the load by the inverter to feeding to the load by the bypass circuit Means ,
Load current analysis means for analyzing the waveform of the current flowing through the load,
After switching from feeding to the load by the inverter to feeding to the load by the bypass circuit,
The load current analyzing means generates a switching permission signal for switching again from power supply to the load by the bypass circuit to power supply to the load by the inverter according to the analysis result of the waveform of the load current .

The invention according to claim 2, in the control device of the uninterruptible power supply according to claim 1, which is shall generate an alarm when not generate the switching換許enable signal.

According to a third aspect of the present invention, in the control device for the uninterruptible power supply according to the first or second aspect, the load current analyzing means is configured to perform the switching permission signal when the DC component of the load current is equal to or less than a reference value. it is shall generate a.

According to a fourth aspect of the present invention, in the control apparatus for the uninterruptible power supply according to the first aspect , the means for counting the number of switching times switched from the power supply to the load by the inverter to the power supply to the load by the bypass circuit. And means for stopping the operation of the apparatus by determining that the apparatus has failed when the count number within a predetermined time of the number of switching times exceeds the reference number .

  According to the present invention, in the uninterruptible power supply in which the main circuit is constituted by a three-level converter / inverter, the DC voltage imbalance can be suppressed by switching from feeding to the load by the inverter to feeding by the bypass circuit, The device can be continuously operated to prevent adverse effects on the load.

It is a main circuit lineblock diagram of an uninterruptible power supply with which an embodiment of the present invention is applied. It is a block diagram of the control apparatus which concerns on 1st Embodiment of this invention. It is a block diagram of the DC voltage imbalance monitoring means in FIG. It is a block diagram of the control means of the converter in 1st Embodiment of this invention. It is a block diagram of the control apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram of the load current analysis means in FIG. It is a block diagram of the control apparatus which concerns on 3rd Embodiment of this invention. It is a main circuit block diagram of a 3 level inverter. It is a block diagram of the prior art described in patent document 1. FIG. It is a block diagram of the prior art described in patent document 2. FIG. It is a block diagram of the prior art described in patent document 3. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 is a main circuit configuration diagram of an uninterruptible power supply to which an embodiment of the present invention is applied. The uninterruptible power supply 10 includes a three-phase three-level converter 11 and a three-level inverter 12 that are connected to each other via a DC unit 14, and a capacitor having an equal capacitance value that is connected in series between the positive and negative circuits of the DC unit 14 C _D1 , C _D2 (N _D indicates a DC midpoint), a switch SW ₁ connected between the three-level inverter 12 and the load, and a bypass circuit 15 for supplying a bypass voltage to the load. and a switch SW _2, and a, a chopper 13 connected between the DC portion 14 and the outside of the power storage locations. Here, the switches SW ₁ and SW ₂ are, for example, electromagnetic contactors.

In the above configuration, the number of capacitors in the DC unit 14 need not be two. That is, the DC unit 14, since it is sufficient to generate a potential of the DC midpoint _{N D} (0 potential) equal in magnitude relative to the positive potential _{(+ E D1)} and a negative potential _{(+ E D1),} connected in series The number of capacitors does not matter.

  Note that an AC voltage is input to the three-level converter 11 from an external three-phase AC power supply, and a bypass voltage is supplied from the three-phase AC power supply or another AC power supply. In FIG. 1, even when the AC input voltage to the converter 11 disappears due to a power failure, if the bypass voltage is supplied from another AC power source, the chopper 13 functions as an uninterruptible power supply. It is not essential.

Next, the general operation of the uninterruptible power supply 10 will be described.
Normal supply switch SW ₁ is turned on, the switch SW ₂ of the bypass circuit 15 is off, the inverter 12 by using the voltage of the DC unit 14 power to the load (inverter power supply state). Since the converter 11 and the inverter 12 are three-level converters, the voltage of the DC unit 14 is divided into two by capacitors C _D1 and C _D2 .

In order to supply power normally to the load by the inverter 12, it is necessary not only to keep the sum of the voltages E _D1 and E _D2 of the capacitors C _D1 and C _D2 above a certain value but also to balance the voltages E _D1 and E _D2 There is. As the means, there are various methods such as providing the unbalance suppression function in the control of the converter 11 or the inverter 12 and providing a dedicated semiconductor switching arm for controlling the DC voltage balance as in the prior art described above. In the present invention, the DC voltage imbalance is suppressed by switching from the power supply to the load by the inverter 12 to the power supply by the bypass circuit 15.

Bypass circuit 15 including a switch SW ₂ is a power supply backup circuit during equipment failure including a direct-current voltage unbalance condition. Converter 11, an inverter 12, and when an overvoltage or overcurrent within the device including a chopper 13 occurs, such as when the DC voltage imbalance is significant, if continuous operation of the apparatus is difficult, the switch SW ₁ is turned off immediately by turning on the switch SW _2, by way of the bypass circuit 15 continues the power supply to the load from an external AC power source (bypass feeding state).

Next, FIG. 2 is a block diagram of the control device according to the first embodiment of the present invention. The first embodiment corresponds to the invention according to claim 1.
In FIG. 2, the DC voltage imbalance monitoring means 20 monitors the voltages E _D1 and E _D2 of the capacitors C _D1 and C _D2 of the DC unit 14 and determines that a DC voltage imbalance has occurred. And a bypass switching command are output.

A configuration example of the DC voltage imbalance monitoring means 20 is shown in FIG.
As shown in FIG. 3, the voltages E _D1 and E _D2 of the capacitors C _D1 and C _D2 are detected, the deviation is obtained by the subtracting means 21, and the absolute value of the deviation is calculated by the absolute value calculating means 22. Then, the deviation absolute value is compared with the first and second reference values by the first and second comparing means 23 and 24, respectively, and a command corresponding to the following condition is output.

  For example, when the deviation absolute value is larger than the first reference value, the first comparison unit 23 outputs an alarm generation command. The alarm generation command is sent to the alarm generation unit 30 in FIG. 2, and the alarm generation unit 30 generates a warning that a DC voltage imbalance has occurred or displays it on a monitor or the like to generate an alarm. . The purpose of this operation is to alert the user that a DC voltage imbalance has occurred, but there is a possibility that the operation may become impossible if the operation continues as it is.

The alarm generation command is sent to the converter control means shown in FIG. 4 at the same time, and attempts to suppress DC voltage imbalance by changing the operation of the converter control.
The converter control means shown in FIG. 4 is general, but the configuration of the converter control means is not limited to FIG.

First, an outline of the operation of FIG. 4 will be described.
A deviation between the DC voltage command output from the converter 11 and the detected DC voltage value is obtained by the subtracting means 52, and the input current command of the converter 11 is calculated by the operation of the PI adjusting means 53 that makes this deviation zero. This input current command is input to the current control means 54, and a voltage command to be output by the converter 11 is calculated. By comparing this output voltage command with the carrier, an on / off command (PWM signal) for each switching element of the converter 11 is generated.

In this embodiment, when a DC voltage imbalance occurs and the above-described alarm generation command is output, the gain adjustment unit 51 sets the gain of the PI adjustment unit 53 that calculates the input current command to the DC voltage imbalance. Switch to a dedicated gain set to suppress.
As the gain adjustment method of the PI adjustment means 53 by the gain adjustment means 51, the converter 11 can be adjusted more than the normal time when no DC voltage imbalance occurs by increasing the proportional gain, reducing the integration time constant, or the like. You can speed up the response. The reason will be described below.

As a factor that causes the DC voltage imbalance, except when a failure occurs somewhere in the apparatus, there is a case where a load in which a positive / negative asymmetric current flows, such as a half-wave rectified load, is connected. This balance imbalance of the DC voltage changes the sum of the current flowing to the DC midpoint N _D, but the state in which the DC voltage of each capacitor is balanced is maintained when the sum is 0 When flows asymmetrical positive and negative currents, the sum of the current flowing to the DC midpoint N _D since shifted in either positive or negative, in order to become leading to a DC voltage imbalance.

Generally, a converter keeps a DC voltage constant by operating so as to flow a sine wave current having a power factor of 1 with respect to an input voltage. Basically, since the input current does not match the load-side current, the input power does not match the output power when viewed from the instantaneous power, but the average value for one cycle operates so as to match the DC voltage. Can be controlled to be constant.
Therefore, when connecting a half-wave rectified load in the load of the inverter 12, the input side is a positive-negative symmetrical current, the output side becomes to flow asymmetrical positive and negative currents, the current flowing into the DC midpoint N _D Since the sum is shifted from 0, the DC voltage is unbalanced easily.

As shown in FIG. 4, when the gain control means 51 is used to increase the response of the converter control, the input / output instantaneous powers coincide with each other. This indicates that the input current waveform approaches the output current waveform when the response of the converter control is increased. Further, if the input current waveform is the same, even asymmetrical positive and negative currents, the sum of the current flowing through the DC midpoint N _D is zero. This indicates that the DC voltage imbalance can be suppressed by increasing the response of the converter control.
However, the function of “converting the input current to a sine wave”, which is the original purpose of the converter, is sacrificed, but in this embodiment, the operation of the device can be continued by minimizing the converter control response. And reliability can be improved.

If the converter control means as shown in FIG. 4 is used, the DC voltage imbalance can be suppressed by increasing the response of the converter control when a predetermined condition is satisfied.
However, there is a certain limit to the range that can be handled by converter control. If a half-wave rectifying load larger than expected is connected, or if a part of the device fails and the DC voltage imbalance suppression function operates normally. If this is not the case, the DC voltage imbalance cannot be suppressed, and the operation cannot be continued. The invention of claim 1 solves this problem, and is specifically as follows.

That is, in the DC voltage imbalance monitoring means shown in FIG. 3, the absolute deviation values of the voltages E _D1 and E _D2 of the capacitors C _D1 and C _D2 exceed the second reference value (> first reference value). In this case, the second comparing means 24 outputs a bypass switching command.
When the bypass switching command is input to the bypass circuit switching means 40 in FIG. 2, the bypass time switching means 40 turns off the switch SW ₁ of FIG. 1, and outputs an on-off command as to turn on the switch SW ₂ At the same time, an inverter control operation switching command for switching the inverter power supply to the bypass power supply is output.

It should be noted that the failure collective signal input to the bypass circuit switching means 40 in FIG. 2 has conventionally existed, and this failure collective signal is obtained by collectively collecting overvoltage detection signals and overcurrent detection signals of each part of the apparatus. This is for switching the inverter power supply to the bypass power supply when it occurs.
However, this embodiment is different from the prior art in that it switches to bypass power supply even when a DC voltage imbalance occurs. That is, with respect to the prior art, only the condition for switching to bypass power supply has changed, and the operation itself of the bypass circuit switching means 40 is not changed.

  As described above, the cause of the DC voltage imbalance is that the DC voltage imbalance suppressing means is connected to a load in which a positive / negative asymmetric current such as a half-wave rectified load is connected. It is conceivable that normal operation is impossible. In any case, once power supply from the inverter 12 to the load is stopped and switched to power supply from the bypass circuit 15, the factor causing the DC voltage imbalance is removed and the imbalance is settled.

However, since it is possible to use the bypass circuit 15 in the uninterruptible power supply in an emergency, it is bypassed when the DC voltage imbalance cannot be suppressed even if the converter 11 control operation is changed by means as shown in FIG. You may make it switch to electric power feeding. Eventually, after the predetermined condition is satisfied, the operation of the apparatus can be continued by automatically switching to the power supply from the inverter 12 again.
As described above, according to the first embodiment, the operation as the uninterruptible power supply can be continued even when a DC voltage imbalance occurs without using the power of the storage battery as in the cited document 3. .

  Furthermore, after detecting DC voltage imbalance and switching to power supply from bypass circuit 15, it is determined what causes DC voltage imbalance has occurred and whether switching to inverter power supply is okay. Thus, the idea of further improving the reliability of the apparatus is the invention of claim 2 and later, which will be described in detail below.

  FIG. 5 is a block diagram showing a second embodiment of the present invention, and corresponds to the invention according to claims 2 to 4. Also in the second embodiment, the DC voltage imbalance monitoring means 20 shown in FIG. 2, the internal configuration of the monitoring means 20 shown in FIG. 3, the converter control means shown in FIG. 4, and the like can be provided.

In FIG. 5, the load current analyzing means 60 detects the load current after the DC voltage imbalance has occurred and switched to the power supply state from the bypass circuit 15, and analyzes the waveform. When it is determined that the load is not a load that causes DC voltage imbalance, such as a half-wave rectifying load, a switching permission signal is sent to the inverter power supply switching means 70. The switching換許friendly signal inverter power supply switching means is input 70 turns on the switch SW ₁ in FIG. 1, and outputs an on-off command for turning off the switch SW _2, back from the bypass feeding state to the inverter power supply state.

On the other hand, if it is determined from the analysis result by the load current analysis means 60 that a DC voltage imbalance has occurred due to the load, an alarm generation command based on the determination result is sent to the alarm generation means 30, and the voice generation is performed in the same manner as described above. An alarm is generated by an information or monitor display to alert the user and take countermeasures.
Note that the inverter power supply switching means 70 in FIG. 5 is a means for executing various processes for switching from the bypass power supply state to the inverter power supply state, and may have the same function as a general uninterruptible power supply.

According to the second embodiment, when an unexpected transient DC voltage imbalance occurs due to an external factor such as a load change, the power supply is once switched to bypass power supply and the DC voltage imbalance is settled. By automatically switching to inverter power feeding, power feeding from the uninterruptible power supply to the load can be stably continued. On the other hand, when a DC voltage imbalance occurs due to the type of load, it is possible to notify the user of the cause and take a countermeasure and then return to normal operation.
In any case, according to the present embodiment, the reliability of the apparatus can be greatly improved.

Next, FIG. 6 is a configuration diagram of the load current analyzing means 60.
U, V, and W phase load current waveforms are acquired inside the control device by current detection means such as DCCT (direct current transformer). The detected load current waveform is input to a low-pass filter 61 _U , 61 _V , 61 _W having a large time constant to extract a DC component, and its absolute value is calculated by absolute value calculation means 62 _U , 62 _V , 62 _W , respectively. .

Next, the outputs of the absolute value calculation means 62 _U , 62 _V , 62 _W are input to the comparison means 63 _U , 63 _V , 63 _W of the respective phases given a common reference value, and these comparison means 63 _U , The outputs of 63 _V and 63 _W are input to the logical sum means 64.
The output of the logical sum means 64 is input to the first logical product means 65 together with the enable signal. Here, the output enable signal is a signal for controlling the external output permission of the alarm generation command and the inverter power supply switching permission signal, for example, after a predetermined delay time has elapsed since switching to bypass power feeding due to DC voltage imbalance. It is a signal that is effective in one shot.
Further, the output of the logical sum means 64 is input to the second logical product means 67 via the negation means 66. An output enable signal is also input to the logical product means 67, and the output of the logical product means 67 is an inverter power supply switching permission signal.

With the above configuration, when the absolute value of the DC component of any of the three phases exceeds the reference value and the output enable signal is valid, an alarm generation command is output, and the absolute value of the DC component is When it is below the reference value, an inverter power supply switching permission signal can be output.
The above operation is for preventing the alarm generation command or the inverter power supply switching permission signal from being output at unnecessary timing, and the delay time corresponds to the time required for analyzing the load current, that is, extracting the DC component. That is, for example, a DC voltage imbalance occurs when a positive and negative asymmetric load current flows, so that the load current is analyzed using the presence or absence of the DC component of the load current.

Next, FIG. 7 is a block diagram showing a third embodiment of the present invention, and corresponds to the invention according to claim 5. Since the basic configuration in FIG. 7 is the same as that in FIG. 2, the difference from FIG. 2 will be mainly described here.
In this embodiment, converter control means including alarm generating means 30 in FIG. 2 and gain adjusting means 51 as shown in FIG. 4 can be provided.

  In FIG. 7, the counter 80 counts the number of times that DC voltage imbalance has occurred and switching to bypass power feeding has been performed. This count value is sent to the failure determination means 90, and when the count value exceeds the reference number within a predetermined time, an apparatus stop command is output to stop the operation of the uninterruptible power supply. Note that the failure determination unit 90 clears the count value of the counter 80 every time the predetermined time elapses.

  The third embodiment is intended to cope with a case where an abnormality occurs in the apparatus and the DC voltage imbalance suppressing means cannot operate normally. In this case, after detecting the DC voltage imbalance and switching to the bypass power supply, no abnormality is detected even if the load current analyzing means 60 in FIG. 5 analyzes the load current. A command to return to the inverter power supply is generated.

However, even if the inverter power supply is restored, the DC voltage imbalance suppression means still cannot operate normally, so the DC voltage imbalance is detected again. As a result, the switching operation between the inverter power supply state and the bypass power supply state is performed. Will be repeated.
Therefore, in this embodiment, when switching to bypass power supply due to DC voltage imbalance frequently occurs in a short time, there is some failure in the device, and it is dangerous to continue operation in this state, so the device The operation is stopped.

As described above, according to each embodiment, in the uninterruptible power supply using a three-level converter, when a DC voltage imbalance occurs, it is possible to perform an optimal treatment according to the generation factor. This greatly contributes to improving the reliability of the apparatus. Further, the present invention can be realized by changing a program mounted on the CPU in the control apparatus, and it is advantageous in terms of cost because it does not require addition of hardware.
Furthermore, since the power of the storage battery is not used as in Patent Document 3 described above, there is an advantage that the backup operation by the inverter is not adversely affected during a power failure of the AC power supply.

10: uninterruptible power supply 11: 3-level converter 12: 3-level inverter 13: chopper 14: DC unit 15: bypass circuit 20: DC voltage imbalance monitoring means 21: subtraction means 22: absolute value calculation means 23, 24: comparison means 30: alarm unit 40: bypass circuit switching means 51: gain adjustment means 52: subtraction means 53: PI regulating unit 54: current control unit 60: load current analysis means _{61 U, 61 V, 61 W} : a low-pass filter 62 _U , 62 _V , 62 _W : absolute value calculation means 63 _U , 63 _V , 63 _W : comparison means 64: logical sum means 65 and 67: logical product means 66: negation means 70: inverter power supply switching means 80: counter 90: failure Discriminating means C _D1 , C _D2 : DC capacitor N _D : DC midpoint SW ₁ , SW ₂ : Switch

Claims (4)

A converter for converting an AC input voltage into a DC voltage and outputting the DC voltage, wherein a plurality of capacitors are connected in series between the positive and negative electric circuits of the DC unit, and a positive potential and a negative potential with reference to a midpoint potential of the series circuit of the capacitors. A three-level converter that generates
A three-level inverter connected to the converter via the DC unit and outputting any one of the positive potential, negative potential, and midpoint potential for each phase and supplying an AC voltage having an arbitrary amplitude and frequency to a load When,
A bypass circuit for supplying an alternating voltage to the load instead of the inverter;
In a control device for controlling an uninterruptible power supply comprising
When the deviation between the magnitude of the positive potential with respect to the midpoint potential and the magnitude of the negative potential exceeds a reference value, switching from feeding to the load by the inverter to feeding to the load by the bypass circuit Means ,
Load current analysis means for analyzing the waveform of the current flowing through the load,
After switching from feeding to the load by the inverter to feeding to the load by the bypass circuit,
The load current analyzing means generates a switching permission signal for switching again from power supply to the load by the bypass circuit to power supply to the load by the inverter according to the analysis result of the waveform of the load current. Uninterruptible power supply controller. In the uninterruptible power supply control device according to claim 1,
Control device for uninterruptible power supply according to claim Rukoto to generate an alarm when not generate the switching換許enable signal. In the control apparatus of the uninterruptible power supply according to claim 1 or 2,
The load current analysis means, the control device of the uninterruptible power supply characterized that you generate the switching換許permission signal when the DC component of the load current is below the reference value. In the uninterruptible power supply control device according to claim 1 ,
Means for counting the number of switching times switched from power feeding to the load by the inverter to power feeding to the load by the bypass circuit;
Means for determining that the device has failed when the number of counts within a predetermined time of the number of switching times exceeds a reference number, and stopping the operation of the device;
Control device for uninterruptible power supply comprising the.

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