JP5591188B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device, and more particularly to a power conversion device having a configuration in which a single-phase inverter is further connected in series to an AC terminal of a three-level inverter.

  In the three-level inverter, the number of voltage levels that can be output to the AC terminal side is larger than that in the two-level inverter. For this reason, it has the feature that the harmonic component contained in the output voltage can be suppressed without increasing the switching frequency, and is often adopted as a main circuit system of a large capacity inverter. Since the three-level inverter outputs positive, zero, and negative voltage pulses, two voltage dividing capacitors for dividing the voltage Vdc on the DC bus are connected in series. The voltage Vc0 divided by the voltage dividing capacitor is 0.5 Vdc with respect to the voltage Vdc. If this divided voltage of 0.5 Vdc is taken as a reference (zero), a positive voltage is output when Vdc is output, and a negative voltage is output when 0 is output.

  By the way, it includes a three-level inverter that generates positive, zero, and negative voltage pulses on the AC terminal side, and further increases the number of AC-side output voltage levels on the AC-side output terminal of the three-level inverter. Furthermore, an inverter device having a configuration for connecting a single-phase inverter (hereinafter referred to as a three-level gradation control inverter) is known. In such a three-level gradation control inverter, switching in a low pulse mode such as one pulse or three pulses is performed in the three-level inverter, and the difference between the voltage command and the three-level inverter output voltage is output in the single-phase inverter. High-speed switching can be performed, and a relatively accurate output voltage can be output as the entire inverter device.

  Further, as the configuration, a high-voltage switching element is used for the three-level inverter, and a switching element that has a low switching loss but is capable of high-speed switching is used for the single-phase inverter. Since the switching element with high withstand voltage has a relatively large switching loss, the main circuit is operated by operating with a pulse command in a low pulse mode such as 1 pulse or 3 pulses, and outputting the difference from the sinusoidal voltage command to the single-phase inverter. It is possible to reduce the loss of the entire unit and improve the accuracy and update speed of the AC output voltage. In a simple three-level inverter, it is necessary to increase the switching frequency in order to improve the AC side output voltage accuracy. Therefore, in a three-level gradation control inverter, compared with a three-level inverter having the same capacity and the same output voltage accuracy. It has the feature of high power conversion efficiency.

  Hereinafter, the potential divided by the voltage dividing capacitor is referred to as a neutral point voltage Vc0. The voltage at the connection point (neutral point) between the voltage dividing capacitors is due to various factors such as unbalanced switching pulses and variations in the capacitance of the voltage dividing capacitor, and the voltage balance between both capacitors is lost and the neutral point voltage Vc0 varies. Occur. This causes distortion in the output voltage of the inverter device. In addition, it is not desirable that a voltage exceeding the breakdown voltage of the voltage dividing capacitor or the switching element is applied, and measures are taken to equalize the voltages of both voltage dividing capacitors. This applies not only to a simple three-level inverter but also to a three-level gradation control inverter. As a countermeasure, for example, as this specific method, the polarity of the output current of the three-level inverter is detected, and the one-pulse command to the three-level inverter is adjusted together with the difference voltage information of the voltage dividing capacitor voltage. By adjusting the point voltage (zero voltage pulse) output section, the neutral point voltage Vc0 is controlled to equalize the voltage burden of the voltage dividing capacitor (for example, see Patent Document 1).

  Similarly, for the purpose of neutral point voltage control of the three-level inverter, a balance circuit composed of a switch and a discharge resistor is connected in parallel with each voltage dividing capacitor, and the voltage burden of both voltage dividing capacitors is There is a battery that discharges by turning on the switch of the large balance circuit to equalize the voltage burden. In this technique, neutral point voltage control can be performed independently of the one-pulse command to the three-level inverter, and the equalization of the voltage burden on the voltage dividing capacitor can be achieved quickly (for example, see Patent Document 2).

Japanese Unexamined Patent Publication No. 7-75345 JP-A-5-244702

  The conventional patent document 1 is configured as described above, detects the polarity of the output current of the three-level inverter, and sends a switching command to the three-level inverter together with the voltage difference information of the voltage dividing capacitor voltage. Since the neutral point voltage is controlled by adjusting, the voltage sharing of the voltage dividing capacitor is equalized, distortion of the output voltage of the three-level inverter is suppressed, and the application of a voltage exceeding the withstand voltage to the switching element is prevented. Can be realized. However, when the method of detecting the polarity of the output current of the three-level inverter is applied to the three-level gradation control inverter, there are problems as described below. For example, if the polarity of the output current is used as a reference, the current polarity may be erroneously discriminated due to noise contained in the detected current, and the pulse command to the three-level inverter may be disturbed, and neutral point voltage control may not be performed satisfactorily. . Therefore, it may not be possible to stably control the voltage sharing of the voltage dividing capacitors to be equal, and the power converter may not operate stably. In particular, since a three-level gradation control inverter performs a high-speed switching operation in a single-phase inverter, switching noise becomes significant and the influence becomes large.

  In addition, a balance circuit composed of a switch and a discharge resistor is connected in parallel with the voltage dividing capacitor shown in Patent Document 2, and the switch of the balance circuit on the side where the voltage burden is large is turned on to discharge the voltage dividing capacitor. When what is performed is applied to a three-level gradation control inverter, neutral point voltage control can be realized stably regardless of the above-described current control system and its response characteristics, but a neutral point voltage control balance circuit. There is a problem that a loss due to the discharge resistance occurs and the power conversion efficiency, which is a merit of the three-level gradation control inverter, is impaired.

  The present invention has been made to solve the above-described problems, and provides a power conversion device that can be stably controlled so that the voltage sharing of the voltage dividing capacitors is equal, has low power loss, and operates stably. The purpose is to obtain.

In the power converter according to the present invention,
A power conversion device including a gradation control inverter that generates a total voltage of an AC side generated voltage of a three-level inverter and a single phase inverter on an AC side, and a control device that controls the gradation control inverter,
The three-level inverter is connected to a DC power source divided by the first and second voltage dividing capacitors and converts DC power to AC power.
The single-phase inverter has a capacitor and a single-phase inverter circuit, the DC side of the single-phase inverter circuit is connected to the capacitor, and the AC side is connected in series to the AC side of the three-level inverter.
The control device is configured to make the voltage sharing of the first and second voltage dividing capacitors equal based on the power output from the three-level inverter and the voltages of the first and second voltage dividing capacitors. A switching command is issued to the three-level inverter.

This invention
A power conversion device including a gradation control inverter that generates a total voltage of an AC side generated voltage of a three-level inverter and a single phase inverter on an AC side, and a control device that controls the gradation control inverter,
The three-level inverter is connected to a DC power source divided by the first and second voltage dividing capacitors and converts DC power to AC power.
The single-phase inverter has a capacitor and a single-phase inverter circuit, the DC side of the single-phase inverter circuit is connected to the capacitor, and the AC side is connected in series to the AC side of the three-level inverter.
The control device is configured to make the voltage sharing of the first and second voltage dividing capacitors equal based on the power output from the three-level inverter and the voltages of the first and second voltage dividing capacitors. Since it issues a switching command to the 3-level inverter,
A power conversion device that operates stably with low power loss can be obtained.

It is a block diagram which shows the structure of the 3 level gradation control inverter which is Embodiment 1 of this invention. It is a block diagram which shows the detailed structure for 1 phase of the 3 level inverter of FIG. It is a block diagram which shows the detailed structure of the single phase inverter of FIG. It is a block diagram which shows the structure of a neutral point voltage control part. It is a block diagram which shows the structure of a 1 pulse switching control part. It is explanatory drawing for demonstrating the process which produces | generates 1 pulse command. It is explanatory drawing for demonstrating sharing of the output voltage of a 3 level inverter and a single phase inverter. It is explanatory drawing for demonstrating sharing of the output voltage of a 3 level inverter and a single phase inverter. It is explanatory drawing for demonstrating pulse width control and pulse phase control. FIG. 5 is a configuration diagram illustrating a configuration of a three-level gradation control inverter according to a second embodiment. It is a block diagram which shows the structure of a balance circuit control part. It is a block diagram which shows the structure of a balance circuit.

Embodiment 1 FIG.
1 to 9 show a first embodiment for carrying out the present invention. FIG. 1 is a configuration diagram showing a configuration of a three-level gradation control inverter, and FIG. 2 is a one-phase portion of the three-level inverter. It is a block diagram which shows detailed structure of these. FIG. 3 is a block diagram showing the detailed configuration of the single-phase inverter, FIG. 4 is a block diagram showing the configuration of the neutral point voltage control unit, and FIG. 5 is a block diagram showing the configuration of the one-pulse switching control unit. FIG. 6 is an explanatory diagram for explaining a process of generating a one-pulse command. 7 and 8 are explanatory diagrams for explaining output voltage sharing between the three-level inverter and the single-phase inverter, and FIG. 9 is an explanatory diagram for explaining the pulse width control and the pulse phase control. In FIG. 1, a three-level gradation control inverter 100 as a power converter is configured as follows. The three-level gradation control inverter 100 is mainly composed of a main circuit unit 200 that performs power conversion operation and an inverter control unit 300 as a control device. The main circuit unit 200 includes a three-level inverter 1, a single-phase inverter 2, and a voltage dividing capacitor device 3. Three-level gradation control inverter 100 generates a total voltage of the AC side generated voltages of three-level inverter 1 and single-phase inverter 2 on the AC side. In the voltage dividing capacitor device 3, the P-side and N-side capacitors 3 a and 3 b as the first and second voltage dividing capacitors having the same specifications such as the capacity are connected to a connection point 3 c (hereinafter sometimes referred to as a neutral point 3 c). Are connected in series. The P-side and N-side capacitors 3a and 3b connected in series are connected in parallel to the DC power source 4 via the DC bus 39, and the DC voltage of the DC power source 4 is divided into about 1/2 each with the connection point 3c. Press. A plus sign is attached to the plus side DC bus 39 and a minus sign is attached to the minus side DC bus 39.

  The three-level inverter 1 has a circuit configuration as shown in FIGS. 2A and 2B, for example, for one arm (the figure shows one phase), and is configured by a semiconductor switching element. The switches A to D are connected as shown. That is, in FIG. 2A, the series circuit of the switches A to D is connected in parallel to the voltage dividing capacitor device 3, and the DC side terminal 1a is connected to the connection point 3c of the capacitors 3a and 3b constituting the voltage dividing capacitor device 3. It is connected. A series circuit of diodes D1 and D2 is connected in parallel to the series circuit of switch B and switch C. A connection point between the diodes D1 and D2 is connected to the DC side terminal 1a, and a connection point between the switch B and the switch C is connected to the AC side terminal 1b.

  In FIG. 2B, a series circuit of a switch A and a switch B is connected in parallel to the voltage dividing capacitor device 3, and a connection point between the switch A and the switch B is connected to the AC side terminal 1b. The connection point between the switch A and the switch B is connected to the DC side terminal 1a through a series circuit of the switch C and the switch D. The DC side terminal 1 a is connected to a connection point 3 c between the P side and N side capacitors 3 a and 3 b constituting the voltage dividing capacitor device 3. Here, assuming that the voltage of the DC bus 39 is Vdc, the switches A to D for outputting positive (Vdc), zero (0.5 Vdc), and negative (0) voltages are shown in FIG. In this case, the circuit is turned on / off as shown in FIG. 2C, and in the case of the circuit shown in FIG. 2B, it is turned on / off as shown in FIG. The neutral point voltage (voltage between the connection point 3c and the DC bus 39 on the negative electrode side) Vc0 fluctuates due to the current at the time of zero voltage output of the three-level inverter 1. For example, as shown in FIG. 2A, when a current is output from the AC side terminal 1b, a current flows through a path indicated by an arrow in FIG. 2A, and the neutral point voltage Vc0 decreases. When the polarity of the current is reversed, the neutral point voltage Vc0 increases.

  One AC terminal 2a (FIG. 3) of the single-phase inverter 2 is connected to the three AC-side terminals 1b (FIG. 2) of the three-level inverter 1, and the single-phase inverter 2 compensates for the output voltage of the three-level inverter 1. The operation is as follows (details will be described later). A three-phase AC power source 8 as a load is connected to the other AC terminal 2 b of each single-phase inverter 2. The DC power source 4 includes a power storage / power generation device such as a battery, a capacitor unit, or a solar cell, and a DC / DC converter that adjusts a voltage level to connect them. Further, although other devices such as a connecting transformer and a reactor are provided, the illustration is omitted. In the example shown in FIG. 1, one single-phase inverter 2 is connected per phase, so there are three units in total for three phases. However, a plurality of single-phase inverters 2 per phase are intended to improve the accuracy of the output voltage on the AC side and expand the output voltage range. Sometimes single-phase inverters are connected in series. The single-phase inverter 2 is configured as shown in FIG. That is, the single-phase inverter 2 is constituted by a single-phase inverter circuit in which four switching elements A to D constituted by semiconductor switching elements are connected to a single-phase full bridge as shown in the figure, and a built-in capacitor 2c as a capacitor. Has been. A built-in capacitor 2c is connected to the DC side of the single-phase inverter circuit, and the AC side of the single-phase inverter circuit is connected to the AC terminal 2a and the AC terminal 2b. If the built-in capacitor 2c is charged with the polarity as shown in FIG. 3 (the upper side in the figure is + polarity), the switching element A in FIG. 3 is turned on when the output voltage command to the single-phase inverter 2 is positive. Switching element B is turned off, and switching elements C and D are repeatedly turned on and off at high speed by PWM. When the output voltage command is negative, the on / off relationship of the switching elements A and B is reversed.

  Note that the output voltage command to the single-phase inverter 2 is a voltage command V2 (see V2 in FIG. 6) to be output by the single-phase inverter 2, and should be output from the three-level gradation control inverter 100 described later. This is a value obtained by subtracting a one-pulse waveform V1 (equivalent to one-pulse command S16 described later) output from the three-level inverter 1 from the voltage Vref (voltage command S14). In addition, the main circuit unit 200 includes a current detection unit 5 that detects the output current of the three-level gradation control inverter 100, and a voltage detection unit 6 that detects the voltages VcP and VcN of the P-side and N-side capacitors 3a and 3b. Is provided. Although not shown, a voltage detector for detecting the voltage of the built-in capacitor 2c (FIG. 3) built in the single-phase inverter 2 is also provided. Such control of the three-level gradation control inverter 100 also requires voltage detection of the three-phase AC power supply 8, but illustration thereof is omitted.

  Next, returning to FIG. 1, the configuration of the inverter control unit 300 will be described. In FIG. 1, an inverter control unit 300 includes a current control unit 11, a current command unit 12, a one-pulse switching control unit 15, a single-phase inverter switching control unit 17, a neutral point voltage control unit 21 as a switching command adjustment unit, a limit A value calculation unit 23 is included. The current control unit 11 performs processing using the detected current signal S10 so that the input / output current of the three-level gradation control inverter 100 matches the current command S13 output from the current command unit 12, and the voltage command S14 (Vref ) Is output. In the present embodiment, the three-level inverter 1 performs one-pulse switching, but the same is true in other pulse modes. The 1-pulse switching control unit 15 performs a 3-level inverter 1 pulse command S16 (hereinafter referred to as a switching command to the 3-level inverter 1) based on the voltage command S14 and the voltage signal S19 (voltages of the P-side and N-side capacitors 3a and 3b). 1 pulse command S16) is generated and output to the 3-level inverter 1.

  As shown in FIG. 6, the 1-pulse command S16 has a voltage of V1, and is output every half cycle, rising at timing (time) t1, falling at timing t2, rising at timing t3, and falling at timing t4. The switches A to D of the three-level inverter 1 are on / off controlled by this one-pulse command S16. That is, when the voltage command S14 (Vref), which is a sinusoidal AC output voltage command, is greater than a predetermined value, the voltage of one pulse that falls when the rising voltage command S14 is less than the predetermined value is the AC output voltage. One pulse command S16 is transmitted so as to output one voltage pulse every half cycle of the command, and the three-level inverter 1 is controlled. The one-pulse command S16 is a voltage pulse that is positive in the period T1 and negative in the period T2. The voltage V1 will be described later. Although details will be described later, the actual generation of the one-pulse command S16 is performed by referring to timing instead of the amplitude comparison as described above.

  Further, the single-phase inverter switching control unit 17 obtains a difference ΔVref between the voltage command S14 and the one-pulse command S16 as shown in FIG. 6, and a voltage command V2 (= ΔVref) for the single-phase inverter 2 based on the difference ΔVref. Further, a PWM control signal is generated by PWM processing based on carrier comparison, and is output as a single-phase inverter switching command S18. By adding the output voltage of the three-level inverter 1 and the output voltage V2 (ΔVref) of the single-phase inverter 2, the sine wave output voltage Vout (= Vref) corresponding to the voltage command S14 is converted into the three-level gradation control inverter 100. Is output from. In the three-level gradation control inverter 100, the voltage of the built-in capacitor 2c of the single-phase inverter 2 is maintained by the power supplied from the three-level inverter 1. For this reason, the total value of the active power exchanged with the three-phase AC power supply 8 and the power required by the single-phase inverter 2 is output from the one-pulse switching control unit 15 so as to be equal to the input or output power of the three-level inverter 1 The width of the pulse command S16 is determined.

  Further, the neutral point voltage control unit 21 will be described with reference to FIG. In FIG. 4, the neutral point voltage control unit 21 includes a subtractor 21a, an LPF (low pass filter) 21b, and an amplifier 21c. The voltage VcP of the P-side capacitor 3a and the voltage VcN of the N-side capacitor 3b are input to the subtractor 21a as the voltage signal S19, and the difference is taken. One pulse command adjustment signal S22 is output by the proportional control by the amplifier 21c via the LPF 21b. The one-pulse switching control unit 15 adjusts the one-pulse command S16 based on the one-pulse command adjustment signal S22 (details will be described later). When the neutral point voltage Vc0 is lower than ½ of the bus voltage Vdc, the one-pulse command adjustment signal S22 is positive. The neutral point voltage Vc0 is a constant value on average, but pulsates as an instantaneous value, and the LPF 21b has a function of removing this pulsation. This pulsation is often synchronized with the output current of the three-level inverter 1, and the sample hold may be performed at the timing of the current polarity inversion or the magnitude inversion for each phase. The voltage of the voltage dividing capacitor device 3 has characteristics equivalent to integration with respect to the passing currents of the P-side and N-side capacitors 3a and 3b. By adjusting the one-pulse command S16 to the three-level inverter 1 with the one-pulse command adjustment signal S22, the energization period that contributes to the change in the neutral point voltage Vc0 of the switches A to D of the three-level inverter 1 is changed.

  Although there is a section that does not contribute to the change of the neutral point voltage Vc0 in the control of the three-level inverter 1, it cannot be said to be a pure integration characteristic, but the difference voltage between the P-side and N-side capacitors 3a and 3b is a characteristic corresponding to the integration. Can be considered as having For this reason, when the neutral point voltage control unit 21 performs proportional control, the closed loop transfer function of the neutral point voltage control system becomes a first-order lag system, and stable control can be achieved. Further, the voltage change of the P-side and N-side capacitors 3a and 3b becomes larger as the energization current becomes larger. For this reason, the fluctuation of the control response of this neutral point voltage control can be suppressed by changing the gain of the proportional control according to the magnitude of the current. Specifically, the gain is set smaller as the energization current is larger. Therefore, the current command S13 (FIG. 1) from the current command unit 12 is input to the amplifier 21c (FIG. 4) of the neutral point voltage control unit 21, and the gain is adjusted according to the magnitude of the current command S13. ing.

  Next, the operation of the limit value calculation unit 23 (FIG. 1) will be described with reference to FIG. The voltage command S14 is positive, and the explanation will be made by taking as an example the positive voltage rising portion of the one-pulse command S16 to the three-level inverter 1. If the voltage drop at the switches A to D is ignored, the amplitude V1p (corresponding to the voltage signal S19) of the output voltage pulse (positive) of the three-level inverter 1 becomes the voltage VcP of the P-side capacitor 3a. The amplitude V2p (corresponding to the voltage signal S20) of the output voltage of the single-phase inverter 2 is added to the amplitude V1p of the output voltage (positive) of the three-level inverter. That is, the voltage range that can be output as the three-level gradation control inverter 100 is a range obtained by adding or subtracting the amplitude V2p of the output voltage of the single-phase inverter 2 to the zero voltage 0 of the three-level inverter 1, or the positive level of the three-level inverter 1 This is a range obtained by adding or subtracting the amplitude V2p of the output voltage of the single-phase inverter 2 to the amplitude V1p of the current. In order to satisfy the voltage command S14, the one-pulse command S16 is raised within a range T11 between a timing ta and a timing tb (described later) shown in FIG. In the limit value calculation unit 23, the timing at the intersection of the voltage (amplitude) V2p and the voltage command S14 (Vref) is the timing ta, the voltage obtained by subtracting the voltage V2p from the voltage (amplitude) V1p, and the voltage command S14 (Vref). Is obtained as a timing tb, and is output as a limit signal S24.

  Next, the 1-pulse switching control unit 15 will be described with reference to FIG. The 1-pulse switching control unit 15 includes a power calculation unit 15a, a 1-pulse phase timing control unit 15b, and R, S, and T-phase pulse generation units 15c. Each pulse generation unit 15c includes a limiter 15e and a one-pulse switching waveform generation unit 15f. The power calculation unit 15a inputs the current command S13 (FIG. 1) from the current command unit 12 and the voltage command S14 from the current control unit 11, and obtains active power and reactive power input / output by the three-level inverter 1. In the 1-pulse phase timing control unit 15b, as described above, the total value of the power required by the single-phase inverter 2 and the active power exchanged with the three-phase AC power supply 8 becomes equal to the input or output power of the three-level inverter 1. As described above, the 1-pulse switching reference timing S33 (t1, t2, etc.) serving as the rise and fall timings of the 1-pulse command S16 is output from the voltage signal S19 (VcP, VcN) of the P-side and N-side capacitors 3a, 3b. .

  This is the result of integrating the product of the current command S13 and the one-pulse output voltage V1 (one-pulse command S16) over one cycle of the voltage command to calculate the average value, which is the active power input or output by the three-level inverter 1 Based on the principle of equality. Therefore, the current command S13, the voltage signal S19 (VcP, VcN) of the P-side and N-side capacitors 3a, 3b, and the active power are input to the one-pulse phase timing control unit 15b. When the neutral point voltage Vc0 is 0.5 Vdc, the adjustment of the one-pulse command S16 described later is unnecessary, and the control is performed using the one-pulse switching reference timing S33 (t1, t2, etc.) as it is. When neutral point voltage control is required, the 1-pulse phase timing control unit 15b further adjusts the 1-pulse switching reference timing S33 (t1, t2, etc.) so as to change the pulse width or pulse phase of the 1-pulse command S16. To do.

  This will be described with reference to FIG. In FIG. 9, the adjustment direction indicated by the arrow F or the arrow G is shown in the direction in which the neutral point voltage Vc0 is increased. FIG. 9A shows the output voltage waveform V1out of the three-level inverter 1 controlled by the one-pulse command S16 when the power factor is 1. When the pulse width is adjusted with respect to the original one-pulse command S16 derived by the above power balance, the change in the neutral point voltage Vc0 when the pulse width is adjusted is indicated by the polygonal line Vc11, and the change when the pulse width is not adjusted is indicated by the polygonal line Vc10. A change in the neutral point voltage Vc0 when the phase is adjusted is indicated by a broken line Vc12. When the pulse width is adjusted, the original timing moves in the direction of arrow F as shown in FIG. 9A, the timing t1 is t11, t2 is t21, t3 is t31, t4 Changes to t41. When the pulse phase is adjusted, the original timing moves in the direction of arrow G, and the timing t1 changes to t12, t2 changes to t21, t3 changes to t32, and t4 changes to t41. For example, the adjustment of the pulse width in the adjustment direction indicated by the arrow F increases the interval in which the current is negative and outputs zero voltage, and the neutral point voltage Vc0 increases. FIG. 9B is a similar diagram, but here the power factor is 0, and the neutral point voltage Vc0 is increased by adjusting the pulse phase. That is, the one-pulse command adjustment method effective for controlling the neutral point voltage Vc0 differs depending on the power factor. In the 1-pulse phase timing control unit 15b (FIG. 5), a 1-pulse command adjustment method is selected according to the power factor of the 3-level inverter 1. As a simpler method, determination may be performed by comparing active power and reactive power instead of the power factor. Specifically, pulse width control is performed when the active power is greater than the reactive power, and pulse phase control is performed when the active power is opposite. The adjustment amount of the pulse width or pulse phase follows the one-pulse command adjustment signal S22.

  If the one-pulse switching reference timing is simply obtained by adjusting the pulse width or pulse phase, the original active power cannot be balanced. For example, when the power output from the three-level inverter 1 is insufficient, the 1-pulse switching reference timing S33 is adjusted so as to further widen the positive voltage pulse and the negative voltage pulse. Since the active power is not exchanged under the condition of power factor 0 shown in FIG. 9B, the balance of the active power is negligible and only the pulse phase control is performed. When the power factor is not 0, that is, when active power is transferred, it is necessary to consider the balance of the active power. The 1-pulse phase timing control unit 15b performs the above operation and outputs 1-pulse switching reference timing S33 (t1, t2, etc.).

  The limiter 15e limits the rising timing of the one-pulse command S16 within the limit signal S24 calculated by the limit value calculation unit 23. That is, the rising timing t1 of the one-pulse command S16 is limited so as to be within the range T11 of the timings ta and tb shown in FIG. Although the falling timing t2 of the one-pulse command S16 is not shown, it is similarly limited so as to be within a predetermined timing range. Based on the 1-pulse switching reference timing S33 adjusted and restricted by the limiter 15e in the above procedure, the 1-pulse switching waveform generation unit 15f generates a 1-pulse command waveform and outputs it as a 1-pulse command S16. Further, as shown in FIG. 8, the voltage (V1p−V2p) obtained by adding the amplitude V1p of the output voltage of the three-level inverter 1 and the negative maximum voltage (amplitude) (−V2p) that can be output by the single-phase inverter 2. Exceeds the command voltage S14 (Vref) to be output by the three-level gradation control inverter 100 (when the rising timing t1 is earlier (smaller) than the timing ta in FIG. 8), it is set so as not to be earlier than the timing ta. The raising timing t1 is limited. Alternatively, between the timing t1 and the timing ta (period T12), the output voltage V2 of the single-phase inverter 2 is set to 0 and the one-pulse command S16 of the three-level inverter 1 is changed to PWM control during the period T12 in FIG. Then, control is performed so that the output voltage of the 3-level inverter 1 becomes the command voltage S14 that the 3-level gradation control inverter 100 should output. At this time, the limiter 15e outputs that the limit has occurred as the limit limit instruction signal S25.

  Although the present embodiment has been described using a three-phase three-level inverter, a single-phase three-level inverter has the same effect. Even if neutral point voltage control is provided for each phase and neutral point voltage control is performed, the same effect can be obtained, but it is necessary to prevent a short circuit between phases particularly in a multi-phase inverter having three or more phases. Since it is necessary to balance the line voltage for phase balance, it is desirable to adjust the one-pulse command S16 with the same one-pulse command adjustment signal S22 in all phases. In particular, in the gradation control inverter, by adjusting the one-pulse command S16 with the same one-pulse command adjustment signal S22 in all phases, the update of the one-pulse command adjustment signal S22 is limited to one time in one voltage command cycle. As a result, the output voltage burden of the single-phase inverter is equalized in each phase. This has the effect of suppressing the imbalance of the voltage of the built-in capacitor 2c of the single-phase inverter 2, and it is possible to further suppress the decrease in output voltage accuracy of the three-level gradation control inverter.

  As described above, the P-side and N-side capacitors 3a and 3b can be stably controlled so that the shared voltages are equal, and the three-level inverter 1 and thus the three-level gradation control inverter 100 can be stably operated. . Unlike the change in the polarity of the output current of the inverter device (for example, the power conversion device of Patent Document 1), the power output from the three-level inverter changes relatively slowly. For this reason, even if a filter with a low cut-off frequency is used to remove noise from the detection signal, the phase delay due to the filter is relatively small compared to the case of current detection. As a result, it is less susceptible to detection noise. For this reason, the adjustment of the one-pulse command to the three-level inverter can be stably performed, and as a result, the neutral point voltage control can be performed stably and promptly. In particular, there is a vicious circle in which current is disturbed by neutral point voltage control, which is a problem that becomes apparent when a current control system is constructed with a three-level gradation control inverter, and further neutral point voltage control is disturbed. This can be avoided, and the stability and reliability of the entire inverter device can be improved.

  Moreover, the following problems can be solved. Not only the three-level gradation control inverter but also the inverter device is connected to a load having a particularly short electric time constant, current ripple due to switching pulses becomes significant. When the neutral point voltage Vc0 is controlled by operating the 3-level inverter in a low pulse mode (for example, 1-pulse mode) and detecting the polarity of the output current of the 3-level inverter as described in Patent Document 1. Although it is necessary to predict the current polarity in the vicinity of the on / off switching of the pulse command, the current ripple problem makes it difficult to predict and the neutral point voltage control may not be performed satisfactorily. In particular, in the three-level gradation control inverter, since a high-speed switching operation is performed in a single-phase inverter, switching noise becomes remarkable and the influence becomes large. Also, in the three-level gradation control inverter, the accuracy of the output voltage and the update speed are compared with the simple three-level inverter having the same output and the same conversion efficiency due to the operation of the single-phase inverter as described in the background section. However, the current command often fluctuates at a relatively high speed with respect to the pulse command of the relatively low pulse mode of the three-level inverter 1 in this case. Even if the current command is used as a substitute for the detected current signal, the one-pulse command to the three-level inverter is disturbed as described above.

  As another issue, when adjusting the 1-pulse command to the 3-level inverter by neutral point voltage control, the voltage that the single-phase inverter should output may exceed the output range of the single-phase inverter depending on the conditions. There was a problem that the accuracy of the output voltage on the AC side was lowered as a whole device. In addition, a three-level gradation control inverter can construct a highly responsive current control system. At this time, the output current accuracy is deteriorated due to the neutral voltage control and the inverter output current is disturbed. There is also a big disturbance in the voltage command. As a result, the one-pulse command to the three-level inverter is also disturbed, and not only the neutral point voltage control is performed well, but also a vicious circle in which the current control performance is deteriorated may occur. This problem can occur even with a simple three-level inverter having a current control system, but this problem becomes apparent in a three-level grayscale control inverter that can realize a higher current control response.

  With the configuration described above, the above problems can be solved. Then, polarity detection of the detection current can be avoided, influence on noise and ripple included in the detection current can be suppressed, and the one-pulse command S16 can be output stably, and the neutral point voltage can be controlled stably. Can do. Further, since the one-pulse command S16 is adjusted by combining the one-pulse switching control unit 15 and the limit operation by the limit value calculation unit 23, an inverter output voltage with a small error with respect to the voltage command can be secured. The control response of the neutral point voltage Vc0 is slightly reduced by limiting the rise / fall timing of the 1-pulse command S16. However, due to the error of the inverter output voltage, which is a particular problem in the 3-level gradation control inverter. A vicious circle in which current disturbance is caused and the voltage command is disturbed by the operation of the current control system can be suppressed, and the stability of the entire three-level gradation control inverter can be improved.

  In addition, as explained in the background section at the beginning of the sentence, the three-level gradation control inverter is characterized by high conversion efficiency, so it can save energy when applied to a device with a very long operating time, such as an uninterruptible power supply or a solar power conditioner. The amount is enormous. Many of such devices have a capacity of several kW to several hundred kW, and a voltage dividing capacitor having a large capacity is used. Such a large-capacitance capacitor has a large variation in actual capacitance, and there is a problem that neutral point voltage fluctuation is likely to occur, and it has been troublesome and costly such as selecting and combining parts. The control of the neutral point voltage Vc0 shown in (2) alleviates the variation allowable value, which leads to labor and cost reduction such as selecting and combining the above components.

Embodiment 2. FIG.
10 to 12 show the second embodiment, FIG. 10 is a configuration diagram showing the configuration of the level gradation control inverter, FIG. 11 is a configuration diagram showing the configuration of the balance circuit control unit, and FIG. 12 is a balance circuit. FIG. 10, the three-level gradation control inverter 500 includes a main circuit unit 600, a balance circuit operation determination unit 26, a balance circuit control unit 28, and an inverter control unit 300. The main circuit unit 600 includes a balance circuit 7 connected in parallel to the voltage dividing capacitor device 3 for neutral point voltage control. The balance circuit 7 includes P-side and N-side balance circuits 7a and 7b having the same specifications, and is connected in parallel to the P-side and N-side capacitors 3a and 3b, respectively. As shown in FIG. 12A, the P-side and N-side balance circuits 7a and 7b include a discharge resistor 71 and a discharge switch 72 connected in series with the discharge resistor 71 in order to turn the discharge resistor 71 on and off. A detailed configuration including other configurations will be described later. The inverter control unit 300 is the same as that shown in FIG. 1 although illustration of a part of the configuration is omitted. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given to the corresponding components and the description thereof is omitted.

  In general, in a three-level gradation control inverter, when adjusting one pulse command to the three-level inverter for neutral point voltage control, the adjustable amount is the built-in capacitor of the single-phase inverter (for example, the built-in capacitor 2c in FIG. 3). ) Is limited by the voltage. As described in the second embodiment, the balance circuit 7 (for example, FIG. 12A) is operated only when the adjustable range of the one-pulse command S16 is exceeded. In this way, since the operation of the balance circuit 7 is limited to only when necessary, the power loss in the built-in discharge resistor 71 can be reduced, and the merits of high-efficiency power conversion of the three-level gradation control inverter Will not be damaged. Reduction of the loss in the discharge resistor 71 has an effect of improving the efficiency of the inverter device and reducing the size of the cooling unit, and the power capacity of the discharge resistor can be reduced. Further, as described in the first embodiment, by limiting the adjustment range of the one-pulse command S16 to the three-level inverter 1, the responsiveness of the neutral point voltage control is slightly lowered, but the balance circuit 7 and the balance The addition of the circuit control unit 28 can suppress a decrease in responsiveness.

  First, the overall operation will be described with reference to FIG. In FIG. 10, the balance circuit 7 operates mainly according to the discharge switch command S <b> 31 by the operation of the balance circuit control unit 28. The 1-pulse switching control unit 15 of the inverter control unit 300 limits the rising t1 and falling timing (not shown) of the 1-pulse command S16 as shown in FIG. Alternatively, as shown in FIG. 8, the output voltage of the single-phase inverter 2 is set to 0 in a region where the rising timing t1 (or falling timing) of the one-pulse command S16 exceeds the limit, for example, between the timing t1 and the timing ta in FIG. In addition, the one-pulse command S16 of the three-level inverter 1 is changed to PWM control, and the PWM control is performed so that the output voltage V1 of the three-level inverter 1 becomes the voltage Vout (Vref) to be output by the inverter. The presence / absence of such a limiting operation is output as a limit limiting instruction signal S25.

  The balance circuit operation determination unit 26 receives the limit restriction instruction signal S25 and outputs a switching signal S27. The switching signal S27 is an instruction signal that validates the operation of the balance circuit control unit 28 when the above-described limiting operation is occurring. The balance circuit operation determination unit 26 detects a malfunction of the current control system and outputs a switching signal S27 so that the operation of the balance circuit control unit 28 is validated. There are the following cases of malfunction of the current control system. Although the amplitude of the voltage command S14 varies depending on the operation of the current control system, it is generally determined by the three-phase AC power supply 8 and the impedance therebetween, and some abnormality occurs when the amplitude of the voltage command S14 is greater than or equal to a predetermined value. Can be determined. Along with this, it can also be determined by the amplitude of the detected current signal S10 and the control deviation from the current command S13. If these signals are equal to or greater than a predetermined value or less than a predetermined value, it can be determined that there is some abnormality, and the balance circuit operation determination unit 26 Outputs a switching signal S27 so as to validate the operation of the balance circuit control unit 28. This balance circuit operation determination unit 26 further suppresses the vicious circle in which current is disturbed by neutral point voltage control described in the section of the problem to be solved by the invention, and further neutral point voltage control is disturbed. realizable.

  Next, the balance circuit control unit 28 will be described in detail with reference to FIG. The balance circuit control unit 28 includes a discharge switch command generation unit 29 and a gate block signal generation unit 30. The difference ΔVc is obtained by subtracting the voltage VcN of the N-side capacitor 3b from the voltage VcP of the P-side capacitor 3a. If the difference ΔVc is positive, the discharge of the P-side balance circuit 7a connected in parallel to the P-side capacitor 3a. A discharge switch command S31 is output to perform the operation. On the other hand, if the difference ΔVc is negative, a discharge switch command S31 is output so that the N-side capacitor 3b is discharged. That is, the discharge operation is performed by the capacitor having the higher voltage. Thereby, the voltage sharing of the P-side and N-side capacitors 3a and 3b can be made equal. Neutral voltage control is possible even when the discharge resistor 71 is energized simultaneously in the P-side balance circuit 7a and the N-side balance circuit 7b, but the DC voltage divided by the discharge resistor 71 built in the P-side balance circuit 7a. Since the voltage of the bus 39 works in a direction that prevents discharge, the discharge speed is reduced. By performing complementary operation as described above, high-speed capacitor discharge operation, that is, neutral point voltage control can be realized.

  In order to avoid unnecessary switching and chattering, the discharge switch command generation unit 29 provides a threshold value Vth1 and outputs a discharge switch command S31 with hysteresis characteristics. A discharge switch 72 (abbreviated as P-side switch in FIG. 11) of the P-side balance circuit 7a with a voltage ΔV having a predetermined width, that is, voltage Vth1 + ΔV, based on the threshold value Vth1 by the discharge switch command S31 having hysteresis characteristics. Is turned on, and the P-side discharge switch 72 is turned off at the voltage Vth1−ΔV. The same applies to the discharge switch of the N-side balance circuit (abbreviated as N-side switch in FIG. 11). The discharge switch command generation unit 29 is configured such that the switches A to D (FIG. 3) of the three-level inverter 1 and the allowable voltage of the voltage dividing capacitor device 3 and the power of the discharge switch 72 (FIG. 12) of the P-side and N-side capacitors 3a and 3b. The threshold value Vth1 is determined in consideration of a burden and the like. The maximum output amplitude of the output voltage of the three-level gradation control inverter 500 is the voltages Vcp and VcN of the P-side and N-side capacitors 3a and 3b and the voltage Vc2 of the built-in capacitor 2c of the single-phase inverter 2 (see FIG. 3). Determined by the addition of The neutral point voltage is set such that the maximum amplitude that can be output as the entire inverter device (three-level gradation control inverter 500) is less than the maximum amplitude Vdc of the voltage command S14 and a voltage that follows the voltage command S14 cannot be output. It is necessary to control. Therefore, if the lower limit allowable amplitude of the output voltage of the three-level inverter 1 obtained by subtracting the voltage Vc2 of the built-in capacitor 2c of the single-phase inverter from the maximum amplitude Vdc of the voltage command S14 is VL, the threshold value Vth1 is “Vdc−VL × 2”. It becomes. These values are estimated in advance, and the threshold value Vth1 is determined. Alternatively, the operation of the neutral point voltage control can be limited by the balance circuit by calculating the threshold value VTh1 during the actual operation and adjusting the threshold value Vth1 online, and the loss due to the discharge resistor 71 can be suppressed. .

  Further, the balance circuit control unit 28 receives the switching signal S27 from the balance circuit operation determination unit 26, and when the balance circuit operation is unnecessary, the discharge switches 72 of the P side and N side balance circuits 7a and 7b are turned off. Thus, the content of the discharge switch command S31 is switched by the command content changeover switch 35 and output. In addition, when the bias of both voltages VcP and VcN of the P-side and N-side capacitors 3a and 3b becomes remarkable, it is assumed that some abnormal state is indicated. I need to stop. For this reason, when the difference ΔVc between the voltage VcP and the voltage VcN of the P-side and N-side capacitors 3a and 3b exceeds a certain threshold value Vth2, a gate block signal is output, and the three-level inverter 1 and the single-phase inverter 2 Stop operation. This operation is performed by the gate block signal generation unit 30, which outputs the gate block signal S32 to the three-level inverter 1 and the single-phase inverter 2 to stop the operation. The threshold value Vth2 is larger than the threshold value Vth1. Unlike the discharge switch command generator 29, the gate block signal generator 30 continues to output the gate block signal S32 in order to maintain the state and continue the gate block state when the threshold Vth2 is exceeded even once. In order to protect the three-level gradation control inverter device, the three-level inverter 1 and the single-phase inverter 2 operate by giving priority to the gate block signal S32 over the respective one-pulse command S16 or single-phase inverter switching command S18.

  Next, details of the balance circuit 7 will be described with reference to FIG. FIG. 12A shows the P-side capacitor 3a and the P-side balance circuit 7a, but the N-side has the same configuration. As described above, the P-side balance circuit 7a includes the discharge resistor 71 and the discharge switch 72 for turning on / off the discharge. The discharge switch 72 is a semiconductor element such as an IGBT or MOSFET, and opens and closes in response to the discharge switch command S31. A self drive circuit 73 is connected to the discharge switch 72. The self-drive circuit 73 quickly discharges the P-side capacitor 3a to a voltage that is safe even if touched by a person such as 20 [V], for example, when the three-level gradation control inverter 500 is stopped or when an abnormality occurs. It is a circuit for making it. The voltage dividing resistor 73a and the voltage dividing resistor 73b define the voltage of the P-side capacitor 3a when the discharge is stopped. For example, when discharging is performed up to 20 [V] and the driving voltage of the discharge switch 72 is 15 [V], the ratio of the resistance value of the voltage dividing resistor 73a and the voltage dividing resistor 73b is 1: 3. When the voltage of the capacitor is 20 [V] or more, 15 [V] or more is applied to the gate portion of the discharge switch 72 and the discharge switch 72 is kept on. When the voltage of the P-side capacitor 3a falls below 20 [V], a sufficient voltage is not applied to the gate portion of the discharge switch 72, and the discharge switch 72 is turned off. At this time, the supply of power from the DC power supply 4 to the P-side and N-side capacitors 3a and 3b is stopped.

  In order to prevent power consumption in the voltage dividing resistors 73a and 73b, the voltage of the DC bus 39 is taken into consideration, and a sufficiently large resistance value, for example, 10 times the resistance value of the discharge resistor 71 is set. A Zener diode 73c connected in parallel to the voltage dividing resistor 73b is selected to have a breakdown voltage that is equal to or higher than the drive voltage of the discharge switch 72 and lower than the allowable voltage of the gate of the discharge switch 72. Prevent voltage from being applied. The photocoupler 74 operates according to the discharge switch command S31. When the discharge switch command S31 is an on command, the photocoupler 74 does not operate and the discharge switch 72 is turned on by the self-drive circuit 73 described above. Conversely, when the discharge switch command S31 is an off command, the photocoupler 74 operates and both ends of the voltage dividing resistor 73b are close to a short circuit, so that a sufficient voltage is not applied to the gate portion of the discharge switch 72 and the discharge switch 72 is discharged. Is turned off. When the inverter power supply is stopped or when the control power supply is stopped due to some abnormality, the operation of the photocoupler 74 is stopped, and the discharge switch 72 is turned on by the self-drive circuit 73 and the discharge operation is performed. With such a circuit configuration, high-speed operation such as PWM control cannot be expected for the discharge switch 72, but it is sufficient to perform the opening / closing hysteresis operation of the discharge switch 72 as shown in FIG.

  Alternatively, the balance circuit can be configured as shown in FIG. Although FIG. 12B shows the P-side capacitor 3a and the P-side balance circuit 87a, the N-side has the same configuration. The P-side balance circuit 87a has a discharge resistor 71 similar to the P-side balance circuit 7a in FIG. 12A and a discharge switch 72 for turning on / off the discharge. A gate drive circuit 81 is connected to the gate of the discharge switch 72 to operate the discharge switch 72. The self-drive circuit 83 includes a voltage dividing resistor 83a, a diode 83b, a voltage dividing resistor 83c, a Zener diode 83d, and a b-contact relay 83e such as a photo moss relay. A voltage dividing resistor 83a, a diode 83b, and a voltage dividing resistor 83c are connected in series, and a Zener diode 83d is connected in parallel to the voltage dividing resistor 83c. A connection point between the diode 83b and the voltage dividing resistor 83c is connected to the gate of the discharge switch 72 through the b contact relay 83e. The self-drive circuit 83 is connected to the gate of the discharge switch 72 via the b-contact relay 83e, and the diode 83b in the self-drive circuit 83 is sufficiently charged to the P-side and N-side capacitors 3a and 3b when the inverter device is activated. If not, current inflow from the gate drive circuit 81 or the like to the P-side and N-side capacitors 3a and 3b is blocked. The operations of the voltage dividing resistor 83a, the voltage dividing resistor 83c, and the Zener diode 83d are the same as those of the voltage dividing resistor 73a, the voltage dividing resistor 73b, and the Zener diode 73c of the P-side balance circuit 7a shown in FIG.

  As described above, when the P-side and N-side balance circuits 7a and 7b are provided in parallel with the P-side and N-side capacitors 3a and 3b, and the voltage command S14 exceeds the adjustable range of the one-pulse command of the three-level inverter 1. By operating the P-side and N-side balance circuits 7a and 7b, the neutral point voltage control with higher accuracy and higher response can be achieved together with the one-pulse command adjustment signal S22 in the first embodiment, By reducing the operation of the discharge resistor 71 of the P-side and N-side balance circuits 7a and 7b to the necessary minimum, a decrease in power conversion efficiency can be suppressed. By connecting the self-drive circuit 73 or the self-drive circuit 83, the P-side and N-side capacitors 3a and 3b are quickly discharged when the three-level gradation control inverter stops or when the control power supply fails due to some abnormality. It can be carried out. Further, since the discharge resistor 71 and the discharge switch 72 for controlling the neutral point voltage can be used for the discharge as described above, the number of parts of the three-level gradation control inverter can be reduced. That is, the neutral point voltage control of the three-level gradation control inverter can be stably performed, and the loss in the balance circuit can be suppressed to obtain a three-level gradation control inverter as a highly efficient power conversion device. Can do.

1 3 level inverter, 1a DC side terminal, 1b AC side terminal,
2 Single-phase inverter, 2a, 2b AC terminal, 2c Built-in capacitor,
3 Voltage divider capacitor, 3a, 3b P side and N side capacitor, 4 DC power supply,
5 current detector, 6 voltage detector, 7 balance circuit, 7a P side balance circuit,
7b N-side balance circuit, 8 3-phase AC power supply, 12 Current command section,
15 1 pulse switching control unit, 15a power calculation unit,
15b 1 pulse phase timing controller, 15c pulse generator, 15e limiter,
15f 1 pulse switching waveform generation unit, 17 single phase inverter switching control unit, 21 neutral point voltage control unit, 21a subtractor, 21b LPF, 21c amplifier,
23 limit value calculation unit, 26 balance circuit operation determination unit, 28 balance circuit control unit, 29 discharge switch command generation unit, 30 gate block signal generation unit, 39 DC bus,
3a P-side capacitor, 3b N-side capacitor, 71 discharge resistance,
72 discharge switch, 73 self-drive circuit, 73a voltage dividing resistor,
73b Voltage dividing resistor, 73c Zener diode, 81 Gate drive circuit,
83 Self-drive circuit, 87a P-side balance circuit,
100 3-level gradation control inverter, 200 main circuit section, 300 inverter control section, 500 3-level gradation control inverter, 600 main circuit section.

Claims (4)

A power conversion device including a gradation control inverter that generates a total voltage of an AC side generated voltage of a three-level inverter and a single phase inverter on an AC side, and a control device that controls the gradation control inverter,
The three-level inverter is connected to a DC power source divided by the first and second voltage dividing capacitors and converts DC power to AC power.
The single-phase inverter has a capacitor and a single-phase inverter circuit, the DC side of the single-phase inverter circuit is connected to the capacitor, and the AC side is connected in series to the AC side of the three-level inverter.
The control device is configured to make the voltage sharing of the first and second voltage dividing capacitors equal based on the power output from the three-level inverter and the voltages of the first and second voltage dividing capacitors. A power converter that issues a switching command to a three-level inverter. The power conversion device according to claim 1, wherein the control device adjusts rising and falling timings of the switching command based on a voltage of the capacitor of the single-phase inverter. The balance is connected to the first and second voltage dividing capacitors and discharges the first and second voltage dividing capacitors to equalize the voltage sharing of the first and second voltage dividing capacitors. Circuit,
3. The power converter according to claim 2, further comprising: a balance circuit control unit that operates the balance circuit when adjustment of a switching command to the three-level inverter exceeds an adjustable range of the switching command. . 4. The power converter according to claim 3, wherein the balance circuit control unit causes the balance circuit to discharge the first and second voltage dividing capacitors when the three-level inverter is stopped or when an abnormality occurs.

Images