JP5294759B2 - Grid-connected inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size and cost of a system-linking inverter in which a gate power source of switching elements is constituted of a bootstrap circuit. <P>SOLUTION: The inverter 5 has a gate power source circuit 11-2, which operates as a driving power source for switching elements (Q2, Q4) of a lower arm, and the bootstrap circuit having capacitors (C1, C3) for the gate power source which operates as a driving power source of switching elements (Q1, Q4) of an upper arm. Gating signals (S1, S2) driving two pairs of switching elements, capable of operating in synchronization are made common. A gate pulse generating circuit 8 controls switching elements (Q2, Q4), contributing to charging the capacitors for the gate power source, so that the charging voltage of the capacitors (C1, C3) for the gate power source is set as a predetermined value or higher by one-time ON/OFF control. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a grid-connected inverter device that can be linked to a power system (hereinafter simply referred to as “system”).

  Conventionally, when a driving power source (gate power source) of a switching element is obtained by a bootstrap method, an inverter circuit has been proposed that enables stable operation without causing thermal loss or damage due to heat loss in the switching element. (For example, Patent Document 1).

  According to the inverter circuit disclosed in Patent Document 1, the gate power source for controlling each switching element of the upper arm is configured by a bootstrap circuit, and the number of gate power source circuits is reduced, while the gate power source capacitor is not used. It is possible to prevent damage to the switching element due to charging.

JP 2002-84762 A

  By the way, space saving and cost saving of electrical equipment are also a recent trend, and further space saving and cost saving are demanded in an inverter device including an inverter circuit.

  For example, in a grid-connected inverter device, a gate signal applied to one switching element that constitutes the upper arm and a switching element that constitutes the lower arm, and other switching elements that operate in synchronization with the one switching element It is conceivable to share both gate signals applied to. With such a configuration, a plurality of (for example, two) arms can be controlled by one gate signal, so that space and cost can be saved.

  However, in the bootstrap type inverter device represented by Patent Document 1 described above, when the gate signal applied to the switching elements operating in synchronization is shared, switching is performed in a state where the gate power supply is not sufficiently charged. Therefore, there is a problem that the switching element is damaged and the switching element is damaged. For this reason, the conventional inverter device has a problem that the effect of space saving and cost saving due to common gate signals cannot be obtained.

  The present invention has been made in view of the above, and provides a grid-connected inverter device that enables further space saving and cost saving in a configuration in which a gate power supply of a switching element is obtained by a bootstrap circuit. For the purpose.

  In order to solve the above-described problems and achieve the object, a grid-connected inverter device according to the present invention includes a plurality of switching elements in a grid-connected inverter device linked to a power system, and an input DC voltage. An inverter that converts the AC voltage into an AC voltage, a switch that switches whether or not the output of the inverter is output to a power system, and a control unit that controls the operation of the inverter and the switch. The inverter operates as a first gate power source that operates as a driving power source for a lower arm switching element among the plurality of switching elements, and as a driving power source for an upper arm switching element among the plurality of switching elements. A bootstrap circuit comprising a gate power supply capacitor to which DC power from the first gate power supply is supplied. A gate signal for driving one pair of switching elements among the two pairs of switching elements capable of operating in synchronization with each other. When configured, the control unit causes the charging voltage of the gate power supply capacitor to become a predetermined value or more by one ON / OFF control when the inverter and the power system are not linked. In addition, the switching element contributing to charging of the gate power supply capacitor is controlled.

  According to the grid-connected inverter device according to the present invention, the first gate power source that operates as a driving power source for the lower arm switching element among the plurality of switching elements included in the inverter, and the plurality of switching elements. And a second gate power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm and includes a gate power source capacitor to which DC power from the first gate power source is supplied. At the same time, when the gate signal for driving one pair of switching elements among the two pairs of switching elements that can operate synchronously is configured to be shared, the inverter and the power system are connected. When not connected, the charging voltage of the gate power supply capacitor exceeds the specified value by one ON / OFF control. Therefore, since the switching element contributing to the charging of the gate power supply capacitor is controlled, the gate power supply of the switching element is configured by a bootstrap circuit in addition to the effect of space saving and cost saving. It is also possible to obtain the effect of space saving and cost saving by sharing the gate signal applied to the switching elements operating in synchronization.

  Embodiments of a grid-connected inverter device according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

<Embodiment 1>
(Configuration of solar power generation system)
FIG. 1 is a diagram illustrating an example in which the grid-connected inverter device according to the first embodiment of the present invention is applied to a photovoltaic power generation system.

  In FIG. 1, the solar cell module 1 is connected to the input end of the grid interconnection inverter device 2, and the system 3 for supplying power of, for example, 50 Hz or 60 Hz is connected to the output end. In the solar power generation system configured as described above, the DC power generated by the solar cell module 1 is converted into AC power by the grid interconnection inverter device 2 and supplied to the grid 3.

(Configuration of grid-connected inverter device)
Next, the configuration of the grid-connected inverter device according to the first embodiment will be described. In FIG. 1, the grid-connected inverter device 2 includes a converter 4, an inverter 5, a control unit 6, an output filter circuit 7, and a switch 8.

  The converter 4 converts the output voltage (DC voltage) of the solar cell module 1 and applies it to the inverter 5. The inverter 5 converts the DC voltage supplied from the converter 4 into an AC voltage and outputs it.

  The output filter circuit 7 is connected to the output terminal of the inverter 5 and smoothes and outputs the AC output from the inverter 5. The switch 8 is inserted between the output filter circuit 7 and the system 3 and executes a switching operation as to whether or not to output the output of the inverter 5 to the system 3 via the output filter circuit 7. The voltage detector 30 is connected to the output end of the grid interconnection inverter device 2 (connection end of the switch 8 and the system 3), and detects the output voltage of the system 3. The control unit 6 controls the converter 4, the inverter 5 and the switch 8.

  Next, the concept of space saving and cost saving of the inverter circuit in the grid-connected inverter device will be described with reference to FIGS. Here, FIG. 2 is a diagram illustrating a configuration example of an inverter circuit in which gate signals for switching elements are shared, and FIG. 3 is a configuration example of an inverter circuit in which the number of gate power supply circuits is reduced by using a bootstrap circuit. FIG. 2 and 3 show a circuit configuration from the inverter 5 to the system 3 and a more detailed configuration of the inverter 5.

  In FIG. 2, an inverter 5 includes a plurality of switching elements 9-1 (Q1) to 9-4 (Q4), which are self-extinguishing semiconductor switching elements (for example, IGBTs) connected in antiparallel. Gate drive circuits 10-1 to 10-4 for applying gate pulses to the elements 9-1 to 9-4, and gate power supply circuits 11-1 to 11- for supplying gate power to the gate drive circuits 10-1 to 10-4 3 and a bus capacitor Cx for storing DC power and gate power supply capacitors C1 to C4.

  Switching elements 9-1 and 9-2 and switching elements 9-3 and 9-4 are connected in series, and are connected between inverter buses 28 and 29 connected to the output terminal of converter 4. A bus capacitor Cx is also connected between the inverter buses 28 and 29. The connection points of the switching elements 9-1 and 9-2 and the switching elements 9-3 and 9-4 are drawn out as AC output terminals and connected to the output filter circuit 7.

  The gate power supply (gate power supply circuit 11-2: first gate power supply) for the switching elements 9-2 and 9-4 constituting the lower arm has the same potential and can be shared. On the other hand, the gate power supply (gate power supply circuits 11-1 and 11-3: second gate power supply) for the switching elements 9-1 and 9-3 constituting the upper arm cannot be shared. -1 and 9-3 are provided individually. For this reason, the gate power supply capacitors C1 and C3 are connected to both ends of the gate power supply circuits 11-1 and 11-3, respectively. On the other hand, the gate power supply capacitors C2 and C4 are connected to both ends of a common gate power supply circuit 11-2.

  The control unit 6 includes a gate pulse generation circuit 12. The gate pulse generation circuit 12 generates gate signals (gate pulses) for the gate drive circuits 10-1 to 10-4 that drive the switching elements 9-1 to 9-4. In the configuration of FIG. 2, the gate pulses applied to the two pairs of switching elements that can operate synchronously are shared. That is, the gate pulses (S1, S4) for the switching elements 9-1 and 9-4 are made common (S1 = S4), and the gate pulses (S2, S3) for the switching elements 9-2 and 9-3 are made common. (S2 = S3).

  According to the configuration of FIG. 2, although the gate pulse is shared, a gate power supply circuit is provided for each switching element (except for the lower arm side gate power supplies having the same potential), Even if the effect of space saving and cost saving by obtaining a common pulse is obtained, the effect of space saving and cost saving by reducing the gate power supply circuit cannot be obtained.

  On the other hand, in the configuration shown in FIG. 3, the gate power supply circuits 11-1 and 11-3 of the upper arm in FIG. 2 are replaced with a gate power supply capacitor C1, a resistor R1 and a diode D1, and a gate power supply capacitor C3 and a resistor, respectively. The bootstrap circuit includes R3 and a diode D3. In the configuration of FIG. 3, the gate pulses (S1 to S4) for the switching elements 9-1 to 9-4 are not shared.

  In FIG. 3, when the switching element 9-2 of the lower arm is turned on, a current in a path indicated by a thick broken line in FIG. 3 flows, and a power source for the gate drive circuit 10-1 that drives the switching element 9-1 (hereinafter referred to as “switching element” A gate power supply capacitor C1 is charged as a gate power supply 9-1 (also expressed for other switching elements).

  On the other hand, as a property of a switching element such as an IGBT, if the gate of the switching element is driven in a state where the gate power supply is not sufficiently charged, the switching element may be damaged. Therefore, when the configuration in which the gate drive signal is shared as shown in FIG. 2 is adopted, for example, when the switching element 9-2 is turned on, the switching element 9-3 is also turned on at the same time. The gate of the switching element 9-3 is driven in a state in which the gate power supply capacitor C3 which is a power source is not sufficiently charged, and there is a concern about the failure of the switching element 9-3. For this reason, in the inverter circuit of FIG. 3, the gate signals are not shared, but are separated.

  According to the configuration of FIG. 3, although the gate power supply circuit is reduced by using the bootstrap circuit, the gate pulse cannot be shared, so that the space and cost can be reduced by reducing the gate power supply circuit. Even if the effect of the reduction is obtained, it is not possible to obtain the effect of saving space and cost by sharing the gate pulse.

FIG. 4 is a diagram showing a change in the voltage between both ends when the gate power supply capacitor shown in FIG. 3 is charged, and the meaning of each symbol is as follows.
Vg: Gate power supply voltage R: Charging circuit resistance C: Capacitance of gate power supply capacitor V (t): Voltage across gate power supply capacitor t: Capacitor charging time

When the switching element in the charging path is turned ON, the voltage across the gate power supply capacitor has a waveform as shown in FIG. This waveform can be expressed using the following equation.
V (t) = Vg (1-e- ^{(1 / CR) t} ) (1)

  The gate power supply capacitor C1 is charged when the switching element 9-2 is turned on, and the gate power supply capacitor C2 is charged when the switching element 9-4 is turned on.

  FIG. 5 is a diagram showing a current flow when the switching elements 9-1 and 9-4 are turned on when the system 3 is in the negative half cycle, and FIG. 6 is a diagram when the system 3 is in the positive half cycle. It is a figure which shows the flow of an electric current when switching element 9-2, 9-3 is turned ON. In the configuration shown in FIG. 5, the gate pulses (S1, S4) for the switching elements 9-1 and 9-4 are shared (S1 = S4). In the configuration shown in FIG. 6, the gate pulses (S2, S3) for the switching elements 9-2, 9-3 are shared (S2 = S3).

  In FIG. 5, when the inverter 5 is stopped and the system 3 is in the negative half cycle, the switching element 9 is used to charge the gate power supply capacitor C3 of the upper arm while being connected to the system 3. When -4 is turned ON, since the gate signal is common, the switching element 9-1 is also turned ON. In this case, as indicated by a thick broken line in FIG. 5, a current flows along the path of the upper end side of the system 3 → the switching element 9-4 → the bus capacitor Cx → the switching element 9-1 → the lower end side of the system 3. For the sake of brevity, the current flow is indicated using symbols in the figure).

  In FIG. 6, when the inverter 5 is stopped and the system is in the positive half cycle, the switching element is used to charge the gate power supply capacitor C1 of the upper arm while being connected to the system 3. When 9-2 is turned on, since the gate signal is common, the switching element 9-3 is also turned on. In this case, as indicated by a thick broken line in FIG. 6, a current flows along the path of the lower end side of the system 3 → Q2Tr → Cx → Q3Tr → the upper end side of the system 3. For example, the notation “Q2Tr” means that the current flows through the transistor side of Q2.

  The current path shown in FIGS. 5 and 6 is a current path from the system 3 toward the inverter 5 in a state where the inverter 5 is stopped. For example, in FIG. 5, when the system 3 is in a negative half cycle, the current that the system 3 supplies to the inverter 5 flows out from the lower terminal and returns to the upper terminal. Is the reverse path. If the voltage of system 3 is Vk and the voltage of bus capacitor Cx is Vo, when the solar cell module is generating power, there is a relationship of Vo> Vk. The path toward the bus capacitor Cx through the diode 3 is blocked.

  In FIG. 6, when the system 3 is in the positive half cycle, the current supplied to the inverter 5 by the system 3 is a current that flows out from the upper terminal and returns to the lower terminal. The route is opposite to the route shown in the figure.

  Therefore, when charging the gate power supply capacitors C1 and C3 in the stop state of the inverter 5, the switch 8 is disconnected so that the reverse current (hereinafter referred to as “reverse current”) does not flow. It is necessary to perform charging in a state where the grid-connected inverter device 2 is not linked to the grid 3.

  FIG. 7 is a diagram illustrating an example of a change in the voltage across the gate power supply capacitor constituting the bootstrap circuit. Here, the minimum voltage required for driving the switching element will be described.

Assuming that the power supply voltage necessary for driving the gate is Vgmin, from the above equation (1),
V (t) = Vg (1-e- ^{(1 / CR) t} )> Vgmin (2)
The following relational expression is derived, and the ON time of the switching element for performing charging necessary for reliable driving of the switching element is:
t> -CR * Ln (1-Vgmin / Vg) (3)
Given in.

Here, when C = 100 μF, R = 23.5Ω, Vg = 15 V, and Vgmin = 7.2 V, from the equation (3),
t> 1.54 msec (4)
The relationship is obtained.

  That is, if the gate power supply capacitors C1 and C3 are charged for 1.54 msec or more with one ON / OFF operation, the switching elements 9-1 and 9-3 are surely driven without causing failure. Is possible.

FIG. 8 is a diagram illustrating a configuration of a main part of the grid interconnection inverter device according to the first embodiment of the present invention, and is a diagram illustrating a configuration embodying the grid interconnection inverter device 2 illustrated in FIG. 1. . The basic configuration is the same as that shown in FIG. 3, but the gate pulses (S1, S4) for the switching elements 9-1 and 9-4 and the gate pulses ( S2 and S3) are made common ( S1 = S4, S2 = S3), respectively. Further, when charging the gate power supply capacitors C1 and C3, the switch 8 needs to be opened.

  Here, consider the operation when the gate power supply capacitors C1 and C3 are charged in a pulse manner at a normal switching frequency when the inverter 5 is started.

(1) First, when the switching element 9-2 is turned on, a charging current as shown by a thick broken line in FIG. 8 flows and the gate power supply capacitor C1 is charged. At this time, the switching element 9-3 does not operate because the gate power supply capacitor C3 is not charged.
(2) Next, when the switching frequency is switched and the switching element 9-4 is turned on, the gate power supply capacitor C3 is charged. At this time, the switching element 9-1 is turned on when the voltage of the gate power supply capacitor C1 reaches the drive voltage of the switching element 9-1 during the charging of (1).
(3) Further, when the switching frequency is switched and the switching element 9-2 is turned on, the gate power supply capacitor C1 is charged. At this time, the switching element 9-3 is turned on when the voltage of the gate power supply capacitor C3 reaches the driving voltage of the switching element 9-3 during the charging of (2).
(4) Thereafter, the operations (2) and (3) are repeated.

When the above charging operation is repeated, the following problems arise.
(A) For example, if the voltage of the gate power supply capacitor C1 is not sufficiently charged in the state (2), the switching element 9-1 may be damaged.
(B) Further, for example, when the voltage of the gate power supply capacitor C3 is not sufficiently charged in the state (3), the switching element 9-3 may be damaged.
Therefore, when the gate power supply capacitors C1 and C3 are charged at the normal switching frequency when the inverter 5 is started, the gate pulses cannot be shared and must be operated independently.

  On the other hand, in the present embodiment, the switching elements 9-1 and 9-3 are controlled so that the charging voltage of the gate power supply capacitors C1 and C3 becomes a predetermined value or more by one ON / OFF control. That is, the switching elements 9-1 and 9-3 are controlled at a switching frequency different from the normal switching frequency so that the charging voltage of the gate power source capacitors C1 and C3 is equal to or higher than Vgmin expressed by the above equation (2). .

  As shown in the description of FIG. 7, when C = 100 μF, R = 23.5Ω, Vg = 15 V, and Vgmin = 7.2 V, the gate power supply capacitors C1 and C3 are applied once. If charging is performed for 1.54 msec or more by turning ON / OFF, the switching elements 9-1 and 9-3 can be reliably driven without causing failure.

  As described above, according to the grid-connected inverter device of this embodiment, the number of gate power supplies can be reduced, so that space and cost can be saved.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to reliably prevent a failure of the switching element due to the uncharged gate power supply capacitor.

<Embodiment 2>
FIG. 9 is a diagram illustrating the configuration of the grid-connected inverter device according to the second embodiment of the present invention. The difference in the device configuration from the first embodiment shown in FIG. 8 is that a gate signal for driving one switching element pair is shared among two switching element pairs capable of operating in synchronization. It is in the point which constituted so. For example, in the configuration shown in FIG. 9, the gate signals of the switching elements 9-1 and 9-4 are shared, but the gate signals of the switching elements 9-2 and 9-3 are not shared. In addition, about others, it is the same as that of the structure of Embodiment 1, or equivalent, attaches | subjects the same code | symbol and abbreviate | omits detailed description.

  In FIG. 9, the switching element 9-2 is turned on to charge the gate power supply capacitor C <b> 1 while the grid-connected inverter device is stopped once and the electric charge is accumulated in the capacitor (filter capacitor) of the output filter circuit 7. Then, as shown by the thick solid line in the figure, the current flows through the path of the lower end side of the filter capacitor (the lower end side of the system 3) → Q2Tr → Q4D → the upper end side of the filter capacitor (the upper end side of the system 3). There is a possibility that the inverter 5 may stop due to erroneous detection of the output overcurrent. The notations “Q2Tr” and “Q4D” in the above mean that the current flows through the transistor side of Q2 and the diode side of Q4, respectively.

  Therefore, in the grid-connected inverter device of the present embodiment, the switching element 9-2 that is not shared is turned on / off by a plurality of times of switching control, and the gate power supply capacitor C1 is charged in a pulse manner. . At this time, the capacitor of the output filter circuit 7 outputs a current in a pulse manner according to the switching frequency of the switching element 9-2. However, since the output filter circuit 7 has a reactor component, the current flowing in a pulse manner is Averaged. This action prevents a short-circuit current from flowing inside the inverter 5.

  In this embodiment, the gate signals for the switching elements 9-1 and 9-4 are made common, while the gate signals for the switching elements 9-2 and 9-3 are not made common, and the above control is performed. However, in contrast to this configuration, the gate signals for the switching elements 9-2 and 9-3 are made common without sharing the gate signals for the switching elements 9-1 and 9-4. You may comprise as follows. In this case, the switching element 9-4 that is not shared may be turned ON / OFF by a plurality of times of switching control to charge the gate power supply capacitor C3 in a pulse manner.

  As described above, according to the grid-connected inverter device of this embodiment, the number of gate power supplies can be reduced, so that space and cost can be saved.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to reliably prevent a failure of the switching element due to the uncharged gate power supply capacitor.

  Further, according to the grid-connected inverter device of this embodiment, charging of the gate power supply capacitor can be started without waiting for the discharge of the charge charged in the capacitor of the output filter circuit.

<Embodiment 3>
(Configuration of solar power generation system)
FIG. 10: is a figure which shows an example at the time of applying the grid connection inverter apparatus concerning Embodiment 3 of this invention to a solar energy power generation system.

  In FIG. 10, the solar cell module 1 is connected to the input end of the grid interconnection inverter device 2 </ b> A, and the grid 3 for supplying power of, for example, 50 Hz or 60 Hz is connected to the output end. In the solar power generation system configured as described above, the DC power generated by the solar cell module 1 is converted into AC power by the grid interconnection inverter device 2A and supplied to the grid 3.

(Configuration of grid-connected inverter device)
Next, the configuration of the grid interconnection inverter device 2A according to the third embodiment will be described. In FIG. 10, the grid-connected inverter device 2 </ b> A includes a converter 4, an inverter unit 20, a control unit 6, an output filter circuit 7, a switch 8, and a voltage detector 30.

  The converter 4 converts the output voltage (DC voltage) of the solar cell module 1 and applies it to the inverter unit 20. The inverter unit 20 includes a plurality of single-phase inverters whose AC-side terminals are connected in series, and is a total voltage generated by each single-phase inverter that converts a DC voltage supplied from the converter 4 into an AC voltage. Is output. A detailed configuration related to the inverter unit 20 will be described later.

  The output filter circuit 7 is connected to the output terminal of the inverter unit 20 and smoothes and outputs the AC output from the inverter unit 20. The switch 8 is inserted between the output filter circuit 7 and the system 3 and executes a switching operation for determining whether or not to transmit the output of the output filter circuit 7 to the system 3. The voltage detector 30 is connected to the output end of the grid interconnection inverter device 2 (connection end of the switch 8 and the system 3), and detects the output voltage of the system 3. The control unit 6 controls the converter 4, the inverter unit 20, and the switch 8 based on the detection voltage of the voltage detector 30. The central part of the present embodiment is that the control unit 6 controls the inverter unit 20 based on the output of the voltage detector 30, and details thereof will be described later.

  Next, the concept of space saving and cost saving in the inverter unit 20 of the grid-connected inverter device 2A having a plurality of single-phase inverters will be described with reference to FIGS. Here, FIG. 11 is a diagram illustrating a configuration example of the inverter unit 20 in which the gate signal for the switching element is shared, and FIG. 12 is a diagram of the inverter unit 20 in which the number of gate power supply circuits is reduced by using a bootstrap circuit. It is a figure which shows the example of a structure. In addition, in FIG. 11 and FIG. 12, while showing the circuit structure from the inverter unit 20 to the system | strain 3, the more detailed structure of the inverter unit 20 is shown.

  In FIG. 11, single-phase inverters 20 a to 20 c, which are a plurality of single-phase inverters (three are illustrated in the figure) constituting the inverter unit 20, include a plurality of self-extinguishing type diodes connected in antiparallel. Switching elements 9-1 (Q1) to 9-12 (Q12), which are semiconductor switching elements (for example, IGBT), and gate drive circuits 10-1 to 10-12 for applying gate pulses to the switching elements 9-1 to 9-12 Gate power supply circuits 11-1 to 11-3, 11-5 to 11-7, 11-9 to 11-11 for supplying gate power to the gate drive circuits 10-1 to 10-12, and DC power are stored. Bus capacitor Ca-Cc and gate power supply capacitors C1-C12 are provided. The control unit 6 includes a gate pulse generation circuit 12.

  In single-phase inverter 20a, switching elements 9-1 and 9-2 and switching elements 9-3 and 9-4 are connected in series, and are connected between inverter buses 28 and 29 connected to the output terminal of converter 4. The A bus capacitor Ca is also connected between the inverter buses 28 and 29. On the other hand, each connection point of the switching elements 9-1 and 9-2 and the switching elements 9-3 and 9-4 is drawn out as an AC output terminal and connected to the switch circuit 22. The single-phase inverters 20b and 20c have the same configuration as that of the single-phase inverter 20a, and a detailed description thereof is omitted here.

  The switch circuit 22 is a short-circuiting switch that short-circuits the AC side terminals of the single-phase inverter 20a, and two self-extinguishing semiconductor switching elements (for example, IGBTs) having diodes connected in antiparallel are serially connected in reverse polarity. It is connected so as to be connected in parallel to the single-phase inverter 20a.

  In addition, one terminal of the switch circuit 22, which is connected to one of the AC terminals of the single-phase inverter 20a, is connected to one of the AC terminals of the single-phase inverter 20b, and the switch circuit 22 The other terminal of the single-phase inverter 20a and the other terminal connected to the other of the AC-side terminals are connected to one of the AC-side terminals of the single-phase inverter 20c.

  Further, the other of the AC side terminals of the single phase inverter 20 b and the other of the AC side terminals of the single phase inverter 20 c constitute an output terminal of the inverter unit 20 and are connected to the output filter circuit 7.

  The inverter unit 20 can output a non-zero or zero voltage as an output voltage by the action of the switch circuit 22.

  Here, the voltages of the bus capacitors Ca to Cc are mentioned. The voltage of the bus capacitor Ca serving as the DC input source of the single-phase inverter 20a is usually larger than the voltage of the bus capacitors Cb and Cc serving as the DC input sources of the other single-phase inverters 20b and 20c. On the other hand, as for the voltage of the bus capacitor Cb and the voltage of the bus capacitor Cc, either may be large, or both voltages may be equal. That is, assuming that the voltages of the bus capacitors Ca to Cc (equal to the bus voltage in each inverter) when the inverter unit 20 is operating are V1, V2, and V3, V1> V2 and V1 are between these voltages. > V3 relationship.

  These single-phase inverters 20a to 20c can generate positive, negative and zero voltages as outputs, and the inverter unit 20 outputs a voltage as a sum total of these generated voltages by gradation control. This output voltage is smoothed by, for example, an output filter circuit 7 that combines a reactor and a capacitor, and a desired AC voltage is supplied to the system 3.

  Next, attention is focused on the configuration of the inverter unit 20 shown in FIG. In the single-phase inverter 20a, the gate power supplies for the switching elements 9-2 and 9-4 constituting the lower arm have the same potential and can be shared. On the other hand, the gate power supply for the switching elements 9-1 and 9-3 constituting the upper arm cannot be made common, and thus is provided for each switching element 9-1 and 9-3. For this reason, the gate power supply capacitors C1 and C3 are connected to both ends of the gate power supply circuits 11-1 and 11-3, respectively. On the other hand, the gate power supply capacitors C2 and C4 are connected to both ends of a common gate power supply circuit 11-2.

  The same applies to the single-phase inverters 20b and 20c. For each single-phase inverter, there are four gate drive circuits that drive each switching element and three gate power supply circuits that supply power to these gate drive circuits. Is provided.

  The gate pulse generation circuit 12 generates a gate signal (gate pulse) for the gate drive circuits 10-1 to 10-12 that drive the switching elements 9-1 to 9-12. In the configuration of FIG. 11, in the single-phase inverter 20a, the gate pulses (S1, S4) for the switching elements 9-1 and 9-4 and the gate pulses (S2, S3) for the switching elements 9-2 and 9-3 are generated. It is common. In the single-phase inverters 20b and 20c, the gate pulses (S5 and S12) for the switching elements 9-5 and 9-12, the gate pulses (S6 and S11) for the switching elements 9-6 and 9-11, and the switching element 9- The gate pulses (S7, S10) for 7, 9-10 and the gate pulses (S8, S9) for the switching elements 9-8, 9-9 are shared.

  According to the configuration of FIG. 11, although the gate pulse is shared, the gate power supply circuit is provided for each switching element (except for the lower arm side gate power supplies having the same potential). Even if the effect of space saving and cost saving by obtaining a common pulse is obtained, the effect of space saving and cost saving by reducing the gate power supply circuit cannot be obtained.

  On the other hand, in the configuration shown in FIG. 12, in the single-phase inverter 20a, the upper arm gate power supply circuits 11-1 and 11-3 are respectively connected to the gate power supply capacitor C1, the resistor R1, the diode D1, and the gate power supply capacitor. The bootstrap circuit includes C3, a resistor R3, and a diode D3. In the configuration of FIG. 3, the gate pulses (S1 to S4) for the switching elements 9-1 to 9-4 are not shared.

  In the single-phase inverter 20b, the upper arm gate power supply circuits 11-5 and 11-7 are booted by the gate power supply capacitor C5, the resistor R5 and the diode D5, and the gate power supply capacitor C7, the resistor R7 and the diode D7, respectively. It consists of a strap circuit. Similarly, in the single-phase inverter 20c, the gate power supply circuits 11-9 and 11-11 of the upper arm are respectively constituted by the gate power supply capacitor C9, the resistor R9 and the diode D9, and the gate power supply capacitor C11, the resistor R11 and the diode D11. It consists of a bootstrap circuit. In the configuration of FIG. 12, the gate pulses (S5 to S12) are not made common to the switching elements 9-5 to 9-12.

  In FIG. 12, when the switching element 9-2 of the lower arm is turned ON, a current in a path indicated by a thick broken line in FIG. 12 flows, and the gate power supply capacitor C1 as the gate power supply of the switching element 9-1 is charged.

  On the other hand, if the gate of the switching element is driven in a state where the gate power supply is not sufficiently charged, the switching element may be damaged. Therefore, when the configuration in which the gate drive signal is shared as shown in FIG. 11 is adopted, for example, when the switching element 9-2 is turned on, the switching element 9-3 is also turned on at the same time. The gate of the switching element 9-3 is driven in a state in which the gate power supply capacitor C3 which is a power source is not sufficiently charged, and there is a concern about the failure of the switching element 9-3. For this reason, the inverter circuit of FIG. 12 is configured to separate the gate signals without sharing them. This also applies to the single-phase inverters 20b and 20c, and the gate signal is not shared.

  According to the configuration of FIG. 12, although the gate power supply circuit is reduced by using the bootstrap circuit, the gate pulse cannot be shared, so that the space and cost can be reduced by reducing the gate power supply circuit. Even if the effect of the reduction is obtained, it is not possible to obtain the effect of saving space and cost by sharing the gate pulse.

  FIG. 13 illustrates the reverse flow phenomenon in a positive half cycle when the direction of the arrow attached to Vk in the figure is positive in an inverter unit in which a plurality of single-phase inverters are connected in series. It is a figure to do. More specifically, FIG. 13 is a diagram showing a current flow when the switching elements 9-1 and 9-4 are turned on when the system 3 is in the negative half cycle. In the configuration shown in FIG. 13, the gate pulses (S1, S4) for the switching elements 9-1 and 9-4 are shared (S1 = S4).

  In FIG. 13, when the inverter unit 20 is stopped, the system is in a positive half cycle, and the absolute value of the system voltage is less than or equal to a predetermined value, the upper arm remains connected to the system 3. When the switching element 9-4 is turned on to charge the gate power supply capacitor C3 (charged by a path indicated by a one-dot chain line in the figure), the switching element 9-1 is also turned on because the gate signal is common. In this case, as indicated by a thick broken line in FIG. 13, a current flows along the path of the lower end side of the system 3 → Q11D → Cc → Q10D → Q4Tr → Ca → Q1Tr → Q7D → Cb → Q6D → the upper end side of the system 3.

  FIG. 14 shows an inverter unit in which a plurality of single-phase inverters are connected in series, when the system is in a negative half cycle when the direction of the arrow attached to Vk in the figure is positive. It is a figure explaining a backflow phenomenon. More specifically, FIG. 14 is a diagram illustrating a current flow when the switching elements 9-2 and 9-3 are turned on when the system 3 is in the positive half cycle. In the configuration shown in FIG. 14, the gate pulses (S2, S3) for the switching elements 9-2, 9-3 are shared (S2 = S3).

  In FIG. 14, when the inverter unit 20 is in a stopped state, the system is in a negative half cycle, and the absolute value of the system voltage is less than or equal to a predetermined value, the upper arm remains connected to the system 3 When the switching element 9-2 is turned on to charge the gate power supply capacitor C1 (charged by the path indicated by the alternate long and short dash line in the figure), the switching signal 9-3 is also turned on because the gate signal is common. In this case, as indicated by a thick broken line in FIG. 14, a current flows along the path of the upper end side of the system 3 → Q5D → Cb → Q8D → Q2Tr → Ca → Q3Tr → Q9D → Cb → Q12D → the lower end side of the system 3.

  The current paths shown in FIGS. 13 and 14 are current paths output from the system 3 to the inverter side in a state where the inverter is stopped.

  For example, in FIG. 13, when the grid 3 is in the positive half cycle, the current that the grid 3 supplies to the inverter unit 20 flows out from the upper terminal and returns to the lower terminal. Is different. In addition, when the voltage of system 3 is Vk, the bus voltage of each single-phase inverter is V1, V2, and V3, and the output voltage of inverter unit 20 is Vo, | Vk | < When there is a relationship of | Vo | = | V1- (V2 + V3) |, the output voltage of the inverter unit 20 is larger, and the output to the system 3 is generated even though the inverter unit 20 is stopped. End up.

  In FIG. 14, when the system 3 is in a negative half cycle, the current supplied to the inverter unit 20 by the system 3 flows out from the lower terminal and returns to the upper terminal. Is the reverse path. At this time, if there is a relationship of | Vk | <| Vo | = | V1- (V2 + V3) | between Vk and Vo, the output to system 3 mentioned above will occur. The same applies to other gate power supply capacitors C5, C7, C9, and C11, although the conditions are different.

  Therefore, when charging the gate power supply capacitors C1, C3, C5, C7, C9, and C11 when the inverter unit 20 is stopped, the switch 8 is disconnected so that no reverse current flows, and the grid interconnection inverter It is necessary to perform charging in a state where the device 2 is not connected to the grid 3. That is, in the configuration shown in FIG. 13 and FIG. 14, it is necessary to control opening / closing of the switch 8 every time the gate power supply capacitor is charged, which causes a problem that the contact life of the switch 8 is shortened.

  As described above, the configurations of FIG. 13 and FIG. 14 obtain the effect of space saving and cost saving by reducing the gate power supply circuit and the effect of space saving and cost saving by sharing some gate pulses. Even if this is possible, a new problem arises that the set life of the switch is shortened.

  FIG. 15 is a diagram illustrating a configuration of a main part of the grid interconnection inverter device according to the third embodiment of the present invention, and is a diagram illustrating a configuration embodying the grid interconnection inverter device 2 illustrated in FIG. 10. . The basic configuration is the same as that shown in FIG. 13 or FIG. 14, but the difference from these figures is that the voltage at the output terminal of the grid-connected inverter device 2 is used as the output voltage monitoring function. The detector 30 is provided, and the control unit 6 controls the inverter unit 20 based on the detection voltage of the voltage detector 30.

  Next, the operation of the grid interconnection inverter device according to the third embodiment will be described with reference to the drawings of FIGS. 16 is a diagram showing a chargeable period of the gate power supply capacitor corresponding to the waveform of the system voltage, FIG. 17 is a diagram showing a plurality of current paths generated in the inverter unit, and FIG. It is the figure which showed the correspondence between the capacitor | condenser for gate power supplies which can be charged, the cycle of a system | strain, a chargeable period, and a current path in detail.

  First, in FIG. 15, in the configuration of FIG. 15, gate pulses (S1, S4) for switching elements 9-1 and 9-4, gate pulses (S2, S3) for switching elements 9-2 and 9-3, switching elements Gate pulses (S5, S12) for 9-5, 9-12, gate pulses (S6, S11) for switching elements 9-6, 9-11, gate pulses (S7, S10) for switching elements 9-7, 9-10 ) And the gate pulses (S8, S9) for the switching elements 9-8, 9-9. Therefore, in the inverter unit 20, the switching elements 9-1 and 9-4, the switching elements 9-2 and 9-3, the switching elements 9-5 and 9-12, the switching elements 9-6 and 9-11, and the switching element 9 −7, 9-10, and the switching elements 9-8, 9-9 perform switching in synchronization with each other.

Next, a case where the gate power supply capacitor C3 is charged will be described as an example. FIG. 16 shows a period T2 in one cycle of the system voltage waveform as a chargeable period of the gate power supply capacitor C3. In addition to this condition, the gate power supply capacitor C3 is charged in the following period. Performed when the conditional expression is satisfied.
Vk> V1- (V2 + V3) (5)
V1, V2 and V3 are preset voltages and are known.

For example, when V1 = 240V and V2 = V3 = 70V, Vk> 240− (70 + 70) = 100V or more in the period expressed by the above equation (5). When the switching elements 9-1 and 9-4 are turned on when this condition is satisfied, the output flow (current path) from the inverter unit 20 toward the system 3 side is
“Q11D → Cc (−V3) → Q10D → Q4Tr → Ca (+ V1) → Q1Tr → Q7D → Cb (−V2) → Q6D” (current path of symbol A in FIG. 17)
It becomes.

Considering the above current path, the output voltage Vo is
Vo = V1- (V2 + V3) <Vk (6)
Thus, the system voltage is larger and is not output to the system 3.

The output flow (current path) from the system 3 toward the inverter unit 20 side is
“Q5D → Cb (−V2) → Q8D → Q1D → Ca (−V1) → Q4D → Q9D → Cc (−V3) → Q12D” (current path of symbol B in FIG. 17)
It becomes.

Considering the above current path, the output voltage Vo is
Vo = V1 + V2 + V3> Vk (7)
Thus, since the output voltage of the inverter unit 20 becomes larger, it is not output to the inverter unit 20.

  Therefore, if the switching elements 9-1 and 9-4 are turned on during a period satisfying Vk> V1- (V2 + V3), no current flows between the system 3 and the inverter unit 20. The capacitor for the gate power supply can be charged while the switch 8 is connected, that is, in a state where the switch 8 is connected.

16 to 18 show the relationship between the chargeable period other than the gate power supply capacitor C3, the current path, and the like. For example, the charge period of the gate power supply capacitor C5 is a chargeable period excluding the period T2, and in this chargeable period, the switching elements 9-6, 9-7, 9-10, 9-11 (Q6, Since Q11 is shared and Q7 and Q10 are shared, S6 and S7 are output). In addition, what is necessary is just to control the said switching element in the period which satisfies the following conditional expression so that a backflow current may not flow.
Vo = − (V1 + V2 + V3) <Vk (8)
Vo = (V2 + V3) −V1> Vk (9)

  As described above, according to the grid-connected inverter device of this embodiment, the gate power supply can be charged in a state linked to the grid, so that the contact life of the switch can be extended. .

  In addition, according to the grid-connected inverter device of this embodiment, the number of gate power supplies can be reduced, so that space and cost can be saved.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

<Embodiment 4>
FIG. 19 is a diagram of a configuration of the grid interconnection inverter device according to the fourth embodiment. The difference from the third embodiment shown in FIG. 15 is that voltage detectors 32a to 32c for monitoring the voltages of bus capacitors Ca to Cc are provided. Other components are the same as or equivalent to those of the third embodiment, and the same reference numerals are given and detailed description thereof is omitted.

In the grid-connected inverter device of the third embodiment, the bus voltage V1, V2, V3 of each single-phase inverter is assumed to be known, and the above equation (5) is determined. On the other hand, if the inverter bus voltage V1 fluctuates in the range of 200V to 240V, the output voltage Vo when charging the gate power supply capacitor C3 is expressed by the following equation as shown in the chart of FIG. The value indicated by can be taken.
Vo = V1- (V2 + V3) (10) (current path A in the chart)
Vo = V1 + V2 + V3 (11) (current path B in the chart)

  When V2 = V3 = 70V, assuming that it fluctuates in the range of V1 = 200 to 240V, the output voltage Vo is 60-100V <Vo <340-380V from the above equations (10) and (11). Will vary in range. Therefore, if the switching element is turned on in accordance with the fluctuation of V1, switching control according to the fluctuation of the inverter bus voltage is possible, and reliable switching control without causing a backflow phenomenon is possible.

  In the above description, the voltage fluctuation of V1 has been described, but it is needless to say that the effect can be obtained even with respect to the voltage fluctuation of V2 and V3.

  As described above, according to the grid-connected inverter device of this embodiment, in addition to the effects of the third embodiment, reliable switching control that does not cause a backflow phenomenon between the grid-connected inverter device and the grid. Is possible.

<Embodiment 5>
Embodiment 5 shows an embodiment for reliably preventing a failure of a switching element constituting an upper arm in an inverter unit in which a plurality of single-phase inverters are connected in series. The basic configuration of the fifth embodiment is the same as that shown in FIG. In the present embodiment, the function of monitoring the voltage of system 3 is not necessary. However, when the gate power supply capacitor is charged (initial charge), the switch 8 needs to be opened.

The power supply voltage Vgmin required for gate driving is the same as in the second embodiment. That is, the ON time of the switching element for performing charging necessary for reliable driving of the switching element is given by the expression (3) shown in the second embodiment.
t> -CR * Ln (1-Vgmin / Vg) (3) (repost)

Here, when C = 100 μF, R = 23.5Ω, Vg = 15 V, and Vgmin = 7.2 V, the following relational expression shown in the second embodiment is obtained.
t> 1.54 msec (4) (repost)

  That is, if each gate power supply capacitor provided in each single-phase inverter of the inverter unit 20 is charged for 1.54 msec or more by one ON / OFF, each switching element to be driven is brought to failure. It can be reliably driven without any problems.

  As described above, according to the grid-connected inverter device of this embodiment, since the number of gate power supplies can be reduced, it is possible to save space and cost.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to reliably prevent a failure of the switching element due to the uncharged gate power supply capacitor.

<Embodiment 6>
Embodiment 6 shows an embodiment for reliably preventing a failure of a switching element constituting an upper arm in an inverter unit in which a plurality of single-phase inverters are connected in series. 5 is that charge control can be performed in a state of being connected to the grid 3. The basic configuration of the sixth embodiment is the same as that shown in FIG. In the present embodiment, a function for monitoring the voltage of system 3 is necessary.

  Specifically, in the sixth embodiment, charging may be performed for 1.54 msec or more with one ON / OFF under the conditions shown in the chart of FIG. 18 (C = 100 μF, R = 23.5Ω, Vg = 15V, Vgmin = 7.2V). For example, the gate power supply capacitor C1 may be charged when Vk <V1− (V2 + V3) and Vk> − (V1 + V2 + V3) in the negative half cycle of the system.

  By performing the control as described above, the switching elements constituting the upper arm can be reliably driven without causing failure.

  As described above, according to the grid-connected inverter device of this embodiment, the gate power supply can be charged in a state linked to the grid, so that the contact life of the switch can be extended.

  In addition, according to the grid-connected inverter device of this embodiment, the number of gate power supplies can be reduced, so that space and cost can be saved.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to reliably prevent a failure of the switching element due to the uncharged gate power supply capacitor.

<Embodiment 7>
FIG. 20 is a diagram of a configuration of the grid interconnection inverter device according to the seventh embodiment. The difference regarding the device configuration from the sixth embodiment shown in FIG. 19 is that the switching element 9-1 and the switching element 9-4 are not shared in the single-phase inverter 20a. Other components are the same as or equivalent to those of the sixth embodiment, and the same reference numerals are given and detailed description thereof is omitted.

  In FIG. 20, the bus voltage V1 is the output of the converter 4 based on the output of the solar cell module. For this reason, the bus capacitor Ca is always charged except in some exceptional cases (for example, at startup). On the other hand, when the grid-connected inverter device is stopped once and the electric charge is accumulated in the capacitor (filter capacitor) of the output filter circuit 7 and the bus capacitors Cb and Cc are uncharged, the gate power supply capacitor C1 is charged. When the switching element 9-2 is turned on, the upper end side of the filter capacitor (the upper end side of the system 3) → Q5D → Cb → Q8D → Q2Tr → Q4D → Q9D → Cc → Q12D → filter as shown by the thick wavy line in FIG. A current of a path called the lower end side of the capacitor (the lower end side of the system 3) flows, and a short circuit current flows through the bus capacitor Cb, Cc. At this time, there is a possibility that the short circuit current detection circuit normally provided in the bus capacitors Cb and Cc may malfunction.

  Therefore, in the grid-connected inverter device of the present embodiment, after switching element 9-4 is turned on and gate power supply capacitor C3 is sufficiently charged, common switching elements 9-2 and 9-3 are connected. Charging is performed by switching control one to several times. At this time, the capacitor of the output filter circuit 7 outputs a current in a pulse manner in accordance with the switching frequency of the switching elements 9-2 and 9-3. However, since the output filter circuit 7 has a reactor component, The current flowing through is averaged. This action prevents a short-circuit current from flowing through the bus capacitors Cb and Cc.

  In this embodiment, the gate pulses (S2, S3) for the switching elements 9-2, 9-3 are shared, while the gate pulses (S1, S4) for the switching elements 9-1, 9-4 are used. Although the above-described control is performed without sharing, the gate pulses (S2, S3) for the switching elements 9-2 and 9-3 are not shared and switching is performed contrary to this configuration. You may comprise so that the gate pulse (S1, S4) with respect to element 9-1, 9-4 may be shared. In this case, after the switching element 9-2 is turned on and the gate power supply capacitor C1 is sufficiently charged, the common switching elements 9-1 and 9-4 are charged by a plurality of switching controls. You can do it.

  Further, in this embodiment, the above control is applied to the configuration of the sixth embodiment shown in FIG. 19, but the present invention is applied to the third to fifth embodiments based on FIG. 15, FIG. Of course, it is possible.

  As described above, according to the grid-connected inverter device of this embodiment, it is possible to easily charge the uncharged gate power supply capacitor at the time of startup or the like.

  In addition, according to the grid-connected inverter device of this embodiment, the number of gate power supplies can be reduced, so that space and cost can be saved.

  Further, according to the grid interconnection inverter device of this embodiment, two arms can be controlled by one gate signal, so that space saving and cost saving can be achieved.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to reliably prevent a failure of the switching element due to the uncharged gate power supply capacitor.

  Further, according to the grid-connected inverter device of this embodiment, it is possible to prevent a short-circuit current from flowing through the bus capacitor when the gate power supply capacitor is charged.

  As described above, the grid-connected inverter device according to the present invention is useful as an invention that extends the contact life of the switch and can save space and cost.

It is a figure which shows an example at the time of applying the grid connection inverter apparatus concerning Embodiment 1 to a solar power generation system. It is a figure which shows the structural example of the inverter circuit which shared the gate signal with respect to a switching element. It is a figure which shows the structural example of the inverter circuit which reduced the number of gate power supply circuits by using a bootstrap circuit. It is a figure which shows the change of the both-ends voltage at the time of charge of the capacitor | condenser for gate power supplies shown in FIG. It is a figure explaining the backflow phenomenon when a system | strain is a negative half cycle. It is a figure explaining the backflow phenomenon when a system | strain is a positive half cycle. It is a figure which shows an example of the change of the both-ends voltage of the capacitor | condenser for gate power supplies which comprises a bootstrap circuit. It is a figure which shows the structure of the principal part of the grid connection inverter apparatus concerning Embodiment 1. FIG. It is a figure which shows the structure of the grid connection inverter apparatus concerning Embodiment 2. FIG. It is a figure which shows an example at the time of applying the grid connection inverter apparatus concerning Embodiment 3 to a solar energy power generation system. It is a figure which shows the structural example of the inverter unit which shared the gate signal with respect to a switching element. It is a figure which shows the structural example of the inverter unit which reduced the number of gate power supply circuits by using a bootstrap circuit. In the inverter unit which connected the several single phase inverter in series, it is a figure explaining the backflow phenomenon when a system | strain is a positive half cycle. In the inverter unit which connected the several single phase inverter in series, it is a figure explaining the backflow phenomenon when a system | strain is a negative half cycle. It is a figure which shows the structure of the principal part of the grid connection inverter apparatus concerning Embodiment 3. FIG. It is a figure which shows the chargeable period of the capacitor | condenser for gate power supplies matched with the waveform of the system voltage. It is a figure which shows the several electric current path which arises in an inverter unit. It is the figure which showed the correspondence relationship between the capacitor | condenser for gate power supplies which can be charged, a system cycle, a chargeable period, and a current path in more detail. It is a figure which shows the structure of the grid connection inverter apparatus concerning Embodiment 4. FIG. FIG. 10 is a diagram illustrating a configuration of a grid interconnection inverter device according to a seventh embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solar cell module 2,2A Grid connection inverter apparatus 3 System | strain 4 Converter 5 Inverter 6 Control part 7 Switch 7 Output filter circuit 8 Switch 9-1 to 9-12 Switching element 10-1 to 10-12 Gate drive circuit 11-1 to 11-3, 11-5 to 11-7, 11-9 to 11-11 Gate power supply circuit 12 Gate pulse generation circuit 20 Inverter unit 20a, 20b, 20c Single-phase inverter 22 Switch circuit 28, 29 Inverter bus 30 Voltage detector 32a, 32b, 32c Voltage detector C1-C12 Capacitor for gate power supply Ca, Cb, Cc, Cx Bus capacitor

Claims (9)

In the grid-connected inverter device linked to the power system,
An inverter that has a plurality of switching elements, converts an input DC voltage into an AC voltage, and outputs the AC voltage;
A switch for switching whether or not to output the output of the inverter to a power system;
A control unit for controlling operations of the inverter and the switch;
With
The inverter is
A first gate power source that operates as a power source for driving a switching element of a lower arm among the plurality of switching elements;
A second power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm among the plurality of switching elements and includes a gate power source capacitor that is supplied with DC power from the first gate power source. Gate power supply,
And having
When the gate signals for driving two pairs of switching elements capable of operating synchronously are configured to be shared,
The control unit is configured to control the gate power supply so that the charging voltage of the gate power supply capacitor becomes a predetermined value or more by one ON / OFF control when the inverter and the power system are not linked. A grid-connected inverter device that controls a switching element that contributes to charging of a capacitor. In the grid-connected inverter device linked to the power system,
An inverter that has a plurality of switching elements, converts an input DC voltage into an AC voltage, and outputs the AC voltage;
A switch for switching whether or not to output the output of the inverter to a power system;
A control unit for controlling operations of the inverter and the switch;
With
The inverter is
A first gate power source that operates as a power source for driving a switching element of a lower arm among the plurality of switching elements;
A second power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm among the plurality of switching elements and includes a gate power source capacitor that is supplied with DC power from the first gate power source. Gate power supply,
And having
Of the two pairs of switching elements capable of operating in synchronism, when the gate signals for driving one pair of switching elements are configured to be shared,
The control unit is configured such that when the inverter and the power system are not linked, the charging voltage of the gate power supply capacitor charged by turning on the switching element of the lower arm that does not share the gate signal is A grid-connected inverter device, wherein the switching element of the lower arm is ON / OFF controlled a plurality of times so as to be a predetermined value or more. In the grid-connected inverter device linked to the power system,
A converter that converts the input DC voltage to output, and
It has a plurality of single-phase inverters that convert the DC voltage output from the converter into an AC voltage and output it, and outputs the total voltage generated by the generated voltages of the plurality of single-phase inverters connected in series with the AC side terminal An inverter unit to
A switch for switching whether to output the output of the inverter unit to a power system;
A control unit for controlling operations of the inverter unit and the switch;
A first voltage detector for detecting a voltage of the power system;
With
The inverter unit is
A first gate power supply that operates as a power supply for driving the switching element of the lower arm among the plurality of switching elements constituting each single-phase inverter;
A second power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm among the plurality of switching elements and includes a gate power source capacitor that is supplied with DC power from the first gate power source. Gate power supply,
And having
Of the two pairs of switching elements capable of operating in synchronism, when the gate signals for driving one pair of switching elements are configured to be shared,
When the inverter unit and the power system are in an interconnected state, and the inverter unit is in a stopped state, the control unit is connected to the inverter unit based on a detection voltage of the first voltage detector. A grid-connected inverter apparatus, wherein the gate power supply capacitor is charged by performing ON / OFF control of the switching element so that no reverse current flows between the power system and the power system. A second voltage detector for detecting a bus voltage of each single-phase inverter;
4. The grid connection according to claim 3, wherein the control unit performs charging of the gate power supply capacitor based on detection voltages of the first voltage detector and the second voltage detector. 5. System inverter device.   The control unit controls a switching element that contributes to charging of the gate power supply capacitor so that a charge voltage of the gate power supply capacitor becomes equal to or higher than a predetermined value by one ON / OFF control. The grid connection inverter apparatus of Claim 3 or 4. In the grid-connected inverter device linked to the power system,
A converter that converts the input DC voltage to output, and
It has a plurality of single-phase inverters that convert the DC voltage output from the converter into an AC voltage and output it, and outputs the total voltage generated by the generated voltages of the plurality of single-phase inverters connected in series with the AC side terminal An inverter unit to
A switch for switching whether to output the output of the inverter unit to a power system;
A control unit for controlling operations of the inverter unit and the switch;
With
The inverter unit is
A first gate power supply that operates as a power supply for driving the switching element of the lower arm among the plurality of switching elements constituting each single-phase inverter;
A second power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm among the plurality of switching elements and includes a gate power source capacitor that is supplied with DC power from the first gate power source. Gate power supply,
And having
Of the two pairs of switching elements capable of operating in synchronism, when the gate signals for driving one pair of switching elements are configured to be shared,
When the inverter unit and the power system are not linked to each other, the control unit includes the gate power supply so that the charging voltage of the gate power supply capacitor becomes a predetermined value or more by one ON / OFF control. A grid-connected inverter device that controls a switching element that contributes to charging of a capacitor for use. In the grid-connected inverter device linked to the power system,
A converter that converts the input DC voltage to output, and
It has a plurality of single-phase inverters that convert the DC voltage output from the converter into an AC voltage and output it, and outputs the total voltage generated by the generated voltages of the plurality of single-phase inverters connected in series with the AC side terminal An inverter unit to
A switch for switching whether to output the output of the inverter unit to a power system;
A control unit for controlling operations of the inverter unit and the switch;
A first voltage detector for detecting a voltage of the power system;
A second voltage detector for detecting a bus voltage of each single-phase inverter;
With
The inverter unit is
A first gate power supply that operates as a power supply for driving the switching element of the lower arm among the plurality of switching elements constituting each single-phase inverter;
A second power source configured by a bootstrap circuit that operates as a driving power source for the switching element of the upper arm among the plurality of switching elements and includes a gate power source capacitor that is supplied with DC power from the first gate power source. Gate power supply,
And having
Of the single-phase inverters constituting the inverter unit, in the first single-phase inverter in which the inverter bus is connected to the output terminal of the converter, among the two pairs of switching elements capable of operating in synchronization While configured to share a gate signal that drives a pair of switching elements,
Among the single-phase inverters constituting the inverter unit, in the single-phase inverters other than the first single-phase inverter, gate signals for driving two pairs of switching elements that can operate synchronously are shared. Configured to be
The controller is configured to charge one or more uncharged inverter bus capacitors in a single-phase inverter other than the first single-phase inverter and charge a gate power supply capacitor of the first single-phase inverter. The grid-connected inverter device is characterized in that the switching element is ON / OFF controlled a plurality of times when charging the gate power supply capacitor to be charged.   The control unit includes the inverter and the power system based on a detection voltage of the first voltage detector when the inverter and the power system are in an interconnected state and the inverter is in a stopped state. The grid-connected inverter device according to claim 7, wherein the gate power supply capacitor is charged by performing ON / OFF control of the switching element so that no backflow current flows between the gate power supply and the switching power supply.   8. The grid connection according to claim 7, wherein the control unit performs charging of the gate power supply capacitor based on detection voltages of the first voltage detector and the second voltage detector. 9. System inverter device.

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