JP5990473B2 - Display device with touch detection function and memory circuit - Google Patents

Description

  Embodiments described herein relate generally to a display device with a touch detection function and a memory circuit.

  In recent years, attention has been paid to a display device in which a touch detection device called a touch panel is mounted on a display device such as a liquid crystal display device or the touch panel and the display device are integrated so that information can be input instead of a normal mechanical button. Has been. Since a display device having such a touch panel does not require an input device such as a keyboard, the use of the display device tends to be expanded in a portable information terminal such as a mobile phone as well as a computer.

  There are several types of touch detection methods, such as optical and resistance methods. Capacitive touch that has a relatively simple structure and can achieve low power consumption, especially in mobile devices. A detection device is expected. For example, in Patent Documents 1 and 2, a display common electrode provided in a display device is also used as one of touch sensor electrodes, and the other electrode (touch detection electrode) is used as the common electrode. There has been proposed a display device arranged so as to intersect.

  A capacitance is formed between the common electrode and the touch detection electrode, and the capacitance changes according to the proximity of an external object. Therefore, the proximity of an external object can be detected by analyzing the touch detection signal that appears on the touch detection electrode when a drive signal for touch detection is applied to the common electrode.

JP 2009-244958 A JP 2012-48295 A

  By the way, in a device sharing an electrode for the display operation and the touch detection operation, it is necessary to stop the scanning line driving circuit for performing display during the touch detection period. The scan line driver circuit is generally configured using a shift register. However, when the shift register is configured using either an NMOS or CMOS transistor, a node in the shift register causes the transistor to leak off during the stop period. May cause potential fluctuations and malfunction.

  The present invention has been made in view of the above, and an object thereof is to provide a display device with a touch detection function that can operate stably even during a touch detection period, and the display device with the touch detection function. Another object is to provide a memory circuit used in the above.

  A display device with a touch detection function according to one embodiment of the present invention includes a plurality of display elements that perform a display operation based on a pixel signal and a display drive signal, and a touch detection element that detects the proximity of an external object based on the touch detection drive signal A scanning line driving circuit for sequentially supplying the pixel signals and the previous display driving signal to the plurality of display elements in a time-sharing manner, and a touch driving circuit for supplying the touch detection driving signal to the touch detection element The touch drive circuit supplies the touch detection drive signal to the touch detection element in a touch detection operation period different from a display operation period in which the display scan is performed, and the scan line drive circuit In the detection period, the display device with a touch detection function uses the touch detection drive signal as a drive circuit operation stabilization signal.

It is a figure showing an example of 1 composition of a display with a touch detection function concerning an embodiment of the invention. It is a figure showing an example of 1 composition of a display with a touch detection function concerning an embodiment of the invention. It is a figure which represents typically the relationship between the display of the display apparatus with a touch detection function which concerns on embodiment of this invention, and touch detection. It is a figure which extracts and shows the structure regarding a liquid crystal display device among the display devices with a touch detection function which concerns on embodiment of this invention. It is a figure which shows the structure of the conventional auxiliary capacitance line drive circuit. It is a figure for demonstrating the example of 1 structure of the auxiliary capacity line drive circuit incorporating the memory circuit. It is a timing chart for demonstrating the drive method of the conventional display apparatus. It is a figure for demonstrating the through-current by the drive method of the conventional display apparatus. 6 is a timing chart for explaining a driving method of a display device incorporating a memory circuit. It is a figure for demonstrating the through current by the drive method of a display apparatus. It is a circuit diagram in which a memory circuit is applied to a shift register in a scanning line driving circuit. It is a block diagram which shows the connection of the whole shift register. It is a figure for demonstrating the problem at the time of applying a shift register to the display apparatus with a touch detection function. FIG. 10 is a circuit diagram in which the memory circuit of the display device with a touch detection function according to the present embodiment is applied to a shift register in a scanning line driving circuit. It is a block diagram which shows the connection of the whole shift register of the display apparatus with a touch detection function which concerns on this Embodiment. It is a timing chart of the shift register of the display device with a touch detection function according to the present embodiment. FIG. 10 is a circuit diagram in which the memory circuit of the display device with a touch detection function according to the present embodiment is applied to a shift register in a scanning line driving circuit.

  FIG. 1 is a diagram illustrating a configuration example of a display device with a touch detection function according to an embodiment of the present invention.

  The display device with a touch detection function 1 uses a liquid crystal display element as a display element. And the liquid crystal display device comprised by a liquid crystal display element and the electrostatic capacitance type touch detection device are integrated. That is, the display device with a touch detection function 1 is a so-called in-cell type display device.

  The display device with a touch detection function 1 includes a control unit CONT, a scanning line drive circuit VD, a touch drive circuit TD, a source driver HD, and a display device with a touch detection function DYP on an array substrate. The display device DYP is divided into a plurality of touch signal blocks.

  The control unit CONT supplies control signals to the scanning line driving circuit VD, the source driver HD, the touch driving circuit TD, and the display device with touch detection function DYP so that these operate in cooperation with each other. Control.

  The scanning line drive circuit VD drives a shift register provided therein based on control signals (clock pulse signal CLK, start pulse signal STP, etc.) supplied from the control unit CONT, and performs display drive of the display device DYP. One horizontal line (scanning line) to be subjected to is sequentially selected. The source driver HD outputs a pixel voltage to the display device DYP based on a control signal and a video signal supplied from the control unit CONT.

  The touch drive circuit TD drives shift registers provided therein based on control signals (such as a clock pulse signal TCLK and a start pulse signal TST) supplied from the control unit CONT, and sequentially outputs switching signals. By this switching signal, driving signals (VCOMAC, VCOMDC) supplied from an external circuit (not shown) are switched, and the driving signal VCOMAC is sequentially output for each touch signal application block. A drive signal VCOMDC is output to a block for which no shift register is selected. In the display device DYP, for example, a plurality of drive electrodes VCOM (not shown) extending in the horizontal direction in the figure are arranged in the vertical direction. The drive signal VCOMAC is supplied to the drive electrode VCOM of the display device DYP.

  FIG. 2 is a diagram illustrating a configuration example of a display device with a touch detection function according to the embodiment of the present invention. In FIG. 2, a counter substrate is shown superimposed on the array substrate of FIG.

  On the counter substrate, a plurality of touch detection electrodes extended in the vertical direction in the figure are arranged in the horizontal direction. For this reason, the drive electrode VCOM and the touch detection electrode are opposed to each other with the dielectric D interposed therebetween to form a capacitive element. And the capacity | capacitance of the element formed changes whether a finger is contacting the touch detection electrode. Accordingly, the touch position can be determined by detecting the potential (touch panel detection signal) of each touch detection electrode generated by the drive signal VCOMAC.

  FIG. 3 is a diagram schematically showing a relationship between display and touch detection of the display device with a touch detection function according to the embodiment of the present invention. In the present embodiment, a touch period is provided every 32 horizontal periods, and the display period and the touch detection period are alternately repeated for each touch signal application block. The drive signal VCOMAC is input to the block only during the touch detection period.

  That is, in the display period of the first block, the gate signals (G1 to G32) are sequentially output to the display rows (1 to 32) to display the first block. In the touch detection period of the first block, the drive signal VCOMAC is input to the touch signal application block 1 to perform touch detection of the first block.

  In the display period of the second block, the gate signals (G33 to G64) are sequentially output to the display rows (33 to 64) to display the second block. In the touch detection period of the second block, the drive signal VCOMAC is input to the touch signal application block 2 and the touch detection of the second block is performed.

  Thereafter, the blocks are sequentially selected, and the display operation and the touch detection operation are performed.

  Subsequently, a circuit configuration of a shift register provided in the scanning line driving circuit VD will be described. The shift register uses a memory circuit devised by the inventors. Since this memory circuit has a characteristic configuration of the drive circuit of this embodiment, the technical significance and configuration of the memory circuit will be described before describing the shift register of this embodiment.

  FIG. 4 is a diagram showing an extracted configuration related to the liquid crystal display device among the display devices with a touch detection function according to the embodiment of the present invention.

  The liquid crystal display device shown in FIG. 4 includes an array substrate SB1, a counter substrate (not shown) disposed so as to face the array substrate SB1, and a liquid crystal layer sandwiched between the array substrate SB1 and the counter substrate. LQ and a display unit DYP including a plurality of display pixels PX arranged in a matrix.

  The array substrate SB1 includes pixel electrodes PE arranged in a matrix so as to correspond to the display pixels PX, and a plurality of scanning lines G (G1, G2,... Gn extending along rows in which the pixel electrodes PE are arranged. ) And auxiliary capacitance lines Cs (Cs1, Cs2,... Csn), a plurality of signal lines S (S1, S2,... Sm) extending along a column in which the pixel electrodes PE are arranged, and a plurality of scanning lines A pixel switch T (T11 to Tnm) disposed in the vicinity of a position where G and the plurality of signal lines S intersect, a scanning line driving circuit VD for driving the plurality of scanning lines G and the auxiliary capacitance lines Cs, and a plurality of signals And a source driver HD for driving the line S. The counter substrate includes a counter electrode arranged to face the plurality of pixel electrodes PE.

  The pixel switch T is, for example, a thin film transistor. The control electrode of the pixel switch T is electrically connected to the corresponding scanning line G. The source electrode of the pixel switch T is electrically connected to the corresponding signal line S. The drain electrode of the pixel switch T is electrically connected to the corresponding pixel electrode PE.

  By the way, the alignment state of the liquid crystal molecules contained in the liquid crystal layer is controlled by the voltage applied to the pixel electrode and the voltage applied to the counter electrode. When the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, resulting in an afterimage phenomenon and shortening the life of the liquid crystal layer. In order to prevent this, in the liquid crystal display device, the voltage applied to the liquid crystal layer is changed to AC every certain time, that is, the voltage applied to the pixel electrode is determined for a certain time based on the voltage applied to the counter electrode. Every time it is changed to the positive voltage side and the negative voltage side.

  As a driving method for applying an alternating voltage to the liquid crystal layer in this way, the voltage of the auxiliary capacitor line is controlled during the period when the pixel switch is off (non-conducting state), and the amount of change in the signal potential supplied to the signal line In addition, a capacitive coupling (CC) driving system that increases the amount of change in pixel electrode potential is known.

  In a liquid crystal display device adopting a capacitive coupling driving method, if a driving circuit for driving an auxiliary capacitance line is constituted by a CMOS circuit, the manufacturing process may increase. Conventionally, in order not to increase the number of manufacturing processes, a technique has been proposed in which a driving circuit for driving an auxiliary capacitance line is configured with either a PMOS or NMOS transistor circuit.

  FIG. 5 is a diagram showing a configuration of a conventional storage capacitor line driving circuit. The auxiliary capacitance line driving circuit shown in FIG. 5 uses an NMOS transistor as a transistor. In FIG. 5, VSRn + 1 is an (n + 1) th scanning line selection signal output from the scanning line driving circuit, and M and MB are alternating signals. VCSH is a positive common signal supplied to the auxiliary capacitance line, and VCSL is a negative common voltage connected to the auxiliary capacitance line.

  When the scanning line selection signal (VSRn + 1) is at a high level, the alternating signal (M) is at a high level, and the alternating signal (MB) is at a low level, the node (ND1) is at a high level and the node (ND2) is at a low level. The positive common voltage (VCSH) is output as the output (Csn).

  When the scanning line selection signal (VSRn + 1) is at a high level, the alternating signal (M) is at a low level, and the alternating signal (MB) is at a high level, the node (ND1) is at a low level and the node (ND2) is at a high level. As a result, a negative common voltage (VCSL) is output as the output (Csn).

  In FIG. 5, in order to make the common voltage applied to the auxiliary capacitance line Csn an alternating current, the potentials of the node (ND1) and the node (ND2) even after the transistor (Tr9) and the transistor (Tr10) are turned off. One of them must be held at the high level and the other at the low level without changing the voltage, and the transistor (Tr11 or Tr12) that outputs the common voltage needs to be continuously turned on for one frame period. is there. Therefore, a memory circuit composed of Tr1, 2, 4, and 5 is provided.

  As shown in FIG. 5, in the memory circuit, the input / output terminals of two NMOS inverters (an inverter composed of Tr1 and Tr2 and an inverter composed of Tr4 and 5) are connected to each other. Yes. The reference voltages (VDD and VSS) of the inverter are voltages corresponding to the high level and low level of the alternating signal (M, MB). By connecting the memory circuits in this manner, the nodes (ND1, ND2) can maintain the high level and the low level without being in a floating state even when the transistors Tr9, Tr10 are OFF. Thus, ON / OFF of Tr12 can be stabilized, and the potential of the output (Csn) can be stabilized.

  However, in the circuit configuration of FIG. 5, in the two NMOS inverters in which the voltage input to the control electrodes of Tr2 and Tr5 is a high level, both the two transistors constituting the inverter are turned on, and VDD → Tr1 There is a problem that a through current is generated along the route of (Tr4) → Tr2 (Tr5) → VSS, resulting in an increase in power consumption.

  In the memory circuit of FIG. 5, high level writing to the node ND1 is performed via the NMOS transistors Tr4 and Tr9, and high level writing to the node ND2 is performed via the NMOS transistors Tr1 and Tr10. Is called. As a result, a drop in Vth occurs, the High level does not rise completely to the VDD potential, and the write characteristics of the output (Csn) via Tr11 and Tr12 may deteriorate.

  Therefore, there has been a demand for a memory circuit that has low power consumption and can suppress a voltage drop at the output level. The inventors have devised a memory circuit that can meet such needs.

FIG. 6 is a diagram for explaining a configuration example of a storage capacitor line driving circuit in which a memory circuit capable of meeting needs is incorporated.
FIG. 6 schematically shows a configuration example of the auxiliary capacitance line driving circuit CAn, but the configurations of the other auxiliary capacitance line driving circuits CA1 to CAn-1 are the same.

  In the circuit of FIG. 6, in the conventional storage capacitor line driving circuit (FIG. 5), the connection destination of the control electrodes of the transistor (Tr1) and the transistor (Tr4) is changed from VDD to the node (ND4) and the node (ND3), respectively. In addition, a transistor (Tr6) and a transistor (Tr3) whose control electrodes are connected to VDD are added between the node ND1 and the node ND3 and between the nodes ND2 and ND4, respectively. The control electrode is connected to the node (ND2), the first electrode is connected to the VDD, the second electrode is connected to the node (ND4) (Tr7), the control electrode is connected to the node (ND1), and the first electrode A transistor (Tr8) in which one electrode is connected to VDD and the second electrode is connected to a node (ND3) is further added. Capacitance elements (C2 and C1) are connected to the node (ND3) and the node (ND4), respectively, and the other end of the capacitance element is connected to the clock signal (CLK).

  In the conventional storage capacitor line driving circuit (FIG. 5), the high level of the node (ND1) is written using the transistors (Tr4 and Tr9). The high level of the node (ND2) is written using the transistors (Tr1 and Tr10). At this time, the control electrodes of the respective transistors (Tr1, Tr4, Tr9, and Tr10) are written at the VDD level, so that the output becomes the VDD-Vth level where the voltage drops by Vth of the transistor. Therefore, even if a voltage drop occurs in the node (ND1) and the node (ND2), in order to ensure switching to the output Csn, it is necessary to set the VDD level higher in advance, which increases circuit power consumption. There is a problem.

  FIG. 7 is a timing chart for explaining a driving method of a conventional display device. Here, each of the periods A and B represents one frame period, and the potential VCs of the storage capacitor line Cs is changed between H (High) and L (Low) in the periods A and B.

  In the conventional storage capacitor line driving circuit (FIG. 5), the control electrodes of the transistor (Tr1) and the transistor (Tr4) are always connected to VDD. Therefore, in the period A in the timing chart of FIG. 7, since the node (ND1) is at the low level and the node (ND2) is at the high level, both the transistor (Tr4) and the transistor (Tr5) are turned on. On the other hand, in the period B, since the node (ND1) is at a high level and the node (ND2) is at a low level, both the transistor (Tr1) and the transistor (Tr2) are turned on. Therefore, as shown in FIG. 8, in any period, a through current flows through the path of VDD → VSS, resulting in a problem that the circuit power consumption increases.

  Note that FIG. 7 shows the potential change of each node in the n-th storage capacitor line drive circuit CAn as an example, but the same problem may occur in other stages. For this reason, the increase in power consumption increases the number of stages of the auxiliary capacitance line driving circuit.

  On the other hand, in the storage capacitor line driving circuit of the embodiment shown in FIG. 6, the control electrodes of the transistor (Tr1) and the transistor (Tr4) are connected to their own inverters via the transistors (Tr3) and (Tr6), respectively. Output (ND2 and ND1 respectively) are connected by feedback, and coupling capacitive elements (C1 and C2 respectively) are connected to the control electrode.

  FIG. 9 is a timing chart for explaining a driving method of a display device incorporating a memory circuit that can meet the needs. That is, FIG. 9 is a timing chart when the storage capacitor line driving circuit shown in FIG. 6 is used.

  At time t1, when the SRn + 1 output becomes high level, the transistors (Tr9, Tr10) are turned on, the low level is set in the nodes (ND1) and (ND3), the high level is set in the nodes (ND2) and (ND4), respectively. Written. At this time, the high level of the node (ND2) and the node (ND4) has a voltage drop from VDD by Vth of the transistor (Tr10).

  When the CLK signal becomes High level at time t2, the potential of the node (ND4) rises due to coupling of the capacitor (C1). For this reason, the transistor (Tr3) is turned off. At this time, if the amplitude of the CLK signal between High and Low is sufficiently large, the potential of the node (ND4) can be made higher than VDD + Vth. As a result, the transistor (Tr1) is reliably turned on, and the VDD level is supplied to the node (ND2).

  When the CLK signal becomes low level at time t3, the node (ND4) is pulled down to the VDD-Vth level and the transistor (Tr1) is turned off, but the node (ND2) remains floating and the VDD level is raised. Keep keeping.

  At time t4, the SRn + 1 output becomes low level and the input to the memory circuit is disconnected, but the high and low states of the nodes (ND1 to ND4) are maintained.

  When the CLK signal again becomes a high level at time t5, the complete VDD level is supplied to the node (ND2) as in the times t2 to t3.

  A series of operations is repeated until time t6 when the SR2 output next becomes a high level.

  As described above, the node (ND2) is repeatedly supplied with the VDD level and in the floating state, but the floating period is only a short period between CLK and Low. Therefore, a voltage drop due to the transistor OFF leakage does not occur, and the VDD level can be maintained.

  On the other hand, the low level (VSS level) is always supplied from the transistor (Tr5) to the node (ND1) and the node (ND3) during the period A. Since the transistor (Tr4) and the transistor (Tr2) are turned off, the potentials of the node (ND1) and the node (ND2) are stably maintained at the VSS level and the VDD level.

  After the time t6, when the SRn + 1 output again becomes a high level, in the period B, signals opposite in phase to the times t1 to t4 are supplied to M and MB, and the nodes (ND1) and (ND3) The node (ND2) and the node (ND4) are inverted to the low level to the high level, and the potentials of the node (ND1) and the node (ND2) are stabilized similarly to the time t1 to t5, and the VDD level and the VSS level are set. Keep keeping.

  As described above, since a voltage drop does not occur in the potentials of the node (ND1) and the node (ND2), the ON / OFF of the transistor (Tr11) and the transistor (Tr12) is stable, and the output Cs1 is stably VCSH. VCSL level can be supplied. When setting the VDD voltage, it is not necessary to consider the voltage drop of the node (ND1) and the node (ND2), and as a result, it is not necessary to set the VDD voltage higher than necessary, so that the power consumption is kept low. I can do it.

  Further, in the period A and the period B in FIG. 9, the potential relationship of the inverter that supplies Low to the output is as shown in FIG.

  Unlike the conventional example shown in FIG. 8, since the transistor (Tr4) in the period A and the transistor (Tr1) in the period B are turned off, no through current is generated between VDD and VSS, and power consumption is kept low. I can do it.

  As described above, the NMOS inverter provided in the memory circuit of FIG. 6 detects the high level of the outputs (ND2, ND1), and inputs to the control electrodes of the transistor (Tr1) and the transistor (Tr4), respectively. The auto-regressive function of enhancing the high level output from the transistor (Tr1) and the transistor (Tr4), respectively, is provided. The inventors have named this circuit SFC (Self Feedback Circuit) because it has such an action.

  Note that the transistor (Tr7) and the transistor (Tr8) have a role of supplementing the holding of the high level when the node (ND4) and the node (ND3) are at the high level.

  When the off-leakage of the transistor (Tr3) and the transistor (Tr6) is large, the high level potentials of the node (ND4) and the node (ND3) may be reduced through these transistors. By disposing the transistor (Tr7) and the transistor (Tr8) whose first electrode is connected to VDD, the voltage drop at the node (ND4) and the node (ND3) can be reduced.

  When the node (ND1, ND3) and the node (ND2, ND4) are at the low level, the transistor (Tr7) and the transistor (Tr8) are turned off, so that the operation is not affected.

  Note that although the CLK signal operates in one cycle in one horizontal period in FIG. 9, the present embodiment is not limited to this form, and the high level of the nodes (ND 1) and (ND 3) The frequency can be lowered within a range that does not cause a drop. If it is operated at a lower frequency, the power consumption of the circuit can be further reduced. Further, although the CLK signals connected to the capacitor elements (C1, C2) have been described as the same signal, the same effect can be obtained even when different CLK signals are input.

  The newly added capacitors (C1, C2) are intended to hold the node (ND3) or the node (ND4) at a voltage equal to or higher than VDD + Vth only when the CLK signal is High. Since it is not necessary to hold the potential of the node (ND1) or the node (ND2) for one frame period, the capacitance value can be set to be considerably small, and the increase in circuit scale due to the addition of the capacitor element is generally suppressed to an error level. It becomes possible.

  Although the above-described memory circuit is applied to an auxiliary capacitance line driving circuit, the present invention is not limited to this, and can be applied to various driving circuits.

  FIG. 11 is a circuit diagram in which the memory circuit is applied to a shift register in the scanning line driving circuit. FIG. 12 is a block diagram showing connections of the entire shift register.

  Input to the memory circuit in the shift register is performed by IN and RESET in FIG. When IN becomes High, the node (ND1) and the node (ND3) become High level, the node (ND2) and the node (ND4) become Low level, and the CLK signal is output to OUT via the Tr11. When RESET becomes High, the node (ND1) and the node (ND3) become Low level, the node (ND2) and the node (ND4) become High level, and the VSS level is output to OUT via the Tr12. The operation of the memory when both IN and RESET are Low is the same as described in the example applied to the storage capacitor line driving circuit.

  As shown in FIG. 12, the previous shift register output is input to IN, and the next shift register output is input to RESET. The shift operation is performed by using the two-phase clock signals CLK1 and CLK2 and alternately inputting the two-phase clock signals to each stage of the shift register.

  The shift register shown in FIG. 11 also prevents the malfunction of the circuit due to the excessive off-leakage current flowing in the transistor because the node (ND1) and the node (ND2) are short in the floating period as in the example of the auxiliary capacitor driving circuit. can do. Further, since no through current is generated via VDD → Tr1 (Tr4) → Tr2 (Tr5) → VSS, the power consumption can be kept low. Further, since the high level Vth drop of the node (ND1) and the node (ND2) does not occur, the switching characteristics of the transistor (Tr11) and the transistor (Tr12) are improved, and the potential of the output OUT can be stabilized. When setting the VDD voltage, it is not necessary to consider the voltage drop of the node (ND1) and the node (ND2), and as a result, it is not necessary to set the VDD voltage higher than necessary, so that the power consumption is kept low. I can do it. Furthermore, since the capacitance values of the capacitive elements (C1, C2) can be set to be quite small, an increase in circuit scale due to the addition of the capacitive elements can be suppressed to an error level.

  However, if the shift register shown in FIG. 11 is applied to a display device with a touch detection function, the following problem occurs.

  FIG. 13 is a diagram for explaining problems when the shift register shown in FIG. 11 is applied to a display device with a touch detection function.

  In the display period, the gate signals (G1 to G32) are sequentially output to the display rows (1 to 32) by the operations of the clocks CLK1 and CLK2, and the first block is displayed. However, since it is necessary to stop the output of the subsequent gate signals (G33 to G64) in the touch detection period, the operation of the shift register must be stopped. For this reason, it is necessary to stop the operations of the clocks CLK1 and CLK2 during the touch detection period.

  Therefore, in the touch detection period, the clocks CLK1 and CLK2 are stopped and the drive signal VCOMAC is input. However, since no clock is input in this state, when there is no coupling signal to the SFC circuit of the memory circuit and the transistor has a large off-leakage, the nodes (ND1 to ND5) change in potential and the shift register operates normally. There is a risk of disappearing. The lower part of FIG. 13 shows the potential fluctuation state of the nodes (ND1 to ND5) in the 33rd stage shift register circuit.

  FIG. 14 is a circuit diagram in which the memory circuit of the display device with a touch detection function according to the embodiment of the present invention is applied to a shift register in a scanning line driving circuit. In FIG. 14, the VCOMAC signal is further connected to the node ND4 of the shift register shown in FIG. 11 via the capacitor C3, and the VCOMAC signal is further connected to the node ND3 via the capacitor C4.

  FIG. 15 is a block diagram showing connections of the entire shift register of the display device with a touch detection function according to the embodiment of the present invention. Each shift register is connected to a VCOMAC that is a signal input to the display device DYP during the touch detection period.

  FIG. 16 is a timing chart of the shift register of the display device with a touch detection function according to the embodiment of the present invention. Since it is necessary to stop the operation of the shift register in the touch detection period, it is necessary to fix the CLK signal to the Low level as shown in FIG. At this time, VCOMAC is used as a coupling signal of the SFC circuit. By using this coupling signal, the nodes (ND1 to ND5) of each shift register can stably hold the High and Low potentials.

  In the present embodiment, the VCOMAC signal is used as the coupling signal during the touch detection period. If a signal other than VCOMAC is used, the signal is applied to the shift register at a timing different from VCOMAC in the touch detection period. For this reason, this signal may be transmitted as noise from the array substrate to the touch detection electrode of the counter substrate via the parasitic capacitance, which may be a factor of deteriorating the sensitivity of the touch panel. On the other hand, by using VCOMAC as a coupling signal, it is possible to eliminate such noise and obtain a good touch function.

  Although the same signal as VCOMAC is used as the coupling signal, the same signal is not necessarily required if the switching timing of High and Low is the same. That is, the coupling signal does not become a noise source of the touch panel even if the VCOMAC is different from the High level voltage and the Low level voltage, so that a good touch function can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  For example, as shown in FIG. 17, the same effect can be obtained even when VCOMAC and CLK from an external circuit (not shown) are switched using a switch between a display period and a touch detection period.

  The same effect can be obtained by using VCOMAC instead of CLK.

  In the present embodiment, the description has been made using the circuit using the NMOS transistor, but it goes without saying that the same effect can be obtained by using the PMOS transistor. It is possible for a person skilled in the art to configure a circuit using a PMOS transistor by demonstrating normal creativity.

  In the present description, the embodiment in which the present invention is applied to a liquid crystal display device has been described. However, the present invention is not limited to this, and can be applied to, for example, an EL display device using an organic EL element or the like. Needless to say.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  LQ ... liquid crystal layer, PX ... display pixel, DYP ... display device, PE ... pixel electrode, G1-Gn ... scanning line, Cs1-Csn ... auxiliary capacitance line, S1-Sm ... signal line, T ... pixel switch, CONT ... control , VD: Scanning line drive circuit, TD: Touch drive circuit, HD: Source driver, C: Auxiliary capacitor, Clc: Liquid crystal capacitor, SR1-SRn + 1: Shift register, CA1-CAn ... Auxiliary capacitance line drive circuit, Tr1-Tr14 ... transistor circuit, VCSH ... reference voltage (high level), VCSL ... reference voltage (low level), VDD, VSS ... reference voltage, C1-C4 ... retention capacitor, ND1-ND5 ... first to fifth nodes, CLK1, 2 ... clock signal, STP ... start pulse, M, MB ... clock signal, VCOMAC ... drive signal.

Claims (7)

A plurality of display elements that perform a display operation based on a pixel signal and a display drive signal;
A touch detection element that detects the proximity of an external object based on a touch detection drive signal;
A scanning line driving circuit for performing a display operation by sequentially supplying the pixel signal and the previous display driving signal to the plurality of display elements in a time-sharing manner;
A touch drive circuit for supplying the touch detection drive signal to the touch detection element,
The touch drive circuit supplies the touch detection drive signal to the touch detection element in a touch detection operation period different from a display operation period in which the display scanning is performed,
The scanning line drive circuit uses the touch detection drive signal as a drive circuit operation stabilization signal in the touch detection period. A display device with a touch detection function.   2. The display device with a touch detection function according to claim 1, wherein the transistor circuit constituting the scanning line driving circuit includes only one of an NMOS transistor and a PMOS transistor. The scanning line driving circuit includes a plurality of memory circuits that store and output a binary level driving signal from the shift register for a predetermined period of time,
The memory circuit includes:
A first transistor circuit, wherein a first power supply voltage is applied to the first electrode, and the control electrode and the second electrode are provided;
A second transistor circuit having a first electrode connected to a second electrode of the first transistor circuit, a second power supply voltage applied to the second electrode, and a control electrode;
A third transistor circuit in which the first power supply voltage is applied to the control electrode, the first electrode is connected to the second electrode of the first transistor circuit, and the second electrode is connected to the control electrode of the first transistor circuit; ,
A first capacitive element formed between a control electrode of the first transistor and a first clock signal electrode to which a clock voltage of a first clock signal is applied;
A third capacitive element formed between a control electrode of the first transistor and a third clock signal electrode to which a clock voltage of the touch detection drive signal is applied;
A seventh transistor circuit having a control electrode connected to the second electrode of the first transistor, the first power supply voltage applied to the first electrode, and a second electrode connected to the control electrode of the first transistor;
A fourth transistor circuit having a control electrode, wherein the first power supply voltage is applied to a first electrode, a second electrode is connected to a control electrode of the second transistor circuit;
A fifth transistor circuit in which a control electrode is connected to a second electrode of the first transistor, a first electrode is connected to a control electrode of the second transistor circuit, and the second power supply voltage is applied to a second electrode; ,
A sixth transistor circuit in which the first power supply voltage is applied to the control electrode, the first electrode is connected to the control electrode of the second transistor circuit, and the second electrode is connected to the control electrode of the fourth transistor circuit;
A second capacitive element formed between a control electrode of the fourth transistor and a second clock signal electrode to which a clock voltage of a second clock signal is applied;
A fourth capacitive element formed between a control electrode of the fourth transistor and a fourth clock signal electrode to which a clock voltage of the touch detection drive signal is applied;
An eighth transistor circuit having a control electrode connected to the control electrode of the second transistor, the first power supply voltage applied to the first electrode, and a second electrode connected to the control electrode of the fourth transistor. The display device with a touch detection function according to claim 2. A clock signal of one level of the drive signal is input to the control electrode of the second transistor circuit,
A clock signal of the other level of the drive signal is input to the control electrode of the fifth transistor circuit,
A clock voltage larger than a voltage obtained by adding a threshold voltage Vth to the first and second power supply voltages is applied to the first and second clock signal electrodes,
The held one of the first power supply voltage and the second power supply voltage is output from the second electrode of the fourth transistor circuit,
4. The display device with a touch detection function according to claim 3, wherein the held one of the first power supply voltage and the second power supply voltage is output from the second electrode of the first transistor circuit. 5.   The clock cycle of the first and second clock signals and the clock cycle of the touch detection drive signal are values in a range in which the voltage of the control electrode of the first and fourth transistor circuits does not cause a voltage drop, respectively. 5. A display device with a touch detection function according to 4. The first capacitive element is shared with the third capacitive element and connected to the first clock signal electrode and the third clock signal electrode via a changeover switch,
4. The touch detection function according to claim 3, wherein the second capacitive element is shared with the fourth capacitive element and is connected to the second clock signal electrode and the fourth clock signal electrode via a changeover switch. 5. Display device.   The said memory circuit provided in the display apparatus with a touch detection function of any one of Claims 1 thru | or 6.

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