JP5982923B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5982923B2
JP5982923B2 JP2012068095A JP2012068095A JP5982923B2 JP 5982923 B2 JP5982923 B2 JP 5982923B2 JP 2012068095 A JP2012068095 A JP 2012068095A JP 2012068095 A JP2012068095 A JP 2012068095A JP 5982923 B2 JP5982923 B2 JP 5982923B2
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bonding
wire
semiconductor chip
relay terminal
lead
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JP2013201238A (en
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裕一 道喜
裕一 道喜
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Yamaha Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

本発明は、半導体チップと接続端子部とをボンディングワイヤにより電気接続した構成の半導体装置に関する。   The present invention relates to a semiconductor device having a configuration in which a semiconductor chip and a connection terminal portion are electrically connected by a bonding wire.

従来の半導体装置には、リードフレームのステージ部の搭載領域面に半導体チップを搭載し、ステージ部の周囲に複数配列されたリードフレームのリード（接続端子部）と半導体チップとをボンディングワイヤにより電気接続したものがある。また、この半導体装置は、ボンディングワイヤが埋設されるように、半導体チップ、ステージ部及び複数のリードを一体に固定する樹脂モールド部を形成して構成されることがある。   In a conventional semiconductor device, a semiconductor chip is mounted on the mounting area surface of the stage portion of the lead frame, and a plurality of lead frame leads (connection terminal portions) arranged around the stage portion are electrically connected to the semiconductor chip by bonding wires. There is something connected. In addition, this semiconductor device may be configured by forming a resin mold portion that integrally fixes a semiconductor chip, a stage portion, and a plurality of leads so that bonding wires are embedded.

ところで、この種の半導体装置において、半導体チップの大きさがステージ部の搭載領域面の面積よりも小さい場合には、あるいは、ステージ部の搭載領域面に対する半導体チップの配置によっては、半導体チップからリードまでの距離が、ステージ部からリードまでの距離と比較して長くなることがある。
そこで、従来では、例えば特許文献１のように、ステージ部（アイランド）の搭載領域面のうち半導体チップ（ペレット）とリード（信号入出力用アウターリード）との間に導電性の中継端子を設け、半導体チップと中継端子との間、及び、中継端子とリードとの間にそれぞれボンディングワイヤを配することで、各ボンディングワイヤの長さを短くすることを図っている。 By the way, in this type of semiconductor device, when the size of the semiconductor chip is smaller than the area of the mounting area surface of the stage portion, or depending on the arrangement of the semiconductor chip with respect to the mounting area surface of the stage portion, the lead from the semiconductor chip is possible. May be longer than the distance from the stage portion to the lead.
Therefore, conventionally, as in Patent Document 1, for example, a conductive relay terminal is provided between the semiconductor chip (pellet) and the lead (signal input / output outer lead) in the mounting area surface of the stage portion (island). The length of each bonding wire is shortened by arranging bonding wires between the semiconductor chip and the relay terminals and between the relay terminals and the leads.

特開平５−２５９２１０号公報JP-A-5-259210

しかしながら、特許文献１に記載の半導体装置では、半導体チップと中継端子との間に配された複数のボンディングワイヤのループ高さが互いに等しいため、相互に隣り合うボンディングワイヤ同士が干渉する、という問題がある。また、相互に隣り合うボンディングワイヤの長さを異ならせることで、ループ高さを相互に異ならせることも考えられるが、この場合には、ループ高さの高いボンディングワイヤの張力が小さくなる。すなわち、ループ高さの高いボンディングワイヤは揺れ動きやすく、隣り合う他のボンディングワイヤと干渉する虞がある。このように、隣り合うボンディングワイヤ同士が干渉することは、特に樹脂モールド部の成形時における溶融樹脂の流れによって生じ易い。
なお、上述した問題は、リードフレームによって構成される半導体装置に限らず、インターポーザ基板等の配線基板の搭載領域面に半導体チップを搭載し、搭載領域面の周囲に複数配列された内部端子面（接続端子部）と半導体チップとをボンディングワイヤにより電気接続した構成の半導体装置にも同様に生じる虞がある。 However, in the semiconductor device described in Patent Document 1, since the loop heights of the plurality of bonding wires arranged between the semiconductor chip and the relay terminal are equal to each other, adjacent bonding wires interfere with each other. There is. Further, it is conceivable to make the loop heights different from each other by making the lengths of the bonding wires adjacent to each other, but in this case, the tension of the bonding wire having a high loop height is reduced. That is, the bonding wire having a high loop height is likely to swing and may interfere with other adjacent bonding wires. Thus, interference between adjacent bonding wires is likely to occur particularly due to the flow of molten resin during molding of the resin mold portion.
The above-described problem is not limited to the semiconductor device constituted by the lead frame, and a plurality of internal terminal surfaces (semiconductor chips are mounted on the mounting region surface of the wiring substrate such as an interposer substrate and arranged around the mounting region surface ( There is a possibility that the same may occur in a semiconductor device having a configuration in which the connection terminal portion) and the semiconductor chip are electrically connected by bonding wires.

本発明は、上述した事情に鑑みてなされたものであって、半導体チップからリード等の接続端子部までの距離がステージ部等の搭載領域面と接続端子部との距離と比較して長くても、相互に隣り合うボンディングワイヤ同士が干渉することを防止できる半導体装置を提供することを目的とする。   The present invention has been made in view of the above-described circumstances, and the distance from the semiconductor chip to the connection terminal portion such as the lead is longer than the distance between the mounting region surface such as the stage portion and the connection terminal portion. Another object of the present invention is to provide a semiconductor device that can prevent bonding wires adjacent to each other from interfering with each other.

上記課題を解決するために、この発明は以下の手段を提案している。
本発明の半導体装置は、半導体チップと、該半導体チップを搭載する搭載領域面、及び、該搭載領域面の周囲に配列された複数の接続端子部を有するベース部とを備え、前記搭載領域面のうち前記半導体チップと複数の前記接続端子部との間には、前記複数の接続端子部の配列方向に配列された複数の接合面を有する中継端子部が設けられ、両端が前記半導体チップと前記接続端子部とに接合されると共に、中途部が前記接合面に接合されることで、前記半導体チップと前記接続端子部とを電気接続するボンディングワイヤを有し、複数の前記接合面のうち、少なくとも前記配列方向に沿って互いに隣り合う二つの接合面の高さ位置が、互いに異なることを特徴とする。
なお、この半導体装置では、複数の接合面に一つずつ接合された複数のボンディングワイヤが、接続端子部の配列方向に沿って配列されることになる。したがって、互いに隣り合うと共に高さ位置が互いに異なる二つの接合面にそれぞれ接合された二つのボンディングワイヤは、接続端子部の配列方向に沿って隣り合うことになる。 In order to solve the above problems, the present invention proposes the following means.
The semiconductor device of the present invention includes a semiconductor chip, a mounting area surface on which the semiconductor chip is mounted, and a base portion having a plurality of connection terminal portions arranged around the mounting area surface. A relay terminal portion having a plurality of joint surfaces arranged in the arrangement direction of the plurality of connection terminal portions is provided between the semiconductor chip and the plurality of connection terminal portions, and both ends thereof are connected to the semiconductor chip. The bonding terminal is bonded to the connection terminal portion, and a midway portion is bonded to the bonding surface, thereby having a bonding wire for electrically connecting the semiconductor chip and the connection terminal portion, and a plurality of the bonding surfaces. The height positions of at least two joint surfaces adjacent to each other along the arrangement direction are different from each other.
In this semiconductor device, a plurality of bonding wires bonded one by one to the plurality of bonding surfaces are arranged along the arrangement direction of the connection terminal portions. Accordingly, two bonding wires that are adjacent to each other and bonded to two bonding surfaces that are different from each other in height are adjacent to each other in the arrangement direction of the connection terminal portions.

そして、前記半導体装置においては、複数の前記接続端子部の一部が直線状に配列されると共に、複数の前記接合面の一部が直線配列された前記接続端子部の配列方向に沿って配列され、直線状に配列された複数の前記接合面は、前記直線状の配列方向の中央に位置する前記接合面から前記配列方向の両端に位置する前記接合面に向かうにしたがって、前記接合面の高さ位置が高くなる、あるいは、低くなるように、階段状に配列されていてもよい。   In the semiconductor device, a part of the plurality of connection terminal portions is arranged in a straight line, and a part of the plurality of joint surfaces is arranged along the arrangement direction of the connection terminal portions arranged in a straight line. A plurality of the joint surfaces arranged in a straight line are arranged such that the joint surfaces of the joint surfaces move from the joint surface located in the center of the linear array direction toward the joint surfaces located at both ends in the array direction. They may be arranged stepwise so that the height position becomes higher or lower.

これらの半導体装置によれば、互いに隣り合う接合面の高さ位置を異ならせることで、半導体チップから中継端子部に至る各ボンディングワイヤのループ高さを最小限に抑えたとしても、隣り合うボンディングワイヤのループ高さが互いに異なるので、接続端子部の配列方向に隣り合うボンディングワイヤが互いに干渉することを防止できる。   According to these semiconductor devices, even if the height of the bonding wires from the semiconductor chip to the relay terminal is minimized by changing the height positions of the bonding surfaces adjacent to each other, the bonding between adjacent bonding surfaces is minimized. Since the wire loop heights are different from each other, it is possible to prevent the bonding wires adjacent in the arrangement direction of the connection terminal portions from interfering with each other.

また、半導体チップから中継端子部に至る全てのボンディングワイヤの長さを最小限にすることで、半導体チップと中継端子部との間に張設されたボンディングワイヤの張力が保たれるので、張設されたボンディングワイヤが外力によって揺れ動くことを抑制できる。さらに、本発明では、相互に隣り合う接合面の高さ位置が互いに異なるので、たとえ張設されたボンディングワイヤが外力によって揺れ動いたとしても、接続端子部の配列方向に隣り合うボンディングワイヤが互いに干渉することを防止できる。
例えば、上記構成の半導体装置が、半導体チップ及びベース部を一体に固定する樹脂モールド部を備える場合でも、この樹脂モールド部の成形時における溶融樹脂の流れによるボンディングワイヤの揺れを抑制でき、樹脂モールド部の成形後においてボンディングワイヤが互いに干渉することを防止できる。 Also, by minimizing the length of all the bonding wires from the semiconductor chip to the relay terminal portion, the tension of the bonding wire stretched between the semiconductor chip and the relay terminal portion is maintained, so It is possible to suppress the bonding wire provided from being shaken by an external force. Furthermore, in the present invention, since the height positions of the adjacent bonding surfaces are different from each other, even if the stretched bonding wires are shaken by an external force, the adjacent bonding wires in the arrangement direction of the connection terminal portions interfere with each other. Can be prevented.
For example, even when the semiconductor device having the above configuration includes a resin mold part that integrally fixes the semiconductor chip and the base part, it is possible to suppress the shaking of the bonding wire due to the flow of the molten resin during molding of the resin mold part. It is possible to prevent the bonding wires from interfering with each other after forming the part.

また、前記半導体装置は、前記ボンディングワイヤの中途部が、前記中継端子部にめり込むように前記接合面に接合されていてもよい。
この半導体装置によれば、中継端子部に対してボンディングワイヤを強固に接合することができる。 The semiconductor device may be bonded to the bonding surface such that a midway portion of the bonding wire is recessed into the relay terminal portion.
According to this semiconductor device, the bonding wire can be firmly bonded to the relay terminal portion.

本発明によれば、半導体チップと接続端子部との距離が、搭載領域面と接続端子部との距離と比較して長くても、接続端子部の配列方向に隣り合うボンディングワイヤが互いに干渉することを防止できる。   According to the present invention, even if the distance between the semiconductor chip and the connection terminal portion is longer than the distance between the mounting region surface and the connection terminal portion, the bonding wires adjacent in the arrangement direction of the connection terminal portions interfere with each other. Can be prevented.

本発明の一実施形態に係る半導体装置を示す要部拡大平面図である。It is a principal part enlarged plan view which shows the semiconductor device which concerns on one Embodiment of this invention. 図１のＡ−Ａ矢視断面図である。It is AA arrow sectional drawing of FIG. 図２のＢ−Ｂ矢視断面図である。It is a BB arrow sectional view of Drawing 2. 図１に示す半導体装置において、中継端子部の接合面に対するボンディングワイヤの接合状態を示す拡大断面図である。2 is an enlarged cross-sectional view illustrating a bonding state of bonding wires to a bonding surface of a relay terminal portion in the semiconductor device illustrated in FIG. 図１〜４に示す半導体装置の製造に際して、配線工程で用いるキャピラリの一例を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing an example of a capillary used in a wiring process when manufacturing the semiconductor device shown in FIGS. 図５に示すキャピラリにより配線工程を実施する拡大断面図であり、（ａ）は中継端子部に対するワイヤの接合を示し、（ｂ）はリードに対するワイヤの接合を示している。FIGS. 6A and 6B are enlarged cross-sectional views in which a wiring process is performed using the capillary shown in FIG. 5, in which FIG. 5A illustrates the bonding of the wire to the relay terminal portion, and FIG. 5B illustrates the bonding of the wire to the lead. 本発明の他の実施形態に係る半導体装置を示す要部拡大平面図である。It is a principal part enlarged plan view which shows the semiconductor device which concerns on other embodiment of this invention. 図７のＣ−Ｃ矢視断面図である。It is CC sectional view taken on the line of FIG. 本発明の他の実施形態に係る半導体装置を示す要部拡大平面図である。It is a principal part enlarged plan view which shows the semiconductor device which concerns on other embodiment of this invention. 中継端子部の変形例を示す要部拡大断面図である。It is a principal part expanded sectional view which shows the modification of a relay terminal part. 本発明の他の実施形態に係る半導体装置を示す要部拡大断面図である。It is a principal part expanded sectional view which shows the semiconductor device which concerns on other embodiment of this invention.

以下、図１〜４を参照して本発明の一実施形態に係る半導体装置について説明する。図１及び図２に示すように、この実施形態に係る半導体装置１は、半導体チップ３と、これを搭載する上面（搭載領域面）５ａを有するステージ部５と、ステージ部５の周囲に間隔をあけて配列される複数のリード（接続端子部）７と、半導体チップ３及び各リード７を相互に電気接続する複数の接続用ワイヤ（ボンディングワイヤ）９と、半導体チップ３、ステージ部５、リード７及び接続用ワイヤ９を一体に固定する樹脂モールド部１１とを備えている。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 1 and 2, the semiconductor device 1 according to this embodiment includes a semiconductor chip 3, a stage portion 5 having an upper surface (mounting area surface) 5 a on which the semiconductor chip 3 is mounted, and a space around the stage portion 5. A plurality of leads (connection terminal portions) 7 arranged with a gap therebetween, a plurality of connection wires (bonding wires) 9 for electrically connecting the semiconductor chip 3 and each lead 7 to each other, the semiconductor chip 3, the stage portion 5, The resin mold part 11 which fixes the lead | read | reed 7 and the wire 9 for a connection integrally is provided.

ステージ部５は、平面視矩形の板状に形成されており、リード７は、ステージ部５の各辺の長手方向に沿って直線状に複数（図示例では７つ）ずつ配列されている。なお、これらステージ部５及びリード７は、金属製薄板に形成されるリードフレーム（ベース部）２を構成するものであり、ステージ部５及びリード７の厚さ寸法は互いに等しい。
半導体チップ３は、ステージ部５と同様に平面視矩形に形成されており、半導体チップ３の各辺がステージ部５の各辺に沿うようにステージ部５の上面５ａに搭載されている。この搭載状態において、半導体チップ３の各辺から各リード７までの距離は、ステージ部５の各辺からリード７までの距離と比較して長く設定されている。
各接続用ワイヤ９の一端は半導体チップ３の上面３ａの周縁に形成された電極パッド（不図示）に接合されており、他端はリード７の上面（内部端子面）７ａに接合されている。なお、電極パッドは、半導体チップ３の上面３ａの各辺に沿って配列されている。 The stage unit 5 is formed in a rectangular plate shape in plan view, and a plurality of leads 7 (seven in the illustrated example) are arranged in a straight line along the longitudinal direction of each side of the stage unit 5. The stage portion 5 and the lead 7 constitute a lead frame (base portion) 2 formed on a thin metal plate, and the thickness dimensions of the stage portion 5 and the lead 7 are equal to each other.
The semiconductor chip 3 is formed in a rectangular shape in plan view like the stage unit 5, and is mounted on the upper surface 5 a of the stage unit 5 so that each side of the semiconductor chip 3 is along each side of the stage unit 5. In this mounted state, the distance from each side of the semiconductor chip 3 to each lead 7 is set to be longer than the distance from each side of the stage unit 5 to the lead 7.
One end of each connection wire 9 is bonded to an electrode pad (not shown) formed on the periphery of the upper surface 3 a of the semiconductor chip 3, and the other end is bonded to the upper surface (internal terminal surface) 7 a of the lead 7. . The electrode pads are arranged along each side of the upper surface 3a of the semiconductor chip 3.

また、上記構成の半導体装置１において、ステージ部５の上面５ａには、各接続用ワイヤ９の中途部を接合する複数の中継端子部２０が設けられている。
各中継端子部２０は、その全体がシリコーンゴムや発泡ゴム等のようにワイヤボンディング時に用いるキャピラリの先端よりも塑性変形しやすく、かつ、リード７よりも展性が高い絶縁材料によって形成されており、半導体チップ３の各辺と直線配列されたリード７との間に配されている。また、各中継端子部２０の突出方向の先端面は、接続用ワイヤ９の中途部を接合する接合面２１をなしている。各中継端子部２０はこの接合面２１を複数有しており、これら複数の接合面２１は直線配列されたリード７の配列方向に沿って配列されている。 In the semiconductor device 1 configured as described above, a plurality of relay terminal portions 20 are provided on the upper surface 5 a of the stage portion 5 to join the midway portions of the connection wires 9.
Each relay terminal portion 20 is formed of an insulating material, such as silicone rubber or foamed rubber, which is more easily plastically deformed than the tip of the capillary used during wire bonding and has higher malleability than the lead 7. The semiconductor chip 3 is arranged between each side of the semiconductor chip 3 and the leads 7 arranged in a straight line. Moreover, the front end surface in the protruding direction of each relay terminal portion 20 forms a joint surface 21 that joins the midway portion of the connection wire 9. Each relay terminal portion 20 has a plurality of joint surfaces 21, and the plurality of joint surfaces 21 are arranged along the arrangement direction of the leads 7 arranged in a straight line.

そして、同一の中継端子部２０に形成された複数の接合面２１は、図２，３に示すように、その配列方向の中央に位置する接合面２１Ａから両端に位置する接合面２１Ｄに向かうにしたがって、接合面２１の高さ位置が高くなるように、階段状に配列されている。なお、図示例においては、中央の接合面２１Ａの両隣に位置する２つの接合面２１Ｂの高さ位置が互いに等しく、また、２つの接合面２１Ｂの外側に隣り合う２つの接合面２１Ｃの高さ位置が互いに等しい。さらに、両端に位置する２つの接合面２１Ｄの高さ位置が互いに等しい。
上記構成の中継端子部２０は、ステージ部５の上面５ａに対向する中継端子部２０の下面自体に接着性を有するように、あるいは、中継端子部２０の下面に接着性を有するテープを設けて構成されてもよいが、例えば別途接着剤によってステージ部５の上面５ａに固定されてもよい。 Then, as shown in FIGS. 2 and 3, the plurality of joining surfaces 21 formed on the same relay terminal portion 20 are directed from the joining surface 21 </ b> A located at the center in the arrangement direction toward the joining surfaces 21 </ b> D located at both ends. Therefore, it arranges in the step shape so that the height position of the joint surface 21 may become high. In the illustrated example, the height positions of the two bonding surfaces 21B located on both sides of the central bonding surface 21A are equal to each other, and the heights of the two bonding surfaces 21C adjacent to the outside of the two bonding surfaces 21B are the same. The positions are equal to each other. Furthermore, the height positions of the two joint surfaces 21D located at both ends are equal to each other.
The relay terminal portion 20 having the above-described configuration has adhesiveness on the lower surface of the relay terminal portion 20 facing the upper surface 5a of the stage portion 5, or is provided with an adhesive tape on the lower surface of the relay terminal portion 20. Although it may be configured, for example, it may be fixed to the upper surface 5a of the stage portion 5 by an adhesive.

そして、図４に示すように、接続用ワイヤ９の中途部は、上記構成の中継端子部２０にめり込むようにして接合面２１に接合されている。この接合状態において、接合面２１には接続用ワイヤ９の中途部が埋設される凹部２３が形成されている。なお、図示例において、接続用ワイヤ９の中途部は、その全てが凹部２３内に埋設されているが、例えば一部のみがこの凹部２３内に埋設されていてもよい。このように接続用ワイヤ９の中途部が凹部２３内に埋設されることで、中継端子部２０に対して接続用ワイヤ９を強固に接合することができる。   As shown in FIG. 4, the midway portion of the connection wire 9 is joined to the joining surface 21 so as to be recessed into the relay terminal portion 20 having the above-described configuration. In this bonded state, the bonding surface 21 is formed with a recess 23 in which a midway portion of the connecting wire 9 is embedded. In the illustrated example, the middle part of the connection wire 9 is all embedded in the recess 23, but only a part of the connection wire 9 may be embedded in the recess 23, for example. In this way, the connection wire 9 can be firmly joined to the relay terminal portion 20 by the midway portion of the connection wire 9 being embedded in the recess 23.

図２に示すように、樹脂モールド部１１は、ステージ部５の上面５ａ及び側面、リード７の上面７ａ及び側面の一部、半導体チップ３、中継端子部２０、並びに、接続用ワイヤ９を封止している。なお、樹脂モールド部１１の側部には、リード７の側面の一部が露出している。また、ステージ部５の厚さ方向に面する樹脂モールド部１１の平坦な下面１１ｂには、ステージ部５の下面５ｂ及びリード７の下面７ｂが外方に露出しており、樹脂モールド部１１の下面１１ｂと共に同一平面を形成している。
すなわち、本実施形態の半導体装置１は、所謂ＱＦＮ（Quad Flat Non-leaded package）として構成されている。 As shown in FIG. 2, the resin mold portion 11 seals the upper surface 5 a and side surfaces of the stage portion 5, a part of the upper surface 7 a and side surfaces of the lead 7, the semiconductor chip 3, the relay terminal portion 20, and the connection wires 9. It has stopped. A part of the side surface of the lead 7 is exposed at the side portion of the resin mold portion 11. Further, on the flat lower surface 11 b of the resin mold portion 11 facing the thickness direction of the stage portion 5, the lower surface 5 b of the stage portion 5 and the lower surface 7 b of the lead 7 are exposed to the outside. The same plane is formed with the lower surface 11b.
That is, the semiconductor device 1 of the present embodiment is configured as a so-called QFN (Quad Flat Non-leaded package).

上記構成の半導体装置１を製造する際には、ステージ部５の上面５ａに半導体チップ３及び中継端子部２０を搭載し（搭載工程）、半導体チップ３と各リード７とをそれぞれ接続用ワイヤ９により接続すればよい（配線工程）。また、これら搭載工程及び配線工程の後に、リードフレーム２を不図示の金型内に配置し、この金型内に溶融樹脂を射出する（モールド工程）ことにより、半導体チップ３、ステージ部５、リード７及び接続用ワイヤ９を一体に固定する樹脂モールド部１１を形成すればよい。   When manufacturing the semiconductor device 1 having the above configuration, the semiconductor chip 3 and the relay terminal portion 20 are mounted on the upper surface 5a of the stage portion 5 (mounting process), and the semiconductor chip 3 and each lead 7 are connected to the connecting wires 9 respectively. (The wiring process). In addition, after the mounting process and the wiring process, the lead frame 2 is placed in a mold (not shown), and molten resin is injected into the mold (molding process), whereby the semiconductor chip 3, the stage unit 5, What is necessary is just to form the resin mold part 11 which fixes the lead | read | reed 7 and the wire 9 for a connection integrally.

なお、配線工程では、例えば以下の手順でワイヤボンディングを実施すればよい。はじめに、予めキャピラリ（例えば図５参照）の先端にトーチ等により接続用ワイヤ９を溶融したボールを形成した状態で、該ボールを半導体チップ３の上面３ａに接合してファーストボンドを形成する。次いで、キャピラリから引き出される接続用ワイヤ９が半導体チップ３の上面３ａと中継端子部２０の接合面２１との間で湾曲したループ形状を形成するように、キャピラリを接合面２１に向けて移動させる。   In the wiring process, for example, wire bonding may be performed according to the following procedure. First, in a state where a ball in which the connecting wire 9 is melted by a torch or the like is formed in advance at the tip of a capillary (for example, see FIG. 5), the ball is bonded to the upper surface 3a of the semiconductor chip 3 to form a first bond. Next, the capillary is moved toward the bonding surface 21 so that the connecting wire 9 drawn from the capillary forms a curved loop shape between the upper surface 3 a of the semiconductor chip 3 and the bonding surface 21 of the relay terminal portion 20. .

そして、キャピラリの先端部により接続用ワイヤ９を接合面２１に接合する。なお、この接合の際には、接続用ワイヤ９が切断されないようにする。
その後、中継端子部２０の接合面２１とリード７の上面７ａとの間で湾曲したループ形状を形成するようにキャピラリをリード７に向けて移動させた上で、キャピラリの先端部により接続用ワイヤ９をリード７の上面７ａに接合してセカンドボンドを形成する。最後に、接続用ワイヤ９を切断することで配線工程が完了する。
なお、上述した配線工程においては、半導体チップ３、中継端子部２０、リード７の順番で接続用ワイヤ９を接合しているが、例えば逆の順番で接合しても構わない。また、配線工程においてファーストボンド及びセカンドボンドを形成した後に、接続用ワイヤ９の中途部を接合面２１に接合してもよい。 Then, the connecting wire 9 is joined to the joining surface 21 by the tip of the capillary. It is to be noted that the connecting wire 9 is not cut during this joining.
Thereafter, the capillary is moved toward the lead 7 so as to form a curved loop shape between the joint surface 21 of the relay terminal portion 20 and the upper surface 7a of the lead 7, and then the connecting wire is connected by the tip of the capillary. 9 is bonded to the upper surface 7a of the lead 7 to form a second bond. Finally, the wiring process is completed by cutting the connecting wire 9.
In the wiring process described above, the connection wires 9 are joined in the order of the semiconductor chip 3, the relay terminal portion 20, and the leads 7, but may be joined in the reverse order, for example. Further, after forming the first bond and the second bond in the wiring process, the midway portion of the connection wire 9 may be bonded to the bonding surface 21.

ところで、上述した配線工程において、接続用ワイヤ９を切断することなく、接続用ワイヤ９の中途部が中継端子部２０にめり込むように、接続用ワイヤ９を接合面２１に接合するためには、例えば図５に示すキャピラリ９０を用いることが好ましい。
このキャピラリ９０は、円錐筒状に形成され、先端部９１に設けられたボンディングワイヤ９９（以下、ワイヤ９９と呼ぶ。）の導出口９３と、導出口９３の周囲に設けられた押付面９４とを有している。ワイヤ９９は、このキャピラリ９０の導出口９３から自在に繰り出せるようになっている。一方、押付面９４は、前述したファーストボンドやセカンドボンドを形成する際に、熱圧着や超音波圧着を実施するための加熱面やホーンの役割を果たす。 By the way, in order to join the connecting wire 9 to the joining surface 21 so that the midway part of the connecting wire 9 is recessed into the relay terminal part 20 without cutting the connecting wire 9 in the wiring process described above. For example, it is preferable to use a capillary 90 shown in FIG.
The capillary 90 is formed in a conical cylinder shape and has a lead-out port 93 for a bonding wire 99 (hereinafter referred to as a wire 99) provided at the tip 91, and a pressing surface 94 provided around the lead-out port 93. have. The wire 99 can be freely drawn out from the outlet port 93 of the capillary 90. On the other hand, the pressing surface 94 serves as a heating surface or a horn for performing thermocompression bonding or ultrasonic pressure bonding when forming the first bond or the second bond described above.

そして、キャピラリ９０の先端部９１は、その中心軸Ｏを含む面で前端側半体部９５と後端側半体部９６とに分割されている。後端側半体部９６は、キャピラリ９０の基端部９２と一体に形成されている。
前端側半体部９５は、キャピラリ９０の基端部９２に対して中心軸Ｏに沿う方向（図５において上下方向）に移動可能に取り付けられている。具体的に説明すれば、前端側半体部９５は、後端側半体部９６に対する前端側半体部９５の下方向への突出長さＬが、ワイヤ９９の径寸法Ｄに対して同等以上となる位置（第一位置９５Ａ）と、ワイヤ９９の径寸法Ｄよりも小さくなる位置（第二位置９５Ｂ）との間で移動可能となっている。 The front end portion 91 of the capillary 90 is divided into a front end side half body portion 95 and a rear end side half body portion 96 on a plane including the central axis O. The rear end side half 96 is formed integrally with the base end 92 of the capillary 90.
The front end side half body portion 95 is attached to the base end portion 92 of the capillary 90 so as to be movable in a direction along the central axis O (vertical direction in FIG. 5). More specifically, in the front end side half body portion 95, the downward protrusion length L of the front end side half body portion 95 with respect to the rear end side half body portion 96 is equal to the diameter D of the wire 99. It can move between the above position (first position 95A) and a position (second position 95B) smaller than the diameter dimension D of the wire 99.

また、前端側半体部９５は、弾性体（不図示）によって第一位置９５Ａから第二位置９５Ｂに向かう方向（図５において下方向）に付勢されている。なお、弾性体の具体例としては、例えば、ゴムやバネなどが挙げられるが、前端側半体部９５が第一位置９５Ａから第二位置９５Ｂに近づくほど、弾性体の付勢力が増すものであればよい。
さらに、このキャピラリ９０は、ワイヤボンディングの際に前端側半体部９５がキャピラリ９０の進行方向前方側に位置するように、中心軸Ｏを中心に回転可能となっている。 Further, the front end side half body portion 95 is biased in a direction (downward in FIG. 5) from the first position 95A to the second position 95B by an elastic body (not shown). Specific examples of the elastic body include rubber and spring. For example, the urging force of the elastic body increases as the front end side half portion 95 approaches the second position 95B from the first position 95A. I just need it.
Further, the capillary 90 is rotatable about the central axis O so that the front end side half body portion 95 is located on the front side in the traveling direction of the capillary 90 during wire bonding.

上記構成のキャピラリ９０を用いて、図６（ａ）に示すように、ワイヤ９９を接続用ワイヤ９として中継端子部２０に接合する場合には、前端側半体部９５における押付面９４を接合面２１に押し付けながら矢印ｉ方向（接合面２１に沿う方向）に進行させればよい。
ここで、中継端子部２０の接合面２１部分は、キャピラリ９０の先端部９１よりも塑性変形しやすく、かつ、リード７よりも展性が高い材料からなるため、前端側半体部９５を接合面２１に押し付けると、前端側半体部９５は、図示例のように弾性体の弾性力に抗って第一位置９５Ａから少しだけ上方向に移動し、あるいは、第一位置９５Ａから移動することなく、前端側半体部９５の先端部分が中継端子部２０にめり込むことになる。なお、弾性体の弾性係数が適切に調整されているため、前端側半体部９５がめり込んだ状態でも、ワイヤ９９は後端側半体部９６によって中継端子部２０に押し付けられない。
そして、前端側半体部９５を中継端子部２０にめり込ませた状態でキャピラリ９０を矢印ｉ方向に進行させることで、前端側半体部９５の先端部分が接合面２１部分を切り裂いて凹部２３を形成しながら、ワイヤ９９を中継端子部２０にめり込ませることができる。ただし、後端側半体部９６は、凹部２３に入り込むワイヤ９９を押し付けないため、この接合に際してワイヤ９９が切断されることはない。 6A, when the wire 99 is joined to the relay terminal portion 20 as the connection wire 9, the pressing surface 94 of the front end side half portion 95 is joined. What is necessary is just to advance to the arrow i direction (direction along the joining surface 21), pressing against the surface 21. FIG.
Here, the joining surface 21 portion of the relay terminal portion 20 is made of a material that is more easily plastically deformed than the distal end portion 91 of the capillary 90 and is more malleable than the lead 7, so the front end side half portion 95 is joined. When pressed against the surface 21, the front end side half 95 moves slightly upward from the first position 95A against the elastic force of the elastic body as shown in the example, or moves from the first position 95A. Instead, the front end portion of the front end side half portion 95 is recessed into the relay terminal portion 20. Since the elastic coefficient of the elastic body is appropriately adjusted, the wire 99 is not pressed against the relay terminal portion 20 by the rear end side half portion 96 even when the front end side half portion 95 is indented.
Then, by causing the capillary 90 to advance in the direction of arrow i with the front end side half portion 95 fitted into the relay terminal portion 20, the tip portion of the front end side half portion 95 cuts the joining surface 21 portion. The wire 99 can be sunk into the relay terminal portion 20 while forming the recess 23. However, since the rear end side half part 96 does not press the wire 99 entering the recess 23, the wire 99 is not cut at the time of this joining.

また、例えば図６（ｂ）に示すように、ワイヤ９９をリード７に接合してセカンドボンドを形成する場合には、前端側半体部９５における押付面９４をリード７の上面７ａに押し付けるように矢印ｊ方向（斜め下方向）に進行させればよい。
ただし、リード７は、キャピラリ９０の先端部９１よりも塑性変形しやすいものの、中継端子部２０よりも展性が低い材料からなるため、押付面９４をリード７の上面７ａに押し付けると、前端側半体部９５が第二位置９５Ｂまで移動し、ワイヤ９９が後端側半体部９６によってリード７の上面７ａに押し付けられることになる。なお、この押し付け状態では、前端側半体部９５の先端部分が少しだけリード７にめり込む。
そして、この押し付け状態において、ワイヤ９９を加熱する、あるいは、ワイヤ９９に超音波を付与することで、ワイヤ９９をリード７に対して熱圧着あるいは超音波圧着で接合することができる。また、この接合後に、キャピラリ９０を固定したままワイヤ９９を矢印ｋ方向（上方向）に引っ張ることで、ワイヤ９９を切断することができる。
なお、半導体チップ３の上面３ａにファーストボンドを形成する際も、上述したセカンドボンドの場合と同様の熱圧着あるいは超音波圧着により、ワイヤ９９を半導体チップ３の上面３ａに接合することが可能である。 For example, as shown in FIG. 6B, when the wire 99 is joined to the lead 7 to form a second bond, the pressing surface 94 in the front end side half 95 is pressed against the upper surface 7 a of the lead 7. And proceed in the direction of arrow j (obliquely downward).
However, the lead 7 is more easily plastically deformed than the distal end portion 91 of the capillary 90, but is made of a material that is less malleable than the relay terminal portion 20. Therefore, when the pressing surface 94 is pressed against the upper surface 7a of the lead 7, The half part 95 moves to the second position 95B, and the wire 99 is pressed against the upper surface 7a of the lead 7 by the rear end side half part 96. In this pressed state, the front end portion of the front end side half body portion 95 is slightly recessed into the lead 7.
In this pressed state, the wire 99 can be bonded to the lead 7 by thermocompression bonding or ultrasonic pressure bonding by heating the wire 99 or applying ultrasonic waves to the wire 99. Further, after this joining, the wire 99 can be cut by pulling the wire 99 in the arrow k direction (upward) while the capillary 90 is fixed.
Even when the first bond is formed on the upper surface 3a of the semiconductor chip 3, the wire 99 can be bonded to the upper surface 3a of the semiconductor chip 3 by the same thermocompression bonding or ultrasonic pressure bonding as in the case of the second bond described above. is there.

以上説明したように、本実施形態の半導体装置においては、図２に示すように、相互に隣り合う接合面２１の高さ位置が異なっていることで、半導体チップ３から中継端子部２０に至る各接続用ワイヤ９のループ高さを最小限に抑えたとしても、隣り合う接続用ワイヤ９のループ高さが互いに異なるので、リード７の配列方向に隣り合う接続用ワイヤ９が互いに干渉することを防止できる。   As described above, in the semiconductor device according to the present embodiment, as shown in FIG. 2, the height positions of the adjacent joint surfaces 21 are different from each other, leading to the relay terminal portion 20 from the semiconductor chip 3. Even if the loop height of each connection wire 9 is minimized, the adjacent connection wires 9 in the arrangement direction of the leads 7 interfere with each other because the loop heights of the adjacent connection wires 9 are different from each other. Can be prevented.

また、半導体チップ３から中継端子部２０に至る全ての接続用ワイヤ９の長さを最小限にすることで、半導体チップ３と中継端子部２０との間に張設された接続用ワイヤ９の張力が保たれるので、張設された接続用ワイヤ９が外力によって揺れ動くことを抑制できる。さらに、相互に隣り合う接合面２１の高さ位置が互いに異なるので、たとえ張設された接続用ワイヤ９が外力によって揺れ動いたとしても、リード７の配列方向に隣り合う接続用ワイヤ９が互いに干渉することを防止できる。
例えば、モールド工程における溶融樹脂の流れによる接続用ワイヤ９の揺れを抑制でき、モールド工程後において接続用ワイヤ９が互いに干渉することを防止できる。
以上のことから、半導体チップ３の各辺からリード７までの距離が、ステージ部５の各辺からリード７までの距離と比較して長くても、リード７の配列方向に隣り合う接続用ワイヤ９が互いに干渉することを防止できる。 Further, by minimizing the length of all the connection wires 9 from the semiconductor chip 3 to the relay terminal portion 20, the connection wires 9 that are stretched between the semiconductor chip 3 and the relay terminal portion 20. Since the tension is maintained, it is possible to suppress the tensioned connecting wire 9 from being shaken by an external force. Furthermore, since the height positions of the bonding surfaces 21 adjacent to each other are different from each other, even if the stretched connection wires 9 are shaken by an external force, the connection wires 9 adjacent in the arrangement direction of the leads 7 interfere with each other. Can be prevented.
For example, the shaking of the connecting wire 9 due to the flow of molten resin in the molding process can be suppressed, and the connecting wires 9 can be prevented from interfering with each other after the molding process.
From the above, even if the distance from each side of the semiconductor chip 3 to the lead 7 is longer than the distance from each side of the stage portion 5 to the lead 7, the connection wires adjacent to each other in the arrangement direction of the leads 7. 9 can be prevented from interfering with each other.

なお、上記実施形態の半導体装置１においては、中継端子部２０全体が電気的な絶縁材料によって形成されるとしたが、少なくともステージ部５の上面５ａに対する中継端子部２０の接触部分と各接合面２１との間で電気的に絶縁されるように構成されればよい。
したがって、例えば図７，８に示すように、中継端子部３０は、ステージ部５の上面５ａに絶縁材料からなる基台３１を設けると共に、基台３１の上面に導電性材料からなる導電パッド３３を積層して構成されてもよい。この構成の半導体装置４では、導電パッド３３の上面が中継端子部３０の接合面３４をなす。
なお、上記実施形態と同様に半導体チップ３とリード７との間を一本の接続用ワイヤ９により接続する場合には、導電パッド３３をリード７よりも展性が高い導電性材料、例えば金、錫、アルミニウム等により形成することが好ましい。この場合、基台３１をなす絶縁材料は、展性が高くても低くても構わない。 In the semiconductor device 1 of the above embodiment, the entire relay terminal portion 20 is formed of an electrically insulating material. However, at least the contact portion of the relay terminal portion 20 with respect to the upper surface 5a of the stage portion 5 and each joint surface What is necessary is just to be comprised so that it may be electrically insulated between 21.
Therefore, for example, as shown in FIGS. 7 and 8, the relay terminal portion 30 includes a base 31 made of an insulating material on the upper surface 5 a of the stage portion 5, and a conductive pad 33 made of a conductive material on the upper surface of the base 31. May be configured. In the semiconductor device 4 having this configuration, the upper surface of the conductive pad 33 forms the bonding surface 34 of the relay terminal portion 30.
When the semiconductor chip 3 and the lead 7 are connected by a single connecting wire 9 as in the above embodiment, the conductive pad 33 is made of a conductive material having higher malleability than the lead 7, for example, gold. , Tin, aluminum and the like are preferable. In this case, the insulating material forming the base 31 may be high or low in malleability.

また、中継端子部３０では、基台３１が上記実施形態の中継端子部２０と同様の階段状（図３参照）に形成され、様々な高さ位置に設定された基台３１の各上面に、同一厚さの導電パッド３３がそれぞれ積層されている。そして、複数の導電パッド３３からなる複数の接合面３４は、上記実施形態と同様に、その配列方向の中央に位置する接合面３４Ａから両端に位置する接合面３４Ｄ，３４Ｅに向かうにしたがって、接合面３４の高さ位置が高くなるように、階段状に配列されている。なお、図示例においては、中央の接合面３４Ａの両隣に位置する２つの接合面３４Ｂ，３４Ｃの高さ位置が互いに等しく、また、両端に位置する２つの接合面３４Ｄ，３４Ｅの高さ位置が互いに等しくなるように設定されている。   Moreover, in the relay terminal part 30, the base 31 is formed in the step shape (refer FIG. 3) similar to the relay terminal part 20 of the said embodiment, and on each upper surface of the base 31 set to various height positions. The conductive pads 33 having the same thickness are stacked. The plurality of bonding surfaces 34 composed of the plurality of conductive pads 33 are bonded to the bonding surfaces 34D and 34E positioned at both ends from the bonding surface 34A positioned at the center in the arrangement direction, as in the above embodiment. The surfaces 34 are arranged stepwise so that the height position of the surface 34 is increased. In the illustrated example, the height positions of the two joint surfaces 34B and 34C located on both sides of the central joint surface 34A are equal to each other, and the height positions of the two joint surfaces 34D and 34E located at both ends are the same. They are set to be equal to each other.

さらに、中継端子部３０の接合面３４部分を導電パッド３３により構成する場合には、半導体チップ３とリード７との間が、上記実施形態のように一本の接続用ワイヤ９で接続されなくてもよく、例えば図７，８に示すように、半導体チップ３と中継端子部３０とを接続する第一ワイヤ部９Ａ、及び、中継端子部３０とリード７とを接続する第二ワイヤ部９Ｂによって接続されてもよい。言い換えれば、半導体チップ３とリード７とを接続する接続用ワイヤ９は、その中途部において第一ワイヤ部９Ａと第二ワイヤ部９Ｂとに分割して構成されてもよい。
なお、第一ワイヤ部９Ａや第二ワイヤ部９Ｂを配する際に、上記実施形態の配線工程のように、接合面３４においてセカンドボンドを形成する場合には、該当する導電パッド３３をリード７のように展性が低い導電性材料により形成することが好ましい。 Furthermore, when the joining surface 34 portion of the relay terminal portion 30 is configured by the conductive pad 33, the semiconductor chip 3 and the lead 7 are not connected by the single connection wire 9 as in the above embodiment. For example, as shown in FIGS. 7 and 8, the first wire portion 9 </ b> A that connects the semiconductor chip 3 and the relay terminal portion 30, and the second wire portion 9 </ b> B that connects the relay terminal portion 30 and the lead 7. May be connected by. In other words, the connecting wire 9 that connects the semiconductor chip 3 and the lead 7 may be divided into a first wire portion 9A and a second wire portion 9B in the middle portion.
When the first wire portion 9A and the second wire portion 9B are arranged, when a second bond is formed on the bonding surface 34 as in the wiring process of the above embodiment, the corresponding conductive pad 33 is connected to the lead 7. It is preferable to form the conductive material with low malleability.

なお、図７，８に示す構成においては、半導体チップ３から引き出される一部（図示例では２本）の接続用ワイヤ９が、電気的に同一の役割（例えばグランド配線、電源配線、同一の電気信号の入出力配線としての役割）を果たしている。この場合には、同一の役割を果たす複数（図示例では２つ）の導電パッド３３Ｃ，３３Ｄをリード７側において互いに連結しておけばよい。そして、複数の導電パッド３３Ｃ，３３Ｄにそれぞれ第一ワイヤ部９Ａを接合し、複数の導電パッド３３Ｃ，３３Ｄの連結部分３５に一つの第二ワイヤ部９Ｂを接合すればよい。すなわち、この構成では、複数の第一ワイヤ部９Ａ及び一つの第二ワイヤ部９Ｂによって半導体チップ３とリード７とを接続する接続用ワイヤ９が構成されている。   7 and 8, some (two in the illustrated example) connection wires 9 drawn out from the semiconductor chip 3 have the same electrical role (for example, ground wiring, power supply wiring, same wiring, etc.). It plays the role of electrical signal input / output wiring). In this case, a plurality (two in the illustrated example) of conductive pads 33C and 33D that play the same role may be connected to each other on the lead 7 side. Then, the first wire portion 9A may be joined to the plurality of conductive pads 33C and 33D, respectively, and one second wire portion 9B may be joined to the connecting portion 35 of the plurality of conductive pads 33C and 33D. That is, in this configuration, the connection wires 9 that connect the semiconductor chip 3 and the leads 7 are configured by the plurality of first wire portions 9A and one second wire portion 9B.

また、中継端子部２０，３０の各接合面２１，３４には、半導体チップ３とリード７とを電気接続する接続用ワイヤ９の中途部のみが接合されるとしたが、これに限ることは無く、例えば図９に示すように、一部の接合面３４Ａ，３４Ｄ，３４Ｅに接地用のボンディングワイヤ３９（以下、接地用ワイヤ３９と呼ぶ。）が接合されていてもよい。
そして、この構成の半導体装置６において、接地用ワイヤ３９の一端は半導体チップ３の周囲近傍に形成された接地用パッド３７に接合され、他端は中継端子部３０の接合面３４に接合されている。この場合、ステージ部５は接地を目的としたものとされ、接地用パッド３７はこのステージ部５に電気接続されている。なお、図示例においては、接地用パッド３７が半導体チップ３の周囲を囲む矩形環状に形成されているが、例えば半導体チップ３の周囲に複数配列されていても構わない。 Further, only the midway part of the connection wire 9 for electrically connecting the semiconductor chip 3 and the lead 7 is joined to the joint surfaces 21 and 34 of the relay terminal parts 20 and 30. However, the present invention is not limited to this. For example, as shown in FIG. 9, a bonding wire 39 for grounding (hereinafter referred to as a grounding wire 39) may be bonded to some of the bonding surfaces 34A, 34D, and 34E.
In the semiconductor device 6 having this configuration, one end of the grounding wire 39 is joined to the grounding pad 37 formed near the periphery of the semiconductor chip 3, and the other end is joined to the joining surface 34 of the relay terminal portion 30. Yes. In this case, the stage unit 5 is intended for grounding, and the grounding pad 37 is electrically connected to the stage unit 5. In the illustrated example, the grounding pads 37 are formed in a rectangular ring shape surrounding the semiconductor chip 3, but a plurality of ground pads 37 may be arranged around the semiconductor chip 3, for example.

また、図９における中継端子部３０の複数の接合面３４は、図７に記載の構成と同様の階段状に配列されている。そして、接続用ワイヤ９が接合された一の接合面３４Ｂ，３４Ｃの両隣に位置する他の接合面３４Ａ，３４Ｄ，３４Ｅに、接地用ワイヤ３９が接合されている。なお、図示例の中継端子部３０は、図７，８に記載のものと同様に、基台３１上に複数の導電パッド３３を積層して構成されているが、例えば上記実施形態の中継端子部２０と同様に、上記導電パッド３３を設けなくても構わない。   Further, the plurality of joining surfaces 34 of the relay terminal portion 30 in FIG. 9 are arranged in a stepped manner similar to the configuration shown in FIG. The grounding wire 39 is joined to the other joining surfaces 34A, 34D, 34E located on both sides of the one joining surface 34B, 34C to which the connection wire 9 is joined. The relay terminal portion 30 in the illustrated example is configured by laminating a plurality of conductive pads 33 on the base 31 in the same manner as shown in FIGS. 7 and 8. For example, the relay terminal portion 30 in the above embodiment is used. Similar to the portion 20, the conductive pad 33 may not be provided.

これにより、上記接地用ワイヤ３９及び接続用ワイヤ９は、それぞれ半導体チップ３側から中継端子部３０側に向けて延びるように配され、さらに、接地用ワイヤ３９の間に接続用ワイヤ９が配されるように、複数の接合面３４の配列方向に沿って交互に配列されている。
以上のように構成された上記半導体装置６では、上記実施形態の場合と同様に、接続用ワイヤ９や接地用ワイヤ３９が外力によって揺れ動くことを抑制できる。また、たとえ接続用ワイヤ９や接地用ワイヤ３９が揺れ動いたとしても、隣り合う接続用ワイヤ９及び接地用ワイヤ３９のループ高さが異なるため、隣り合う接続用ワイヤ９及び接地用ワイヤ３９が互いに干渉することを防止できる。
さらに、接続用ワイヤ９が半導体チップ３から出力される電気信号を通す信号用ワイヤであっても、外部からの電磁気的なノイズを接地用ワイヤ３９において除去することができ、接続用ワイヤ９のＳ／Ｎ比の向上を図ることができる。 Thereby, the grounding wire 39 and the connecting wire 9 are arranged so as to extend from the semiconductor chip 3 side toward the relay terminal portion 30 side, respectively, and the connecting wire 9 is arranged between the grounding wires 39. As shown, the plurality of bonding surfaces 34 are alternately arranged along the arrangement direction.
In the semiconductor device 6 configured as described above, the connection wire 9 and the grounding wire 39 can be prevented from being shaken by an external force, as in the case of the above embodiment. Even if the connecting wire 9 and the grounding wire 39 are shaken, the adjacent connecting wire 9 and the grounding wire 39 have different loop heights. Interference can be prevented.
Furthermore, even if the connection wire 9 is a signal wire that passes an electrical signal output from the semiconductor chip 3, electromagnetic noise from the outside can be removed by the ground wire 39, and the connection wire 9 The S / N ratio can be improved.

また、中継端子部２０，３０は、いずれも複数の接合面２１，３４を有するように基台３１等によって一体に形成されているが、例えば図１０に示すように、中継端子部４０は、ステージ部５の上面５ａから突出する中継端子４１を複数配列して構成されてもよい。この構成では、各中継端子４１の突出方向の先端面が１つの接合面４２をなしている。
また、この構成では、複数の中継端子４１が絶縁材料であればステージ部５の上面５ａにそれぞれ直接固定されてもよいが、図示例のように、接着性を有する帯状のテープ４３に複数の中継端子４１を固定した中継端子部４０を構成してもよい。さらに、テープ４３が絶縁性を有していれば、複数の中継端子４１は導電性材料によって形成されていてもよい。 Moreover, although the relay terminal parts 20 and 30 are integrally formed by the base 31 etc. so that all may have the some joint surfaces 21 and 34, as shown, for example in FIG. A plurality of relay terminals 41 protruding from the upper surface 5a of the stage unit 5 may be arranged. In this configuration, the leading end surface of each relay terminal 41 in the protruding direction forms one joining surface 42.
Further, in this configuration, if the plurality of relay terminals 41 are insulating materials, they may be directly fixed to the upper surface 5a of the stage portion 5, respectively. However, as shown in FIG. You may comprise the relay terminal part 40 to which the relay terminal 41 was fixed. Furthermore, as long as the tape 43 has insulating properties, the plurality of relay terminals 41 may be formed of a conductive material.

さらに、同一の中継端子部２０，３０，４０に形成された複数の接合面２１，３４，４２は、その高さ位置が中央の接合面から両端の接合面に向けて順次高くなるように階段状に配列されることに限らず、複数の接合面２１，３４，４２のうち、少なくとも互いに隣り合う二つの接合面の高さ位置が互いに異なっていればよい。
したがって、複数の接合面２１，３４，４２は、例えば、配列方向の中央に位置する接合面から両端に位置する接合面に向かうにしたがって、接合面の高さ位置が低くなるように階段状に配列されてもよい。また、半導体装置１，４，６の厚さ寸法を考慮しなければ、複数の接合面２１，３４，４２は、配列方向の一端に位置する接合面から他端の接合面に向かうにしたがって、接合面２１，３４，４２の高さ位置が順次高くなるように、あるいは、低くなるように階段状に配列されてもよい。さらに、複数の接合面２１，３４，４２は、例えば、その高さ位置が配列方向に沿って高低を繰り返すように配列されてもよい。 Further, the plurality of joint surfaces 21, 34, and 42 formed on the same relay terminal portion 20, 30, and 40 are stepped so that the height position sequentially increases from the central joint surface toward the joint surfaces at both ends. The height positions of at least two joining surfaces adjacent to each other among the plurality of joining surfaces 21, 34, 42 may be different from each other.
Therefore, for example, the plurality of bonding surfaces 21, 34, 42 are stepped so that the height positions of the bonding surfaces become lower from the bonding surface located at the center in the arrangement direction toward the bonding surfaces located at both ends. It may be arranged. If the thickness dimensions of the semiconductor devices 1, 4, 6 are not taken into consideration, the plurality of bonding surfaces 21, 34, 42 move from the bonding surface located at one end in the arrangement direction toward the bonding surface at the other end. The joint surfaces 21, 34, and 42 may be arranged stepwise so that the height positions thereof are sequentially increased or decreased. Further, the plurality of bonding surfaces 21, 34, 42 may be arranged such that the height position repeats heights along the arrangement direction, for example.

また、複数の接合面２１，３４，４２のうち一部については、例えば、隣り合う接合面の高さ位置が互いに等しくてもよい。
なお、互いに隣り合って高さ位置の等しい二つの接合面には、同一の役割を果たし、互いに接触してもよい接続用ワイヤ９（例えばグランド配線やテスト用配線）を接合することが可能である。言い換えれば、互いに隣り合って高さ位置が異なる二つの接合面には、少なくとも互いに異なる役割を果たす接続用ワイヤ９（例えば互いに異なる電気信号用の入出力配線）、すなわち、互いに接触することが好ましくない接続用ワイヤ９が接続されていればよい。
また、上記実施形態では、半導体チップ３とリード７とを電気接続する全ての接続用ワイヤ９が、中継端子部２０にも接合されているが、例えば、一部の接続用ワイヤ９だけが中継端子部２０に接合され、残りの接続用ワイヤ９は中継端子部２０に接合されなくてもよい。 For some of the plurality of bonding surfaces 21, 34, 42, for example, the height positions of adjacent bonding surfaces may be equal to each other.
In addition, it is possible to join connection wires 9 (for example, ground wiring or test wiring) that play the same role and may be in contact with each other on two joint surfaces that are adjacent to each other and have the same height position. is there. In other words, it is preferable that two connecting surfaces adjacent to each other and having different height positions be in contact with each other, ie, connection wires 9 that play different roles (for example, different input / output wirings for electrical signals), that is, mutually contact. It is only necessary that the connecting wire 9 not to be connected is connected.
Further, in the above embodiment, all the connection wires 9 that electrically connect the semiconductor chip 3 and the leads 7 are also joined to the relay terminal portion 20, but for example, only some of the connection wires 9 are relayed. The remaining connecting wires 9 are joined to the terminal portion 20 and may not be joined to the relay terminal portion 20.

なお、本発明の半導体装置は、上記実施形態のものに限らず、例えば各リード７の一部が樹脂モールド部１１の側部から突出するＱＦＰ（Quad Flat Package）にも適用することが可能である。
また、本発明の半導体装置は、リードフレーム２によって構成されるものに限らず、少なくとも半導体チップ３を搭載する搭載領域面の周囲に、接続用ワイヤ９によって半導体チップ３に電気接続される複数の接続端子部を配列したベース部を備える構成に適用することができる。すなわち、本発明は、例えば図１１に示すように、インターポーザ基板等のように内部配線５２Ｃを有する配線基板（ベース部）５１の搭載領域面５１ａに半導体チップ３を搭載し、搭載領域面５１ａの周囲に複数配列された接続端子部５２の内部端子面５２Ａと半導体チップ３とを接続用ワイヤ９により電気接続した半導体装置８にも適用できる。ここで、搭載領域面５１ａは、内部端子面５２Ａが露出する配線基板５１の上面のうち内部端子面５２Ａが形成される領域よりも内側の所定領域を示す面である。
なお、図示例の半導体装置８は、配線基板５１の下面５１ｂに露出する接続端子部５２の外部端子５２Ｂが平面電極パッドであるＬＧＡ（Land Grid Array）を構成しているが、例えば平面電極パッドの代わりにボール状電極を設けたＢＧＡ（Ball Grid Array）を構成してもよい。 The semiconductor device of the present invention is not limited to the above embodiment, and can be applied to, for example, a QFP (Quad Flat Package) in which a part of each lead 7 protrudes from the side portion of the resin mold portion 11. is there.
In addition, the semiconductor device of the present invention is not limited to the one constituted by the lead frame 2, and at least around the mounting area surface on which the semiconductor chip 3 is mounted, a plurality of wires electrically connected to the semiconductor chip 3 by the connection wires 9. The present invention can be applied to a configuration including a base portion in which connection terminal portions are arranged. That is, according to the present invention, for example, as shown in FIG. 11, the semiconductor chip 3 is mounted on a mounting region surface 51a of a wiring substrate (base portion) 51 having an internal wiring 52C such as an interposer substrate, and the mounting region surface 51a The present invention can also be applied to the semiconductor device 8 in which a plurality of internal terminal surfaces 52A of the connection terminal portions 52 arranged around and the semiconductor chip 3 are electrically connected by the connection wires 9. Here, the mounting area surface 51a is a surface showing a predetermined area inside the area where the internal terminal surface 52A is formed, of the upper surface of the wiring board 51 where the internal terminal surface 52A is exposed.
In the semiconductor device 8 in the illustrated example, an external terminal 52B of the connection terminal portion 52 exposed on the lower surface 51b of the wiring substrate 51 forms an LGA (Land Grid Array) which is a planar electrode pad. Instead of this, a BGA (Ball Grid Array) provided with ball-shaped electrodes may be configured.

以上、本発明の実施形態について図面を参照して詳述したが、具体的な構成はこの実施形態に限られるものではなく、本発明の要旨を逸脱しない範囲の設計変更等も含まれる。   As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

１，４，６，８…半導体装置、２…リードフレーム（ベース部）、３…半導体チップ、５ａ…上面（搭載領域面）、７…リード（接続端子部）、９…接続用ワイヤ（ボンディングワイヤ）、９Ａ…第一ワイヤ部、９Ｂ…第二ワイヤ部、２０…中継端子部、２１…接合面、３０…中継端子部、３１…基台、３３…導電パッド、３４…接合面、４０…中継端子部、４１…中継端子、４２…接合面、５１…配線基板（ベース部）、５１ａ…搭載領域面、５２…接続端子部 DESCRIPTION OF SYMBOLS 1, 4, 6, 8 ... Semiconductor device, 2 ... Lead frame (base part), 3 ... Semiconductor chip, 5a ... Upper surface (mounting area surface), 7 ... Lead (connection terminal part), 9 ... Connection wire (bonding) Wire), 9A ... first wire portion, 9B ... second wire portion, 20 ... relay terminal portion, 21 ... joint surface, 30 ... relay terminal portion, 31 ... base, 33 ... conductive pad, 34 ... joint surface, 40 DESCRIPTION OF SYMBOLS ... Relay terminal part, 41 ... Relay terminal, 42 ... Joint surface, 51 ... Wiring board (base part), 51a ... Mounting area surface, 52 ... Connection terminal part

Claims (3)

半導体チップと、該半導体チップを搭載する搭載領域面、及び、該搭載領域面の周囲に配列された複数の接続端子部を有するベース部とを備え、
前記搭載領域面のうち前記半導体チップと複数の前記接続端子部との間には、前記複数の接続端子部の配列方向に配列された複数の接合面を有する中継端子部が設けられ、
両端が前記半導体チップと前記接続端子部とに接合されると共に、中途部が前記接合面に接合されることで、前記半導体チップと前記接続端子部とを電気接続するボンディングワイヤを有し、
複数の前記接合面のうち、少なくとも前記配列方向に沿って互いに隣り合う二つの接合面の高さ位置が、互いに異なることを特徴とする半導体装置。 A semiconductor chip, a mounting area surface for mounting the semiconductor chip, and a base portion having a plurality of connection terminal portions arranged around the mounting area surface;
Between the semiconductor chip and the plurality of connection terminal portions in the mounting area surface, a relay terminal portion having a plurality of joint surfaces arranged in an arrangement direction of the plurality of connection terminal portions is provided,
Both ends are bonded to the semiconductor chip and the connection terminal portion, and a midway portion is bonded to the bonding surface, thereby having a bonding wire for electrically connecting the semiconductor chip and the connection terminal portion,
Among the plurality of bonding surfaces, at least two bonding surfaces adjacent to each other along the arrangement direction have different height positions. 複数の前記接続端子部の一部が直線状に配列されると共に、複数の前記接合面の一部が直線配列された前記接続端子部の配列方向に沿って配列され、
直線状に配列された複数の前記接合面は、前記直線状の配列方向の中央に位置する前記接合面から前記配列方向の両端に位置する前記接合面に向かうにしたがって、前記接合面の高さ位置が高くなる、あるいは、低くなるように、階段状に配列されていることを特徴とする請求項１に記載の半導体装置。 Some of the plurality of connection terminal portions are arranged in a straight line, and some of the plurality of joint surfaces are arranged along the arrangement direction of the connection terminal portions arranged in a straight line,
A plurality of the joint surfaces arranged in a straight line form a height of the joint surface from the joint surface located in the center of the linear array direction toward the joint surfaces located at both ends in the array direction. 2. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged in a stepped manner so that the position becomes higher or lower. 前記ボンディングワイヤの中途部が、前記中継端子部にめり込むように前記接合面に接合されていることを特徴とする請求項１又は請求項２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a midway part of the bonding wire is joined to the joining surface so as to be embedded in the relay terminal part. 4.
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