JP5966357B2 - Imaging device and imaging apparatus - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

  When high-intensity light is incident on a CMOS (complementary metal oxide semiconductor) type solid-state imaging device, the charge may overflow into the floating diffusion even if the charge transfer transistor of the light receiving device is off. In the above case, since the level of the dark signal of the pixel becomes very high, the pixel value after subtracting the dark signal from the bright signal of the pixel becomes small (for example, a high-luminance subject such as the sun becomes black on the image) Expressed).

  As a countermeasure for the above, for example, a solid-state imaging device in which clip circuits are provided on the input side and output side of a column amplifier has been proposed.

International Publication WO2009 / 047883

  By the way, when the column amplifier or the clip circuit is driven at a low voltage for speeding up the signal processing, the level difference between the bright signal and the dark signal becomes very small. When the clipping circuit on the output side of the column amplifier in the conventional technique is driven at a low voltage, a sufficient difference between the bright signal and the dark signal in consideration of the dead zone of the clipping circuit cannot be secured, and as a result, on the image There is a possibility that a phenomenon in which a high-luminance subject is blackened cannot be sufficiently suppressed.

One aspect der Ru IMAGING element of the present invention are arranged in a matrix, and a pixel to convert incident light into electrical signals, and a plurality of vertical signal lines, and the column amplifiers, and a clip portion, the column A / D converter And a detector. The vertical signal line is connected to a plurality of pixels in the column direction, and reads out a dark signal including a noise component and a bright signal including a light receiving component from the pixel. The column amplifier amplifies the signal read to the vertical signal line. The clip unit is connected to the vertical signal line on the input side of the column amplifier, and clips a signal outside a predetermined voltage. The column A / D converter is disposed on the output side of the column amplifier, and performs A / D conversion on the signal and outputs it. The detection unit outputs a notification signal to the column A / D conversion unit when the level of the dark signal output from the column amplifier is larger than the threshold value. Then, the column A / D conversion unit outputs a code corresponding to the white level as pixel value information when the notification signal is received. The power supply voltages of the column amplifier and the column A / D conversion unit are lower than the power supply voltages of the pixels and the clip unit.
An image sensor according to another aspect of the present invention compares a signal line that outputs a signal read from a pixel portion with a signal and a reference signal, and outputs a notification signal when the signal is larger than the reference signal. A signal conversion unit connected to the signal line and the detection unit, the signal conversion unit outputting a signal as a constant digital signal when a notification signal is input, and a power source for the signal conversion unit The voltage is lower than the power supply voltage of the pixel portion.

According to an imaging device of one embodiment or another embodiment of the present invention, even at a low voltage driving, high luminance object on the image can be prevented the phenomenon of blackening.

The block diagram which shows the structural example of the solid-state image sensor in one Embodiment The figure which shows the circuit structural example of pixel PX. The figure which shows the circuit structural example of a 1st signal output circuit The figure which shows the structural example of the voltage generation part in a bias circuit Timing chart showing an example of operation of the solid-state imaging device in one embodiment The figure which shows the circuit structural example of the 1st signal output circuit in other embodiment. Timing chart showing an operation example of a solid-state imaging device in another embodiment The figure which shows the structural example of an imaging device The figure which shows the modification of a pixel The figure which shows the modification of a pixel

<Description of One Embodiment>
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to one embodiment. The solid-state image sensor in one embodiment is an XY address type solid-state image sensor formed on a silicon substrate using a CMOS (complementary metal oxide semiconductor) process. The solid-state imaging device of one embodiment is mounted on an imaging device such as a digital still camera or a video camera (a configuration example of the imaging device will be described later).

  The solid-state imaging device 11 includes a pixel array 12, a plurality of horizontal control signal lines 13, a plurality of vertical signal lines 14, a first signal output circuit 15, a second signal output circuit 16, a drive circuit 17, and a bias. Circuit 18. Here, the drive circuit 17 supplies various control signals to the pixel array 12, the first signal output circuit 15, and the second signal output circuit 16 in response to, for example, an instruction from the control unit of the imaging apparatus. The bias circuit 18 is an example of a voltage generator, and supplies various reference voltages to the first signal output circuit 15 and the second signal output circuit 16.

  In one embodiment, the power supply voltages of the pixel array 12, the drive circuit 17, and the bias circuit 18 are relatively in consideration of the ease of signal readout from the photodiode and the expansion of the dynamic range of the image signal. A high first voltage is set. On the other hand, the power supply voltages of the first signal output circuit 15 and the second signal output circuit 16 are set to a second voltage lower than the first voltage in order to drive the circuit at high speed. As an example, the first voltage is 5V and the second voltage is 3V or less.

  The pixel array 12 has a plurality of pixels PX that convert incident light into electrical signals. The pixels PX of the pixel array 12 are arranged in a matrix in the first direction D1 and the second direction D2 on the light receiving surface. Hereinafter, the first direction D1 and the second direction D2 are also referred to as a row direction D1 and a column direction D2, respectively. In FIG. 1, the arrangement of the pixels PX is shown in a simplified manner, but it goes without saying that a larger number of pixels are arranged on the light receiving surface of the actual solid-state imaging device.

  Here, on the front surface of each pixel PX, a plurality of types of color filters that transmit light of different color components are arranged in a known Bayer array. Therefore, the pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter. That is, green (Gb) and blue (B) color filters are alternately arranged in odd rows of the pixel array 12, and red (R) and green (Gr) color filters are alternately arranged in even rows of the pixel array 12. Arranged. In the entire pixel array 12, the green filters are arranged in a checkered pattern. Thereby, the solid-state image sensor 11 can acquire a color image at the time of imaging.

  Further, a horizontal control signal line 13 connected to the drive circuit 17 is arranged in each row of the pixel array 12. Each horizontal control signal line 13 supplies control signals (a selection signal φSEL, a reset signal φRST, and a transfer signal φTX, which will be described later) output from the drive circuit 17 to the pixel groups arranged in the row direction D1.

  A vertical signal line 14 is arranged in each column of the pixel array 12. The plurality of pixels PX arranged in the column direction D2 are connected to each other by a vertical signal line 14 provided for each column. That is, in the pixel array 12, output signals from a plurality of pixels PX arranged in the same column are output via a common vertical signal line 14.

  In one embodiment, the odd-numbered vertical signal lines 14 corresponding to the green pixel (Gb) and the red pixel (R) are respectively connected to the first signal output circuit 15 located on the lower side of FIG. . Further, the even-numbered vertical signal lines 14 corresponding to the blue pixel (B) and the green pixel (Gr) are respectively connected to the second signal output circuit 16 located on the upper side of FIG.

  Here, a circuit configuration example of the pixel PX will be described with reference to FIG.

  The pixel PX includes a photodiode PD, a transfer transistor TX, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and a floating diffusion FD.

  The photodiode PD generates a signal charge by photoelectric conversion according to the amount of incident light. The transfer transistor TX is turned on during the high level period of the transfer signal φTX, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD.

  The source of the transfer transistor TX is a photodiode PD, and the drain of the transfer transistor TX is a floating diffusion FD. The floating diffusion FD is a diffusion region formed by introducing impurities into a semiconductor substrate, for example. The floating diffusion FD is connected to the gate of the amplification transistor AMP and the source of the reset transistor RST.

  The reset transistor RST is turned on during a high level period of the reset signal φRST, and resets the floating diffusion FD to the power supply voltage VDD. The amplification transistor AMP has a drain connected to the power supply voltage VDD, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a constant current source connected to the vertical signal line 14. A source follower circuit having a load 19 (not shown in FIG. 1) is configured. The amplification transistor AMP outputs a read current via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during a high level period of the selection signal φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 14.

  Note that when the reset transistor RST of the pixel PX is turned on, a dark signal including a noise component is read out to the vertical signal line 14. Further, based on the charge transferred from the photodiode PD to the floating diffusion FD, a bright signal including a noise component and a light receiving component is read out to the vertical signal line 14.

  Returning to FIG. 1, the first signal output circuit 15 and the second signal output circuit 16 are arranged in parallel vertically with the pixel array 12 interposed therebetween. The first signal output circuit 15 is arranged on the lower side of FIG. 1 and reads out the image signals (Gb or R) of the odd-numbered columns of the pixel array 12 for each color in the row direction D1. Further, the second signal output circuit 16 is arranged on the upper side of FIG. 1 and reads the image signals (B or Gr) of the even-numbered columns of the pixel array 12 for each color in the row direction D1. As described above, by providing the signal output circuits on both sides (upper and lower sides) of the pixel array 12, the image signal can be read from the pixel array 12 at high speed. The second signal output circuit 16 has the same basic configuration as the first signal output circuit 15 except that the even-numbered vertical signal lines 14 are connected. Therefore, in this specification, only a configuration example of the first signal output circuit 15 will be described, and a duplicate description regarding the second signal output circuit 16 will be omitted.

  The first signal output circuit 15 includes a plurality of column amplifiers 22, a column A / D conversion unit 25 (hereinafter also referred to as a column ADC), and a horizontal data bus 26. One pair of column amplifier 22 and one column ADC 25 is provided for each vertical signal line 14, and the column ADC 25 is connected to the subsequent stage of the column amplifier 22 in each pair. In the first signal output circuit 15, a plurality of pairs of column amplifiers 22 and column ADCs 25 are arranged along the row direction D1. Further, only one horizontal data bus 26 is provided in the first signal output circuit 15. The horizontal data bus 26 is connected to the output of each column ADC 25, and outputs the image signal processed by the column amplifier 22 and the column ADC 25 to the outside in units of rows.

  Next, a detailed circuit configuration example of the first signal output circuit 15 will be described with reference to FIG. For simplicity, FIG. 3 shows a configuration example from the pixel PX to the column ADC 25 among the elements corresponding to one vertical signal line 14.

  As shown in FIG. 3, the first signal output circuit 15 includes a constant current source 19, a clip unit 21, a column amplifier 22, a sample hold unit 23, a detection unit 24, and a column ADC 25 for each vertical signal line 14. Each is provided.

  The clip unit 21 is connected to the vertical signal line 14 on the input side of the column amplifier 22. The clip unit 21 clips a dark signal outside a predetermined voltage when reading the dark signal from the pixel PX.

  For example, the clip unit 21 has a cascode-connected clip voltage generation transistor MCL1 and a clip voltage control transistor MCL2. The transistor MCL1 has a drain connected to the power supply voltage VDD, a source connected to the drain of the transistor MCL2, and a gate receiving the clip voltage Vrefdclp. The source of the transistor MCL2 is connected to the vertical signal line 14, and the gate of the transistor MCL2 receives the control signal φDclp_EN. Note that when the control signal φDclp_EN is at a high level, the clipping unit 21 clips the voltage of the connected vertical signal line 14 to a predetermined value. Note that the power supply voltage of the clip unit 21 may be the first voltage.

  The column amplifier 22 is an inverting amplifier that inverts and amplifies a signal read from the pixel PX to the vertical signal line 14 for each column. The column amplifier 22 includes an input capacitor Ci having one end connected to the vertical signal line 14, an operational amplifier OP, feedback capacitors Cf1 and Cf2, and switches AZSW, SW1 and SW2.

  A PGA reference voltage Vrefpga is supplied to the non-inverting input terminal (+) of the operational amplifier OP. On the other hand, the inverting input terminal (−) of the operational amplifier OP is connected to the other end of the input capacitor Ci. The output terminal of the operational amplifier OP is connected to the sample hold unit 23 in the subsequent stage.

  The switch AZSW has one end connected to the output terminal of the operational amplifier OP and the other end connected to the inverting input terminal of the operational amplifier OP. The switch AZSW is turned on when the control signal φPGA_AZ is at a high level, and the column amplifier 22 is reset when the switch AZSW is turned on.

  The feedback capacitor Cf1 has one end connected to the output terminal of the operational amplifier OP and the other end connected to the inverting input terminal of the operational amplifier OP via the switch SW1. The feedback capacitor Cf2 has one end connected to the output terminal of the operational amplifier OP and the other end connected to the inverting input terminal of the operational amplifier OP via the switch SW2. The switches SW1 and SW2 are switches for adjusting the gain of the column amplifier 22, and are turned on when the control signals φPGAga1 and φPGAga2 are at a high level, respectively. The feedback capacitors Cf1 and Cf2 form a combined capacitor that varies according to the on / off state of the switches SW1 and SW2.

  The sample hold unit 23 samples the input analog signal at a predetermined timing, holds the sampled analog signal for a predetermined period, and outputs the analog signal to the subsequent column ADC 25. The sample hold unit 23 includes a bright signal selection switch MS1, a bright signal output switch MS2, a dark signal selection switch MN1, a dark signal output switch MN2, capacitors CTS and CTD, and a sample hold amplifier SHA. Yes.

  For example, the bright signal selection switch MS1 is turned on while the control signal φSH_S_in is at a high level, and outputs a bright signal (image signal including a light receiving component and a noise component) input from the column amplifier 22 to the capacitor CTS. The bright signal output switch MS2 is turned on while the control signal φSH_S_o is at a high level, and outputs the voltage held in the capacitor CTS to the sample hold amplifier SHA.

  On the other hand, for example, the dark signal selection switch MN1 is turned on while the control signal φSH_D_in is at a high level, and outputs the dark signal input from the column amplifier 22 to the capacitor CTD. The dark signal output switch MN2 is turned on while the control signal φSH_D_o is at a high level, and outputs the voltage held in the capacitor CTD to the sample hold amplifier SHA.

  The sample hold amplifier SHA is an amplifier that holds and outputs the voltage of the bright signal or the dark signal when not reset. The sample hold amplifier SHA is reset when the control signal φSH_RST becomes high level. The output of the sample hold amplifier SHA is connected to the detection unit 24 and the column ADC 25, respectively.

  The detection unit 24 is a circuit that detects whether the level of the dark signal amplified by the column amplifier 22 is equal to or higher than a threshold, and includes a comparator COM and a latch circuit LA.

  The comparator COM compares the dark signal output of the sample-and-hold amplifier SHA with a reference voltage (black reference voltage Vrefdcomp) serving as a black level threshold. When the dark signal output is larger than the black reference voltage Vrefdcomp, a notification signal is output. Is output. Further, the latch circuit LA latches the output of the comparator COM and outputs the latched voltage to the column ADC 25 when the control signal φDarkcomp_EN is at a high level.

  In consideration of injection and feedthrough during the reset operation, the dark signal is generally higher than the PGA reference voltage Vrefpga of the column amplifier 22. That is, in order to determine the level of the dark signal, it is necessary to supply a voltage slightly higher than the PGA reference voltage Vrefpga to the comparator COM as the black reference voltage Vrefdcomp. In one embodiment, the bias circuit 18 generates the black reference voltage Vrefdcomp by resistance division.

  As an example, FIG. 4 shows a configuration example of a voltage generation unit in the bias circuit 18. The voltage generation unit includes a resistor group 27 and an adjustment unit 28. The resistor group 27 is formed by connecting a plurality of resistors in series between the power supply voltage VDD and the PGA reference voltage Vrefpga. The level of resistance division is different between the resistors of the resistor group 27. The adjustment unit 28 is a selector that selects an arbitrary connection point from among the connection points between the resistors and connects it to the output of the black reference voltage Vrefdcomp. When the connection point with the resistor group 27 is switched by the adjusting unit 28, the resistance division ratio is changed, and the black reference voltage Vrefdcomp is adjusted. With this configuration, the black reference voltage Vrefdcomp can be adjusted to a desired value only by setting the selector.

  Returning to FIG. 3, the column ADC 25 A / D converts the input bright signal and dark signal. Further, the column ADC 25 subtracts the level of the dark signal from the level of the bright signal after A / D conversion, and outputs the pixel value information from which the noise component is removed to the horizontal data bus 26. Note that when the column ADC 25 in one embodiment receives the notification signal from the detection unit 24, the code corresponding to the white level (final pixel value) is used as pixel value information regardless of the output from the column amplifier 22. Output a code indicating the maximum value in the gradation range.

  Hereinafter, an operation example of the solid-state imaging device according to the embodiment will be described with reference to the timing chart of FIG. FIG. 5 shows the behavior of each control signal in the vertical blanking period (1H) in an arbitrary column of the solid-state imaging device. FIG. 5 also shows an example of the output waveform of the vertical signal line and an example of the output waveform from the column amplifier 22 along with the change of the control signal.

  (Timing T0): The reset signal φRST is input to the gate of the reset transistor RST of the pixel PX, and the floating diffusion FD of the pixel PX is reset to the reset voltage. Further, the selection signal φSEL is input to the gate of the selection transistor SEL of the pixel PX, and the charge accumulated in the floating diffusion FD is read out to the vertical signal line 14 through the amplification transistor AMP.

  (Timing T1): After the reset signal φRST becomes low level and the reset of the floating diffusion FD is released, the control signal φDclip_EN becomes high level. Thereby, the vertical signal line 14 is clipped.

  At the stage T1, the control signals φSH_D_in, φSH_S_in, φSH_D_o, and φSH_S_o are all at a low level, and the control signal φSH_RST is at a high level.

  (Timing T2): The control signal φPGA_AZ becomes a high level, and the switch AZSW of the column amplifier 22 is turned on. As a result, the feedback capacitors Cf1 and Cf2 are short-circuited, the column amplifier 22 is reset, and the output of the column amplifier 22 becomes equal to the PGA reference voltage Vrefpga. Note that the period during which the column amplifier 22 is reset is a period during which the control signal φPGA_AZ is at a high level.

  (Timing T3): After the control signal φPGA_AZ becomes low level and the reset of the column amplifier 22 is released, the control signal φSH_D_in becomes high level. Thereby, after the dark signal read to the vertical signal line 14 by the column amplifier 22 is amplified, the dark signal is accumulated in the capacitor CTD of the sample hold unit 23.

  (Timing T4): The control signal φSH_D_in becomes a low level, and the accumulation of the dark signal in the capacitor CTD ends. At this time, the control signal φDclip_EN becomes a low level, and the clipping of the vertical signal line 14 is released.

  (Timing T5): The transfer signal φTX is input to the gate of the transfer transistor TX of the pixel PX, and the signal charge accumulated in the photodiode PD is transferred to the floating diffusion FD. At this time, the voltage of the floating diffusion FD decreases according to the amount of charge transferred from the photodiode PD, and the signal voltage read to the vertical signal line 14 via the amplification transistor AMP and the selection transistor SEL also decreases.

  (Timing T6): The control signal φSH_S_in becomes a high level. Thereby, after the bright signal read to the vertical signal line 14 by the column amplifier 22 is amplified, the bright signal is accumulated in the capacitor CTS of the sample hold unit 23. The period during which the bright signal is accumulated in the capacitor CTS of the sample hold unit 23 is a period in which the control signal φSH_S_in is at a high level.

  (Timing T7): After the control signal φSH_S_in becomes low level, the control signal φSH_RST becomes low level, and the reset of the sample hold amplifier SHA is released. At this time, the control signal φSH_D_o becomes a high level, and the voltage held in the capacitor CTD is output to the sample hold amplifier SHA. As a result, a dark signal is output to the column ADC 25 and the detection unit 24. The comparator COM of the detection unit 24 compares the dark signal output with the black reference voltage Vrefdcomp, and outputs a notification signal (for example, a high level signal) when the dark signal output is larger than the black reference voltage Vrefdcomp. .

  (Timing T8): During a period when the control signal φSH_S_o is at a high level, the control signal φDarkcomp_EN is at a high level. As a result, the latch circuit LA of the detection unit 24 latches the output voltage of the comparator COM and outputs it to the column ADC 25.

  (Timing T9): After the control signal φSH_S_o becomes low level, the control signal φSH_RST becomes high level, and the sample hold amplifier SHA is reset again.

  (Timing T10): After the control signal φSH_RST becomes low level and the reset of the sample hold amplifier SHA is released, the control signal φSH_S_o becomes high level, and the voltage held in the capacitor CTS is output to the sample hold amplifier SHA. As a result, a bright signal is output to the column ADC 25.

  Then, the column ADC 25 A / D converts the pixel signal read out during the period (1H) during the signal reading period of the next pixel. Further, the column ADC 25 subtracts the dark signal from the bright signal after A / D conversion to obtain pixel value information. When the notification signal latched at the timing T8 is at a high level, the column ADC 25 outputs a code corresponding to the white level as pixel value information regardless of the output from the column amplifier 22.

  Next, a case where high-intensity light is incident on the solid-state imaging device of one embodiment will be described.

  When high-intensity light is incident on the solid-state imaging device 11, the charge may overflow into the floating diffusion FD even if the transfer transistor TX of the pixel PX is off. At this time, the voltage of the floating diffusion FD decreases, and the voltage of the vertical signal line 14 when reading the dark signal gradually decreases. In the above case, since the dark signal outside the predetermined voltage is usually clipped by the operation of the clip unit 21 connected to the input side of the column amplifier 22, the dark signal output from the column amplifier 22 has a small value ( In this case, the vertical signal lines and the waveform of the column amplifier are indicated by broken lines in FIG. That is, the pixel value after subtracting the dark signal from the bright signal is a substantially normal value, and the bright part of the subject is expressed brightly and the dark part is dark on the image.

  However, for example, when the gain of the column amplifier 22 is high, the signal handled by the vertical signal line 14 is a signal with a relatively small amplitude (for example, 0.1 to 0.5 V or less) and is generated in the above photographing environment. Overflowing can be at a relatively small level. On the other hand, there is always a dead zone in an analog clip circuit.

  Therefore, when the gain of the column amplifier 22 is high and the dark signal applied to the dead zone of the clip unit 21 is amplified with a high gain, the level of the dark signal becomes much higher than the original level ( The waveforms of the vertical signal line and column amplifier in this case are indicated by solid lines in FIG. That is, in such a case, when the pixel value is obtained by subtracting the dark signal from the bright signal as it is, the pixel value becomes small even for a high-luminance subject, and the high-luminance subject on the image is expressed in black.

  As the above countermeasure, in the solid-state imaging device 11 of one embodiment, the detection unit 24 outputs a notification signal when the output of the dark signal is larger than the black reference voltage Vrefdcomp. When the column ADC 25 receives the notification signal, the column ADC 25 outputs a code corresponding to the white level as pixel value information. Thereby, in one embodiment, since the pixel value becomes a white level in the case where the output of the dark signal rises, it is possible to prevent the high-luminance subject from being expressed in black.

  In particular, in one embodiment, even when the peripheral circuit of the image sensor is driven at a low voltage for speeding up signal reading, the clip unit 21 connected to the input side of the column amplifier 22 cannot cope with it. This can prevent the blackening phenomenon of a high brightness subject.

<Description of other embodiments>
FIG. 6 is a diagram illustrating a circuit configuration example of the first signal output circuit 15 in another embodiment. FIG. 6 corresponds to the configuration of FIG. 4 in the one embodiment described above. For this reason, in other embodiments, elements that are the same as those in the first embodiment are assigned the same reference numerals, and redundant descriptions are omitted.

  The configuration of another embodiment is an example of a circuit configuration when digital CDS (correlated double sampling) is performed. The first signal output circuit 15 shown in FIG. 6 is different from the example of FIG. 4 in that there is no sample hold unit 23 and the output of the column amplifier 22 is connected to the detection unit 24 and the column ADC 25. In the example of FIG. 6, a switch ADC_in is provided on the input side of the column ADC 25. The switch ADC_in is turned on when the control signal φADC_in is at a high level, and inputs the output of the column amplifier 22 to the column ADC 25. In addition, when the column ADC 25 in another embodiment receives the notification signal from the detection unit 24, the column ADC 25 replaces the gradation value of the dark signal with a preset black reference value. This black reference value is a value corresponding to the level of the dark signal obtained under normal photographing conditions, for example, and is a relatively small value.

  Hereinafter, an example of the operation of the solid-state imaging device according to another embodiment will be described with reference to the timing chart of FIG. Note that the descriptions of the timings T11 to T13 illustrated in FIG. 7 are the same as the descriptions of the timings T0 to T2 in the example of FIG.

  (Timing T14): After the control signal φPGA_AZ becomes low level and the reset of the column amplifier 22 is released, the control signal φADC_in becomes high level. As a result, the dark signal read to the vertical signal line 14 is amplified by the column amplifier 22 and then input to the column ADC 25.

  The dark signal is also input to the detection unit 24. Therefore, the comparator COM of the detection unit 24 compares the dark signal output with the black reference voltage Vrefdcomp, and outputs a notification signal (for example, a high level signal) when the dark signal output is larger than the black reference voltage Vrefdcomp. .

  (Timing T15): At the time of dark signal reading (a period in which the control signal φADC_in is at a high level), the control signal φDarkcomp_EN is at a high level. As a result, the latch circuit LA of the detection unit 24 latches the output voltage of the comparator COM and outputs it to the column ADC 25.

  (Timing T16): The control signal φADC_in becomes a low level, and the input of the dark signal to the column ADC 25 is completed. At this time, the control signal φDclip_EN becomes a low level, and the clipping of the vertical signal line 14 is released.

  After T16, the column ADC 25 performs A / D conversion of the dark signal, and latches and holds the dark signal. When the notification signal latched at the timing T15 is at a high level, the column ADC 25 does not use the output of the input dark signal, but replaces the gradation value of the dark signal with a preset black reference value. To do.

  (Timing T17): The transfer signal φTX is input to the gate of the transfer transistor TX of the pixel PX, and the signal charge accumulated in the photodiode PD is transferred to the floating diffusion FD. At this time, the voltage of the floating diffusion FD decreases according to the amount of charge transferred from the photodiode PD, and the signal voltage read to the vertical signal line 14 via the amplification transistor AMP and the selection transistor SEL also decreases.

  (Timing T18): The control signal φADC_in becomes high level, and the bright signal read out to the vertical signal line 14 is amplified by the column amplifier 22 and then input to the column ADC 25.

  Note that the control signal φADC_in becomes a low level after a lapse of a predetermined period from T18. Thereafter, the column ADC 25 performs A / D conversion of the bright signal, and latches and holds the bright signal.

  In the first signal output circuit 15 of another embodiment, the bright signal and the dark signal of the pixel PX held in each column ADC 25 are scanned in the row direction D1 by the horizontal data bus 26. Then, the dark signal is subtracted from the bright signal for each pixel by a differential amplifier provided at one end of the horizontal data bus 26. Thereby, pixel value information is output from the first signal output circuit 15.

  In another embodiment, in the case where the dark signal output is larger than the black reference voltage Vrefdcomp and the dark signal output rises, the column ADC 25 replaces the dark signal with a small black reference value. In the above case, since the bright signal has a very large value, if the dark signal after replacement is subtracted from the bright signal, a code corresponding to the white level is output as pixel value information.

  Therefore, the effects similar to those of the first embodiment can be obtained by the configurations of the other embodiments.

<Configuration example of imaging device>
FIG. 8 is a diagram illustrating a configuration example of an electronic camera that is an example of an imaging apparatus.

  The electronic camera includes an imaging optical system 31, the solid-state imaging device 32 according to one or other embodiments described above, an analog front-end circuit 33 (AFE circuit), an image processing unit 34, a monitor 35, and a recording. An I / F 36, a control unit 37, and an operation unit 38 are provided. Here, the solid-state imaging device 32, the analog front end circuit 33, the image processing unit 34, and the operation unit 38 are connected to the control unit 37, respectively.

  The imaging optical system 31 includes a plurality of lenses including, for example, a zoom lens and a focus lens. For the sake of simplicity, FIG. 8 shows the imaging optical system 31 with a single lens.

  The solid-state imaging device 32 images the image of the subject by the light flux that has passed through the imaging optical system 31. The output of this image sensor is connected to an analog front end circuit 33.

  In the shooting mode of the electronic camera, the solid-state imaging device 32 shoots a recording still image or moving image accompanied by recording in a nonvolatile storage medium (39) in response to an input from the operation unit 38. In addition, the solid-state imaging device 32 continuously captures observation images (through images) at predetermined intervals even during standby for recording still images for recording. The through image data (or the moving image data) acquired in time series is used for moving image display on the monitor 35 and various arithmetic processes by the control unit 37. Note that the electronic camera may record a through image during moving image shooting.

  The analog front end circuit 33 is a circuit that sequentially performs analog signal processing and A / D conversion processing on an image signal input in a pipeline manner. The output of the analog front end circuit 33 is connected to the image processing unit 34.

  The image processing unit 34 performs image processing (color interpolation processing, gradation conversion processing, contour enhancement processing, white balance adjustment, etc.) on the digital image signal input from the analog front end circuit 33. Note that a monitor 35 and a recording I / F 36 are connected to the image processing unit 34.

  The monitor 35 is a display device that displays various images. For example, the monitor 35 performs moving image display (viewfinder display) of a through image under the shooting mode under the control of the control unit 37.

  The recording I / F 36 has a connector for connecting a nonvolatile storage medium 39. The recording I / F 36 writes / reads data to / from the storage medium 39 connected to the connector. The storage medium 39 includes a hard disk, a memory card incorporating a semiconductor memory, or the like. In FIG. 8, a memory card is illustrated as an example of the storage medium 39.

  The control unit 37 is a processor that comprehensively controls the operation of the electronic camera. The operation unit 38 receives an instruction to acquire a recording still image (for example, a full press operation of a release button) from the user.

  Since the electronic camera uses the solid-state imaging device 32 of the above-described one embodiment or another embodiment, it is possible to prevent a high-luminance subject from being expressed in black while performing high-speed signal readout by low-voltage driving. .

<Supplementary items of the embodiment>
(Supplement 1): In the other embodiment described above, the column ADC 25 may perform the subtraction of the bright signal and the dark signal before the horizontal scanning.

  (Supplement 2): In each of the above embodiments, all the vertical signal lines may be connected to the first signal output circuit 15 and the second signal output circuit 16, respectively. At this time, a column selector is provided in each of the first signal output circuit 15 and the second signal output circuit 16, and odd column reading and even column reading are performed between the first signal output circuit 15 and the second signal output circuit 16. May be switched alternately for each line. In this case, for example, since the signal of the green pixel (Gr, Gb) can be read out through the same column amplifier 22, the level difference of the signal of the green pixel (Gr, Gb) can be reduced.

  (Supplement 3): In the above-described embodiment, an example in which one pixel includes four transistors has been described. However, in the solid-state imaging device of the present invention, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are shared between a plurality of pixels (for example, a 2.5Tr configuration including two transistors and five transistors, or four pixels). 1.75Tr configuration having seven transistors).

  FIG. 9 shows a modification of the pixel PX. The configuration of the pixel PX shown in FIG. 9 is that the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the floating diffusion FD are shared by two pixels (PX1 to PX2) adjacent in the column direction D2 of the pixel array. Is the same as the pixel PX of FIG. 2 described above. For the pixel PX shown in the figure, a plurality of floating diffusions FD adjacent to each other in the column direction D2 may be connected by a switch, and addition reading in the column direction D2 may be enabled (illustration is omitted in this case).

  FIG. 10 shows a modification of the pixel PX. The configuration of the pixel PX shown in FIG. 10 is that the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the floating diffusion FD are shared by four pixels (PX1 to PX4) adjacent in the column direction D2 of the pixel array. Is the same as the pixel PX of FIG. 2 described above.

  (Supplement 4): In the above embodiment, the configuration of the electronic camera has been described as an example of the imaging apparatus. However, the image pickup apparatus of the present invention may be an on-chip integrated solid-state image pickup device and various signal processing circuits.

  (Supplement 5): In the above embodiment, the color filter array of the solid-state imaging device is not limited to the Bayer array, and other color filter arrays (for example, complementary color filters using magenta, green, cyan, and yellow) It may be.

  From the above detailed description, features and advantages of the embodiments will become apparent. It is intended that the scope of the claims extend to the features and advantages of the embodiments as described above without departing from the spirit and scope of the right. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to use appropriate improvements and equivalents within the scope disclosed in.

DESCRIPTION OF SYMBOLS 11 ... Solid-state image sensor, 12 ... Pixel array, 13 ... Horizontal control signal line, 14 ... Vertical signal line, 15 ... 1st signal output circuit, 16 ... 2nd signal output circuit, 17 ... Drive circuit, 18 ... Bias circuit, DESCRIPTION OF SYMBOLS 19 ... Constant current source, 21 ... Clip part, 22 ... Column amplifier, 23 ... Sample hold part, 24 ... Detection part, 25 ... Column A / D conversion part (column ADC), 26 ... Horizontal data bus, 27 ... Resistor Group, 28 ... adjustment unit

Claims (11)

Pixels arranged in a matrix and converting incident light into electrical signals;
A plurality of vertical signal lines connected to the plurality of pixels in the column direction and reading out a dark signal including a noise component and a bright signal including a light receiving component from the pixel;
A column amplifier for amplifying the signal read to the vertical signal line;
A clip unit that is connected to the vertical signal line on the input side of the column amplifier and clips a signal outside a predetermined voltage;
A column A / D converter that is arranged on the output side of the column amplifier and outputs the signal after A / D conversion;
A detector that outputs a notification signal to the column A / D converter when the level of the dark signal output from the column amplifier is greater than a threshold;
The column A / D converter outputs a code corresponding to a white level as pixel value information when receiving the notification signal ,
The power supply voltage of the column amplifier and the column A / D conversion unit is an image sensor that is lower than the power supply voltage of the pixel and the clip unit . In an imaging device according to claim 1,
A sample hold unit that holds the bright signal and the dark signal is further provided in a subsequent stage of the column amplifier,
The detection unit compares the level of the dark signal output from the sample hold unit with the threshold value, and outputs the notification signal.
The column A / D conversion unit, wherein upon reception of the broadcast signal irrespective of the output from the column amplifier, the output to that an imaging device the corresponding code to the white level. In an imaging device according to claim 1 or claim 2,
The column A / D converter replaces the gradation value of the dark signal with a predetermined black reference value when the notification signal is received, and obtains a difference between the gradation value of the bright signal and the black reference value. in, you output a code corresponding to the white level IMAGING element. In an imaging device according to any one of claims 1 to 3,
A voltage generation unit that supplies the detection unit with a black reference voltage that defines the threshold;
The voltage generator is
A group of resistors connected between a power supply voltage and a reference voltage of the column amplifier;
Wherein by switching the connection of the resistor group, an adjustment unit for adjusting the black reference voltage by a change in resistance division ratio, the including an imaging element. Provided that an imaging apparatus an imaging element according to any one of claims 4 claim 1. A signal line for outputting a signal read from the pixel portion;
  A detection unit that compares the signal and a reference signal and outputs a notification signal when the signal is larger than the reference signal;
  A signal conversion unit connected to the signal line and the detection unit, the signal conversion unit outputting the signal as a constant digital signal when the notification signal is input,
  The power supply voltage of the signal conversion unit is an image sensor that is lower than the power supply voltage of the pixel unit. The image sensor according to claim 6, wherein
  A clip unit that is connected to the signal line between the pixel unit and the detection unit and adjusts the voltage of the signal line so as not to exceed a predetermined threshold;
The power supply voltage of the signal conversion unit is an image sensor that is lower than the power supply voltage of the clip unit. In the imaging device according to claim 6 or 7,
  An amplifier connected to the signal line for amplifying the signal;
  The detection unit compares the signal amplified by the amplification unit with the reference signal, and outputs the notification signal when the signal is larger than the reference signal. The image sensor according to claim 8, wherein
  The power supply voltage of the amplification unit is an image sensor that is lower than the power supply voltage of the pixel unit. In the imaging device according to claim 8 or 9,
  The power supply voltage of the amplifying unit is an image sensor that is lower than the power supply voltage of the clip unit. An imaging device comprising the imaging device according to any one of claims 6 to 10.

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