JP4485275B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging device in which unit cells for photoelectric conversion upon incidence of light are arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and in particular, a phenomenon that an image is blackened when strong light is incident. It relates to technology to prevent.

In recent years, imaging devices using an imaging device such as a home video camera and a digital still camera have been widely used.
Some of these imaging devices include an amplification type image sensor as an imaging device.
The amplification type image sensor has excellent characteristics such as low noise, but has a problem that the image is blacked out when strong light is incident.

Japanese Patent Application Laid-Open No. 2000-287131 discloses an outline of a CMOS image sensor which is an amplification type image sensor, the same problems as described above, and the incidence of strong light based on the output voltage at reset for each pixel sensor. A CMOS image sensor that detects the above and replaces the reset voltage with another voltage is disclosed, and it is described that the problem can be prevented.
JP 2000-287131 A

In Japanese Patent Application Laid-Open No. 2000-287131, the change in the output voltage at the time of resetting as an index when detecting a pixel sensor in which the image is crushed is a cause of the image being crushed, even if the amount of change is small. Even if it exists, it directly affects the luminance information.
However, in order to detect the change in the output voltage at the time of resetting, the change cannot be detected unless the amount of change exceeds a certain level. Therefore, it is difficult to completely eliminate the adverse effects caused by the change.

In addition, since the characteristics of the change in the output voltage at the time of resetting when strong light is incident are steep and difficult to detect with high accuracy, it is not easy to reliably prevent blackout.
For example, with a CMOS image sensor disclosed in Japanese Patent Application Laid-Open No. 2000-287131, if an object whose center portion is sufficiently bright and its peripheral portion gradually darkens is photographed, blackening will occur in a sufficiently bright region in the center portion. Although it can be prevented, the periphery of the area where blackout is prevented is photographed darker than the surrounding dark portion, and ring-shaped blackening occurs depending on the degree.

  Accordingly, the present invention is an image pickup apparatus that can reliably solve the problem that the image is blackened when a strong light is incident, and can reliably eliminate the adverse effects caused by the voltage change at the time of resetting. And it aims at providing the imaging method.

In order to achieve the above object, the imaging apparatus according to the present invention uses a reset voltage corresponding to an output voltage of the photoelectric conversion unit when the photoelectric conversion unit is an initial voltage and an output voltage of the photoelectric conversion unit according to the amount of received light. Imaging having an imaging unit in which a plurality of unit cells that output corresponding read voltages are arranged one-dimensionally or two-dimensionally, and an output unit that outputs voltage information corresponding to the amount of received light for each unit cell The output means is connected to the imaging means and receives a signal output line for receiving the read voltage and the reset voltage, a clamp capacitor connected to the signal output line, and a gate potential as a fixed potential, When the lead voltage is in a predetermined range, the terminals of the clamp capacitor are in a non-conductive state, and when the lead voltage is not in a predetermined range, the terminals are in a conductive state. Characterized in that it comprises a first transistor.

In order to achieve the above object, the imaging method according to the present invention provides a reset voltage corresponding to an output voltage of the photoelectric conversion unit when the photoelectric conversion unit is an initial voltage and an output voltage of the photoelectric conversion unit corresponding to the amount of received light. An imaging region in which a plurality of unit cells that output corresponding read voltages are arranged one-dimensionally or two-dimensionally, a signal output line that is connected to the imaging means and receives the read voltage and the reset voltage, and the signal output An imaging method in an imaging apparatus , comprising: a clamp capacitor connected to a line; and a first transistor connected in parallel to the clamp capacitor and having a gate potential of a fixed potential , wherein the first cell for each unit cell by the potential indicating the potential of the transistor, a judgment step of the read voltage to determine whether a voltage of a predetermined range, the predetermined range by said determination step Comprising the steps of a non-conductive state between the terminals of the clamping capacitor when it is determined that the voltage, the step of between said terminals to a conductive state when it is determined not to be the voltage of the predetermined range by said determination step It is characterized by including.

With the configuration described in the means for solving the problem, the voltage at the time of reading is used as an index when detecting a pixel sensor in which the image is blacked out, so that a change in the voltage at the time of reset that causes blackout is generated. Measures can be taken with a margin from incident light that is sufficiently weaker than incident light.
Therefore, it is possible to more reliably solve the problem that the image is blacked out when strong light is incident, and to reliably eliminate the adverse effects caused by the voltage change at the time of reset.

  In the imaging apparatus, the output unit is connected to the imaging unit and receives the reset voltage and the read voltage output from the unit cell, and is connected to a subsequent circuit to the subsequent circuit. The second output line for outputting the luminance information, the clamp capacitor connected in series between the first output line and the second output line, and the voltage applied between the terminals of the clamp capacitor connected in parallel with the clamp capacitor And a bypass transistor that makes the terminals non-conductive when the voltage is in the predetermined range, and makes the terminals conductive when the voltage applied between the terminals is not the voltage in the predetermined range. You can also

Thereby, when the voltage applied between the terminals of the clamp capacitor is not in a predetermined range, the voltage of the second output line is replaced with the voltage of the first output line without any special operation, and this is output as luminance information. The object can be achieved by adding only one bypass transistor for each output means.
In the imaging device, the voltage in the predetermined range of the bypass transistor is a case where the potential of the first output line is higher than the potential indicating the potential of the bypass transistor. The case where the voltage is not within the range may be a case where the potential of the first output line is equal to or lower than the potential indicating the potential of the bypass transistor.

Thus, when the potential of the first output line is higher than the potential indicating the potential of the bypass transistor, the voltage of the second output line is replaced with the voltage of the first output line without any special operation, and this is output as luminance information. Therefore, the object can be achieved only by adding one bypass transistor for each output means.
In the imaging apparatus, the output unit may further include a sampling capacitor connected in series between the second output line and a predetermined voltage terminal, and a series connection between the second output line and a reference voltage terminal. A clamp transistor connected to the first output line, a reset voltage is output to the first output line in a state in which the clamp transistor is turned on and the second output line is set to a reference voltage, and then the first transistor in a state in which the clamp transistor is turned off. Control means for outputting a read voltage to the output line, and a reset voltage that is a voltage within the predetermined range is output to the first output line in a state where the clamp transistor is turned on and the second output line is set to a reference voltage. In the state where the voltage corresponding to the difference between the reference voltage and the reset voltage is held in the clamp capacitor, and then the clamp transistor is turned off. When a read voltage that is a voltage within the predetermined range is output to the first output line, the voltage of the second output line changes from the reference voltage by the amount held in the clamp capacitor, and as a result When the luminance information indicating the difference between the reset voltage and the read voltage is output, and the read voltage that is not in the predetermined range is output to the first output line with the clamp transistor turned off, the bypass transistor Makes the voltage between the terminals of the clamp capacitor conductive, so that the voltage of the second output line is replaced with the lead voltage, and as a result, regardless of whether the reset voltage is within the predetermined range or not. Luminance information indicating high luminance can be output.

  In the imaging apparatus, the output unit may further include a sampling capacitor connected in series between the second output line and a predetermined voltage terminal, and a series connection between the second output line and a reference voltage terminal. And a control means for turning on the clamp transistor with the read voltage being output to the first output line and then turning off the clamp transistor and outputting a reset voltage to the first output line When a clamp transistor is turned on in a state where a read voltage that is a voltage in the predetermined range is output to the first output line, a voltage corresponding to a difference between the reference voltage and the read voltage is a clamp capacitance. Then, with the clamp transistor turned off, a reset voltage that is a voltage within the predetermined range is output to the first output line. When this is done, the voltage of the second output line changes from the reset voltage by the voltage held in the clamp capacitor, and as a result, luminance information indicating the difference between the reset voltage and the read voltage is output, When the read voltage that is not in the predetermined range is output to the first output line, the bypass transistor conducts between the terminals of the clamp capacitor, so that no voltage is held in the clamp capacitor. As a result, luminance information indicating high luminance can be output.

As a result, when the read voltage is not in the predetermined range, the voltage of the second output line is replaced with the read voltage, which is output as luminance information, so only one bypass transistor is added for each output means. Can achieve the purpose.
In the imaging apparatus, the output unit may further include a voltage supply unit that supplies a bias voltage to the gate of the bypass transistor.

As a result, the dynamic characteristics of the bypass transistor can be determined at a later time and at different times depending on the bias voltage to be supplied, so that the versatility is high.
In the imaging device, the bypass transistor may be a depletion type transistor.
This eliminates the need to supply a bias voltage to the bypass transistor, thereby simplifying the circuit.

  Further, in the imaging apparatus, each of the unit cells in the imaging means includes a light receiving element that generates a charge corresponding to the amount of received light, a charge detection unit that holds the charge generated by the light receiving element and outputs it as a voltage signal, and a reset reference A reset transistor connected between the voltage terminal and the charge detection unit, wherein the charge detection unit is reset to a reference voltage when a gate voltage is applied and is in a conductive state; an amplification reference voltage terminal; and a first output line And a voltage signal applied to the gate and amplified by the voltage signal applied to the gate and amplified and output to the first output line, and the potential indicating the potential of the bypass transistor is reset. An amplifying transistor included in the unit cell depending on the potential of the reset transistor when the transistor is non-conductive Can also be characterized by higher predetermined difference than the saturation signal output potential is output.

As a result, if the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential is larger than a certain level, it functions as a bypass transistor, so that the effect can be expected.
In the imaging apparatus, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential may be approximately 0.1V.

Thereby, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential can be set to approximately 0.1V.
In the imaging apparatus, the output means further includes voltage supply means for supplying a bias voltage to the gate of the bypass transistor, and the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential is the bias. It can also be characterized by being given by voltage.

Thereby, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential can be set by supplying the bias voltage.
In the imaging device, the bypass transistor and the reset transistor may be produced in the same process.
Thereby, since the bypass transistor and the reset transistor are produced in the same process, the electrical characteristics of the element are approximated, so that the variation in the supplied bias voltage is reduced and the setting is facilitated.

In the imaging apparatus, the voltage supply unit may include a bias voltage setting circuit that can set an appropriate bias voltage that differs for each imaging apparatus from the outside.
Thereby, since the bias voltage can be set from the outside, it is possible to align individual characteristics for each image pickup apparatus that usually tends to vary.

Further, in the imaging device, the reset transistor is produced by a predetermined implantation, and the bypass transistor is produced through an additional implantation in addition to the predetermined implantation, and a potential indicating the potential of the bypass transistor and the saturation signal output potential The difference may be given by the additional injection.
Thereby, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential can be set by additional injection.

Further, in the imaging device, a substrate bias voltage having a potential different from that of the reset transistor is applied to the bypass transistor, and a difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential is a difference of the substrate bias voltage. It can also be characterized by being controlled by.
Thereby, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential can be set by the difference in the substrate bias voltage.

In the imaging apparatus, the output unit may further include a subsequent analog as luminance information indicating the high luminance when the voltage between the first output line and the second output line is not in the predetermined range. A clipping transistor that outputs a voltage that matches the input dynamic range of the circuit may be included.
As a result, a voltage matching the input dynamic range of the subsequent analog circuit can be output as the luminance information indicating high luminance, so that the performance of the analog circuit can be utilized efficiently.

  In the imaging device, the clipping transistor is connected between a voltage terminal corresponding to the upper limit voltage of the input dynamic range of the analog circuit in the subsequent stage and the second output line, and a predetermined voltage is applied to the gate. When in the conductive state, a voltage matching the input dynamic range of the subsequent analog circuit is output from the second output line to the subsequent circuit, and the output means further inputs the luminance information to the subsequent analog circuit. A clipping transistor control means for applying a pulse voltage to the gate of the clipping transistor to drive the clipping transistor so that the clipping transistor is temporarily turned on. You can also

As a result, the clipping transistor can be pulse-driven, so that power consumption is low.
In the imaging apparatus, the output unit may further include a sampling transistor connected in series between the first output line and the clamp capacitor, and a vertical blanking period in which luminance information is not output from the imaging unit. And sampling transistor control means for bringing the sampling transistor into a non-conductive state.

As a result, the sampling transistor can be made non-conductive in the vertical blanking period, so that the first output line and the clamp capacitor are non-conductive, and no charge is held in the clamp capacitor. Can be output.
Accordingly, since a saturated output signal is not output during the vertical blanking period, the input dynamic range of the subsequent output amplifier is not restricted.

  Further, in the imaging apparatus, each of the unit cells in the imaging means is connected between the reference voltage terminal for amplification and the first output line, and the voltage signal converted by the charge detection unit is applied to the gate so that the voltage signal is converted. An amplifying transistor for amplifying and outputting to the first output line, and a select transistor connected in series between the amplifying reference voltage terminal and the amplifying transistor or between the amplifying transistor and the first output line The output means further includes a load transistor that reads the output voltage through the amplifying transistor and the select transistor by applying a load to the first output line in the conductive state, and the load transistor is in the conductive state. Before switching, select transistors of any unit cell are turned on and all unit cells are selected. Control means for making the load transistor non-conductive before making the transistor non-conductive, and making the load transistor non-conductive during the vertical blanking period in which no luminance information is output from any unit cell. It can also be characterized.

As a result, the load transistor can be made non-conductive in the vertical blanking period, so that no charge is held in the clamp capacitor and luminance information indicating low luminance can be output.
Accordingly, since a saturated output signal is not output during the vertical blanking period, the input dynamic range of the subsequent output amplifier is not restricted.

(Embodiment 1)
<Configuration>
FIG. 1 is a diagram showing a schematic configuration of an imaging apparatus according to Embodiment 1 of the present invention.
As shown in FIG. 1, the imaging apparatus according to the first embodiment includes an imaging unit 1, a load circuit 2, a row selection encoder 3, a column selection encoder 4, a signal processing unit 5, and an output circuit 6.

The imaging unit 1 is an imaging region in which unit cells are arranged one-dimensionally or two-dimensionally. Here, a case of 9 pixels arranged in 3 × 3 two dimensions will be described as an example. However, the actual number of pixels is several thousand in one dimension and several hundred thousand to several million in two dimensions. About one.
The load circuit 2 is a circuit in which one identical circuit is connected for each vertical column, and a load is applied to the pixels of the imaging unit 1 in units of columns in order to read the output voltage.

The row selection encoder 3 includes three control lines “RESET”, “READ”, and “LSEL” for each horizontal row, and resets (initializes) the pixels of the imaging unit 1 in units of rows. Read (read) and line select (row selection) are controlled.
The column selection encoder 4 includes control lines and sequentially selects columns.
The signal processing unit 5 is connected to one identical circuit for each vertical column, and processes the column unit output from the imaging unit 1 and sequentially outputs it.

The output circuit 6 performs conversion necessary for outputting to the outside to the output of the signal processing unit 5 and outputs the result.
FIG. 2 is a diagram schematically illustrating a circuit of the imaging apparatus according to the first embodiment.
As shown in FIG. 2, the imaging device of Embodiment 1 includes a load circuit 100, a pixel circuit 110, and a signal processing circuit 120.

The load circuit 100 describes one circuit in the load circuit 2 of FIG. 1 and includes a load transistor 101 connected between the first signal output line and GND, and a load voltage (LG). Is supplied.
The pixel circuit 110 describes one unit cell in the imaging unit 1 of FIG. 1, and a reset signal obtained by amplifying the voltage at the time of initialization and a read voltage obtained by amplifying the voltage at the time of reading by the first signal. It outputs to an output line, photoelectrically converts incident light and outputs a charge, and the like. The light receiving element 111 such as a photodiode, the charge generated by the light receiving element 111 are accumulated, and the accumulated charge is output as a voltage signal. A capacitor 112, a reset transistor 113 that resets the voltage indicated by the capacitor 112 to be an initial voltage (here, VDD), a read transistor 114 that supplies electric charge output from the light receiving element 111 to the capacitor 112, An amplifying transistor 115 that outputs a voltage that changes following the indicated voltage, and the row selection encoder 3 And a line select transistor 116 that outputs an output of the amplifier transistor 115 to the first signal output line upon receipt of a line select signal. Here, in this specification, in order to facilitate the following description, a reset transistor 113, a read transistor 114, and an amplifying transistor 115, which indicate a voltage corresponding to the accumulated charge in the capacitor 112, are connected. This portion is particularly referred to as a charge detection unit 117.

  The signal processing circuit 120 describes one circuit for one vertical column in the signal processing unit 5 of FIG. 1, and is output by the unit cell when the read voltage is a voltage within a predetermined range. Luminance information indicating a difference between the reset voltage and the read voltage is output, and luminance information indicating high luminance is output when the read voltage is not in the predetermined range. A sampling transistor 121 and a clamp capacitor 122 connected in series between the line and the second signal output line; a sampling capacitor 123 connected in series between the second signal output line and GND; and a second signal output The clamp transistor 124 connected in series between the line and the reference voltage terminal VDD and the clamp capacitor 122 are connected in parallel, and the voltage applied between the terminals of the clamp capacitor 122 is the predetermined voltage. If not exceeding voltage between the terminals and a non-conductive state, when the voltage applied between the terminals exceeds the predetermined voltage includes a bypass transistor 125 between the terminal conductive.

  Here, the pixel circuit 110 receives a reset pulse (initialization signal: RESET), a read pulse (readout pulse: READ), and a line select pulse (row selection signal: LSEL), and the signal processing circuit 120 receives sampling. A pulse (SP) and a clamp pulse (CP) are supplied at a predetermined timing, and transistors corresponding to the respective control pulses are opened / closed (OFF / ON).

FIG. 3 is a diagram illustrating the timing of each control pulse in the imaging apparatus according to the first embodiment.
By giving each control pulse at the timing as shown in FIG. 3, the first signal output line is turned on with the line select transistor 116 turned on, the clamp transistor 124 turned on and the second signal output line is set to the reference voltage. The reset voltage is output (a in FIG. 3), and when the reset voltage is within a predetermined range, the difference between the reference voltage and the reset voltage is held in the clamp capacitor 122 (b in FIG. 3). Then, a read voltage is output to the first signal output line with the clamp transistor 124 turned off (c in FIG. 3). When the read voltage is a voltage within a predetermined range, the voltage of the second signal output line is The difference from the reference voltage is equivalent to the difference between the reset voltage and the read voltage (d in FIG. 3), and this can be output as luminance information. When mode voltage is not the voltage of the predetermined range, by the bypass transistor 125 is between the terminals to the conductive state, the voltage of the second signal output line is replaced by the read voltage can be output as brightness information.

Here, as a method of setting a voltage within a predetermined range, for example, a depletion type transistor may be built as the bypass transistor 125 at the time of manufacture, or a bias voltage is always applied to the gate of the bypass transistor 125 by the voltage supply means or at a necessary timing. (C to d in FIG. 3) may be supplied.
For example, a bias voltage may be output to the gate of the bypass transistor 125 and a pulse may be output during a period in which the read voltage is read from the pixel circuit 110.

<Operation>
FIGS. 4A to 4D show the pixel circuit 110 at each timing when the light is not so strong as to darken the image or the image is blackened (hereinafter referred to as “normal time”). It is a figure which shows the state of the potential for every area | region.
Here, FIGS. 4A to 4D correspond to the timings of FIGS. 3A to 3D, respectively.

FIG. 5A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing shown in FIG.
FIG. 5B is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the normal time.
FIG. 5C is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG.

Here, in each figure of FIG. 4 and FIG. 5, the upper half shows the outline of the circuit, and the lower half shows the state of the potential for each region corresponding to each position of the upper half circuit.
The potential transition for each region in the pixel circuit 110 and the potential transition for each region in the signal processing circuit 120 in the normal state will be described below with reference to FIGS. 4 (a) to 4 (d) and FIG. 5 (a). It demonstrates along-(c).

(1) Since the read transistor 114 is OFF and the reset transistor 113 is ON at the timing of FIG. 3A, the charge generated in the light receiving element 111 moves to the charge detection unit 117 as shown in FIG. Instead, the charge of the charge detection unit 117 moves to the VDD terminal.
(2) At the timing of FIG. 3B, the reset transistor 113 is turned from ON to OFF, and as shown in FIG. 4B, the voltage of the charge detection unit 117 is reset to VDD, and the clamp transistor 124 is turned on. Therefore, as shown in FIG. 5A, the voltage of the second signal output line is reset to VDD.

(3) At the timing of FIG. 3B ′, the clamp transistor 124 is turned from ON to OFF, and as shown in FIG. 5B, the difference between the reset voltage and VDD is held in the clamp capacitor 122.
(4) At the timing shown in FIG. 3C, the reset transistor 113 remains OFF and the read transistor 114 turns ON. Therefore, as shown in FIG. Move to 117.

(5) At the timing of FIG. 3 (d), as shown in FIG. 4 (d), the reset transistor 113 remains OFF and the read transistor 114 is OFF. The data is read by the unit 117.
Here, the voltage of the charge detection unit 117 changes, and the voltage after this change is amplified by the amplifying transistor 115, so that the voltage of the first signal output line changes to the read voltage, and the reset voltage and VDD Since the difference equivalent is held in the clamp capacitor 122, the voltage of the second signal output line becomes “VDD−corresponding to the change in voltage of the first signal output line” as shown in FIG. Is output as luminance information (when the voltage change of the first signal output line is SIG, the clamp capacitor 122 is Ccp, and the sampling capacitor 123 is Csp: the voltage of the second signal output line is VDD−SIG × Ccp / (Ccp + Csp ).

6 (a) to 6 (d) and FIG. 7 show pixels at each timing when light that is strong enough to darken the image or darken the image (hereinafter referred to as "high brightness") is entered. FIG. 3 is a diagram showing a potential state for each region in a circuit 110.
Here, FIGS. 6A to 6D correspond to the timings of FIGS. 3A to 3D, respectively, and FIG. 7 shows the case of FIG. 3 corresponds to the timing when the strong light is incident or later than FIG. 3D, and shows a state where blackout occurs if no measures are taken.

In this specification, even when the brightness is high, the case where the charge of the first signal output line does not exceed the potential of the bypass transistor 125 at the timing of FIG. A case where the charge of the first signal output line exceeds the potential of the bypass transistor 125 is referred to as a second high brightness state.
FIG. 8A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B at the time of the first high luminance.

FIG. 8B is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the time of the first high luminance.
FIG. 8C is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3D at the time of the first high luminance.
FIG. 9A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B at the time of the second high luminance.

FIG. 9B is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the second high luminance.
FIG. 9C is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3D at the time of the second high luminance.
6, 7, 8, and 9, the upper half shows the outline of the circuit, and the lower half shows the state of potential for each region corresponding to each position of the upper half circuit. Show.

The potential transition for each region in the pixel circuit 110 and the potential transition for each region in the signal processing circuit 120 at the time of high luminance will be described below with reference to FIGS. 6 (a) to 6 (d), FIG. Description will be made along 8 (a) to (c) and FIGS. 9 (a) to 9 (c).
(1) Since the read transistor 114 is OFF and the reset transistor 113 is ON at the timing of FIG. 3A, the charge generated in the light receiving element 111 does not move to the charge detection unit 117 in the normal state. At the time of high luminance and at the time of second high luminance, as shown in FIG. 6A, the charge generated in the light receiving element 111 exceeds the potential of the read transistor 114 and moves to the charge detection unit 117, and at the same time, the charge detection unit. The electric charge 117 moves to the VDD terminal.

  (2) Although the reset transistor 113 is turned from ON to OFF at the timing of FIG. 3B, the charge generated in the light receiving element 111 continues to exceed the potential of the read transistor 114 as shown in FIG. 6B. Since it moves to the charge detection unit 117, the voltage of the charge detection unit 117 is lower than VDD. Since the clamp transistor 124 is ON at this time, the voltage of the second signal output line is reset to VDD and the charge of the first signal output line is bypassed as shown in FIG. At the time of the second high luminance without exceeding the potential of the transistor 125, as shown in FIG. 9A, the voltage of the second signal output line is reset to VDD, but at the same time, the charge of the first signal output line is reduced. The potential of the bypass transistor 125 is exceeded, and the signal moves to the second signal output line.

  (3) At the timing of FIG. 3B ′, the clamp transistor 124 is turned from ON to OFF, and in the normal state, the voltage of the second signal output line is reset to VDD. Is held in the clamp capacitor 122, but at the time of the first high luminance, as shown in FIG. 8B, the difference between the reset voltage smaller than the normal time and VDD is held in the clamp capacitor 122, At the time of the second high luminance, as shown in FIG. 9B, the charge of the first signal output line moves to the second signal output line beyond the potential of the bypass transistor 125, and almost no voltage is applied to the clamp capacitor 122. Differences are not retained.

Note that at the timing of FIGS. 3B and 3B ′, at the second high luminance, the charge of the first signal output line exceeds the potential of the bypass transistor 125 and moves to the second signal output line. Although the voltage difference is hardly held in the capacitor 122, the output result is the same even in such a case, and the subsequent operation is important.
(4) At the timing shown in FIG. 3C, the reset transistor 113 remains OFF and the read transistor 114 turns ON. Therefore, as shown in FIG. Move to 117.

(5) At the timing of FIG. 3 (d), as shown in FIG. 6 (d), the reset transistor 113 remains OFF and the read transistor 114 is OFF. The data is read by the unit 117.
Here, the voltage of the charge detection unit 117 is changed, and the voltage after the change is amplified by the amplifying transistor 115. Therefore, the voltage of the first signal output line is changed to the read voltage. Since the difference between the voltage and VDD is held in the clamp capacitor 122, the voltage of the second signal output line becomes “VDD−corresponding to the change in voltage of the first signal output line”, and this voltage is output as luminance information. However, at the time of the first high luminance and the second high luminance, the charge of the first signal output line exceeds the potential of the bypass transistor 125 as shown in FIGS. 8C and 9C, respectively. Since the voltage of the second signal output line becomes “corresponding to the voltage of the first signal output line”, the voltage of the second signal output line becomes a voltage indicating high luminance, and this voltage is output as luminance information.

<Summary>
FIG. 10A is a diagram illustrating the voltage characteristics of the first signal output line at the time of resetting.
FIG. 10B is a diagram illustrating a voltage characteristic of the first signal output line at the time of reading.
FIG. 10C is a diagram illustrating the output voltage characteristics of a conventional imaging device that does not take any measures against dark images or blackened images. -Corresponds to FIG.

FIG. 10D is a diagram showing the characteristics of the output voltage in the imaging apparatus according to Embodiment 1 of the present invention. When the voltage exceeds a predetermined voltage, the voltage becomes high and the image becomes dark. The image is never blackened.
10A to 10D, the horizontal axis indicates the intensity of incident light (right is strong), the vertical axis indicates voltage ((a) and (b) are positive, and (c) and (d). ) Indicates minus on the top.

As described above, the first embodiment of the present invention focuses on the voltage at the time of reading shown in FIG. 10B, and bypasses when the voltage at the time of reading reaches a voltage around which the amplifier circuit is saturated. Since the transistor directly replaces the output voltage with a voltage indicating high brightness, the image is displayed when strong light is incident by taking measures with sufficient margin from incident light that is sufficiently weaker than incident light where the image becomes dark or blackout occurs. The problem of black crushing can be solved more reliably than before, and adverse effects due to voltage changes at reset can be reliably eliminated.
(Embodiment 2)
<Configuration>
FIG. 11 is a diagram schematically illustrating a circuit of the imaging apparatus according to the second embodiment.

In the second embodiment, instead of the signal processing circuit 120 of the first embodiment, the second signal output line is changed so that the second signal output line does not change to a voltage exceeding the input dynamic range of the output amplifier in the subsequent stage. A signal processing circuit 130 to which a clip transistor 131 connected in series with a clip voltage terminal (CLIPDC) is added is provided.
The image pickup apparatus according to Embodiment 2 includes the clip transistor 131, so that the voltage of the second signal output line can be prevented from becoming a certain voltage or less.

Here, as a driving method of the clip transistor 131, there are DC driving that operates at a constant voltage and pulse driving that applies a clip pulse (CLIP) at an appropriate timing.
The timing of each control pulse when the clip transistor 131 is DC-driven is the same as that in FIG. 3 of the first embodiment.
The timing of each control pulse when the clip transistor 131 is pulse-driven will be described below.

FIG. 12 is a diagram illustrating the timing of each control pulse including a clip pulse when the clip transistor 131 is pulse-driven in the imaging apparatus according to the second embodiment.
As shown in FIG. 12, when the clip transistor 131 is pulse-driven, the clip pulse is turned on after the sampling pulse is turned off (e in FIG. 12) so that the voltage of the second signal output line does not become a certain voltage or lower. To. Here, (a) to (d) in FIG. 12 are the same as (a) to (d) in FIG.

<Operation 1>
The operation when the clip transistor 131 is DC-driven will be described below.
FIG. 13 is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing shown in FIG.
Here, in FIG. 13, the upper half shows an outline of the circuit, and the lower half shows a potential state for each region corresponding to each position of the upper half circuit.

Hereinafter, the state of potential for each region in the signal processing circuit 120 at the time of high luminance will be described with reference to FIG.
(1) At the timing shown in FIG. 3 (d), as shown in FIG. 13, the GND charge moves over the potential of the load transistor 101 to the first signal output line, and the sampling transistor 121 is ON. Moves beyond the potential of each transistor, and a steady current flows from the clip voltage terminal to GND. Here, since the voltage of the second signal output line is determined by the potential of the clip transistor 131, it can be determined by the gate voltage of the clip transistor 131.

Note that the potential of the clip transistor 131 may be set by manufacturing a depletion type transistor as the clip transistor 131 at the time of manufacture.
Here, the potential of the first signal output line is determined by the source follower circuit configured by the amplification transistor 115 in the pixel circuit 110 and the load transistor 101 in the load circuit, and is the same potential as GND. Do not mean.

As can be seen from FIG. 13, when the clip transistor 131 is DC-driven, there is a path through which current flows from GND to CLIPDC.
<Operation 2>
The operation when the clip transistor 131 is pulse-driven will be described below.

FIG. 14A is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing of FIG. 12D when the luminance is high.
FIG. 14B is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing shown in FIG.
Here, in FIGS. 14A and 14B, the upper half shows an outline of the circuit, and the lower half shows the state of potential for each region corresponding to each position of the upper half circuit.

Below, the state of the potential for each region in the signal processing circuit 120 when the luminance is high will be described with reference to FIGS.
(1) At the timing shown in FIG. 12 (d), as shown in FIG. 14 (a), the charge on the GND exceeds the potential of the load transistor 101 and moves to the first signal output line, and the sampling transistor 121 is turned on. Since the clip transistor 131 is OFF, the charge sequentially moves to the second signal output line beyond the potential of each transistor.

Here, the potential of the first signal output line is determined by the source follower circuit configured by the amplification transistor 115 in the pixel circuit 110 and the load transistor 101 in the load circuit, and is the same potential as GND. Do not mean.
(2) At the timing shown in FIG. 12 (e), as shown in FIG. 14 (b), the GND charge exceeds the potential of the load transistor 101 and moves to the first signal output line, and the sampling transistor 121 is turned OFF. Since the clip transistor 131 is ON, the charge moves beyond the potential of each transistor on the right side of the sampling transistor 121. This charge movement occurs when the voltage of each signal line changes to a voltage determined by the potential of each transistor. Stop. Here, the voltage of the second signal output line can be determined by the pulse voltage of the clip transistor 131.

Here, as can be seen from FIGS. 14A and 14B, when the clip transistor 131 is pulse-driven, there is no path through which current flows from GND to CLIPDC, so that the clip transistor 131 is DC-driven. And has the advantage of low power consumption.
<Summary>
As described above, in the second embodiment of the present invention, since the clip transistor 131 is further added to the imaging device of the first embodiment, the voltage of the second signal output line is set to the input dynamic range of the output amplifier in the subsequent stage. It can be set so that it does not change until the voltage exceeds it.
(Embodiment 3)
<Configuration>
FIG. 15 is a diagram schematically illustrating a circuit of the imaging apparatus according to the third embodiment.

As shown in FIG. 15, the third embodiment includes a pixel circuit 140 instead of the pixel circuit 110 of the first embodiment, and a signal processing circuit 150 instead of the signal processing circuit 120 of the first embodiment.
The pixel circuit 140 outputs a reset voltage obtained by amplifying the voltage at the time of initialization and a read voltage obtained by amplifying the voltage at the time of reading to the first signal output line. A light receiving element 141 such as a photodiode that generates and accumulates and outputs the accumulated charge as a voltage signal, and charges accumulated in the light receiving element 141 are swept out so that the voltage here becomes the initial voltage (here, VDD). A reset transistor 142 that resets to a voltage, an amplifying transistor 143 that outputs a voltage that changes in accordance with a voltage due to charges accumulated in the light receiving element 141, and an amplifying transistor 143 that receives a line select signal from the row selection encoder 3. And a line select transistor 144 for outputting the output to the first signal output line.

Here, the pixel circuit 140 has a reset pulse (initialization signal: RESET) and a line selection pulse (row selection signal: LSEL), and the signal processing circuit 120 has a sampling pulse (SP) and a clamp pulse. (CP) is supplied at a determined timing, and the transistors corresponding to these control pulses are opened and closed (OFF / ON).
The signal processing circuit 150 includes the same components as those of the signal processing circuit 120 according to the first embodiment. The difference is that the clamp transistor 124 is different from the second signal output line and the reference voltage terminal in the signal processing circuit 120 according to the first embodiment. The signal processing circuit 150 is only connected in series between the second signal output line and the clamping voltage terminal VCL in the signal processing circuit 150.

Here, the clamping voltage terminal VCL is somewhat higher than the potential VφSKIP indicating the potential of the bypass transistor 125 so that the potential of the second signal output line does not exceed the potential of the bypass transistor 125 when the clamp transistor 124 is turned on. It is a high potential, and VCL = VφSKIP + 0.1V is desirable.
Further, as a method of setting the potential of VCL, for example, a depletion type transistor may be built as the clamp transistor 124 at the time of manufacturing, or a bias voltage is applied to the gate of the clamp transistor 124 by the voltage supply means at a constant time or at a necessary timing (FIG. C to d, etc.) may be supplied.

For example, the bias voltage may be output to the gate of the clamp transistor 124 and the pulse voltage may be output during a period in which the read voltage is read from the pixel circuit 140.
FIG. 16 is a diagram illustrating the timing of each control pulse in the imaging apparatus according to the third embodiment.
By giving each control pulse at the timing as shown in FIG. 16, the clamp transistor 124 is turned on while the line select transistor 116 is turned on, and the second voltage is output while the read voltage is output to the first signal output line. The signal output line is set as a reference voltage (a in FIG. 16). When the read voltage is within a predetermined range, the difference between the read voltage and the reference voltage is held in the clamp capacitor 122, and then the clamp transistor 124 is turned on. In the OFF state (b in FIG. 16), a reset voltage is output to the first signal output line (c in FIG. 16), and the voltage of the second signal output line is changed from the reference voltage by an amount corresponding to the difference between the reset voltage and the read voltage. (D in FIG. 16), this can be output as luminance information, and when the lead voltage is not within a predetermined range, When the register 125 conducts between the terminals, the difference between the first signal output line and the second signal output line disappears, and the charge is not held in the clamp capacitor 122. Thereafter, the voltage of the second signal output line is reset. It is replaced with voltage, and this can be output as luminance information.

Here, as a method of setting a voltage within a predetermined range, for example, a depletion type transistor may be built as the bypass transistor 125 at the time of manufacture, or a bias voltage is always applied to the gate of the bypass transistor 125 by the voltage supply means or at a necessary timing. (C to d in FIG. 16) may be supplied.
For example, a bias voltage may be output to the gate of the bypass transistor 125 and a pulse may be output during a period in which the read voltage is read from the pixel circuit 110.

<Operation>
FIGS. 17A to 17D are diagrams illustrating potential states for each region in the pixel circuit 140 at each normal timing.
Here, FIGS. 17A to 17D correspond to the timings of FIGS. 16A to 16D, respectively.

FIG. 18A is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing of FIG. 16A at the normal time.
FIG. 18B is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing illustrated in FIG.
FIG. 18C is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing illustrated in FIG.

Here, in each figure of FIG. 17 and FIG. 18, the upper half shows the outline of the circuit, and the lower half shows the state of potential for each region corresponding to each position of the upper half circuit.
The potential transition for each region in the pixel circuit 140 and the potential transition for each region in the signal processing circuit 150 in the normal state will be described below with reference to FIGS. 17 (a) to 17 (d) and FIG. 18 (a). It demonstrates along-(c).

  (1) At the timing of FIG. 16A, the reset transistor 142 is OFF, and as shown in FIG. 17A, the voltage of the light receiving element 141 changes due to the charge generated in the light receiving element 141, and the line select transistor Since 144 is ON, the voltage after this change is amplified by the amplifying transistor 143, the voltage of the first signal output line is changed to the read voltage, and the clamp transistor 124 is ON, so that as shown in FIG. In addition, the voltage of the second signal output line is reset to VCL.

Here, the potential VφSKIP indicating the potential of the bypass transistor 125 is about 0.7 V, the clamping voltage terminal VCL is about 0.8 V, and the read voltage output to the first signal output line is about 1.5 V, for example.
(2) At the timing of FIG. 16B, the clamp transistor 124 is turned from ON to OFF, and the difference between the read voltage and VCL is held in the clamp capacitor 122 as shown in FIG.

Here, for example, a difference equivalent to about 0.7 V between the read voltage of about 1.5 V and the VCL of about 0.8 V is held in the clamp capacitor 122.
(3) Since the reset transistor 142 is turned on at the timing of FIG. 16C, the charge generated in the light receiving element 141 moves to the VDD terminal as shown in FIG.

(4) At the timing of FIG. 16D, the reset transistor 142 is turned from ON to OFF, and as shown in FIG. 17D, the voltage of the light receiving element 141 is reset to VDD.
Here, the voltage of the light receiving element 141 changes to VDD, and the voltage after this change is amplified by the amplifying transistor 115, so that the voltage of the first signal output line changes to the reset voltage, and the read voltage, VCL, 16 is held in the clamp capacitor 122, the voltage of the second signal output line becomes “VCL + corresponding to the change in the voltage of the first signal output line” as shown in FIG. Is output as luminance information (when the voltage change of the first signal output line is SIG, the clamp capacitor 122 is Ccp, and the sampling capacitor 123 is Csp: the voltage of the second signal output line is VCL + SIG × Ccp / (Ccp + Csp) Become).

Here, for example, when the reset voltage Vreset output to the first signal output line is about 2.0 V and Ccp = Csp, the voltage Vnrm of the second signal output line is Vnrm = VCL + SIG × Ccp / (Ccp + Csp) = 0. .8+ (2.0−1.5) × (1/2) = 1.05 (V).
FIGS. 19A to 19D are diagrams showing potential states for each region in the pixel circuit 140 at each timing when the luminance is high.

Here, each of FIGS. 19A to 19D corresponds to the timings of FIGS. 16A to 16D, respectively.
FIG. 20A is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing of FIG. 16A when the luminance is high.
FIG. 20B is a diagram showing a potential state of each region in the signal processing circuit 150 at the timing of FIG.

FIG. 20C is a diagram illustrating a potential state of each region in the signal processing circuit 150 at the timing of FIG.
Here, in each figure of FIG. 19 and FIG. 20, the upper half shows the outline of the circuit, and the lower half shows the state of potential for each region corresponding to each position of the upper half circuit.
The potential transition for each region in the pixel circuit 140 and the potential transition for each region in the signal processing circuit 150 at high luminance will be described below with reference to FIGS. 19 (a) to 19 (d) and FIG. ) To (c).

  (1) At the timing of FIG. 16A, the reset transistor 142 is OFF, and as shown in FIG. 19A, the voltage of the light receiving element 141 changes due to the charge generated in the light receiving element 141, and the line select transistor Since 144 is ON, the voltage after the change is amplified by the amplifying transistor 143, the voltage of the first signal output line is changed to a read voltage, and since the clamp transistor 124 is ON, the voltage of the second signal output line is Reset to VCL.

Here, the potential VφSKIP indicating the potential of the bypass transistor 125 is about 0.7 V, the clamping voltage terminal VCL is about 0.8 V, and the read voltage output to the first signal output line is about 0.5 V, for example.
(2) At the timing of FIG. 16 (b), the clamp transistor 124 is turned from ON to OFF. Here, in a normal time, the difference between the read voltage and the reference voltage is held in the clamp capacitor 122. At the time of luminance, as shown in FIG. 20B, the potential of the read voltage exceeds the potential of the bypass transistor 125, and the bypass transistor 125 conducts between the terminals, so that no charge is held in the clamp capacitor 122.

Here, for example, since the read voltage of about 0.5 V exceeds VφSKIP of about 0.7 V, the voltages of the first signal output line and the second signal output line are both about 0.5 V, and the charge is held in the clamp capacitor 122. Not.
(3) Since the reset transistor 142 is turned on at the timing shown in FIG. 16C, the charge generated in the light receiving element 141 moves to the VDD terminal as shown in FIG. 19C.

(4) At the timing of FIG. 16D, the reset transistor 142 is turned from ON to OFF, but as shown in FIG. 19D, the light receiving element 141 receives VDD from the high-intensity light incident. A slightly lower voltage is output.
Here, since no electric charge is held in the clamp capacitor 122, the voltage of the second signal output line becomes a voltage corresponding to the reset voltage as shown in FIG. This voltage is output as luminance information.

  Specifically, while the voltage of the first signal output line exceeds the potential of the bypass transistor, the voltage of the first signal output line = the voltage of the second signal output line. Becomes a voltage higher than the potential of the bypass transistor, the voltage of the second signal output line changes with a constant ratio determined by the sampling capacitor Csp and the clamp capacitor Ccp with respect to the voltage fluctuation of the first signal output line. The voltage Vov of the second signal output line is expressed by the following equation.

Vov = VφSKIP + (Vreset−VφSKIP)
× Ccp / (Ccp + Csp)
Here, for example, when the reset voltage Vreset output to the first signal output line is about 1.9 V and Ccp = Csp, the voltage Vov of the second signal output line is Vov = VφSKIP + (Vreset−VφSKIP) × Ccp / (Ccp + Csp) = 0.7 + (1.9−0.7) × (1/2) = 1.3 (V).

According to the above example, Vov> Vnrm holds.
However, when VCL >> VφSKIP, Vov> Vnrm does not hold, so the difference between VCL and VφSKIP is limited to the range where Vov> Vnrm holds as described above. For example, VCL = about 0.8 V, VφSKIP = about It is 0.7V, and the difference is suitably about 0.1V.

<Summary>
The characteristics of the output voltage in the imaging apparatus according to the third embodiment of the present invention are the same as those in the first embodiment. When the read voltage exceeds a predetermined voltage, the voltage becomes high and the image becomes dark. In other words, the same effect as in the first embodiment can be obtained.
(Modification 1)
FIGS. 21A and 21B are diagrams showing the relationship between the potential of the reset transistor and the potential of the bypass transistor.

Hereinafter, the relationship between the potential VφR indicating the potential of the reset transistor and the potential VφSKIP indicating the potential of the bypass transistor will be described with reference to FIGS.
Here, the amplification factor of the amplifying transistor is α, and the threshold voltage is Vt.
As shown in FIG. 21A, when VφSKIP is set below the minimum potential “Vmin = (VφR−Vt) × α” of the first signal output line determined by VφR (VφSKIP / α + Vt ≦ VφR), The saturation signal component is “Vsat = VDD−VφR”, and a substantial saturation output potential can be secured to the maximum. However, since the bypass transistor is not turned on at high luminance, it does not function as a bypass transistor.

  As shown in FIG. 21B, when VφSKIP is set higher than the minimum potential “Vmin = (VφR−Vt) × α” of the first signal output line determined by VφR, VφSKIP / α + Vt> VφR) The saturation signal becomes “Vsat = VDD− (VφSKIP / α + Vt)”, and functions as a bypass transistor if the difference between VφSKIP and Vmin is larger than a certain level. However, the larger this difference is, the lower the substantial saturation output potential is. .

Here, the difference between VφSKIP and Vmin is preferably about 0.1V.
The bypass transistor and the reset transistor are produced in the same process, and a bias voltage is supplied to the gate of the bypass transistor. Here, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential depends on the bias voltage. May be given.

The reset transistor is produced by a predetermined implantation, and the bypass transistor is produced through an additional implantation in addition to the predetermined implantation. Here, the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential is May be given by additional injection.
<Summary>
As described above, according to Modification 1 of the present invention, a substantial saturation output voltage is sufficiently ensured and functions as a bypass transistor, so that the effect can be expected.
(Modification 2)
The imaging apparatus has a vertical blanking period in which luminance information for a predetermined number of pixels is not output from the imaging unit for each frame.

When the vertical blanking period is driven in the same manner as in the normal period, the load circuit causes the potential of the first signal output line to be 0 V and an excessive saturation output signal is output, so the input dynamic range of the output amplifier in the subsequent stage However, there is a problem that the gain of a minute signal cannot be sufficiently increased.
Therefore, in order to solve such a problem, the second modification of the present invention provides an imaging apparatus, an imaging method, and the like that do not output a saturated output signal in the vertical blanking period.

FIG. 22 is a diagram illustrating the timing of sampling pulses in the second modification.
Here, the sampling pulse shown in FIG. 22 shows an example of being output to the same imaging apparatus as in the first embodiment, and is output by the sampling transistor control unit included in the column selection encoder 4.
As shown in FIG. 22, in the vertical blanking period, since the sampling transistor control unit does not output a sampling pulse, the sampling transistor 121 becomes non-conductive, and no charge is held in the clamp capacitor 122, resulting in a low level. Luminance information indicating the luminance is output.

<Summary>
As described above, according to the second modification of the present invention, since a saturated output signal is not output during the vertical blanking period, the input dynamic range of the output amplifier at the subsequent stage is not restricted.
(Modification 3)
Modification 3 of the present invention provides an imaging apparatus that does not output a saturated output signal in the vertical blanking period, an imaging method, and the like in order to solve the same problem as Modification 2.

FIG. 23 is a diagram illustrating the control timing of the load transistor in the third modification.
Here, the control of the gate voltage of the load transistor shown in FIG. 23 is an example performed for the same image pickup apparatus as that in the first embodiment, and is performed by the load transistor control unit included in the column selection encoder 4. Shall be.
As shown in FIG. 23, in the vertical blanking period, the load transistor control unit does not apply a bias voltage to the load transistor, so that the load transistor 101 becomes non-conductive and no charge is held in the clamp capacitor 122. As a result, luminance information indicating low luminance is output.

<Summary>
As described above, according to the third modification of the present invention, since a saturated output signal is not output in the vertical blanking period, the input dynamic range of the output amplifier at the subsequent stage is not restricted.
Note that each circuit used in the description of the present invention is merely an example, and may be another circuit or the like having a similar function.

  Further, instead of each signal processing circuit, the reset voltage and the read voltage may be separately measured, and based on these measurement results, the same processing as each signal processing circuit may be realized by a general-purpose processor. Also, it operates normally with a conventional signal processing circuit, and a general-purpose processor determines that the brightness is high only when the read voltage is not within a predetermined range, and the output signal at this time is It may be replaced with luminance information indicating.

In addition, in order to set each bias voltage supplied by the voltage supply means to each gate such as a clamp transistor and a bypass transistor to an appropriate value for each imaging device, the voltage supply means internally sets each bias voltage. A bias voltage setting circuit that can be set from the outside and can store the set value may be included.
In this bias voltage setting circuit, for each transistor to which a bias voltage is to be supplied, a plurality of wirings such as polysilicon that can be cut by applying a predetermined voltage to a specific terminal from the outside are connected in parallel. Each is equipped with an element that can change the voltage, such as the same or different resistance, while monitoring the output data so that the potential of the connected transistor becomes the optimum value at the final stage of the manufacturing process. Cut any of the plurality of wires. For example, by bypassing any of the plurality of wirings while monitoring the voltage of the second signal output line so that the difference between the potential indicating the potential of the bypass transistor and the saturation signal output potential becomes an optimum value. Sets the transistor bias voltage.

In each embodiment and each modification of the present invention, the case where the signal charge is an electron has been described as an example. However, the signal charge can be realized as a hole. When the signal charge is a hole, the signal polarity is reversed and the potential relationship is only reversed as compared with the case where the signal charge is an electron.
In each embodiment and each modification of the present invention, a MOS type amplification transistor has been described as an example. However, an imaging apparatus that requires an FPN removal circuit such as CMD, BASIS, or SIT can also be realized. is there.

The present invention can be applied to imaging devices such as home video cameras and digital still cameras. According to the present invention, there is provided a solid-state imaging device that can reliably solve the problem that an image is blacked out when strong light is incident, and can reliably eliminate the adverse effects caused by a voltage change at reset. This can contribute to the improvement of the image quality of the imaging device.
Further, it can be applied not only to home use but also to any imaging device.

FIG. 1 is a diagram showing a schematic configuration of an imaging apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram schematically illustrating a circuit of the imaging apparatus according to the first embodiment. FIG. 3 is a diagram illustrating the timing of each control pulse in the imaging apparatus according to the first embodiment. 4A to 4D are diagrams illustrating potential states for each region in the pixel circuit 110 at each normal timing. FIG. 5A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing shown in FIG.

FIG. 5B is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the normal time.
FIG. 5C is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG.
FIGS. 6A to 6D are diagrams showing potential states for each region in the pixel circuit 110 at each timing when the luminance is high. FIG. 7 is a diagram illustrating a potential state for each region in the pixel circuit 110 at each timing when the luminance is high. FIG. 8A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B at the time of the first high luminance.

FIG. 8B is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the time of the first high luminance.
FIG. 8C is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3D at the time of the first high luminance.
FIG. 9A is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B at the time of the second high luminance.

FIG. 9B is a diagram showing a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3B ′ at the second high luminance.
FIG. 9C is a diagram illustrating a potential state for each region in the signal processing circuit 120 at the timing of FIG. 3D at the time of the second high luminance.
FIG. 10A is a diagram illustrating the voltage characteristics of the first signal output line at the time of resetting.

FIG. 10B is a diagram illustrating a voltage characteristic of the first signal output line at the time of reading.
FIG. 10C is a diagram illustrating the output voltage characteristics of a conventional imaging device that does not take any measures against dark images or blackened images. -Corresponds to FIG.
FIG. 10D is a diagram showing the output voltage characteristics in the imaging apparatus according to Embodiment 1 of the present invention.
FIG. 11 is a diagram schematically illustrating a circuit of the imaging apparatus according to the second embodiment. FIG. 12 is a diagram illustrating the timing of each control pulse including a clip pulse when the clip transistor 131 is pulse-driven in the imaging apparatus according to the second embodiment. FIG. 13 is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing shown in FIG. FIG. 14A is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing of FIG. 12D when the luminance is high.

FIG. 14B is a diagram showing a potential state for each region in the signal processing circuit 130 at the timing shown in FIG.
FIG. 15 is a diagram schematically illustrating a circuit of the imaging apparatus according to the third embodiment. FIG. 16 is a diagram illustrating the timing of each control pulse in the imaging apparatus according to the third embodiment. FIGS. 17A to 17D are diagrams illustrating potential states for each region in the pixel circuit 140 at each normal timing. FIG. 18A is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing of FIG. 16A at the normal time.

FIG. 18B is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing illustrated in FIG.
FIG. 18C is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing illustrated in FIG.
FIGS. 19A to 19D are diagrams showing potential states for each region in the pixel circuit 140 at each timing when the luminance is high.

FIG. 20A is a diagram illustrating a potential state for each region in the signal processing circuit 150 at the timing of FIG. 16A when the luminance is high.
FIG. 20B is a diagram showing a potential state of each region in the signal processing circuit 150 at the timing of FIG.

FIG. 20C is a diagram illustrating a potential state of each region in the signal processing circuit 150 at the timing of FIG.
FIGS. 21A and 21B are diagrams showing the relationship between the potential of the reset transistor and the potential of the bypass transistor. FIG. 22 is a diagram illustrating the timing of sampling pulses in the second modification. FIG. 23 is a diagram illustrating the control timing of the load transistor in the third modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Load circuit 3 Row selection encoder 4 Column selection encoder 5 Signal processing part 6 Output circuit 100 Load circuit 101 Load transistor 110 Pixel circuit 111 Light receiving element 112 Capacitor 113 Reset transistor 114 Read transistor 115 Amplification transistor 116 Line select transistor 117 Charge Detection Unit 120 Signal Processing Circuit 121 Sampling Transistor 122 Clamp Capacitor 123 Sampling Capacitor 124 Clamp Transistor 125 Bypass Transistor 130 Signal Processing Circuit 131 Clip Transistor 140 Pixel Circuit 141 Light Receiving Element 142 Reset Transistor 143 Amplifying Transistor 144 Line Select Transistor 150 Signal Processing circuit

Claims (15)

The unit cell that outputs the reset voltage corresponding to the output voltage of the photoelectric conversion unit when the photoelectric conversion unit is the initial voltage and the read voltage corresponding to the output voltage of the photoelectric conversion unit according to the amount of received light is one-dimensional, Or a plurality of imaging means arranged two-dimensionally;
An output device that outputs voltage information corresponding to the amount of received light for each unit cell,
The output means includes
A signal output line connected to the imaging means for receiving the read voltage and the reset voltage;
A clamp capacitor connected to the signal output line;
The gate potential to a fixed potential, when the read voltage is a voltage of a predetermined range, the non-conductive state between the terminals of the clamp capacitance, between the corresponding pin when the read voltage is not a voltage of a predetermined range An imaging device comprising: a first transistor that is in a conductive state. The case where the voltage is within the predetermined range is a case where the potential of the signal output line is higher than the potential indicating the potential of the first transistor, and the case where the voltage is not within the predetermined range. The imaging apparatus according to claim 1, wherein the potential of the output line is equal to or lower than the potential indicating the potential of the first transistor. The output means further includes:
The imaging apparatus according to claim 1, further comprising voltage supply means for supplying a bias voltage to the gate of the first transistor. The imaging device according to claim 1, wherein the first transistor is a depletion type transistor. Each unit cell in the imaging means is
A light receiving element that generates a charge corresponding to the amount of light received;
A charge detector that holds the charge generated by the light receiving element and outputs it as a voltage signal;
A reset transistor connected between a reference voltage terminal for reset and the charge detection unit, wherein the charge detection unit is reset to a reference voltage when a gate voltage is applied and is in a conductive state;
An amplifying transistor that is connected between an amplifying reference voltage terminal and the signal output line, applies a voltage signal converted by the charge detector to the gate, amplifies the voltage signal, and outputs the amplified voltage signal to the signal output line Including
The potential indicating the potential of the first transistor is higher than a saturation signal output potential that is an output of the amplifying transistor included in the unit cell depending on the potential of the reset transistor when the reset transistor is in a non-conductive state. The imaging apparatus according to claim 1, wherein the imaging apparatus is higher by a predetermined difference. The imaging apparatus according to claim 5, wherein a difference between a potential indicating the potential of the first transistor and the saturation signal output potential is approximately 0.1V. The output means further includes:
Voltage supply means for supplying a bias voltage to the gate of the first transistor;
The imaging device according to claim 5, wherein a difference between a potential indicating the potential of the first transistor and the saturation signal output potential is given by the bias voltage. The imaging device according to claim 5, wherein the first transistor and the reset transistor are produced in the same process. The voltage supply means includes
The image pickup apparatus according to claim 7, further comprising a bias voltage setting circuit capable of setting an appropriate bias voltage that is different for each image pickup apparatus from outside. The reset transistor is produced by a predetermined implantation implantation,
The first transistor is produced through an additional implantation in addition to the predetermined implantation implantation,
The imaging apparatus according to claim 5, wherein the difference between the potential indicating the potential of the first transistor and the saturation signal output potential is given by the additional injection. The unit cell that outputs the reset voltage corresponding to the output voltage of the photoelectric conversion unit when the photoelectric conversion unit is the initial voltage and the read voltage corresponding to the output voltage of the photoelectric conversion unit according to the amount of received light is one-dimensional, or A plurality of imaging means arranged in a two-dimensional manner;
An output device that outputs voltage information corresponding to the amount of received light for each unit cell,
The output means includes
A first signal output line connected to the imaging means and receiving the read voltage and the reset voltage;
A second signal output line for outputting the voltage information;
A clamp capacitor connected in series between the first signal output line and the second signal output line;
A first transistor connected in parallel with the clamp capacitor, having a source electrode connected to the first signal output line and a drain electrode connected to the second signal output line, the gate potential being a fixed potential; When the read voltage is in a predetermined range, the transistor 1 is in a non-conductive state between the terminals of the clamp capacitor, and when the read voltage is not in the predetermined range, the transistor is connected between the terminals. you characterized in that the conductive state imaging device. The output means further includes:
A sampling capacitor connected in series between the second signal output line and a predetermined voltage terminal;
A clamp transistor connected in series between the second signal output line and a reference voltage terminal;
The reset signal is output to the first signal output line with the clamp transistor turned on and the second signal output line set to a reference voltage, and then the first signal output with the clamp transistor turned off. Control means for outputting the lead voltage to a wire,
When a reset voltage that is a voltage within the predetermined range is output to the first signal output line with the clamp transistor turned on and the second signal output line set to a reference voltage, the reference voltage, the reset voltage, When a read voltage that is a voltage within the predetermined range is output to the first signal output line in a state where the clamp transistor is turned off, the voltage corresponding to the difference of the second is output to the second signal output line. The voltage of the signal output line changes from the reference voltage by the voltage held in the clamp capacitor, and as a result, voltage information indicating the difference between the reset voltage and the read voltage is output.
When a read voltage that is not in the predetermined range is output to the first signal output line with the clamp transistor turned off, the first transistor brings the terminals of the clamp capacitor into a conductive state. the voltage of the second signal output line is replaced by the read voltage, the imaging apparatus according to claim 11, characterized in that the voltage information is outputted indicating the person said read voltage. The output means further includes:
A sampling capacitor connected in series between the second signal output line and a predetermined voltage terminal;
A clamp transistor connected in series between the second signal output line and a reference voltage terminal;
Control means for turning on the clamp transistor with the read voltage output to the first signal output line, and then turning off the clamp transistor to output the reset voltage to the first signal output line; Including
When the clamp transistor is turned on in a state where a read voltage that is a voltage in the predetermined range is output to the first signal output line, a voltage corresponding to a difference between the reference voltage and the read voltage is held in the clamp capacitor. Thereafter, when a reset voltage, which is a voltage within the predetermined range, is output to the first signal output line with the clamp transistor turned off, the voltage of the second signal output line is As a result, voltage information indicating a difference between the reset voltage and the read voltage is output.
In a state where a read voltage that is not within the predetermined range is output to the first signal output line, voltage information indicating the read voltage is output when the first transistor conducts between the terminals of the clamp capacitor. The imaging apparatus according to claim 11, wherein: A clip transistor for outputting a voltage matching the input dynamic range of a subsequent analog circuit as voltage information indicating the read voltage when the read voltage of the signal output line is not in a predetermined range; The imaging device according to claim 1. A unit cell that outputs a reset voltage corresponding to the output voltage of the photoelectric conversion unit when the photoelectric conversion unit is the initial voltage and a read voltage corresponding to the output voltage of the photoelectric conversion unit according to the amount of received light is one-dimensional. Or a plurality of two-dimensionally arranged imaging regions;
Connected to said image pickup means, and a signal output line for receiving said read voltage and the reset voltage, a clamp capacitor which is connected to the signal output line, which is connected in parallel with the clamp capacitance, Gate potential and the fixed potential An imaging method in an imaging device including the first transistor,
A determination step for determining, for each unit cell, whether or not the read voltage is in a predetermined range based on a potential indicating the potential of the first transistor ;
A step of setting a non-conducting state between the terminals of the clamp capacitor when it is determined by the determination step that the voltage is within a predetermined range;
An imaging method comprising the step of bringing the terminals into a conductive state when the determination step determines that the voltage is not within a predetermined range .

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