JP5965076B2 - 訂正不能メモリエラー処理方法及びその可読媒体 - Google Patents
訂正不能メモリエラー処理方法及びその可読媒体 Download PDFInfo
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- 238000003672 processing method Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims description 142
- 230000008569 process Effects 0.000 claims description 121
- 239000002574 poison Substances 0.000 claims description 94
- 231100000614 poison Toxicity 0.000 claims description 94
- 238000010926 purge Methods 0.000 claims description 23
- 238000001514 detection method Methods 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000011084 recovery Methods 0.000 description 11
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- 230000002950 deficient Effects 0.000 description 6
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
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- Techniques For Improving Reliability Of Storages (AREA)
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Description
Claims (13)
- 訂正不能メモリエラーの表示をプロセッサから受信するステップと、
前記訂正不能メモリエラーの通知をオペレーティングシステムに送信するステップと、
初期化するメモリアドレスの範囲を前記オペレーティングシステムから受信するステップであって、該アドレスの範囲は、前記訂正不能メモリエラーのアドレスを含んでいるステップと
を含み、
少なくとも前記メモリアドレスの範囲について訂正不能メモリエラーの検出を無効化するステップと、
前記メモリアドレスの範囲を初期化するステップと、
前記メモリアドレスの範囲を検査するステップと、
訂正不能メモリエラーの検出を再有効化するステップと
を更に含む、方法。 - 前記オペレーティングシステムが前記訂正不能メモリエラーから回復したか否かを示す表示を前記オペレーティングシステムから受信するステップと、
前記訂正不能メモリエラーをエラーログにログ記録するステップであって、該ログ記録することは、前記オペレーティングシステムが前記エラーから回復したか否かを含んでいるステップと
を更に含む、請求項1に記載の方法。 - 前記訂正不能メモリエラーの前記表示は、前記プロセッサがポイズンを消費することによって引き起こされたプロセッサマシンチェック例外である、請求項1に記載の方法。
- 前記メモリアドレスの範囲の前記検査の結果に基づいて、初期化に成功したメモリアドレスを前記オペレーティングシステムに通知するステップを更に含む、請求項1に記載の方法。
- 前記メモリアドレスの範囲の前記検査の結果に基づいて、初期化に成功しなかった前記メモリアドレスの範囲内にあるメモリアドレスを前記オペレーティングシステムに通知するステップを更に含む、請求項1に記載の方法。
- 訂正不能メモリエラーの表示を、プロセッサ上で実行されているファームウェアから受信するステップと、
アドレス範囲が前記訂正不能メモリエラーを含むプロセスを回復させることができるか否かを判断するステップと、
初期化されるメモリアドレスの範囲を前記ファームウェアに送信するステップであって、該範囲は、前記訂正不能メモリエラーのアドレスを含んでいるステップと
を含む、方法。 - 前記プロセスを回復させることができる場合、前記方法は前記プロセスをパージするステップを更に含む、請求項6に記載の方法。
- 初期化に成功した前記メモリアドレスの範囲の表示を前記ファームウェアから受信するステップと、
初期化に成功したメモリアドレスを、使用のために利用可能であるとしてマーキングするステップと、
初期化に成功しなかったメモリアドレスを利用不能であるとしてマーキングするステップと
を更に含む、請求項7に記載の方法。 - 前記プロセスを回復させることができない場合、前記方法は、
内容がログにダンプされるメモリアドレスの範囲を前記ファームウェアに送信するステップと、
訂正不能エラーを含む前記メモリアドレスの範囲内にあるメモリロケーションの表示を前記ファームウェアから受信するステップと、
訂正不能メモリエラーを含まない前記メモリアドレスの範囲内にあるメモリロケーションのメモリアドレスを前記ログにダンプするステップと
を更に含む、請求項6に記載の方法。 - 前記訂正不能メモリエラーの前記表示は、前記プロセッサがポイズンを消費することによって引き起こされるプロセッサマシンチェック例外である、請求項6に記載の方法。
- 非一時的プロセッサ可読媒体であって、プロセッサによって実行されると、該プロセッサに、
メモリロケーションにアクセスさせ、
前記メモリロケーションがポイズンを含むと判断させ、
ポイズンの消費をオペレーティングシステムへ通知させ、
前記メモリロケーションに関連付けられたプロセスによって占有されたメモリアドレスの範囲を前記オペレーティングシステムから受信させ、
訂正不能メモリエラーを含む前記メモリアドレスの範囲内にあるメモリアドレスを判断させる
一組のプロセッサ実行可能命令を含み、
前記プロセッサに、
ポイズン監視を無効化させ、
前記メモリアドレスの範囲内にあるメモリアドレスを初期化させ、
前記メモリアドレスの範囲内にある前記メモリアドレスを検査して、初期化の成功を判断させ、
初期化に成功した前記メモリアドレスの範囲を前記オペレーティングシステムへ送信させる
命令を更に含む、非一時的プロセッサ可読媒体。 - 前記プロセッサに、
ポイズン監視を無効化させ、
前記メモリアドレスの範囲内にあるメモリアドレスを検査して、どのアドレスが訂正不能エラーを含むのかを判断させ、
訂正不能エラーを含む前記メモリアドレスの範囲を前記オペレーティングシステムへ送信させる、
命令を更に含む、請求項11に記載の媒体。 - 前記プロセッサは、マシンチェック例外を引き起こすポイズンの消費によって該ポイズンを検出する、請求項11に記載の媒体。
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PCT/US2012/057107 WO2014051550A1 (en) | 2012-09-25 | 2012-09-25 | Notification of address range including non-correctable error |
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US (1) | US9804917B2 (ja) |
EP (1) | EP2901281B1 (ja) |
JP (1) | JP5965076B2 (ja) |
CN (1) | CN104685474B (ja) |
TW (1) | TWI543179B (ja) |
WO (1) | WO2014051550A1 (ja) |
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US9378829B2 (en) * | 2013-02-07 | 2016-06-28 | Cypress Semiconductor Corporation | Non-volatile memory device with an EPLI comparator |
US10261852B2 (en) * | 2013-05-31 | 2019-04-16 | Hewlett Packard Enterprise Development Lp | Memory error determination |
US9323607B2 (en) * | 2014-04-29 | 2016-04-26 | Seagate Technology Llc | Data recovery once ECC fails to correct the data |
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EP2901281A1 (en) | 2015-08-05 |
CN104685474A (zh) | 2015-06-03 |
US9804917B2 (en) | 2017-10-31 |
TWI543179B (zh) | 2016-07-21 |
US20150234702A1 (en) | 2015-08-20 |
TW201415476A (zh) | 2014-04-16 |
CN104685474B (zh) | 2018-04-20 |
EP2901281B1 (en) | 2017-11-01 |
JP2015529927A (ja) | 2015-10-08 |
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EP2901281A4 (en) | 2016-06-22 |
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