JP5964113B2 - Display drive device, display drive method, display device, electronic device, display drive program, and recording medium - Google Patents

Description

  The present invention relates to a display driving device that drives a display device that can be driven at a low frequency, and more particularly to a display driving device that is effective in reducing power consumption of the display device.

  In recent years, display devices such as FPD (Flat Panel Display) that can be reduced in size and weight have been improved in performance, and such display devices have been installed in various electronic devices. In particular, in portable electronic devices, reduction of power consumption is an issue, and development for reducing power consumption is underway.

  In general, the power consumed by the drive circuit accounts for a large proportion of the power consumed by the display device. Since the power consumption of the drive circuit is proportional to the drive frequency, it is necessary to reduce the drive frequency in order to reduce the power consumption. Alternatively, power consumption can be reduced by intermittently operating the drive circuit. For example, Patent Document 1 discloses controlling a liquid crystal module that operates in a scanning mode in which the liquid crystal module is scanned and a pause mode in which the scanning process is paused.

JP 2012-18271 A (published January 26, 2012)

  By the way, conventionally, in a liquid crystal display device, a liquid crystal panel using a thin film transistor (TFT) formed of CGS (Continuous Grain Silicon) or a-Si (amorphous Silicon) as a switching element in the liquid crystal panel has been mainstream. In a liquid crystal display device using such a liquid crystal panel, the liquid crystal is AC driven at a driving frequency of about 60 Hz.

  In such a liquid crystal display device, when the drive frequency is lowered in order to reduce power consumption, the leakage current through the liquid crystal layer and the switching element between the pixel electrode and the counter electrode in the liquid crystal panel causes the pixel electrode. The voltage drops. For this reason, the display luminance fluctuates due to the decrease in the driving frequency, and this fluctuation is observed as flicker, resulting in a decrease in display quality.

  On the other hand, a TFT formed of an oxide semiconductor such as IGZO (InGaZnOx) has higher on-state electron mobility and very excellent on characteristics than an α-TFT formed of a-Si. It has attracted attention because it has the characteristic of being. In a liquid crystal panel using a TFT formed of such an oxide semiconductor as a switching element, a transistor as a switching element can be reduced in size from the above characteristics of the TFT. Thereby, since leakage of the transistor is reduced, it is difficult for the charge held in the liquid crystal pixel to escape, and as a result, low frequency driving up to 1 Hz is possible. For this reason, even if the drive frequency is reduced to 1 Hz, the above-described disadvantage does not occur. Therefore, it can be expected that power consumption is reduced by driving the liquid crystal panel at a low frequency.

  In the driving method disclosed in Patent Document 1, when such a liquid crystal panel is used to display a still image, driving for refreshing can be performed at a low frequency, and consumption is not reduced without degrading display quality. Reduction of power can be realized. However, when the displayed image includes not only a moving image but also a still image, still images that do not need to be refreshed are refreshed at a uniform driving frequency (60 Hz) as in the case of moving images. Therefore, even when a liquid crystal panel capable of low frequency driving as described above is used, in the display of a still image portion, power consumption cannot be reduced as in the case of using a conventional liquid crystal panel.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display driving device capable of reducing power consumption when displaying an image including a portion without change. is there.

  The display driving device according to the present invention is a display driving device that drives a display unit that displays an image based on image data in accordance with a refresh rate. Image comparison means for comparing data in units of a predetermined number of pixel data, and determining a matching portion and a mismatching portion in both image data in units of lines, and specifying non-update of an image for the line of the matching portion and the line The refresh rate when displaying the image is set to be lower than the maximum refresh rate defined by the display unit, while the image refresh is specified for the line of the inconsistent portion and the refresh when the line is displayed Refresh rate setting means for setting the rate to the maximum, and the set refresh rate Based on Shureto is characterized in that it comprises a drive timing generating means for generating a driving timing.

  The display driving method according to the present invention is a display driving method for driving a display unit that displays an image based on image data in accordance with a refresh rate. An image comparison step of comparing data in units of a predetermined number of pixel data, and determining a matching portion and a mismatching portion in both image data in units of lines, and specifying non-update of an image for the line of the matching portion and the line The refresh rate when displaying the image is set to be lower than the maximum refresh rate defined by the display unit, while the image refresh is specified for the line of the inconsistent portion and the refresh when the line is displayed Refresh rate setting step to set the rate to the shortest and before the set Is characterized in that a driving timing generation step of generating a driving timing based on the refresh rate.

  In the above configuration, as a result of comparing two pieces of image data that are successively input in units of a predetermined number of pixel data by the image comparison means (image comparison step), the matching portion and the mismatching portion in both image data are lined. Judged in units. For the line for which the matching portion is determined, the refresh rate setting means (refresh rate setting means step) identifies non-update of the image, and the refresh rate when displaying the line is lower than the maximum refresh rate. Is set. On the other hand, for the line for which the inconsistent portion is determined, the refresh rate setting means (refresh rate setting means step) specifies the update of the image and sets the refresh rate when displaying the line to the maximum.

  For the line for which non-update of the image is specified, the drive timing is generated by the drive timing generation means (drive timing generation step) based on the set refresh rate (low refresh rate). On the other hand, the drive timing is generated based on the set refresh rate (high refresh rate) by the drive timing generation means (drive timing generation step) for the line for which the image update is specified.

  Since the drive timing is generated based on the refresh rate set in units of lines as described above, the line displayed on the display unit that is not updated such as a still image is driven at a low refresh rate. Therefore, even if the displayed image includes an updated portion such as a moving image, the driving is not performed uniformly at a high refresh rate. In a display portion that can be driven at a low frequency, driving can be performed at a low refresh rate. Therefore, the power consumption in the display driving device can be reduced by performing low frequency driving even partially.

  In the display driving device, the refresh rate setting means further includes the above when the non-update of the image is specified even if the image of a predetermined number of frames is displayed for the line where the non-update of the image is specified. It is preferable to set the refresh rate to a predetermined minimum value by repeatedly setting the refresh rate low.

  In the above configuration, when non-update of an image is specified, the refresh rate is lowered stepwise to the lowest refresh rate by the refresh rate setting means. Thereby, a sudden change in the refresh rate can be avoided. Therefore, the refresh rate can be reduced without reducing the image display quality.

  In the display drive device, it is preferable that the drive timing generation unit adjusts the drive timing of each line to the same vertical synchronization period while a plurality of frames of images are displayed.

  Thereby, the drive timing of each line is adjusted to the same vertical synchronization period, so that the drive period can be reduced. Therefore, it is possible to further reduce the power consumption of the display driving device.

  In the display driving apparatus, it is preferable that the refresh rate setting unit sets update or non-update of an image and sets the refresh rate in units of lines.

  As a result, at least driving at different refresh rates for each line is performed, so that power consumption can be finely reduced.

  In the display driving device, it is preferable that the refresh rate setting unit performs pixel-specific settings for specifying whether an image is updated or not and setting the refresh rate.

  As a result, the range that can be driven at a low refresh rate can be expanded as compared with processing in units of lines. Therefore, power consumption can be further reduced.

  In the display driving device, the image comparison unit includes a frame memory for storing one frame of image data to be input, image data read from the frame memory, and image data input subsequent to the image data. And a comparison circuit that determines a matching portion and a mismatching portion in both image data in units of lines.

  Accordingly, it is possible to easily perform matching determination of image data using a general image comparison technique.

  In the display driving device, it is preferable that the frame memory writes only image data of a line determined to be a mismatched portion by the comparison circuit.

  As a result, unnecessary writing is avoided, so that the writing operation of the frame memory can be performed efficiently, and the power consumption can be reduced as compared with the case where writing is always performed.

  A display device according to the present invention is a display device that includes a display unit that displays an image based on image data, and a display drive device that drives the display unit according to a refresh rate. Any one of the display driving devices is characterized.

  Thus, as described above, even if the displayed image includes an updated portion such as a moving image, the drive is not performed uniformly at a high refresh rate. In a display portion that can be driven at a low frequency, driving can be performed at a low refresh rate. Therefore, power consumption of the display device can be reduced.

  The display device according to the present invention is a liquid crystal display device.

  In particular, in the display device, the display unit includes a switching element that switches application of a voltage according to image data to the pixel electrode, and the switching element is a thin film transistor (IGZO-TFT) formed of IGZO. Is preferred.

  As described above, the display unit can be driven at a low frequency by providing the IGZO-TFT as a switching element, and thus can be driven at a low refresh rate of 1 Hz. Therefore, the power consumption can be further reduced.

  An electronic apparatus according to the present invention is an electronic apparatus including a display device that displays an image, wherein the display device is any one of the display devices described above.

  Thereby, the power consumption of the electronic device which mounts a display apparatus can be reduced.

  The display driving program of the present invention is a program for causing a computer to function as each means in the display driving device. The recording medium of the present invention is a computer-readable recording medium that records the display driving program. These display drive programs and recording media are also included in the technical scope of the present invention.

  The display driving device according to the present invention, which is configured as described above, has an effect that power consumption can be reduced when an image including a portion without change is displayed.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on this embodiment. It is a block diagram which shows the structure of the panel driver in the said liquid crystal display device. It is a circuit diagram which shows schematic structure of the liquid crystal panel in the said liquid crystal display device. It is a figure which shows the state by which all the pixel electrodes corresponding to one gate line were each connected to the corresponding source line in the drive of the said liquid crystal panel. It is a figure which shows the state in which the pixel electrode of R (red) was connected to the source driver through the switch in the drive of the said liquid crystal panel. It is a figure which shows the state in which the voltage was applied from the source driver to the R pixel electrode in the drive of the said liquid crystal panel. It is a figure which shows the state in which the voltage was applied to the pixel electrode of G (green) from the source driver via the switch in the drive of the said liquid crystal panel. It is a figure which shows the state in which the voltage was applied to the pixel electrode of B (blue) from the source driver through the switch in the drive of the said liquid crystal panel. FIG. 6 is a diagram illustrating a state in which all pixel electrodes corresponding to the next gate line are connected to corresponding source lines in driving the liquid crystal panel, and a voltage is applied to the R pixel electrode from a source driver through a switch. is there. FIG. 10 is a waveform diagram showing the operation of each part in the liquid crystal panel in each of the driving states shown in FIGS. 5 to 9 when driven by a normal driving method. It is a wave form diagram which shows operation | movement of each part in the said liquid crystal panel in each state of the drive shown to FIGS. 5-9 in the case of driving with the drive method using the said panel driver. It is a figure which shows the state by which the image was displayed by the drive by the said panel driver in the smart phone carrying the said liquid crystal display device. It is a flowchart which shows the procedure of the process in which the refresh controller of the said panel driver changes a refresh rate. (a) is a timing chart showing a state in which the drive timing is controlled by the timing generator of the panel driver, and (b) is a timing chart in which the drive timing is further adjusted within one frame period by the drive timing adjustment unit of the timing generator. It is a timing chart which shows a state. It is a figure which shows the state from which the timing from which a refresh rate is changed differs between lines. (A) is a figure which shows the state from which a drive timing differs between lines, (b) is a figure which shows the state in which a drive timing corresponds between lines. (A) is a block diagram showing a configuration of the drive timing adjustment unit, and (b) is a diagram showing a drive timing adjustment operation by the drive timing adjustment unit.

  An embodiment according to the present invention will be described below with reference to FIGS.

[Configuration of liquid crystal display device]
[Overall configuration of liquid crystal display device]
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 1 according to the present embodiment.

  As shown in FIG. 1, the liquid crystal display device 1 (display device) includes a host controller 2, a panel driver 3, and a liquid crystal panel 4.

  The host controller 2 temporarily stores the input image data and transfers it to the panel driver 3 as necessary. Therefore, the host controller 2 includes a CPU 21, a VRAM (Video RAM) 22, and a timing generator 23.

<Configuration of host controller>
The CPU 21 controls writing of image data input from the outside to the VRAM 22 and reading of the image data from the VRAM 22. Specifically, the CPU 21 controls writing and reading of image data by a user operation (for example, a screen switching operation) or an instruction from an application program (for example, an image change).

  The image data input to the host controller 2 is image data generated inside the electronic device in which the liquid crystal display device 1 is mounted, or image data input from the outside of the electronic device. The image data generated inside the electronic device is, for example, image data generated by an application program or broadcast image image data received by a TV tuner. The image data input from the outside of the electronic device is image data transmitted from the external device by wire or wireless.

  The VRAM 22 is an image memory that temporarily stores image data written by the CPU 21.

  The timing generator 23 transfers the image data read from the VRAM 22 to the panel driver 3 at a timing synchronized with the vertical synchronization signal.

<Configuration of panel driver>
FIG. 2 is a block diagram showing the configuration of the panel driver 3.

  The panel driver 3 is a display driving device that drives the liquid crystal panel 4 so that the image data transferred from the host controller 2 is displayed on the liquid crystal panel 4. The panel driver 3 drives the liquid crystal panel 4 so as to perform refresh display at the maximum refresh rate (60 Hz) defined for the liquid crystal panel 4 when displaying a moving image. The panel driver 3 sets a refresh rate (drive cycle) according to whether or not the input image data is updated, generates a drive timing based on the set refresh rate, and a liquid crystal panel based on the drive timing 4 is driven. As shown in FIG. 2, the panel driver 3 includes a frame memory 31, a comparison circuit 32, a refresh controller 33, a timing generator 34, a source driver 35, and a gate driver 36 in order to realize such a drive function. Yes. The frame memory 31 and the comparison circuit 32 constitute an image comparison unit 37.

  The panel driver 3 may be formed as a dedicated driver LSI, but may be formed on a later-described active matrix substrate (glass substrate) of the liquid crystal panel 4 in a COG (Chip ON Glass) configuration.

<Configuration of image comparison unit>
The image comparison unit 37 (image comparison means) compares two consecutively input image data in units of a predetermined number of pixel data, and determines a matching portion and a mismatching portion in both image data in units of lines. As a unit of this comparison, if it is a unit of a predetermined number of pixel data, it can be one pixel data, a plurality of pixel data, one line, a plurality of lines, or a block (rectangular range) depending on the design specifications of the panel driver 3 There may be.

  The frame memory 31 constituting the image comparison unit 37 is an image memory (frame buffer) that stores input image data of one frame for each line, and is configured by a dual port RAM or the like. The frame memory 31 delays the input of the image data by one frame by temporarily storing and reading the image data. Thereby, the input timings of the image data and the next input image data are synchronized.

  The frame memory 31 writes input image data each time, but only changed (updated) image data may be written. For example, the frame memory 31 temporarily holds the input image data without writing it, and writes the image data of the line for which the image data mismatch is determined by the comparison circuit 32, while the image data match is determined. Do not write line image data. Thereby, unnecessary writing is avoided, so that the writing operation of the frame memory 31 can be performed efficiently and the power consumption can be reduced.

  The comparison circuit 32 configuring the image comparison unit 37 compares the image data read from the frame memory 31 with the image data input next to the image data in units of pixels, and the image data match or mismatch. Is determined in line units. Such a comparison circuit 37 can be realized by a comparator for coincidence detection, for example.

  The comparison circuit 32 outputs the match determination result as “1” and the mismatch determination result as “0”. These values of “1” or “0” are input to the refresh controller 33 as an update presence / absence signal. That is, if there is an update in each line of the image data, the update presence / absence signal is “0”, and if there is no update in each line of the image data, the update presence / absence signal is “1”.

  In addition, the comparison circuit 32 generates an update presence / absence determination timing with respect to an update presence / absence determination timing indicating which line in the image data matches or does not match (update presence / absence determination). Since the comparison operation is performed based on the clock in the comparison circuit 32, the update presence / absence determination timing can be generated by counting this clock from the first line of the image data.

  In the image comparison unit 37, the frame memory 31 is used to delay the image data by one frame. However, the present invention is not limited to this, and any delay circuit capable of delaying the image data by one frame can be used. It can be used in place of the frame memory 31.

<Refresh controller configuration>
The refresh controller 33 (refresh rate setting means) specifies non-update of the image for the line of the matching portion and specifies update of the image for the line of the non-matching portion based on the update presence / absence determination timing and the update presence / absence signal. The refresh controller 33 holds this identification result for each line in the update identification register. For example, the refresh controller 33 turns on the flag for image update in the update specific register and turns off the flag for non-update of the image.

  In addition, the refresh controller 33 sets the refresh rate when displaying the line of the matching portion to a register lower than the maximum refresh rate (usually about 60 Hz) for moving image display (usually about 1 Hz). In other words, in this case, the refresh controller 33 sets the drive cycle longer than the shortest drive cycle (usually about 16.67 ms). On the other hand, the refresh controller 33 sets the refresh rate at the time of displaying the mismatched part line in the register to the highest refresh rate. In other words, in this case, the refresh controller 33 sets the drive cycle to the shortest drive cycle.

  In addition, the refresh controller 33 has a function of gradually decreasing the refresh rate for the matching line. In order to realize this function, the refresh controller 33 includes a refresh rate changing unit 331.

  The refresh rate changing unit 331 further sets the refresh rate to a lower level when the non-update of the image is specified even if the image of the predetermined number of frames is displayed for the line for which the non-update of the image is specified. Is repeated to set the refresh rate to a predetermined minimum value. Specifically, the refresh rate changing unit 331 counts the number of frames that specify non-updating images for the same line, and performs an operation of reducing the refresh rate to a predetermined refresh rate when the count value reaches a predetermined value. repeat. As a result, the refresh rate changing unit 331 gradually decreases the refresh rate as long as the non-update of the image is maintained for the same line, and finally sets the lowest refresh rate.

<Timing generator configuration>
The timing generator 34 (drive timing generation means) generates drive timing (drive pattern) based on the refresh rate set as described above.

  Specifically, the timing generator 34 determines the presence / absence of driving for each line based on the presence / absence of update of the specified image and the set refresh rate. As shown in FIG. 2, “+” represents positive voltage drive, “−” represents negative voltage drive, and “x” represents non-drive.

Thus, for example, the following drive timing is generated based on the set refresh rate.
(1) Refresh rate 60Hz
Positive voltage driving and negative voltage driving are alternately repeated for each frame.
(2) Refresh rate 30Hz
There is non-drive for one frame between the positive voltage drive and the negative voltage drive.
(3) Refresh rate 15Hz
There is non-driving for three frames between positive voltage driving and negative voltage driving.
(4) Refresh rate 1Hz
There is 59 frames of non-drive between the positive voltage drive and the negative voltage drive.

  Thus, the driving state which is different for each line is set by the timing generator 34.

  The timing generator 34 provides image data to the source driver 35 in synchronization with the drive timing, and generates various control signals for controlling the operations of the source driver 35 and the gate driver 36. Specifically, the timing generator 34 outputs image data to the source driver 35 when performing positive voltage driving and negative voltage driving, and does not output image data to the source driver 35 when not driving. In addition, the timing generator 34 generates a source clock and source start pulse for the source driver 35 and a gate clock and gate start pulse for the gate driver 36.

  Further, the timing generator 34 outputs control signals CNT1 to CNT3 for controlling ON / OFF operations of switches SW1 to SW3 (see FIG. 3) provided on the liquid crystal panel 4 described later. In addition, the timing generator 34 generates a drive enable signal DENABLE (see FIG. 11) to be described later during the non-drive period. The drive enable signal DENABLE is used as a control signal that outputs the control signals CNT1 to CNT3 when active and does not output the control signals CNT1 to CNT3 when inactive. For example, whether the control signals CNT1 to CNT3 are valid or invalid can be selected by a logical product of the drive enable signal DENABLE and the control signals CNT1 to CNT3. The AND circuit for outputting such a logical product may be included in the timing generator 34 or may be provided outside the timing generator 34 (such as the liquid crystal panel 4).

  Further, the timing generator 34 has a function of aligning the drive timing of each line in the same vertical synchronization period while a plurality of frames of images are displayed. In order to realize this function, the timing generator 34 includes a drive timing adjustment unit 341. Details of the drive timing adjustment unit 341 will be described later.

<Configuration of source driver>
The source driver 35 saves and outputs the image data input from the timing generator 34 for one line at the timing generated by the shift register. Specifically, the shift register of the source driver 35 sequentially shifts and outputs the aforementioned source start pulse in synchronization with the source clock. Further, the source driver 35 selects a gradation voltage corresponding to the gradation represented by the image data output from the shift register, and outputs it as a data voltage to each source line described later in the liquid crystal panel 4. Furthermore, the source driver 35 has source amplifiers (amplifiers) provided in the same number as the source lines at the output stage, and outputs data voltages to the source lines via the source amplifiers.

<Configuration of gate driver>
The gate driver 35 generates a gate signal to be output to each gate line to be described later in the liquid crystal panel 4 based on the above-described gate start pulse and gate clock. Specifically, the gate driver 35 sequentially shifts the gate start pulse in synchronization with the gate clock by the shift register and outputs a gate signal. The gate driver 35 selects the gate lines line-sequentially by outputting such a gate signal.

<Configuration of LCD panel>
FIG. 3 is a circuit diagram showing a schematic configuration of the liquid crystal panel 4 in the liquid crystal display device 1.

  Although not shown, the liquid crystal panel 4 (display unit) includes an active matrix substrate, a counter substrate, and liquid crystal sandwiched between both substrates. The active matrix substrate and the counter substrate are translucent substrates made of glass or the like.

  As shown in FIG. 3, the active matrix substrate includes a plurality of source lines S1, S2, S3,... Sm arranged in parallel and a plurality of gate lines G1, G2, G3,. Gn is formed so as to cross each other.

  In the following description, when the description is common to the source lines S1, S2, S3,..., Sm, it is referred to as the source line S and is described in common to the gate lines G1, G2, G3,. In this case, it is called a gate line G.

  On the active matrix substrate, pixel electrodes Pr, Pg, and Pb corresponding to R (red), G (green), and B (blue), respectively, are formed along the gate line G. On the active matrix substrate, transistors Tr, Tg, and Tb (switching elements) corresponding to the pixel electrodes Pr, Pg, and Pb are formed in the vicinity of the intersection of the gate line G and the source line S, respectively. .

  The transistors Tr, Tg, and Tb are thin film transistors (TFTs), and their semiconductor layers are formed of an oxide semiconductor. As this oxide semiconductor, for example, IGZO (InGaZnOx) is preferable.

  Since IGZO has an electron mobility of about 20 to 50 times higher than that of a-Si, the TFT can be miniaturized. Thereby, the pixel aperture ratio can be improved. In addition, the liquid crystal panel 4 using the IGZO-TFT can be driven at a low frequency, and the refresh rate can be reduced to about 1 Hz.

  The transistors Tr, Tg, and Tb each have a source connected to the source line S and a gate connected to the gate line G. The drains of the transistors Tr, Tg, and Tb are connected to the pixel electrodes Pr, Pg, and Pb, respectively. Thereby, the transistors Tr, Tg, and Tb are turned on when the gate signal output from the gate driver 36 to the gate line G is active (H level), and when the gate signal is inactive (L level). Turn off. The transistors Tr, Tg, and Tb are turned on to make the source line S and the pixel electrodes Pr, Pg, and Pb conductive.

  Switches SW1 to SW3 are formed on the active substrate. The switches SW1 to SW3 are disposed between the source driver 35 and the pixel electrodes Pr, Pg, and Pb in the source line S, one end is connected to the pixel electrodes Pr, Pg, and Pb, respectively, and the other end is the source line. Connected to S. The switches SW1 to SW3 are ON / OFF controlled by control signals CNT1 to CNT3 supplied from the timing generator 34, respectively.

  On the other hand, a counter electrode COM is formed on the counter substrate to face the pixel electrodes Pr, Pg, Pb. In FIG. 3, the counter electrode COM is drawn so as to individually face the pixel electrodes Pr, Pg, and Pb, but is formed to be large as a whole so as to be common to the pixel electrodes Pr, Pg, and Pb. It may be. The counter electrode COM is given a ground potential as a counter potential.

  A liquid crystal capacitor is formed by the pixel electrodes Pr, Pg, and Pb, the counter electrode COM facing them, and the liquid crystal therebetween. A voltage applied between the pixel electrodes Pr, Pg, Pb and the counter electrode COM is held by the liquid crystal capacitance, and the alignment state of the liquid crystal is controlled by this voltage. As a result, irradiation light from a backlight device (not shown) is emitted at a gradation (luminance) corresponding to the applied voltage when it enters the liquid crystal panel 4.

  Further, the above-described one set of transistors Tr, Tg, Tb, one set of pixel electrodes Pr, Pg, Pb, the counter electrode COM, and the liquid crystal between the pixel electrodes Pr, Pg, Pb and the counter electrode COM, One pixel region PIX is formed. The pixel area PIX is composed of three sub-pixel areas divided by pixel electrodes Pr, Pg, and Pb. In the pixel area PIX, by controlling the alignment state of the liquid crystal in each sub-pixel area with the above-described data voltage, pixels having gradations and colors corresponding to image data (pixel data) are displayed. A line is constituted by the pixel region PIX connected to one gate line G.

[Display operation of liquid crystal display]
Here, the display operation of the liquid crystal display device 1 will be described.

[Operation of panel driver]
In the panel driver 3, first, image data of the first frame from the host controller 2 is input to the timing generator 34 and written to the frame memory 31 of the image comparison unit 37. As for the image data of the first frame, since there is no image data to be compared in the image comparison unit 37, the timing generator 34 generates the drive timing at the highest refresh rate.

  The subsequent second frame image data is similarly input to the timing generator 34 and written to the frame memory 31. In the image comparison unit 37, the image data of the first frame stored in the frame memory 31 is sequentially read out from the first line, and the unit of the image data and pixel data of the second frame is read out by the comparison circuit 32. Are compared (image comparison step). Then, the comparison circuit 32 determines for each line whether the two image data match or does not match, that is, whether or not the image data is updated. As a result of this comparison determination, the comparison circuit 32 outputs the above-described determination presence / absence determination timing and update presence / absence signal.

  In the refresh controller 33, based on the determination presence / absence determination timing and the update presence / absence signal, update or non-update of the image is specified for each input image data. In the refresh controller 33, a high refresh rate (60 Hz) is set for the updated line, and a low refresh rate is set for the line that has not been updated (refresh rate setting step).

  In the timing generator 34, based on the refresh rate of each line set by the refresh controller 33, a drive timing is generated for which line is driven or not driven for each line (drive timing generation step). For example, since there is a change for an updated line, a driving timing for driving at 60 Hz for driving a moving image is generated, while there is no change for an unupdated line, so 30 Hz, 15 Hz,. A drive timing for driving at 1 Hz or the like is generated.

  The liquid crystal panel 4 is driven by the source driver 35 and the gate driver 36 based on the drive timing, image data, and various control signals given from the timing generator 34. At this time, the updated line is driven at the drive timing based on the high refresh rate, and the line not updated is driven at the drive timing based on the low refresh rate.

[Basic display operation of LCD panel]
Next, the display operation (display driving method) of the liquid crystal panel will be described.

  4 to 9 are diagrams showing driving states at each stage (operation timing) in the display panel 1. FIG.

  4 to 9, for convenience, only the source lines S1 to S3 and the gate lines G1 to G3 and the corresponding parts are shown, and the following description is also limited to the corresponding parts.

<Operation timing T1>
At the operation timing T1 shown in FIG. 4, when the gate signal output to the gate line G1 becomes active (H level), all the transistors Tr, Tg, Tb connected to the gate line G1 are turned ON. In this state, the switches SW1 to SW3 are still OFF.

<Operation timing T2>
At the operation timing T2 shown in FIG. 5, only the switch SW1 is turned ON when the control signal CNT1 becomes active (H level). As a result, the source lines S1 to S3 and the pixel electrode Pr are conducted through the transistor Tr.

<Operation timing T3>
At the operation timing T3 shown in FIG. 6, the data voltage corresponding to R is output from the source driver 35, so that the data voltage is applied to the pixel electrode Pr via the transistor Tr. Thereby, the display state of the R sub-pixel region is controlled in the pixel region PIX selected by the gate line G1.

<Operation timing T4>
At the operation timing T4 shown in FIG. 7, only the switch SW2 is turned ON when the control signal CNT2 becomes active. As a result, the source lines S1 to S3 and the pixel electrode Pg are conducted through the transistor Tg. Further, when the data voltage corresponding to G is output from the source driver 35, the data voltage is applied to the pixel electrode Pg via the transistor Tg. As a result, the display state of the G sub-pixel region is further controlled in the pixel region PIX selected by the gate line G1.

<Operation timing T5>
At the operation timing T5 shown in FIG. 8, only the switch SW3 is turned ON when the control signal CNT3 becomes active. As a result, the source lines S1 to S3 and the pixel electrode Pb are conducted through the transistor Tb. Further, when the data voltage corresponding to B is output from the source driver 35, the data voltage is applied to the pixel electrode Pb via the transistor Tb. As a result, the display state of the B sub-pixel region is further controlled in the pixel region PIX selected by the gate line G1.

<Operation timing T6>
At the operation timing T6 shown in FIG. 9, when the gate signal output to the gate line G2 becomes active, all the transistors Tr, Tg, Tb connected to the gate line G2 are turned ON. In this state, when the control signal CNT1 becomes active and only the switch SW1 is turned on, the source lines S1 to S3 and the pixel electrode Pr are brought into conduction through the transistor Tr. Then, when the data voltage corresponding to R is output from the source driver 35, the data voltage is applied to the pixel electrode Pr via the transistor Tr. Thereby, the display state of the R sub-pixel region is controlled in the pixel region PIX selected by the gate line G2.

  By repeating the above operation, an image of one frame is displayed.

[Normal display operation]
Here, a normal display operation will be described for reference.

  FIG. 10 shows gate signals in the gate lines G1 to G3, ON / OFF of the switches SW1 to SW3, and data in the source lines S1 to S3 in each state of the operation timings T1 to T6 when driven by a normal driving method. It is a wave form diagram which shows a voltage.

  As shown in FIG. 10, first, the potential (gate signal) of the gate line G1 changes to the H level at the operation timing T1. From this state, after the operation timing T2, the switches SW1 to SW3 are sequentially turned on at the operation timings T3 to T5.

  At the operation timing T3, the data voltage output to the source lines S1 and S3 is applied to the pixel electrode Pr (positive voltage drive). At the subsequent operation timing T4, the data voltage output to the source lines S1 and S3 is applied to the pixel electrode Pg (negative voltage driving). Further, at the operation timing T5, the data voltage output to the source lines S1 and S3 is applied to the pixel electrode Pb (positive voltage drive).

  For the source line S2, data voltages having opposite polarities to the source lines S1, S3 are applied to the pixel electrodes Pr, Pg, Pb, respectively. In this way, dot inversion driving in which the polarity of the same applied voltage is different for each sub-pixel region is performed.

  In the present embodiment, as described above, the driving by the dot inversion sub-pixel inversion method is described, but the driving method of the present embodiment can be applied to other driving methods. As such a driving method, for example, a dot inversion pixel inversion method (a method in which a positive voltage and a negative voltage are inverted in RGB units constituting one pixel) and a line inversion method (a positive voltage in all pixels of one line). And a method in which the negative voltage is inverted).

  Such an operation is repeated after the operation timing T6 when the gate line G2 is selected. In this way, in a normal display operation, positive voltage driving and negative voltage driving are repeated at a refresh rate of 60 Hz regardless of whether the image is a moving image or a still image.

[Display operation by panel driver]
Subsequently, a display operation by the panel driver 3 will be described.

  FIG. 11 shows gate signals in each gate line G in each state of operation timings T1 to T6 when driven by a driving method using the panel driver 3, ON / OFF of the switches SW1 to SW3, and each source line S. It is a wave form diagram which shows the data voltage in.

  As shown in FIG. 11, the drive enable signal DENABLE from the timing generator 34 is active (H level) during the period when the potential (gate signal) of the gate line G1 is at the H level at the operation timing T1. Thereby, the control signals CNT1 to CNT3 become effective, and the switches SW1 to SW3 are sequentially turned on at the operation timings T3 to T5.

  At operation timings T3 to T4, driving is performed in the same manner as in the case shown in FIG. Up to this point, the updated image line is displayed, which is the same as the normal display operation described above.

  Next, at the operation timing T6 when the gate line G2 is selected, the image data is not updated with respect to the line of the gate line G1, and therefore the non-driving drive timing is generated by the timing generator 34. Further, the drive enable signal DENABLE is inactive (L level). As a result, the control signals CNT1 to CNT3 become invalid and the switches SW1 to SW3 are not turned ON. Therefore, no data voltage is applied to the pixel electrodes Pr, Pg, Pb connected to the gate line G2 (non-driving).

  At the subsequent operation timing when the gate line G3 is selected, the image data is updated with respect to the gate line G2, so that the timing generator 34 drives the positive voltage drive or negative voltage drive as described above. Is generated. The drive enable signal DENABLE is active. As a result, the control signals CNT1 to CNT3 become effective, and the switches SW1 to SW3 are turned on. Therefore, since the data voltage is output to the pixel electrodes Pr, Pg, Pb, the updated image is displayed in the same manner as the operation timings T3 to T5.

[Display on smartphone]
Here, display of an image in a specific electronic device will be described.

  FIG. 12 is a diagram illustrating a state in which an image is displayed by driving by the panel driver 3 in the smartphone 11 on which the liquid crystal display device 1 is mounted.

  As shown in FIG. 12, a smartphone 11 as an electronic device is equipped with the liquid crystal display device 1 described above. In this smartphone 11, the liquid crystal panel 4 is provided on the operation surface side of the housing 11a. A touch panel (not shown) is provided on the liquid crystal panel 4. Then, the liquid crystal panel 4 displays the application image 101 generated by the application program.

  The application image 101 includes user interface areas 101a and 101b, a data display area 101c, and a moving image display area 101d.

  The user interface area 101a is an area used for a user interface for displaying time, communication status, and the like. The user interface area 101b is an area used for operating an application program. Since the display state of the user interface area 101a changes only when the time or communication status changes, the display state does not always change like a moving image. Further, the display state of the user interface area 101b does not change unless the user performs a touch operation. Therefore, the panel driver 3 drives the liquid crystal panel 4 at a low refresh rate of 1 Hz during a period when the image data is not updated. Thus, the user interface areas 101a and 101b are displayed by driving at a low refresh rate.

  The data display area 101c is an area where data acquired by the application program is displayed. The display state of the data display area 101c does not change unless new data is acquired. Therefore, the data display area 101c is also displayed by driving at a low refresh rate of 1 Hz during a period when the image data is not updated.

  Since the moving image display area 101d is an area for displaying a moving image, image data is constantly updated. For this reason, the panel driver 3 drives the liquid crystal panel 4 at a high refresh rate of 60 Hz with the update of the image data. Thus, the moving image display area 101d is displayed by driving at a high refresh rate.

[Stepwise change of refresh rate]
As described above, the refresh controller 33 sets a low refresh rate for lines that are not updated. At this time, when the refresh rate is changed from 60 Hz to 1 Hz, a rapid refresh rate change is easily recognized by the user as a change in color or brightness. For this reason, the refresh rate is gradually reduced by the refresh rate changing unit 331 for the lines that are not updated, so that the display changes as described above are not noticeable. Here, the process performed by the refresh rate changing unit 331 will be described.

  FIG. 13 is a flowchart showing a procedure of processing in which the refresh controller 33 changes the refresh rate.

  As shown in FIG. 13, first, initialization processing is performed (step S1). Here, the update presence / absence determination timing and the update presence / absence signal from the image comparison unit 37 are captured.

  Next, when there is an update presence / absence determination timing (step S2), the presence / absence of image update is confirmed for each line based on the update presence / absence signal (step S3). If there is an update, the refresh rate is updated to 60 Hz (step S4). If there is no update, it is determined whether or not a predetermined number of frames have been displayed since the current refresh rate was set (step S5).

  In step S5, if a predetermined number of frames of images are not displayed, the process returns to step S2. If a predetermined number of frames of images are displayed, it is determined whether or not the current refresh rate is 60 Hz (step S6). Here, when it is determined that the refresh rate is 60 Hz, the refresh rate is changed to 30 Hz (step S7), and the process returns to step S2. If it is determined that the refresh rate is not 60 Hz, it is further determined whether or not the refresh rate is 30 Hz (step S8).

  If it is determined in step S8 that the refresh rate is 30 Hz, the refresh rate is changed to 15 Hz (step S9), and the process returns to step S2. If it is determined that the refresh rate is not 30 Hz, it is further determined whether or not the refresh rate is 15 Hz (step S10).

  If it is determined in step S10 that the refresh rate is 15 Hz, the refresh rate is changed to 8 Hz (step S11), and the process returns to step S2. If it is determined that the refresh rate is not 15 Hz, it is further determined whether or not the refresh rate is 8 Hz (step S12).

  If it is determined in step S12 that the refresh rate is 8 Hz, the refresh rate is changed to 4 Hz (step S13), and the process returns to step S2. If it is determined that the refresh rate is not 8 Hz, it is further determined whether or not the refresh rate is 4 Hz (step S14).

  If it is determined in step S14 that the refresh rate is 4 Hz, the refresh rate is changed to 2 Hz (step S15), and the process returns to step S2. If it is determined that the refresh rate is not 4 Hz, it is further determined whether or not the refresh rate is 2 Hz (step S16).

  If it is determined in step S16 that the refresh rate is 2 Hz, the refresh rate is changed to 1 Hz (step S17), and the process returns to step S2. If it is determined that the refresh rate is not 2 Hz, the process returns to step S2.

  In this way, for the lines that are not updated, the refresh rate is set so as to gradually decrease, and finally the refresh rate is set to the lowest 1 Hz at which the liquid crystal panel 4 can be driven.

  In addition, about the space | interval which reduces a refresh rate, although it is set to 60Hz, 30Hz, 15Hz, 8Hz, 4Hz, 2Hz, 1Hz in said example, it is not limited to this. For example, 60 Hz, 30 Hz, 15 Hz, 7.5 Hz, 3.75 Hz, 1.88 Hz, and 0.94 Hz may be set to be halved. However, when setting in this way, the minimum refresh rate must be set to a value close to the minimum refresh rate at which the liquid crystal can be driven.

[Driving timing adjustment]
Next, the drive timing adjustment operation by the drive timing adjustment unit 341 in the timing generator 34 will be described.

  FIG. 14A is a timing chart showing a state in which the drive timing is controlled by the timing generator 34. FIG. 14B is a timing chart showing a state in which the drive timing is further aligned within one frame period by the timing generator 34. FIG. 15 is a diagram illustrating a state in which the timing at which the refresh rate is changed differs between lines. FIG. 16A is a diagram illustrating a state in which driving and non-driving timings are shifted between lines, and FIG. 16B is a diagram illustrating a state in which driving and non-driving timings are consistent between lines. FIG. FIG. 17A is a block diagram illustrating a configuration of the drive timing adjustment unit 341. FIG. 17B is a diagram illustrating the drive timing adjustment operation by the drive timing adjustment unit 341.

  14 (a) and 14 (b), only the gate lines G1 to G3 and the corresponding parts are shown for convenience, and the following description is also limited to the corresponding parts.

  As described above, since the presence / absence of update is determined for each line and the refresh rate is changed accordingly, the determination of the presence / absence of update for each line and the timing of the refresh rate change differ depending on the image. For this reason, as shown in FIG. 14A, the timing at which the gate lines G1 to G3 are driven (selected) may not be performed within one frame period. The reason will be described below.

  The timing at which the refresh rate of each line is lowered stepwise as described above is determined by the timing at which the line was last updated.

  FIG. 15 shows that the mth line is updated last in the second frame (Y) and is not updated thereafter (N), and the nth line is updated last in the fifth frame (Y) and thereafter. (N) and the refresh rate decreases every 6 frames. In such a case, the drive proceeds with a shift of 3 frames between both lines. Further, even when the refresh rate is finally set to 1 Hz, the refresh timing is fixed with the three frames being shifted between both lines.

  In this state, as shown in FIG. 14A, the period during which the source line S is driven varies, and the source driver 35 drives the source line S in each period. Since the source driver 35 includes an amplifier in the output stage as described above, power consumption increases when the drive period varies as described above. Therefore, the drive timing adjustment unit 341 adjusts the drive timing that varies as described above, thereby, as shown in FIG. 14B, a period of one frame period (vertical synchronization period) defined by the vertical synchronization signal VSYNC. ).

  The drive timing adjustment unit 341 determines the drive timing of the reference line (for example, the first line), calculates a deviation from the drive timing of each line with respect to this drive timing, and the number of non-drives corresponding to each deviation. The timing is thinned out from the drive line of each line. For example, as shown in FIG. 16A, when the generated drive timing is shifted by 3 frames between the m-th line and the n-th line, the drive timing of the m-th line is used as a reference. Each non-driving period at the driving timing of the n line is thinned out by 3 frames. As a result, as shown in FIG. 16B, the drive timing is aligned in the same frame on the mth line and the nth line.

  Alternatively, the drive timing adjustment unit 341 may be configured to adjust the drive timing using a feedback method. For this reason, the adjustment unit 341 includes a reference period generation unit 314a, a timing difference detection unit 341b, and a pause period adjustment unit 341c as illustrated in FIG.

  The reference period generation unit 341a generates a drive timing (for example, 1 Hz) having a reference period (frequency). The timing difference detection unit 341b compares the driving timing of the reference period with each driving timing, and detects the timing difference. The pause period adjustment unit 341c adjusts the pause period in which the drive is paused by changing the number of non-drive periods so that the detected timing difference is reduced.

  In the drive timing adjustment unit 341 configured as described above, as shown in FIG. 17B, the timing difference with respect to the drive timing of the reference period of the drive timing to be compared is compared by the timing difference detection unit 341b. Detected. When this timing difference is 3 frames, the pause period adjustment unit 341c thins out the non-drive period for 1 frame and adjusts the pause period to be shorter by 1 frame. Then, by repeating the processing by the timing difference detection unit 341b and the pause period adjustment unit 341c for the drive timing in which the pause period is adjusted in this way, the drive timing that is finally compared and the drive timing of the reference cycle are compared. Eliminate timing differences.

  Since such processing can be realized by a PLL (Phase Rocked Loop) or the like, the drive timing adjustment unit 341 can be designed relatively easily.

[Effects of panel driver]
As described above, the panel driver 3 in the liquid crystal display device 1 determines whether or not an image is updated in units of lines, changes the refresh rate according to the presence or absence of the update, and sets the drive timing based on the changed refresh rate. Generate. Specifically, the drive timing is generated at a high refresh rate for the line for which the image update is specified, and the drive timing is generated at the low refresh rate for the line for which the image non-update is specified.

  As a result, in the image displayed on the liquid crystal panel 4, a non-updated portion such as a still image is driven at a low refresh rate. Therefore, even if the displayed image includes an updated portion such as a moving image, the driving is not performed uniformly at a high refresh rate. In addition, by providing the IGZO-TFT as a switching element, the liquid crystal panel 4 that can be driven at a low frequency of about 1 Hz can be driven at a refresh rate of 1 Hz. Therefore, the power consumption can be further reduced.

  When non-update of the image is specified, the refresh rate changing unit 331 reduces the refresh rate stepwise to the lowest refresh rate. Thereby, a sudden change in the refresh rate can be avoided. Therefore, the refresh rate can be reduced without reducing the image display quality. In the display of a still image or an image with a relatively long update interval, a change in the display state due to a sudden change in the refresh rate is conspicuous, and therefore, in the setting of the refresh rate, a process for decreasing the refresh rate in stages is included. It is preferable.

  When non-update of an image is specified and a drive pause period is provided, the drive timing is adjusted by the drive timing adjustment unit 341 so that the drive timing of each line is aligned with the same frame period. Thereby, since the period during which the source driver 35 is driven is reduced, the power consumption can be further reduced.

  Further, in the present embodiment, the example in which the refresh controller 33 specifies the update or non-update of the image and the setting of the refresh rate (drive period) has been described. However, the specification of image update or non-update and the setting of the refresh rate are not limited to line units, but may be performed, for example, on a pixel basis. As a result, the range that can be driven at a low refresh rate can be expanded as compared with the processing in line units. Therefore, power consumption can be further reduced.

  Note that in order to perform such pixel-by-pixel processing, the liquid crystal panel 4 needs to be able to control ON / OFF in units of the pixel region PIX.

[Realization of panel driver]
Each block of the image comparison unit 32, the refresh controller 33, and the timing generator 34 in the panel driver 3 is configured by hardware logic. However, each of the above blocks may be realized by software (display drive program) using a CPU as described below. That is, this display driving program causes the computer to function as each of the above blocks. Or each said block may be implement | achieved by the process by the program using DSP (Digital Signal Processor).

  The program code (execution format program, intermediate code program, source program) of the above software may be recorded on a recording medium recorded so as to be readable by a computer. The object of the present invention can also be achieved by supplying the recording medium to the liquid crystal display device 1 and reading and executing the program code recorded on the recording medium by the CPU.

  Examples of the recording medium include magnetic tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, and optical disks such as CD-ROM / MO / MD / BD / DVD / CD-R. Can be used. In addition, a card system such as an IC card (including a memory card) / optical card or a semiconductor memory system such as a mask ROM / EPROM / EEPROM / flash ROM can be used as the recording medium.

  Further, the liquid crystal display device 1 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. As this communication network, for example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication network, etc. can be used. It is. In addition, a wired medium or a wireless medium can be used as a transmission medium constituting the communication network. Examples of the wired medium include IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, and the like. Examples of the wireless medium include infrared rays such as IrDA and remote control, Bluetooth (registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like.

  The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

[Additional Notes]
In the present embodiment, an example in which the display device is the liquid crystal display device 1 has been described. However, the display device is not limited to the liquid crystal display device 1. For example, the display device is an FPD (Flat Panel Display) such as a PDP (Plasma Display Panel), an EL (Electroluminescence) display, or an FED (Field Emission Display).

  In the present embodiment, the example in which the electronic device on which the display device is mounted is the smartphone 11 has been described. However, as the electronic device, any low power consumption of display devices such as other portable terminals and electronic dictionaries is effective. Electronic devices are targeted.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The display driving device according to the present invention can be suitably used for a matrix display device that can be driven at a low frequency by including a switching element formed of an oxide semiconductor such as an IGZO-TFT.

1 Liquid crystal display device 3 Panel driver (display drive device)
4 LCD panel 11 Smartphone (electronic equipment)
31 frame memory 32 comparison circuit 33 refresh controller (refresh rate setting means)
34 Timing generator (drive timing generation means)
35 Source Driver 36 Gate Driver 37 Image Comparison Unit (Image Comparison Unit)
101 Application image 101a User interface area 101b User interface area 101c Data display area 101d Movie display area 331 Refresh rate change unit 341 Drive timing adjustment unit 341a Reference period generation unit 341b Timing difference detection unit 341c Pause period adjustment unit CNT1 Control signal CNT2 Control signal CNT3 control signal PIX pixel region Pr pixel electrode Pg pixel electrode Pb pixel electrode Tr transistor Tg transistor Tb transistor SW1 switch SW2 switch SW3 switch

Claims (7)

In a display driving device that drives a display unit that displays an image based on image data according to a refresh rate,
Image comparison means for comparing two consecutively input image data in units of a predetermined number of pixel data and determining matching and non-matching portions in both image data in units of lines;
The non-update of the image is specified for the line of the matching part and the refresh rate when displaying the line is set lower than the maximum refresh rate defined by the display unit, while the line of the non-matching part Refresh rate setting means for specifying the update of the image and setting the refresh rate to the highest when displaying the line;
Drive timing generation means for generating drive timing based on the set refresh rate ,
The refresh rate setting means further sets the refresh rate to be lower when a non-update of an image is specified even if an image for a predetermined number of frames is displayed for a line for which the non-update of the image is specified. Repeat that
The display drive apparatus according to claim 1, wherein the drive timing generation means aligns the drive timing of each line in the same vertical synchronization period while a plurality of frames of images are displayed .   The refresh rate setting means further sets the refresh rate to be lower when a non-update of an image is specified even if an image for a predetermined number of frames is displayed for a line for which the non-update of the image is specified. The display driving apparatus according to claim 1, wherein the refresh rate is set to a predetermined minimum value by repeating this operation. A display device comprising: a display unit that displays an image based on image data; and a display drive device that drives the display unit according to a refresh rate,
Display device, wherein the display driving device is a display driving device according to claim 1 or 2. An electronic device having a display device for displaying an image,
An electronic apparatus, wherein the display device is the display device according to claim 3 . Display driving program to function as the means of the display driving device according to the computer to claim 1 or 2. A computer-readable recording medium on which the display driving program according to claim 5 is recorded. In a display driving method for driving a display unit that displays an image based on image data according to a refresh rate,
An image comparison step of comparing two pieces of image data input in succession in units of a predetermined number of pixel data, and determining a matching portion and a mismatching portion in both image data in units of lines;
The non-update of the image is specified for the line of the matching part and the refresh rate when displaying the line is set lower than the maximum refresh rate defined by the display unit, while the line of the non-matching part A refresh rate setting step for specifying the update of the image and setting the refresh rate to the maximum when displaying the line;
A drive timing generation step of generating a drive timing based on the set refresh rate ,
In the refresh rate setting step, when the non-update of the image is specified for the line for which the non-update of the image is specified, even when the image of a predetermined number of frames is displayed, the refresh rate is further set lower. Repeat that
In the drive timing generation step, the display drive method is characterized in that the drive timing of each line is aligned in the same vertical synchronization period while an image of a plurality of frames is displayed .

Images