JP5932275B2 - Image processing system - Google Patents

Description

  The present invention relates to an image processing system.

  2. Description of the Related Art Conventionally, there is known an image display system that outputs different images to be displayed on m display units having an arbitrary natural number m of 2 or more as one image from one image generation apparatus. (For example, refer to Patent Document 1).

JP 2000-3164 A

By the way, in the above-described image display system according to the prior art, one image output from the image generation device is decomposed into m images in accordance with a synchronization signal shifted by 1 / m period, and m display devices are displayed. Is displayed.
That is, it is assumed that m images corresponding to m displays have the same resolution. For example, when m images having different resolutions are mixed to form one image. However, even if a synchronization signal shifted by 1 / m period is used, this one image cannot be appropriately decomposed.
In response to the occurrence of such problems, for example, m images with different resolutions can be mixed to form a single image, which improves the versatility of image display and system versatility. It is hoped that

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an image processing system capable of easily processing various images and improving versatility.

In order to solve the above problems and achieve the object, an image processing system according to the present invention has a period set by an integer having [nsec] as a unit for each of two images, and has one frame. wherein the dot clock signal having the common dot clock cycle is 1/2 of the greatest common divisor or the greatest common denominator of the dot clock period is the reciprocal of the frequency of drawing the points of one dot in the drawing of the image for each 2 image generating means for integrating one of the image into one integrated image, individual dot clock obtained by multiplying the division ratio set for each of the two images with respect to the common dot clock period A dot clock signal having a period and an individual synchronization signal corresponding to the individual dot clock signal for displaying each of the two images on a corresponding display screen. And an image dividing unit that divides the integrated image into the two images by the number, and the dot clock cycle is set by the integer different for each of the two images.

  According to the image processing system of the present invention, for a plurality of images having different clock cycles, the greatest common divisor of a plurality of different clock cycles or a common clock cycle that is 1/2 of the greatest common divisor is integrated. For example, even when a plurality of images having different dot clocks and resolutions are displayed on a plurality of different display screens, only one integrated image is output from one image generation unit. In addition, it is possible to easily process various images and improve versatility while preventing the system configuration from becoming complicated.

1 is a configuration diagram of an image processing system according to an embodiment of the present invention. It is a figure which shows the example of the synthesized image produced | generated by the image processing system which concerns on embodiment of this invention. It is a block diagram of the image division | segmentation apparatus which concerns on embodiment of this invention. It is a block diagram of the image processing system which concerns on the modification of embodiment of this invention.

Hereinafter, an image processing system according to an embodiment of the present invention will be described with reference to the accompanying drawings.
An image processing system 10 according to the present embodiment includes, as shown in FIG. 1, for example, one image drawing device 11 and a plurality of (for example, n by two or more arbitrary natural numbers k, n (n> k)). An image dividing device 12 and a screen display device 13 are provided.

  The image drawing device 11 is, for example, a VDP (Video Display Processor) made of an IC such as a graphic chip or an LSI, and includes an oscillator (not shown) such as a crystal resonator and a memory (not shown). Yes.

The image drawing device 11 acquires, for example, image data (for example, RGB data) for a plurality of screens displayed on the plurality of screen display devices 13 from an external memory (not shown), and the like. The image data is integrated into image data for one screen by being developed in the memory so as to be virtually drawn, and temporarily stored in the memory as image data for each frame (integrated image data).
In particular, the image drawing device 11 can use, for example, a plurality of image data having different dot clocks and resolutions, for example, a common dot that is the greatest common divisor of the dot clock cycle of the plurality of image data or 1/2 of the greatest common divisor. Drawing multiple screens according to the clock cycle.

  More specifically, for example, the image drawing device 11 has a maximum value when the greatest common divisor of the dot clock cycle of the plurality of image data is the same as the dot clock cycle of any one of the plurality of image data. When a common dot clock cycle is set to 1/2 of the common divisor, and the maximum common divisor of the dot clock cycle of the plurality of image data is different from the dot clock cycle of any image data of the plurality of image data, this maximum commitment One half of the number is set as a common dot clock cycle.

  For example, as shown in FIG. 2A, for two image data having the same resolution and the same dot clock cycle (for example, 25 nsec) for two screens A and B, 1/2 the dot clock cycle of each image data. Is a common dot clock cycle (12.5 nsec), and two screens A and B are drawn by this common dot clock cycle.

  For example, as shown in FIG. 2B, for two image data of different resolutions and different dot clock periods (for example, 24 nsec and 32 nsec) for the two screens A and B, the dot clock period of each image data Is set to a common dot clock cycle (for example, 8 nsec), and two screens A and B are drawn by this common dot clock cycle.

  Further, the image drawing apparatus 11 divides the plurality of image data by, for example, control data having a predetermined dot pattern when drawing for a plurality of screens with a common dot clock cycle for the plurality of image data.

  The image drawing apparatus 11 receives predetermined control data (for example, control DATA 1 and 2) such as a dot pattern that repeats black and white one dot at a time as shown in FIGS. 2 (A) and 2 (B), for example. Arranged adjacent to image data.

  For example, as shown in FIG. 2A, when two image data of the same resolution and dot clock cycle for two screens A and B are arranged in the horizontal direction in the integrated image data for each frame, the horizontal Two control data (for example, control DATA 1 and 2) having the same dot pattern, for example, are given adjacent to each image data in the direction.

  For example, as shown in FIG. 2B, when two image data having different resolutions and different dot clock periods for the two screens A and B are arranged in the horizontal direction in the integrated image data for each frame. Adjacent to each image data in the horizontal direction, for example, two control data having different dot patterns (for example, control DATA 1 and 2) are given.

  Note that, for example, as shown in FIG. 2B, the image data of the screen B in the vertical direction in the integrated image data for each frame, because the two image data for the two screens A and B have different resolutions. When it is necessary to indicate the division of image data in the vertical direction, such as when there is no image data below the control data (for example, in the vertical direction, the dot pattern has been changed) The control DATA 1) having different dot patterns above and below the boundary position indicating the division of the image data is assigned between the two image data for the two screens A and B.

  As described above, the image drawing device 11 uses, for example, the maximum common divisor of the dot clock periods of a plurality of image data or a common dot clock period that is ½ of the maximum common divisor based on the reference signal generated by the oscillation of the oscillator. (That is, a signal indicating a frequency at which a dot dot is drawn in the integrated image data for each frame).

  Further, the image drawing apparatus 11 is configured to generate a vertical synchronization signal (VSYNC) and a horizontal synchronization signal (HSYNC) for developing image data for a plurality of screens in a memory so as to virtually draw based on the dot clock signal. A synchronization signal such as a data enable signal (DE) is generated.

The horizontal synchronization signal (HSYNC) is a signal indicating the drawing timing of image data for one line of pixels in the horizontal direction of the integrated image data for each frame.
The vertical synchronization signal (VSYNC) is a signal indicating the drawing timing of image data for one frame in the vertical direction of the integrated image data for each frame.
The data enable signal (DE) is a signal indicating a drawing period of image data for one line in the horizontal direction of the integrated image data for each frame.

  Then, for example, the image drawing apparatus 11 reads the integrated image data for each frame temporarily stored in the memory for each line, and the integrated image data (line data) for each line is timed according to the synchronization signal. And a dot clock signal having a common dot clock cycle and a synchronization signal corresponding to the dot clock signal.

  For example, as shown in FIG. 3, the image dividing device 12 includes a frequency dividing circuit 21, a control circuit 22, and a register 23, and forms line data of integrated image data output from the image drawing device 11. Any one of predetermined image data displayed on the screen display device 13 corresponding to the image dividing device 12 is extracted from the plurality of image data.

  The frequency dividing circuit 21 is configured to include, for example, a counter, a PLL, and the like. Based on the dot clock signal output from the image drawing device 11, the frequency dividing circuit 21 is provided for each of a plurality of image data constituting the integrated image data for each frame. An individual dot clock signal having an individual dot clock period obtained by dividing a common dot clock period of the dot clock signal by any one of the set division ratios is output.

  The control circuit 22 includes, for example, control data and dot clock signals and synchronization signals included in the line data of the integrated image data output from the image drawing device 11, and individual dot clock signals output from the frequency divider circuit 21. Based on the above, the vertical corresponding to the individual dot clock signal for displaying any one of the plurality of image data constituting the integrated image data for each frame on the display screen of the screen display device 13 Individual synchronization signals such as a synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), and a data enable signal (DE) are generated, and these synchronization signals are output.

  Further, the control circuit 22 converts the line data of the integrated image data based on, for example, the control data included in the line data of the integrated image data output from the image drawing device 11 and the synchronization signal output from the image drawing device 11. It is determined whether or not a plurality of pieces of image data are any one of predetermined image data, and a signal indicating the determination result is output.

The register 23 includes, for example, a FIFO, and inputs, stores, and outputs image data output from the image drawing device 11 in synchronization with the frequency dividing circuit 21 and the control circuit 22.
More specifically, the register 23 is selected from among a plurality of pieces of image data constituting line data of the integrated image data output from the image drawing device 11 in accordance with the determination result signal output from the control circuit 22. Any one of predetermined image data is extracted, and the image data is output in synchronization with the individual dot clock signal output from the frequency divider circuit 21.

  The screen display device 13 includes, for example, a liquid crystal display, a cathode ray tube display, and the like, and the image output from the image dividing device 12 according to the individual dot clock signal and the individual synchronization signal output from the image dividing device 12. Data (that is, any one of a plurality of pieces of image data constituting the line data of the integrated image data output from the image drawing device 11) is displayed.

As described above, according to the image processing system 10 according to the present embodiment, the maximum common divisor of a plurality of different dot clock periods or 1/2 of the maximum common divisor for a plurality of image data having different dot clocks. Integration and division processing are performed using a certain common dot clock cycle.
Thus, for example, even when a plurality of image data having different dot clocks and resolutions are displayed on a plurality of different display screens, it is only necessary to output one integrated image data from one image drawing device 11. While preventing the configuration from becoming complicated, versatility can be improved by easily processing various images.

  In addition, the plurality of image data constituting the integrated image data can be easily and properly classified by the control data.

In the embodiment described above, it is determined which of the plurality of image data forms the integrated image data based on the control data. However, the present invention is not limited to this. For example, the control data is omitted. Then, based on other signals, for example, dot clock signals of image data for a plurality of screens, it may be determined which of the plurality of image data forms the integrated image data.
In this case, the image drawing device 11 may output a dot clock signal of image data for a plurality of screens in addition to a dot clock signal having a common dot clock cycle, and the control circuit 22 of the image dividing device 12 Based on the dot clock signal of the image data for a plurality of screens, it may be determined whether or not the plurality of image data constituting the line data of the integrated image data is any one of the predetermined image data. .

  In the above-described embodiment, for example, as in the modification shown in FIG. 4, one image drawing apparatus 11 and a plurality (for example, two or more arbitrary natural numbers k, n (n> k) n) ) Of the image dividing device 12 and the screen display device 13, and a combination of image data for a plurality of screens displayed on the plurality of screen display devices 13 in accordance with the control of the control device 30. In addition, the dot clock, the resolution, the frequency division ratio, and the like may be changed as appropriate.

DESCRIPTION OF SYMBOLS 10 Image processing system 11 Image drawing apparatus 12 Image dividing apparatus 13 Screen display apparatus 21 Frequency dividing circuit 22 Control circuit 23 Register

Claims (3)

A dot clock cycle which is a cycle set as an integer in units of [nsec] for each of two images and is the reciprocal of the frequency at which a dot dot is drawn in drawing the image for each frame. image generating means for integrating the two images by a dot clock signal to one of the integrated image with the greatest common divisor or common dot clock cycle is 1/2 of the greatest common divisor of,
And a dot clock signal having a respective dot clock period obtained by multiplying the division ratio set for each of the two images with respect to the common dot clock period, corresponding to each of the two images An image dividing means for dividing the integrated image into the two images by an individual synchronization signal corresponding to the individual dot clock signal for displaying on the display screen .
The dot clock cycle is set with the integer that is different for each of the two images. The image generation means, when integrating the two images into the integrated image, a section where one of the two images exists in the integrated image, and the two in the integrated image one of the divided the two images both by the control data indicating the segment is not present in the image,
Said image splitting means when dividing the integrated image on the two images, according to claim 1, characterized in that to determine which of the two images by the control data Image processing system. The image dividing unit is configured to determine which of the two images is based on a dot clock signal of an image for a plurality of screens when dividing the integrated image into the two images. The image processing system according to claim 1.

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