JP5931942B2 - Photovoltaic element and manufacturing method thereof - Google Patents

Photovoltaic element and manufacturing method thereof Download PDF

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JP5931942B2
JP5931942B2 JP2014042794A JP2014042794A JP5931942B2 JP 5931942 B2 JP5931942 B2 JP 5931942B2 JP 2014042794 A JP2014042794 A JP 2014042794A JP 2014042794 A JP2014042794 A JP 2014042794A JP 5931942 B2 JP5931942 B2 JP 5931942B2
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JP2014175661A (en
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布迪 賈約諾
布迪 賈約諾
明瑞 楊
明瑞 楊
傳文 丁
傳文 丁
玉▲てい▼ 邱
玉▲てい▼ 邱
任廷 譚
任廷 譚
文生 ▲呉▼
文生 ▲呉▼
國偉 沈
國偉 沈
芳維 胡
芳維 胡
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中美▲せき▼晶製品股▲ふん▼有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E10/00Energy generation through renewable energy sources
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    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description

本発明は、発生誘発電位減衰(potential-induced degradation、 PID)効果を有効的に抑制させる光起電素子及びその製造方法に関する。   The present invention relates to a photovoltaic device that effectively suppresses the potential-induced degradation (PID) effect and a method for manufacturing the photovoltaic device.

近年、PID効果が光起電素子及び光起電素子が装設されるモジュールの信頼性に与える問題は日増しに重要になっている。光起電素子の製造メーカーは皆、PID効果の発生を抑制させる光起電素子及び光起電素子が装設されるモジュールの開発に注力している。   In recent years, the problem that the PID effect gives to the reliability of photovoltaic modules and modules in which the photovoltaic elements are installed has become increasingly important. All manufacturers of photovoltaic elements are focusing on developing photovoltaic elements that suppress the occurrence of the PID effect and modules on which the photovoltaic elements are installed.

PID効果は2005年にサンパワー社がn型態シリコンベース光起電素子中から最初に発見した。しかしながら、装設モジュールが長時間高温下におかれ、湿度の高い環境で高電圧で使用するとガラスや装設材料の間に漏電が発生し、大量の電荷が光起電素子の表面に集中し、光起電素子の表面の効果が劣化し、光起電素子の機能特性、充填比(FF)、短絡電流密度(JSC)、開路電圧(VOC)等が急激に低下し、装設モジュールの機能が設計時よりも低下する。減衰を引き起こすこれらの現象は誘発電位減衰(PID)効果と称される。 The PID effect was first discovered in 2005 by Sunpower in an n-type silicon-based photovoltaic device. However, if the installation module is kept at a high temperature for a long time and used at a high voltage in a high humidity environment, electric leakage occurs between the glass and the installation material, and a large amount of charge is concentrated on the surface of the photovoltaic device. The surface effect of the photovoltaic element deteriorates, the functional characteristics, filling ratio (FF), short circuit current density (J SC ), open circuit voltage (V OC ), etc. Module functionality is lower than at design time. These phenomena that cause decay are referred to as evoked potential decay (PID) effects.

シリコンベース光起電素子は、従来の技術ではSiN反射防止層の屈折率を調整させることでPID効果の抑制を達成させる。然しながら、前述の方法は反射防止層自体の効果を犠牲にするため、反射防止層での反射率が高まる。また、前記の方法は他の型態の光起電素子には適用出来ない。 The silicon-based photovoltaic device achieves the suppression of the PID effect by adjusting the refractive index of the SiN X antireflection layer in the prior art. However, since the above-described method sacrifices the effect of the antireflection layer itself, the reflectance at the antireflection layer is increased. In addition, the above method cannot be applied to other types of photovoltaic elements.

また、関連する文献では誘発電位減衰効果の一般的な区分は以下の3種に分類されている。第1は半導体材料の表面の活性領域への影響である。第2は半導体の接合部の性能の減衰及び分流現象である。第3は電解腐食及び金属導電イオンの転移である。一般的には、PID効果の多くは光起電素子の辺縁から発生する。故に、光起電素子及び光起電素子モジュールはPID効果の発生を如何に抑制させるか、特に光起電素子の辺縁から発生するPID効果を抑制させ、光起電素子の耐用年数を延長させる方法を本分野の専門家達が研究を続けている。   In the related literature, general categories of the evoked potential decay effect are classified into the following three types. The first is the effect on the active region of the surface of the semiconductor material. The second is the performance attenuation and shunting phenomenon of the semiconductor junction. The third is electrolytic corrosion and metal conductive ion transfer. In general, much of the PID effect occurs from the edge of the photovoltaic element. Therefore, photovoltaic devices and photovoltaic device modules can suppress the generation of PID effect, in particular, suppress the PID effect generated from the edge of the photovoltaic device and extend the useful life of the photovoltaic device. Experts in this field continue to study how to make this possible.

そこで、本発明者は上記の欠点が改善可能と考え、鋭意検討を重ねた結果、合理的設計で上記の課題を効果的に改善する本発明の光起電素子及びその製造方法の提案に到った。   Therefore, the present inventor considers that the above-mentioned drawbacks can be improved, and as a result of intensive studies, the present inventors have arrived at a proposal of a photovoltaic element of the present invention and a method for manufacturing the same, which can effectively improve the above-described problems through rational design. It was.

本発明は、このような従来の問題に鑑みてなされたものである。上記課題解決のため、本発明は、PID効果の発生を有効的に抑制させる光起電素子及びその製造方法を提供することを主目的とする。   The present invention has been made in view of such conventional problems. In order to solve the above problems, it is a main object of the present invention to provide a photovoltaic device that effectively suppresses the occurrence of the PID effect and a method for manufacturing the photovoltaic device.

上述した課題を解決し、目的を達成するために、本発明に係る光起電素子は、
複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層を備え、半導体構成の組合せは表の表面及び表の表面に対する裏の表面を更に有し、表の表面には粗化処理が施され、第一保護層は表の表面の辺縁まで延出されると共に裏の表面の辺縁まで延出され、光起電素子は、表の表面に形成されると共に表の表面の辺縁の第一保護層を被覆させて延出される反射防止層と、反射防止層に形成され、表の表面と共にオーム接触を形成させる正極と、裏の表面に形成される少なくとも1つの裏面バス電極と、裏の表面に形成されると共に裏の表面を被覆させて少なくとも1つの裏面バス電極以外の領域を形成させるバック接点を更に備え、第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする。
In order to solve the above-described problems and achieve the object, the photovoltaic device according to the present invention is:
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction a combination of a semiconductor structure comprising any one of the joint which is selected from among, formed by coating the side surfaces of the multiple, and the for photovoltaic devices to suppress the evoked potential damping effect to be generated and a first protective layer, a combination of the semiconductor structure further comprises a back surface to the surface of the surface and the table of the table, on the surface of the table roughening treatment is performed, the first protective layer side of the surface of the table Reflected to extend to the edge and to the edge of the back surface, and the photovoltaic element is formed on the front surface and extends to cover the first protective layer on the edge of the front surface Formed on the back surface and the positive electrode that is formed on the anti-reflective layer, anti-reflective layer and forms ohmic contact with the front surface At least one back surface bus electrode, and a back contact formed on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode. aluminum, titanium, zirconium oxide, selected from any one of the group constituted by a mixture of hafnium oxide, and aforementioned compounds characterized Rukoto.

さらに、本発明に係る光起電素子は第二保護層を更に備える。第二保護層は第一保護層を被覆させて形成される。   Furthermore, the photovoltaic device according to the present invention further comprises a second protective layer. The second protective layer is formed by covering the first protective layer.

また、本発明の実施形態に係る光起電素子の製造方法については、まず半導体構成の組合せを準備する。半導体構成の組合せは複数の側表面を有し、またp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、多重接合部、或いは他の型態の接合部を備える。次に、本発明の方法は第一保護層を形成させ、半導体構成の組合せの複数の側表面を被覆させる。半導体構成の組合せは表の表面及び表の表面に対する裏の表面を更に有し、また、表の表面に粗化処理を施す工程と、第一保護層を表の表面の辺縁まで延出させ、且つ第一保護層を裏の表面の辺縁まで延出させる工程と、反射防止層を表の表面に接して形成させ、表の表面の辺縁の第一保護層を被覆させて延出させる工程と、正極を反射防止層に形成させ、且つ正極と表の表面と共にオーム接触を形成させる工程と、少なくとも1つの裏面バス電極を裏の表面に形成させる工程と、バック接点を裏の表面に形成させ、裏の表面を被覆させて少なくとも1つの裏面バス電極以外の領域を形成させる工程を更に含み、第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される。
In addition, regarding the method for manufacturing a photovoltaic device according to the embodiment of the present invention, first, a combination of semiconductor configurations is prepared. The combination of the semiconductor configuration has a plurality of side surfaces, and a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. Or, it has a joint portion of another type . Next , the method of the present invention forms a first protective layer and covers a plurality of side surfaces of a combination of semiconductor configurations. The combination of semiconductor structures further includes a front surface and a back surface relative to the front surface, and a step of roughening the front surface and the first protective layer extending to the edge of the front surface. And extending the first protective layer to the edge of the back surface and forming an antireflection layer in contact with the front surface, covering the first protective layer on the front surface edge and extending Forming a positive electrode on the antireflection layer, forming an ohmic contact with the positive electrode and the front surface, forming at least one back surface bus electrode on the back surface, and forming a back contact on the back surface And forming a region other than the at least one back surface bus electrode by covering the back surface, and the first protective layer is composed of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and the above-mentioned Consists of a mixture of compounds It is selected from any one of the groups being.

本発明によれば、半導体構成の組合せの複数の側表面を被覆させる第一保護層による本発明の光起電素子が発生させるPID効果の有効的に抑制が得られる。   According to the present invention, the PID effect generated by the photovoltaic element of the present invention can be effectively suppressed by the first protective layer covering a plurality of side surfaces of a combination of semiconductor configurations.

本発明の一好ましい実施形態に係る光起電素子を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the photovoltaic device which concerns on one preferable embodiment of this invention. 本発明の一好ましい実施形態に係る光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the photovoltaic element which concerns on one preferable embodiment of this invention. 本発明の一好ましい実施形態に係る光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the photovoltaic element which concerns on one preferable embodiment of this invention. 本発明の第1範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 1st example of this invention. 本発明の第1範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 1st example of this invention. 本発明の第1範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 1st example of this invention. 本発明の第1範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 1st example of this invention. 本発明の第2範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 2nd example of this invention. 本発明の第2範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 2nd example of this invention. 本発明の第3範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 3rd example of this invention. 本発明の第3範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon-based photovoltaic element of the 3rd example of this invention. 本発明の第4範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon base photovoltaic device of the 4th example of this invention. 本発明の第4範例のシリコンベース光起電素子の製造方法を説明する断面模式図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the silicon base photovoltaic device of the 4th example of this invention.

本発明における好適な実施の形態について、添付図面を参照して説明する。尚、以下に説明する実施の形態は、特許請求の範囲に記載された本発明の内容を限定するものではない。また、以下に説明される構成の全てが、本発明の必須要件であるとは限らない。   Preferred embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below do not limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily essential requirements of the present invention.

図1に示す光起電素子1は半導体構成の組合せ10及び第一保護層12を備える。半導体構成の組合せ10は複数の側表面102を有し、且つp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、多重接合部、或いは他の型態の接合部を備える。つまりは、本発明の光起電素子1は単結晶シリコンの光起電素子、擬似単結晶シリコンの光起電素子、多結晶シリコンの光起電素子、ヒ化ガリウムの光起電素子、薄膜アモルファスシリコンの光起電素子、薄膜微結晶(μ-Si)の光起電素子、薄膜硫化カドミウム(CdS)の光起電素子、薄膜アンチモン化カドミウム(CdTe)の光起電素子、薄膜セレン化銅インジウム(CuInSe2、 CIS)の光起電素子、薄膜セレン化ガリウムインジウム銅(Cu(In、Ga)Se2、 CIGS)の光起電素子、薄膜染料増感(DSSC)の光起電素子等の様々な型態の光起電素子が適用可能である。図1では、半導体構成の組合せ10は接合部104を代表として図示する。 The photovoltaic element 1 shown in FIG. 1 comprises a combination 10 of semiconductor configurations and a first protective layer 12. The semiconductor configuration combination 10 has a plurality of side surfaces 102 and has a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A junction or other type of junction is provided. In other words, the photovoltaic device 1 of the present invention includes a single crystal silicon photovoltaic device, a pseudo single crystal silicon photovoltaic device, a polycrystalline silicon photovoltaic device, a gallium arsenide photovoltaic device, and a thin film. Amorphous silicon photovoltaic device, thin film microcrystalline (μ-Si) photovoltaic device, thin film cadmium sulfide (CdS) photovoltaic device, thin film cadmium antimonide (CdTe) photovoltaic device, thin film selenization Indium copper (CuInSe 2 , CIS) photovoltaic devices, Thin film gallium indium copper selenide (Cu (In, Ga) Se 2 , CIGS) photovoltaic devices, Thin film dye sensitized (DSSC) photovoltaic devices Various types of photovoltaic elements can be applied. In FIG. 1, the semiconductor configuration combination 10 is illustrated with the junction 104 as a representative.

特に、第一保護層12は半導体構成の組合せ10の複数の側表面102を被覆させて形成される。これにより、第一保護層12は本発明の光起電素子1が発生させる誘発電位減衰効果を有効的に抑制させる。   In particular, the first protective layer 12 is formed by covering a plurality of side surfaces 102 of the semiconductor configuration combination 10. Thereby, the first protective layer 12 effectively suppresses the evoked potential attenuation effect generated by the photovoltaic device 1 of the present invention.

好適な実施の形態では、第一保護層12の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、或いは他の金属酸化物ないしは上述の化合物の混合物である。   In a preferred embodiment, the first protective layer 12 is composed of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, or other metal oxide or a mixture of the above compounds.

好適な実施の形態では、第一保護層12の厚さは約0.2〜100nmである。   In a preferred embodiment, the thickness of the first protective layer 12 is about 0.2-100 nm.

さらに、図1に示すように、本発明の光起電素子1は第二保護層14を更に備える。第二保護層14は第一保護層12を被覆させて形成される。   Furthermore, as shown in FIG. 1, the photovoltaic device 1 of the present invention further includes a second protective layer 14. The second protective layer 14 is formed by covering the first protective layer 12.

好適な実施の形態では、第二保護層14の構成は窒化シリコン、酸窒化シリコン、或いは上述の化合物の混合物である。   In a preferred embodiment, the second protective layer 14 is composed of silicon nitride, silicon oxynitride, or a mixture of the above compounds.

図2ないし図3は、本発明の具体的な一好ましい実施形態に係わる図1に示すような光起電素子の製造方法の断面模式図である。   2 to 3 are schematic cross-sectional views of a method for manufacturing a photovoltaic device as shown in FIG. 1 according to a specific preferred embodiment of the present invention.

まず、本発明の方法は半導体構成の組合せ10を準備し、半導体構成の組合せ10は複数の側表面102を有し、且つp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、多重接合部、或いは他の型態接合部を備える。図2では、半導体構成の組合せ10は接合部104を代表として図示する(図2参照)。   First, the method of the present invention provides a semiconductor configuration combination 10, the semiconductor configuration combination 10 having a plurality of side surfaces 102, and a pn junction, an np junction, and a pin junction. Part, nip junction, double junction, multiple junction, or other type junction. In FIG. 2, the combination 10 of the semiconductor configuration is illustrated with the junction 104 as a representative (see FIG. 2).

最後に、本発明の方法は第一保護層12を形成させ、半導体構成の組合せ10の複数の側表面102を被覆させる(図3参照)。   Finally, the method of the present invention forms the first protective layer 12 and covers the plurality of side surfaces 102 of the semiconductor configuration combination 10 (see FIG. 3).

さらに、本発明の方法は第一保護層12を被覆させる第二保護層14を形成させ、図1に示す光起電素子1の構造を完成させる。   Furthermore, the method of the present invention forms a second protective layer 14 that covers the first protective layer 12 to complete the structure of the photovoltaic device 1 shown in FIG.

以下、幾つかの範例を詳述し、本発明の光起電素子1及びその製造方法をシリコンベース光起電素子の構造及びその製造方法に実施する方法について説明する。   Hereinafter, several examples will be described in detail, and a method of implementing the photovoltaic device 1 and the manufacturing method thereof of the present invention in the structure of the silicon-based photovoltaic device and the manufacturing method thereof will be described.

図4ないし図7は、本発明の第1範例のシリコンベース光起電素子の製造方法及び構造の断面模式図である。   4 to 7 are schematic cross-sectional views of the manufacturing method and structure of the silicon-based photovoltaic device according to the first example of the present invention.

図4によれば、まず、本発明の方法は半導体構成の組合せ10を準備し、半導体構成の組合せ10は複数の側表面102、表の表面106、及び表の表面106に対する裏の表面108を有する。図4では、半導体構成の組合せ10に接合部104を代表として図示する。第一導電型態を有するシリコンベース材101を備える半導体構成の組合せ10を準備し、シリコンベース材101は単結晶シリコンベース材、擬似単結晶シリコンベース材、或いは多結晶シリコンベース材等でもよい。シリコンベース材101の厚さは約150マイクロメートル〜220マイクロメートルであり、但し、この範囲に限定されない。   According to FIG. 4, first, the method of the present invention provides a semiconductor configuration combination 10, which includes a plurality of side surfaces 102, a front surface 106, and a back surface 108 relative to the front surface 106. Have. In FIG. 4, the junction 104 is shown as a representative in the combination 10 of the semiconductor configuration. A semiconductor configuration combination 10 including a silicon base material 101 having a first conductivity type is prepared, and the silicon base material 101 may be a single crystal silicon base material, a pseudo single crystal silicon base material, a polycrystalline silicon base material, or the like. The thickness of the silicon base material 101 is about 150 to 220 micrometers, but is not limited to this range.

半導体構成の組合せ10は接合部104を更に備え、接合部104の型態は上述のとおりであり、再述はしない。   The semiconductor configuration combination 10 further includes a joint 104, and the type of the joint 104 is as described above, and will not be described again.

なお、図4に示すように、本発明の方法は表の表面106には粗化(texturing)処理が施される。即ち、表の表面106は粗化表面である。表の表面106の粗化は酸やアルカリエッチングにより、表の表面106に大きさの不均一なピラミッド型(pyramid texture)構造を形成させる。表の表面106は入光面となり、粗化された表の表面106は入射光の反射率を有効的に低下させる。   As shown in FIG. 4, in the method of the present invention, the front surface 106 is subjected to a texturing process. That is, the front surface 106 is a roughened surface. The roughening of the front surface 106 causes acid or alkali etching to form a pyramid texture structure having a non-uniform size on the front surface 106. The front surface 106 becomes a light entrance surface, and the roughened front surface 106 effectively reduces the reflectance of incident light.

よくある表面粗化技術はV字型溝部或いはピラミッド型構造を形成させ、これら粗化表面の粗度は数センチメートルから数マイクロメートルのサイズである。光起電素子に対する光電変換効率を維持するため、光起電素子の入射表面の粗度をナノメートルサイズまで高めた技術が既に開発されている。これら光起電素子の入射表面はナノスケールの柱が分布する構造になり、これらナノスケールの柱構造は非常に高い根入幅比を有する(深さ~1・m、幅~100nm)。ナノメートルサイズで粗化された入射表面を有する光起電素子は300nm〜1000nmの入射光に対し反射率を5%以下まで低下させる。
[範例1]
Common surface roughening techniques form V-shaped grooves or pyramid structures, and the roughness of these roughened surfaces is a size from a few centimeters to a few micrometers. In order to maintain the photoelectric conversion efficiency with respect to the photovoltaic element, a technique for increasing the roughness of the incident surface of the photovoltaic element to a nanometer size has already been developed. The incident surface of these photovoltaic elements has a structure in which nanoscale pillars are distributed, and these nanoscale pillar structures have a very high penetration width ratio (depth˜1 · m, width˜100 nm). A photovoltaic device having an incident surface roughened at a nanometer size reduces the reflectivity to 5% or less for incident light of 300 nm to 1000 nm.
[Example 1]

第1範例において、本発明の方法は、ドープ剤を粗化された表の表面106の一定の範囲内に添加させ、第二導電型態を有する半導体領域103を形成させ、シリコンベース光起電素子のエミッタ(emitter)とする。この好適な実施の形態では、ドープ剤はホウ素、リン、或いはヒ素等である。上述のドープ剤の添加には拡散炉(Diffusion Furnace)、スクリーン印刷、回転塗布(Spin Coating)、或いは噴射等の工程を用いて行う。   In the first example, the method of the present invention adds a dopant within a range of the roughened surface 106 to form a semiconductor region 103 having a second conductivity type, and to form a silicon-based photovoltaic. The emitter of the element. In this preferred embodiment, the dopant is boron, phosphorus, arsenic, or the like. The doping agent is added using a diffusion furnace, screen printing, spin coating, spraying, or the like.

好適な実施の形態では、シリコンベース材101はp型態であり、半導体領域103はn型態である。ほかの好適な実施の形態では、シリコンベース材101はn型態であり、半導体領域103はp型態である。   In a preferred embodiment, the silicon base material 101 is p-type and the semiconductor region 103 is n-type. In another preferred embodiment, the silicon base material 101 is n-type and the semiconductor region 103 is p-type.

次は本発明の第1範例の方法は第一保護層12を形成させ、半導体構成の組合せ10の複数の側表面102を被覆させる。また、本発明の第1範例の方法は第一保護層12を表の表面106の辺縁まで延出させ、且つ第一保護層12を裏の表面108の辺縁まで延出させる(図5参照)。   Next, the method of the first example of the present invention forms the first protective layer 12 and coats the plurality of side surfaces 102 of the semiconductor configuration combination 10. The first exemplary method of the present invention also extends the first protective layer 12 to the edge of the front surface 106 and extends the first protective layer 12 to the edge of the back surface 108 (FIG. 5). reference).

好適な実施の形態では、第一保護層12が表の表面106の辺縁まで延出される幅は約0.1mm〜100mmの間であり、第一保護層12が裏の表面108の辺縁まで延出される幅は約0.1mm〜100mmの間であるが、但しこれらに制限されない。第一保護層12の厚さは上述の通りであり、再述は省く。   In a preferred embodiment, the width that the first protective layer 12 extends to the edge of the front surface 106 is between about 0.1 mm and 100 mm, and the first protective layer 12 is the edge of the back surface 108. The width extended to about 0.1 mm to 100 mm is not limited thereto. The thickness of the first protective layer 12 is as described above, and the re-description is omitted.

続いて、好適な実施の形態では、第一保護層12の形成はプラズマCVD(plasma-enhanced chemical vapor deposition、 PECVD)工程、大気圧CVD(atmospheric pressure chemical vapor deposition、 APCVD)工程、有機金属気相成長法(metalorganic chemical vapor deposition、 MOCVD)工程、原子層堆積法(atomic layer deposition、 ALD)工程、或いは物理気相成長(physical vapor deposition、 PVD)工程等により実行される。   Subsequently, in a preferred embodiment, the first protective layer 12 is formed by plasma CVD (plasma-enhanced chemical vapor deposition (PECVD)), atmospheric pressure chemical vapor deposition (APCVD), It is performed by a growth method (metalorganic chemical vapor deposition (MOCVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or the like.

第一保護層12が続いて形成される電極中の金属元素により汚染されるのを回避させるため、本発明の第1範例の方法は第二保護層14を更に形成させて第一保護層12を被覆させる。第二保護層14の構成は上述の通りであり、再述はしない(図5参照)。   In order to avoid contamination of the first protective layer 12 by the metallic elements in the electrode subsequently formed, the method of the first example of the present invention further forms a second protective layer 14 to form the first protective layer 12. To coat. The configuration of the second protective layer 14 is as described above and will not be described again (see FIG. 5).

また、本発明の第1範例の方法は反射防止層16を表の表面106に形成させ、表の表面106の辺縁の第一保護層12を被覆させて延出させる。好適な実施の形態では、反射防止層16の形成には化学気相成長(CVD)工程、或いは物理気相成長(PVD)工程により実行する。このほか、反射防止層16はシリコンベース光起電素子1の表面のキャリアの複合速度を低下させる以外、更に光電流を高め、シリコンベース光起電素子1の保護(例えば、防傷、防湿)等の効果を達成させる(図6参照)。   In the first exemplary method of the present invention, the antireflection layer 16 is formed on the front surface 106, and the first protective layer 12 on the edge of the front surface 106 is covered and extended. In a preferred embodiment, the antireflection layer 16 is formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. In addition, the antireflection layer 16 further increases the photocurrent and reduces the composite current of carriers on the surface of the silicon-based photovoltaic element 1 to protect the silicon-based photovoltaic element 1 (for example, scratch and moisture). Etc. (see FIG. 6).

なお、本発明の第1範例の方法は正極17を表の表面106上の反射防止層16に形成させ、表の表面106と共にオーム接触(Ohmic contact)を形成させる。この好適な実施の形態では、正極17は所定の金属ペースト(例えば、銀ペースト(silver paste))を表の表面106に局部スクリーン印刷或いは塗布し、焼結させて完成させる。焼結過程では、銀ペースト中のガラス粉末に反射防止層16及び表の表面106のシリコンを貫通させて接触を形成させ、正極17と表の表面106とにオーム接触を形成させる。ほかの好適な実施の形態では、本発明の第1範例の方法は反射防止層16上に溝部を形成させ、溝部内の表の表面106を外に露出させ、正極17を溝部内に形成させて外に露出される表の表面106を被覆させてもよい(図7参照)。   In the first exemplary method of the present invention, the positive electrode 17 is formed on the antireflection layer 16 on the front surface 106, and an ohmic contact is formed together with the front surface 106. In this preferred embodiment, the positive electrode 17 is completed by local screen printing or application of a predetermined metal paste (eg, silver paste) to the front surface 106 and sintering. In the sintering process, the glass powder in the silver paste is penetrated by the silicon of the antireflection layer 16 and the front surface 106 to form a contact, and an ohmic contact is formed between the positive electrode 17 and the front surface 106. In another preferred embodiment, the method of the first example of the present invention forms a groove on the antireflection layer 16, exposes the front surface 106 in the groove, and forms the positive electrode 17 in the groove. The front surface 106 exposed to the outside may be coated (see FIG. 7).

次に本発明の第1範例の方法は、少なくとも1つの裏面バス電極18を裏の表面108に形成させる(図7参照)。   The first exemplary method of the present invention then forms at least one backside bus electrode 18 on the backside surface 108 (see FIG. 7).

最後に、本発明の第1範例の方法は、バック接点19を裏の表面108に形成させて裏の表面108を被覆させ、少なくとも1つの裏面バス電極18以外の領域を形成させ、シリコンベース光起電素子1を完成させる。この好適な実施の形態では、正極17、少なくとも1つの裏面バス電極18、及びバック接点19は所定の金属ペーストを反射防止層16及び裏の表面108に局部スクリーン印刷(Sreen print)或いは塗布し、共燃焼(co-firing)工程により570℃〜840℃の温度で焼結させて完成させる。続いて、シリコンベース光起電素子1は装設されてモジュール化される。前記モジュールの使用中、半導体構成の組合せ10の複数の側表面102を被覆させる第一保護層12は封装材料(通常はエチレン酢酸ビニル(ethylene-vinyl acetate、 EVA)或いはガラス板)に累積される電荷を第一保護層12の表面に沿わせて第一導電型態を有するシリコンベース材101に導入させる。これにより、第一保護層12は本発明のシリコンベース光起電素子1が発生させる誘発電位減衰効果、特にシリコンベース光起電素子1の側表面102から発せられる誘発電位減衰効果を有効的に抑制させる。
[範例2]
Finally, the first exemplary method of the present invention causes the back contact 19 to be formed on the back surface 108 to cover the back surface 108 to form regions other than the at least one backside bus electrode 18 to form a silicon-based optical The electromotive element 1 is completed. In this preferred embodiment, the positive electrode 17, the at least one backside bus electrode 18, and the back contact 19 apply a predetermined metal paste to the antireflection layer 16 and the back surface 108 by local screen printing (Sreen print). It is completed by sintering at a temperature of 570 ° C. to 840 ° C. by a co-firing process. Subsequently, the silicon-based photovoltaic element 1 is installed and modularized. During use of the module, the first protective layer 12 that covers the plurality of side surfaces 102 of the semiconductor component combination 10 is accumulated in a sealing material (usually ethylene-vinyl acetate (EVA) or glass plate). Electric charges are introduced along the surface of the first protective layer 12 into the silicon base material 101 having the first conductivity type. As a result, the first protective layer 12 effectively exhibits the induced potential attenuation effect generated by the silicon-based photovoltaic device 1 of the present invention, particularly the induced potential attenuation effect emitted from the side surface 102 of the silicon-based photovoltaic device 1. Let it be suppressed.
[Example 2]

図8及び図9は断面模式図により本発明の第2範例のシリコンベース光起電素子の製造方法及びその構造を図示する。   8 and 9 illustrate a method for manufacturing a silicon-based photovoltaic device according to the second example of the present invention and the structure thereof by way of schematic cross-sectional views.

本発明の第2範例の製造方法は本発明の第1範例の製造方法と大方類似するため、以下では本発明の第1範例の製造方法と異なる部分のみについて説明する。図8を示すように、本発明の第2範例の製造方法は第一保護層12を延出させて表の表面106を被覆させ、第一保護層12を裏の表面108の辺縁まで延出させる。   Since the manufacturing method of the second example of the present invention is almost similar to the manufacturing method of the first example of the present invention, only parts different from the manufacturing method of the first example of the present invention will be described below. As shown in FIG. 8, the manufacturing method of the second example of the present invention extends the first protective layer 12 to cover the front surface 106, and extends the first protective layer 12 to the edge of the back surface 108. Let it come out.

本発明の第2範例の製造方法は、反射防止層16を形成させて表の表面106を覆う第一保護層12を被覆させる。同様に図8に示すように、本発明の第2範例の製造方法は、第二保護層14を形成させて第一保護層12を被覆させる(図8参照)。   In the manufacturing method of the second example of the present invention, the first protective layer 12 that covers the front surface 106 is formed by forming the antireflection layer 16. Similarly, as shown in FIG. 8, in the manufacturing method of the second example of the present invention, the second protective layer 14 is formed to cover the first protective layer 12 (see FIG. 8).

最後に、図9を示すように、本発明の第2範例の製造方法は正極17を反射防止層16に形成させ、表の表面106と共にオーム接触を形成させる。また、本発明の第2範例の製造方法は少なくとも1つの裏面バス電極18を裏の表面108に形成させ、バック接点19を裏の表面108に形成させて裏の表面108を被覆させることで前記少なくとも1つの裏面バス電極18以外の領域を形成させ、シリコンベース光起電素子1を完成させる。具体的な実施例は、本発明の第2範例の方法は、焼結過程中に銀ペースト中のガラス粉末が反射防止層16及び表の表面106のシリコンを貫通させて接触を形成させ、正極17と表の表面106とがオーム接触を形成させる。他の具体な実施例では、本発明の第2範例の方法は反射防止層16及び第一保護層12に溝部を形成させ、溝部内の表の表面106を外に露出させ、正極17を溝部内に形成させて外に露出される表の表面106を被覆させる。
[範例3]
Finally, as shown in FIG. 9, the second exemplary manufacturing method of the present invention forms the positive electrode 17 on the antireflection layer 16 and forms an ohmic contact with the front surface 106. In the second exemplary manufacturing method of the present invention, at least one back surface bus electrode 18 is formed on the back surface 108, a back contact 19 is formed on the back surface 108, and the back surface 108 is coated. Regions other than the at least one backside bus electrode 18 are formed to complete the silicon-based photovoltaic device 1. In a specific embodiment, the method of the second example of the present invention is such that the glass powder in the silver paste penetrates the antireflection layer 16 and the silicon on the front surface 106 during the sintering process to form a contact. 17 and the front surface 106 form an ohmic contact. In another specific embodiment, the method of the second exemplary embodiment of the present invention causes grooves to be formed in the antireflection layer 16 and the first protective layer 12, the front surface 106 in the grooves is exposed to the outside, and the positive electrode 17 is exposed to the grooves. A front surface 106 formed inside and exposed outside is coated.
[Example 3]

図10及び図11では断面模式図を用いて本発明の第3範例のシリコンベース光起電素子の製造方法及び構造を図示する。   10 and 11 illustrate a method and a structure for manufacturing a silicon-based photovoltaic device according to the third example of the present invention, using schematic cross-sectional views.

本発明の第3範例の製造方法は本発明の第1範例の製造方法に大方類似するため、以下では本発明の第1範例の製造方法と異なる部分のみ説明する。本発明の第3範例の製造方法は前記第一保護層12を表の表面106の辺縁まで延出させ、且つ第一保護層12を延出させることで裏の表面108を被覆させる(図10参照)。   Since the manufacturing method of the third example of the present invention is almost similar to the manufacturing method of the first example of the present invention, only parts different from the manufacturing method of the first example of the present invention will be described below. In the manufacturing method of the third example of the present invention, the first protective layer 12 is extended to the edge of the front surface 106, and the first protective layer 12 is extended to cover the back surface 108 (see FIG. 10).

図10を示すように、本発明の第3範例の製造方法は、反射防止層16を表の表面106に形成させ、表の表面106の辺縁の第一保護層12を被覆させて延出させる。同様に図10に示すように、本発明の第3範例の製造方法は第二保護層14を形成させて第一保護層12を被覆させる。   As shown in FIG. 10, in the manufacturing method of the third example of the present invention, the antireflection layer 16 is formed on the front surface 106, and the first protective layer 12 on the edge of the front surface 106 is covered and extended. Let Similarly, as shown in FIG. 10, in the third exemplary manufacturing method of the present invention, the second protective layer 14 is formed to cover the first protective layer 12.

続いて、本発明の第3範例の製造方法は、少なくとも1つの裏面バス電極18を第一保護層12に形成させ、少なくとも1つの裏面バス電極18と裏の表面108とによりオーム接触を形成させる。図10によれば、本発明の第3範例の製造方法は裏の表面108を被覆させる第一保護層12に少なくとも1つの溝部122を形成させ、少なくとも1つの溝部122内の裏の表面108は外に露出される。次は、図11を示すように、本発明の第3範例の製造方法は、少なくとも1つの裏面バス電極18を少なくとも1つの溝部122内に形成させて外に露出される裏の表面108を被覆させる。本発明の第3範例の製造方法では溝部122を形成せず、焼結過程で銀ペースト中のガラス粉末が第一保護層12及び裏の表面108のシリコンを貫通させて接触を形成させ、少なくとも1つの裏面バス電極18と裏の表面108とがオーム接触を形成させてもよい。   Subsequently, in the manufacturing method of the third example of the present invention, at least one back surface bus electrode 18 is formed on the first protective layer 12, and ohmic contact is formed between the at least one back surface bus electrode 18 and the back surface 108. . Referring to FIG. 10, the third exemplary manufacturing method of the present invention causes at least one groove 122 to be formed in the first protective layer 12 covering the back surface 108, and the back surface 108 in the at least one groove 122 is Exposed outside. Next, as shown in FIG. 11, the manufacturing method according to the third example of the present invention covers the back surface 108 exposed to the outside by forming at least one back surface bus electrode 18 in at least one groove 122. Let In the manufacturing method of the third example of the present invention, the groove 122 is not formed, and the glass powder in the silver paste penetrates the silicon of the first protective layer 12 and the back surface 108 during the sintering process to form a contact. One back bus electrode 18 and the back surface 108 may form an ohmic contact.

最後は、本発明の第3範例の製造方法は正極17を反射防止層16に形成させ、表の表面106と共にオーム接触を形成させる。本発明の第3範例の製造方法は、少なくとも1つの裏面バス電極18を形成させ、またバック接点19を形成させて裏の表面108を覆う第一保護層12を被覆させ、少なくとも1つの裏面バス電極18は被覆させず、シリコンベース光起電素子1を完成させる(図11参照)。この好適な実施の形態では、本発明の第3範例の方法は、焼結過程中に銀ペースト中のガラス粉末が反射防止層16、第一保護層12、及び表の表面106のシリコンを貫通させて接触を形成させ、正極17と表の表面106とによりオーム接触が形成される。なお、ほかの好適な実施の形態では、本発明の第3範例の方法は、反射防止層16と第一保護層12とにより溝部が形成され、溝部内の表の表面106は外に露出され、正極17は溝部内に形成されて外に露出される表の表面106を被覆させる。
[範例4]
Finally, in the third exemplary manufacturing method of the present invention, the positive electrode 17 is formed on the antireflection layer 16 and an ohmic contact is formed with the front surface 106. The manufacturing method of the third example of the present invention forms at least one back surface bus electrode 18, forms a back contact 19 and covers the first protective layer 12 covering the back surface 108, and forms at least one back surface bus. The electrode 18 is not covered, and the silicon-based photovoltaic element 1 is completed (see FIG. 11). In this preferred embodiment, the third exemplary method of the present invention is such that the glass powder in the silver paste penetrates the antireflective layer 16, the first protective layer 12, and the silicon on the front surface 106 during the sintering process. Thus, contact is formed, and ohmic contact is formed by the positive electrode 17 and the front surface 106. In another preferred embodiment, in the method of the third example of the present invention, a groove is formed by the antireflection layer 16 and the first protective layer 12, and the front surface 106 in the groove is exposed to the outside. The positive electrode 17 is formed in the groove and covers the front surface 106 exposed to the outside.
[Example 4]

図12及び図13では断面模式図により本発明の第4範例のシリコンベース光起電素子の製造方法及び構造を図示する。   FIGS. 12 and 13 illustrate a method and structure for manufacturing a silicon-based photovoltaic device according to the fourth example of the present invention by using schematic cross-sectional views.

本発明の第4範例の製造方法は本発明の第1範例の製造方法に大方類似するため、以下では本発明の第1範例の製造方法と異なる部分のみ説明する。本発明の第4範例の製造方法は、第一保護層12が延出されて表の表面106を被覆させ、且つ第一保護層12が延出されて裏の表面108を被覆させる(図12参照)。   Since the manufacturing method of the fourth example of the present invention is almost similar to the manufacturing method of the first example of the present invention, only parts different from the manufacturing method of the first example of the present invention will be described below. In the manufacturing method of the fourth example of the present invention, the first protective layer 12 is extended to cover the front surface 106, and the first protective layer 12 is extended to cover the back surface 108 (FIG. 12). reference).

同様に、図12を示すように、本発明の第4範例の製造方法は、反射防止層16が形成されて表の表面106を覆う第一保護層12を被覆させる。同様に図12に図示するように、本発明の第4範例の製造方法は第二保護層14が形成されて第一保護層12を被覆させる。   Similarly, as shown in FIG. 12, the manufacturing method according to the fourth example of the present invention covers the first protective layer 12 on which the antireflection layer 16 is formed and covers the front surface 106. Similarly, as illustrated in FIG. 12, in the manufacturing method of the fourth example of the present invention, the second protective layer 14 is formed to cover the first protective layer 12.

続いて、本発明の第4範例の製造方法は、少なくとも1つの裏面バス電極18が第一保護層12に形成され、少なくとも1つの裏面バス電極18と裏の表面108とによりオーム接触が形成される。例えば、図12に示す本発明の第4範例の製造方法は、裏の表面108を被覆させる第一保護層12には少なくとも1つの溝部122が形成され、少なくとも1つの溝部122内の裏の表面108は外に露出される。次は、本発明の第4範例の製造方法は、少なくとも1つの裏面バス電極18が少なくとも1つの溝部122内に形成され、外に露出される裏の表面108を被覆させる。本発明の第4範例の製造方法では、溝部122が形成されず、焼結過程中に銀ペースト中のガラス粉末が第一保護層12及び裏の表面108のシリコンを貫通させて接触を形成させ、少なくとも1つの裏面バス電極18と裏の表面108とによりオーム接触が形成されてもよい(図13参照)。   Subsequently, in the manufacturing method of the fourth example of the present invention, at least one back surface bus electrode 18 is formed on the first protective layer 12, and at least one back surface bus electrode 18 and the back surface 108 form ohmic contact. The For example, in the manufacturing method of the fourth example of the present invention shown in FIG. 12, at least one groove 122 is formed in the first protective layer 12 covering the back surface 108, and the back surface in the at least one groove 122 is formed. 108 is exposed to the outside. Next, in the manufacturing method of the fourth example of the present invention, at least one back surface bus electrode 18 is formed in at least one groove portion 122 to cover the back surface 108 exposed outside. In the manufacturing method of the fourth example of the present invention, the groove 122 is not formed, and the glass powder in the silver paste penetrates the silicon of the first protective layer 12 and the back surface 108 during the sintering process to form a contact. The ohmic contact may be formed by the at least one back surface bus electrode 18 and the back surface 108 (see FIG. 13).

図13を示すように、最後に、本発明の第4範例の製造方法は、正極17が反射防止層16に形成され、表の表面106と共にオーム接触を形成させる。本発明の第4範例の製造方法は、少なくとも1つの裏面バス電極18が形成され、バック接点19が形成されて裏の表面108を覆う第一保護層12を被覆させ、少なくとも1つの裏面バス電極18は被覆されず、シリコンベース光起電素子1を完成させる。好適な実施の形態では、本発明の第4範例の方法は、焼結過程で銀ペースト中のガラス粉末が反射防止層16、第一保護層12、及び表の表面106のシリコンを貫通させて接触を形成させ、正極17と表の表面106とによりオーム接触が形成される。また、ほかの好適な実施の形態では、本発明の第4範例の方法は、反射防止層16及び第一保護層12には溝部が形成され、溝部内の表の表面106は外に露出され、正極17は溝部内に形成されて外に露出される表の表面106を被覆させる。   As shown in FIG. 13, finally, according to the manufacturing method of the fourth example of the present invention, the positive electrode 17 is formed on the antireflection layer 16 to form an ohmic contact with the front surface 106. In the manufacturing method of the fourth example of the present invention, at least one back surface bus electrode 18 is formed, a back contact 19 is formed and the first protective layer 12 covering the back surface 108 is coated, and at least one back surface bus electrode is formed. 18 is not coated, completing the silicon-based photovoltaic element 1. In a preferred embodiment, the fourth exemplary method of the present invention is such that the glass powder in the silver paste penetrates the antireflective layer 16, the first protective layer 12, and the silicon on the front surface 106 during the sintering process. A contact is formed and an ohmic contact is formed by the positive electrode 17 and the front surface 106. In another preferred embodiment, according to the method of the fourth example of the present invention, a groove is formed in the antireflection layer 16 and the first protective layer 12, and the front surface 106 in the groove is exposed to the outside. The positive electrode 17 is formed in the groove and covers the front surface 106 exposed to the outside.

以下には数例のAシリコンベース光起電素子、数例のBシリコンベース光起電素子、及び数例のCシリコンベース光起電素子に関するPIDの測定結果を例示する。Aシリコンベース光起電素子は本発明の第3範例の方法により製造されたシリコン結晶光起電素子であり、構造は図11に示す。Bシリコンベース光起電素子は従来の技術によりSiN反射防止層の屈折率を調整させPID効果の抑制を達成させる。Cシリコンベース光起電素子は一般的なシリコンベース光起電素子によりPID効果を抑制させない設計となっている。本発明で採用するPID測定方法は、シリコンベース光起電素子が装設される装設モジュールにPID測定を行い、測定条件は、温度85℃、湿度為85%RH、測定時間96時間である。 The following are examples of PID measurement results for several A silicon based photovoltaic elements, several B silicon based photovoltaic elements, and several C silicon based photovoltaic elements. The A silicon-based photovoltaic device is a silicon crystal photovoltaic device manufactured by the method of the third example of the present invention, and the structure is shown in FIG. The B silicon-based photovoltaic device achieves suppression of the PID effect by adjusting the refractive index of the SiN X antireflection layer by conventional techniques. C silicon-based photovoltaic elements are designed not to suppress the PID effect by typical silicon-based photovoltaic elements. The PID measurement method employed in the present invention performs PID measurement on an installation module on which a silicon-based photovoltaic element is installed. The measurement conditions are a temperature of 85 ° C., a humidity of 85% RH, and a measurement time of 96 hours. .

表1はAシリコンベース光起電素子、Bシリコンベース光起電素子、及びCシリコンベース光起電素子を表示し、また、PID測定後の初期光電変換効率、測定後の光電変換効率、減衰率、及び分路抵抗(shunt resistance、 Rshunt)を表示する。分路抵抗の定義はシリコンベース光起電素子の漏電の大きさであり、つまり、分路抵抗が大きいと漏電が小さくなる。表1のデータはAシリコンベース光起電素子及びBシリコンベース光起電素子の光電変換効率が皆Cシリコンベース光起電素子より高いことを証明しており、皆PID効果を有効的に抑制する。Cシリコンベース光起電素子の減衰幅は非常に大きく、分路抵抗が非常に低い。Bシリコンベース光起電素子は反射防止層自体の効果を犠牲にし、Bシリコンベース光起電素子の光電変換効率はAシリコンベース光起電素子の光電変換効率より低く、減衰率はAシリコンベース光起電素子の減衰率より高く、分路抵抗はAシリコンベース光起電素子の分路抵抗より低い。本発明の光起電素子がPID効果を抑制させる効果は従来の技術によるPID効果の抑制効果よりも明らかに優れている。更に、本発明の光起電素子及びその製造方法は様々な型態の光起電素子に広く応用可能である。

Figure 0005931942
Table 1 shows A silicon-based photovoltaic elements, B silicon-based photovoltaic elements, and C silicon-based photovoltaic elements, and also shows initial photoelectric conversion efficiency after PID measurement, photoelectric conversion efficiency after measurement, and attenuation. Displays the rate and shunt resistance (Rshunt). The definition of shunt resistance is the magnitude of the leakage of a silicon-based photovoltaic element, that is, the leakage is reduced when the shunt resistance is large. The data in Table 1 proves that the photoelectric conversion efficiencies of the A silicon-based photovoltaic element and the B silicon-based photovoltaic element are all higher than those of the C silicon-based photovoltaic element, and all effectively suppress the PID effect. To do. The attenuation width of C silicon-based photovoltaic elements is very large and the shunt resistance is very low. The B silicon-based photovoltaic element sacrifices the effect of the antireflection layer itself, the photoelectric conversion efficiency of the B silicon-based photovoltaic element is lower than the photoelectric conversion efficiency of the A silicon-based photovoltaic element, and the attenuation rate is A silicon-based It is higher than the attenuation factor of the photovoltaic element, and the shunt resistance is lower than that of the A silicon-based photovoltaic element. The effect of the photovoltaic element of the present invention to suppress the PID effect is clearly superior to that of the conventional technique. Furthermore, the photovoltaic device and the manufacturing method thereof of the present invention can be widely applied to various types of photovoltaic devices.
Figure 0005931942

以上、本発明の実施形態について図面を参照して詳述したが、具体的な構成はこの実施形態に限られるものではなく、本発明の要旨を逸脱しない範囲の設計変更等も含まれる。
なお、本願明細書に記載の実施形態によれば、以下の構成もまた開示される。
[項目1]
複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、
前記複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層を備えることを特徴とする光起電素子。
[項目2]
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする、項目1に記載の光起電素子。
[項目3]
前記第一保護層を被覆させて形成される第二保護層を更に備え、前記第二保護層の構成は窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする、項目2に記載の光起電素子。
[項目4]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面の辺縁まで延出されると共に前記裏の表面の辺縁まで延出され、
前記光起電素子は、
前記表の表面に形成されると共に前記表の表面の辺縁の前記第一保護層を被覆させて延出される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記裏の表面に形成される少なくとも1つの裏面バス電極と、
前記裏の表面に形成されると共に前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させるバック接点を更に備えることを特徴とする、項目2または3に記載の光起電素子。
[項目5]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面を被覆させて延出され、且つ前記裏の表面の辺縁まで延出され、
前記光起電素子は、
前記表の表面を覆う前記第一保護層を被覆させて形成される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記裏の表面に形成される少なくとも1つの裏面バス電極と、
前記裏の表面に形成されると共に前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させるバック接点を更に備えることを特徴とする、項目2から4の何れか1項に記載の光起電素子。
[項目6]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面の辺縁まで延出され、且つ前記裏の表面を被覆させて延出され、
前記光起電素子は、
前記表の表面に形成されると共に前記表の表面の辺縁の前記第一保護層を被覆させて延出される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記第一保護層に形成され、前記裏の表面と共にオーム接触を形成させる少なくとも1つの裏面バス電極と、
前記第一保護層を被覆させて形成され且つ前記少なくとも1つの裏面バス電極を被覆させないバック接点を更に備えることを特徴とする、項目2から5の何れか1項に記載の光起電素子。
[項目7]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面を被覆させて延出され、且つ前記裏の表面を被覆させて延出され、また、前記光起電素子は、
前記表の表面を被覆させる前記第一保護層を被覆させて形成される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記第一保護層に形成され、前記裏の表面と共にオーム接触を形成させる少なくとも1つの裏面バス電極と、
前記第一保護層を被覆させて形成され且つ前記少なくとも1つの裏面バス電極は被覆させないバック接点を更に備えることを特徴とする、項目2から6の何れか1項に記載の光起電素子。
[項目8]
半導体構成の組合せは複数の側表面を有すると共にp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部からなる、半導体構成の組合せの準備工程と、
前記複数の側表面を被覆させ、且つ光起電素子が発生させる誘発電位減衰効果を抑制させる第一保護層を形成させる工程を含むことを特徴とする光起電素子の製造方法。
[項目9]
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする、項目8に記載の光起電素子の製造方法。
[項目10]
前記第一保護層を被覆させ、窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される、第二保護層を形成させてる工程を更に含むことを特徴とする、項目9に記載の光起電素子の製造方法。
[項目11]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を前記表の表面の辺縁まで延出させ、且つ前記第一保護層を前記裏の表面の辺縁まで延出させる工程と、
反射防止層を前記表の表面に形成させ、前記表の表面の辺縁の前記第一保護層を被覆させて延出させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記裏の表面に形成させる工程と、
バック接点を前記裏の表面に形成させ、前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させる工程を更に含むことを特徴とする、項目9または10に記載の光起電素子の製造方法。
[項目12]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を延出させて前記表の表面を被覆させ、前記第一保護層を前記裏の表面の辺縁まで延出させる工程と、
反射防止層を形成させて前記表の表面を被覆させる前記第一保護層を被覆させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記裏の表面に形成させる工程と、
バック接点を前記裏の表面に形成させ、前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させる工程を更に含むことを特徴とする、項目9から11の何れか1項に記載の光起電素子の製造方法。
[項目13]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を前記表の表面の辺縁まで延出させ、且つ前記第一保護層を延出させて前記裏の表面を被覆させる工程と、
反射防止層を前記表の表面に形成させ、前記表の表面の辺縁の前記第一保護層を被覆させて延出させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記第一保護層に形成させ、前記少なくとも1つの裏面バス電極と前記裏の表面と共にオーム接触を形成させる工程と、
バック接点を形成させて前記第一保護層を被覆させ、前記少なくとも1つの裏面バス電極は被覆させない工程を更に含むことを特徴とする、項目9から12の何れか1項に記載の光起電素子の製造方法。
[項目14]
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を延出させて前記表の表面を被覆させ、且つ前記第一保護層を延出させて前記裏の表面を被覆させる工程と、
反射防止層を形成させて前記表の表面を被覆させる前記第一保護層を被覆させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記第一保護層に形成させ、前記少なくとも1つの裏面バス電極と前記裏の表面と共にオーム接触を形成させる工程と、
バック接点を形成させて前記第一保護層を被覆させ、前記少なくとも1つの裏面バス電極は被覆させない工程を更に含むことを特徴とする、項目9から13の何れか1項に記載の光起電素子の製造方法。
As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.
In addition, according to embodiment described in this-application specification, the following structures are also disclosed.
[Item 1]
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction A combination of semiconductor configurations including any one junction selected from:
A photovoltaic device comprising a first protective layer formed by covering the plurality of side surfaces and for suppressing an induced potential attenuation effect generated by the photovoltaic device.
[Item 2]
Item 1 is characterized in that the configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds. The photovoltaic element as described in.
[Item 3]
A second protective layer formed by covering the first protective layer, wherein the second protective layer has any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above-mentioned compounds; The photovoltaic element according to item 2, wherein the photovoltaic element is selected from the group consisting of:
[Item 4]
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is subjected to a roughening treatment, and the first protective layer extends to the edge of the front surface. Extended to the edge of the back surface,
The photovoltaic element is
An antireflection layer formed on the surface of the front surface and extending by covering the first protective layer on the edge of the front surface of the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one back surface bus electrode formed on the back surface;
4. The photovoltaic device according to item 2 or 3, further comprising a back contact formed on the back surface and covering the back surface to form a region other than the at least one back bus electrode. Electric element.
[Item 5]
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is roughened, and the first protective layer covers the front surface. Extended to the edge of the back surface,
The photovoltaic element is
An antireflection layer formed by covering the first protective layer covering the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one back surface bus electrode formed on the back surface;
Any one of items 2 to 4, further comprising a back contact formed on the back surface and covering the back surface to form a region other than the at least one back bus electrode. The photovoltaic element as described in.
[Item 6]
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is subjected to a roughening treatment, and the first protective layer extends to the edge of the front surface. Extended and covered with the back surface,
The photovoltaic element is
An antireflection layer formed on the surface of the front surface and extending by covering the first protective layer on the edge of the front surface of the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one backside bus electrode formed on the first protective layer and forming an ohmic contact with the backside surface;
The photovoltaic device according to any one of items 2 to 5, further comprising a back contact formed by covering the first protective layer and not covering the at least one backside bus electrode.
[Item 7]
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is roughened, and the first protective layer covers the front surface. Extending and covering the back surface, and the photovoltaic element is
An antireflection layer formed by coating the first protective layer covering the surface of the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one backside bus electrode formed on the first protective layer and forming an ohmic contact with the backside surface;
The photovoltaic device according to any one of items 2 to 6, further comprising a back contact formed by covering the first protective layer and not covering the at least one backside bus electrode.
[Item 8]
The combination of semiconductor configurations has multiple side surfaces and includes a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A step of preparing a combination of semiconductor configurations, comprising any one junction selected from the group to be configured;
A method of manufacturing a photovoltaic device, comprising: forming a first protective layer that covers the plurality of side surfaces and suppresses an induced potential attenuation effect generated by the photovoltaic device.
[Item 9]
Item 8 is characterized in that the configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds. The manufacturing method of the photovoltaic element of description.
[Item 10]
Coating the first protective layer and forming a second protective layer selected from any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above compounds 10. The method for producing a photovoltaic element according to item 9, comprising:
[Item 11]
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to the edge of the front surface and extending the first protective layer to the edge of the back surface;
Forming an antireflection layer on the front surface, covering and extending the first protective layer on the edge of the front surface; and
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the backside surface;
Item 11. The light according to item 9 or 10, further comprising a step of forming a back contact on the back surface and covering the back surface to form a region other than the at least one backside bus electrode. Manufacturing method of electromotive element.
[Item 12]
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to cover the front surface, and extending the first protective layer to the edge of the back surface;
Coating the first protective layer to form an antireflection layer to cover the front surface;
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the backside surface;
Any one of items 9 to 11, further comprising a step of forming a back contact on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode. The manufacturing method of the photovoltaic element of description.
[Item 13]
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to the edge of the front surface, and extending the first protective layer to cover the back surface;
Forming an antireflection layer on the front surface, covering and extending the first protective layer on the edge of the front surface; and
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the first protective layer and forming an ohmic contact with the at least one backside bus electrode and the back surface;
13. The photovoltaic device of any one of items 9 to 12, further comprising the step of forming a back contact to cover the first protective layer and not to cover the at least one backside bus electrode. Device manufacturing method.
[Item 14]
The combination of semiconductor configurations further comprises a front surface and a back surface relative to the front surface;
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to cover the front surface, and extending the first protective layer to cover the back surface;
Coating the first protective layer to form an antireflection layer to cover the front surface;
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the first protective layer and forming an ohmic contact with the at least one backside bus electrode and the back surface;
14. The photovoltaic device of any one of items 9 to 13, further comprising a step of forming a back contact to cover the first protective layer and not to cover the at least one backside bus electrode. Device manufacturing method.

1 光起電素子
10 半導体構成の組合せ
101 シリコンベース材
102 側表面
103 半導体領域
104 接合部
106 表の表面
108 裏の表面
12 第一保護層
122 溝部
14 第二保護層
16 反射防止層
17 正極
18 裏面バス電極
19 バック接点
DESCRIPTION OF SYMBOLS 1 Photovoltaic element 10 Combination of semiconductor structure 101 Silicon base material 102 Side surface 103 Semiconductor region 104 Joint part 106 Front surface 108 Back surface 12 First protective layer 122 Groove part 14 Second protective layer 16 Antireflection layer 17 Positive electrode 18 Back bus electrode 19 Back contact

Claims (8)

複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、
前記複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層と
を備え、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面の辺縁まで延出されると共に前記裏の表面の辺縁まで延出され、
前記光起電素子は、
前記表の表面に接して形成されると共に前記表の表面の辺縁の前記第一保護層を被覆させて延出される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記裏の表面に形成される少なくとも1つの裏面バス電極と、
前記裏の表面に形成されると共に前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させるバック接点を更に備え、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させて形成される第二保護層を更に備え、前記第二保護層の構成は窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする光起電素子。
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction A combination of semiconductor configurations including any one junction selected from:
A first protective layer formed by covering the plurality of side surfaces and for suppressing an evoked potential attenuation effect generated by the photovoltaic element;
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is subjected to a roughening treatment, and the first protective layer extends to the edge of the front surface. Extended to the edge of the back surface,
The photovoltaic element is
An antireflection layer that is formed in contact with the surface of the table and extends to cover the first protective layer on the edge of the surface of the table;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one back surface bus electrode formed on the back surface;
A back contact formed on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
A second protective layer formed by covering the first protective layer, wherein the second protective layer has any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above-mentioned compounds; photovoltaic element characterized Rukoto selected either from one.
複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、
前記複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層と
を備え、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面を被覆させて延出され、且つ前記裏の表面の辺縁まで延出され、
前記光起電素子は、
前記表の表面を覆う前記第一保護層を被覆させて形成される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記裏の表面に形成される少なくとも1つの裏面バス電極と、
前記裏の表面に形成されると共に前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させるバック接点を更に備え、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させて形成される第二保護層を更に備え、前記第二保護層の構成は窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする光起電素子。
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction A combination of semiconductor configurations including any one junction selected from:
A first protective layer formed by covering the plurality of side surfaces and for suppressing an evoked potential attenuation effect generated by the photovoltaic element;
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is roughened, and the first protective layer covers the front surface. Extended to the edge of the back surface,
The photovoltaic element is
An antireflection layer formed by covering the first protective layer covering the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one back surface bus electrode formed on the back surface;
A back contact formed on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
A second protective layer formed by covering the first protective layer, wherein the second protective layer has any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above-mentioned compounds; photovoltaic element characterized Rukoto selected either from one.
複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、
前記複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層と
を備え、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面の辺縁まで延出され、且つ前記裏の表面を被覆させて延出され、
前記光起電素子は、
前記表の表面に形成されると共に前記表の表面の辺縁の前記第一保護層を被覆させて延出される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記第一保護層に形成され、前記裏の表面と共にオーム接触を形成させる少なくとも1つの裏面バス電極と、
前記第一保護層を被覆させて形成され且つ前記少なくとも1つの裏面バス電極を被覆させないバック接点を更に備え、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させて形成される第二保護層を更に備え、前記第二保護層の構成は窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする光起電素子。
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction A combination of semiconductor configurations including any one junction selected from:
A first protective layer formed by covering the plurality of side surfaces and for suppressing an evoked potential attenuation effect generated by the photovoltaic element;
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is subjected to a roughening treatment, and the first protective layer extends to the edge of the front surface. Extended and covered with the back surface,
The photovoltaic element is
An antireflection layer formed on the surface of the front surface and extending by covering the first protective layer on the edge of the front surface of the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one backside bus electrode formed on the first protective layer and forming an ohmic contact with the backside surface;
A back contact formed by covering the first protective layer and not covering the at least one backside bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
A second protective layer formed by covering the first protective layer, wherein the second protective layer has any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above-mentioned compounds; photovoltaic element characterized Rukoto selected either from one.
複数の側表面を有し、p―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部を含む半導体構成の組合せと、
前記複数の側表面を被覆させて形成され、且つ光起電素子が発生させる誘発電位減衰効果を抑制させるための第一保護層と
を備え、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、前記表の表面には粗化処理が施され、前記第一保護層は前記表の表面を被覆させて延出され、且つ前記裏の表面を被覆させて延出され、また、前記光起電素子は、
前記表の表面を被覆させる前記第一保護層を被覆させて形成される反射防止層と、
前記反射防止層に形成され、前記表の表面と共にオーム接触を形成させる正極と、
前記第一保護層に形成され、前記裏の表面と共にオーム接触を形成させる少なくとも1つの裏面バス電極と、
前記第一保護層を被覆させて形成され且つ前記少なくとも1つの裏面バス電極は被覆させないバック接点を更に備え、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させて形成される第二保護層を更に備え、前記第二保護層の構成は窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択されることを特徴とする光起電素子。
A group having a plurality of side surfaces and comprising a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction A combination of semiconductor configurations including any one junction selected from:
A first protective layer formed by covering the plurality of side surfaces and for suppressing an evoked potential attenuation effect generated by the photovoltaic element;
The combination of the semiconductor configurations further includes a front surface and a back surface with respect to the front surface, the front surface is roughened, and the first protective layer covers the front surface. Extending and covering the back surface, and the photovoltaic element is
An antireflection layer formed by coating the first protective layer covering the surface of the front surface;
A positive electrode formed on the antireflective layer and forming an ohmic contact with the front surface;
At least one backside bus electrode formed on the first protective layer and forming an ohmic contact with the backside surface;
A back contact formed by covering the first protective layer and not covering the at least one backside bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
A second protective layer formed by covering the first protective layer, wherein the second protective layer has any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above-mentioned compounds; photovoltaic element characterized Rukoto selected either from one.
半導体構成の組合せは複数の側表面を有すると共にp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部からなる、半導体構成の組合せの準備工程と、
前記複数の側表面を被覆させ、且つ光起電素子が発生させる誘発電位減衰効果を抑制させる第一保護層を形成させる工程を含み、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を前記表の表面の辺縁まで延出させ、且つ前記第一保護層を前記裏の表面の辺縁まで延出させる工程と、
反射防止層を前記表の表面に接して形成させ、前記表の表面の辺縁の前記第一保護層を被覆させて延出させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記裏の表面に形成させる工程と、
バック接点を前記裏の表面に形成させ、前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させる工程を更に含み、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させ、窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される、第二保護層を形成させる工程を更に含むことを特徴とする光起電素子の製造方法。
The combination of semiconductor configurations has multiple side surfaces and includes a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A step of preparing a combination of semiconductor configurations, comprising any one junction selected from the group to be configured;
Forming a first protective layer that covers the plurality of side surfaces and suppresses the evoked potential decay effect generated by the photovoltaic element;
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to the edge of the front surface and extending the first protective layer to the edge of the back surface;
Forming an antireflection layer in contact with the surface of the front surface, covering and extending the first protective layer on the edge of the front surface of the front surface; and
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the backside surface;
A step of forming a back contact on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
The method further includes the step of covering the first protective layer and forming a second protective layer selected from any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above compounds. method of manufacturing a photovoltaic element characterized and this.
半導体構成の組合せは複数の側表面を有すると共にp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部からなる、半導体構成の組合せの準備工程と、
前記複数の側表面を被覆させ、且つ光起電素子が発生させる誘発電位減衰効果を抑制させる第一保護層を形成させる工程を含み、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を延出させて前記表の表面を被覆させ、前記第一保護層を前記裏の表面の辺縁まで延出させる工程と、
反射防止層を形成させて前記表の表面を被覆させる前記第一保護層を被覆させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記裏の表面に形成させる工程と、
バック接点を前記裏の表面に形成させ、前記裏の表面を被覆させて前記少なくとも1つの裏面バス電極以外の領域を形成させる工程を更に含み、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させ、窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される、第二保護層を形成させる工程を更に含むことを特徴とする光起電素子の製造方法。
The combination of semiconductor configurations has multiple side surfaces and includes a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A step of preparing a combination of semiconductor configurations, comprising any one junction selected from the group to be configured;
Forming a first protective layer that covers the plurality of side surfaces and suppresses the evoked potential decay effect generated by the photovoltaic element;
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to cover the front surface, and extending the first protective layer to the edge of the back surface;
Coating the first protective layer to form an antireflection layer to cover the front surface;
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the backside surface;
A step of forming a back contact on the back surface and covering the back surface to form a region other than the at least one back surface bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
The method further includes the step of covering the first protective layer and forming a second protective layer selected from any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above compounds. method of manufacturing a photovoltaic element characterized and this.
半導体構成の組合せは複数の側表面を有すると共にp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部からなる、半導体構成の組合せの準備工程と、
前記複数の側表面を被覆させ、且つ光起電素子が発生させる誘発電位減衰効果を抑制させる第一保護層を形成させる工程を含み、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、また、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を前記表の表面の辺縁まで延出させ、且つ前記第一保護層を延出させて前記裏の表面を被覆させる工程と、
反射防止層を前記表の表面に形成させ、前記表の表面の辺縁の前記第一保護層を被覆させて延出させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記第一保護層に形成させ、前記少なくとも1つの裏面バス電極と前記裏の表面と共にオーム接触を形成させる工程と、
バック接点を形成させて前記第一保護層を被覆させ、前記少なくとも1つの裏面バス電極は被覆させない工程を更に含み、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させ、窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される、第二保護層を形成させる工程を更に含むことを特徴とする光起電素子の製造方法。
The combination of semiconductor configurations has multiple side surfaces and includes a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A step of preparing a combination of semiconductor configurations, comprising any one junction selected from the group to be configured;
Forming a first protective layer that covers the plurality of side surfaces and suppresses the evoked potential decay effect generated by the photovoltaic element;
The combination of semiconductor configurations further comprises a front surface and a back surface to the front surface, and
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to the edge of the front surface, and extending the first protective layer to cover the back surface;
Forming an antireflection layer on the front surface, covering and extending the first protective layer on the edge of the front surface; and
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the first protective layer and forming an ohmic contact with the at least one backside bus electrode and the back surface;
Forming a back contact to cover the first protective layer and not to cover the at least one backside bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
The method further includes the step of covering the first protective layer and forming a second protective layer selected from any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above compounds. method of manufacturing a photovoltaic element characterized and this.
半導体構成の組合せは複数の側表面を有すると共にp―n接合部、n―p接合部、p―i―n接合部、n―i―p接合部、二重接合部、及び多重接合部により構成されるグループの内から選択される何れか1つの接合部からなる、半導体構成の組合せの準備工程と、
前記複数の側表面を被覆させ、且つ光起電素子が発生させる誘発電位減衰効果を抑制させる第一保護層を形成させる工程を含み、
前記半導体構成の組合せは表の表面及び前記表の表面に対する裏の表面を更に有し、
前記表の表面に粗化処理を施す工程と、
前記第一保護層を延出させて前記表の表面を被覆させ、且つ前記第一保護層を延出させて前記裏の表面を被覆させる工程と、
反射防止層を形成させて前記表の表面を被覆させる前記第一保護層を被覆させる工程と、
正極を前記反射防止層に形成させ、且つ前記正極と前記表の表面と共にオーム接触を形成させる工程と、
少なくとも1つの裏面バス電極を前記第一保護層に形成させ、前記少なくとも1つの裏面バス電極と前記裏の表面と共にオーム接触を形成させる工程と、
バック接点を形成させて前記第一保護層を被覆させ、前記少なくとも1つの裏面バス電極は被覆させない工程を更に含み、
前記第一保護層の構成は酸化アルミニウム、酸化チタン、酸化ジルコニウム、酸化ハフニウム、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択され
前記第一保護層を被覆させ、窒化シリコン、酸窒化シリコン、及び上述の化合物の混合物により構成されるグループの内の何れか1つから選択される、第二保護層を形成させる工程を更に含むことを特徴とする光起電素子の製造方法。
The combination of semiconductor configurations has multiple side surfaces and includes a pn junction, an np junction, a pin junction, an nip junction, a double junction, and a multiple junction. A step of preparing a combination of semiconductor configurations, comprising any one junction selected from the group to be configured;
Forming a first protective layer that covers the plurality of side surfaces and suppresses the evoked potential decay effect generated by the photovoltaic element;
The combination of semiconductor configurations further comprises a front surface and a back surface relative to the front surface;
Applying a roughening treatment to the surface of the table;
Extending the first protective layer to cover the front surface, and extending the first protective layer to cover the back surface;
Coating the first protective layer to form an antireflection layer to cover the front surface;
Forming a positive electrode on the antireflection layer and forming an ohmic contact with the positive electrode and the front surface;
Forming at least one backside bus electrode on the first protective layer and forming an ohmic contact with the at least one backside bus electrode and the back surface;
Forming a back contact to cover the first protective layer and not to cover the at least one backside bus electrode;
The configuration of the first protective layer is selected from any one of the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and a mixture of the above compounds ,
The method further includes the step of covering the first protective layer and forming a second protective layer selected from any one of the group consisting of silicon nitride, silicon oxynitride, and a mixture of the above compounds. method of manufacturing a photovoltaic element characterized and this.
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