JP5925150B2 - DC power supply - Google Patents

Description

  The present invention relates to a DC power supply device that converts an input DC voltage into a DC voltage that can be used by a load device.

  DC power supply systems that use high-voltage DC power as an input include power systems that rectify and use the output voltage of three-phase AC generators, such as for ships or aircraft, or by connecting multiple batteries in series. There are power supply systems such as electric vehicles that use primary power. In this type of power supply system, a high-efficiency DC power supply that maintains high conversion efficiency, keeps power consumption low, and is compact, lightweight, and highly reliable while the output current varies widely from a nearly no-load condition to a rated load. Is required.

  Here, in a conventional DC power supply device used in a ship or aircraft power supply system, the four switching elements are alternately turned on / off, and the primary current of the switching transformer is allowed to flow in both directions to use the transformer. A device equipped with a full-bridge type DC power supply device with improved efficiency is known.

  As such a full-bridge type DC power supply device, a DC / DC converter circuit by a switching method using a FET (Field Effect Transistor) as a switching element is generally used, but silicon (hereinafter referred to as “Si”). In the circuit using the power semiconductor element using “)”, although the on-resistance and the saturation voltage are required to be reduced, the technical limit is being reached. It is also at the peak of efficiency.

  However, in recent years, as a result of research on wide band gap semiconductors (hereinafter referred to as “WBG semiconductors”) having a value about twice that of Si, the results are low on-resistance, high breakdown voltage, and high current. In addition, FETs using gallium nitride (hereinafter referred to as “GaN”) and switching devices using silicon carbide (hereinafter referred to as SiC) that are capable of high-speed switching are beginning to be used.

  In general, it is known that if a FET using GaN or SiC is used, switching loss can be reduced, and a more compact and highly efficient DC / DC converter circuit can be provided.

  However, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor) made of GaN and SiC, which are currently in practical use, have higher withstand voltage, lower on-resistance, and higher temperature than MOSFETs made of Si. There is no deterioration in characteristics even during operation, and the loss in the conducting state (hereinafter referred to as “conducting loss”) is small, but since the parasitic capacitance between the drain and source and between the drain and gate is large, it was stored when the FET was off. Charge / discharge loss that consumes charge at the same time as turning on is large.

  Furthermore, when the FET shifts from the off state to the on state, the current flowing during the time until the voltage applied between the drain and the source becomes the saturation voltage and the voltage applied between the drain and the source during that time A loss corresponding to the value obtained by integrating the product over time occurs. Conversely, when the FET changes from the on state to the off state, the voltage applied until the current flowing between the drain and the source becomes zero. And a loss corresponding to a value obtained by time-integrating the product of the flowed current. These losses are called switching losses and increase in proportion to the switching frequency.

  In general, a so-called zero voltage switching technique, a zero current switching technique, or the like is used as a method for reducing the switching loss. As a zero voltage switching technique applied to a full-bridge type DC power supply device, a so-called phase shift full A bridge method is known.

  In this phase shift full bridge system, two sets of bridge circuits in which two FETs operating in phase with each other by 180 ° are connected in series, connected in parallel with the input capacitor, and the midpoint of the first bridge circuit is set. Connect to one terminal of the switching transformer primary winding via a resonance coil, connect the midpoint of the second bridge circuit to the other terminal of the switching transformer primary winding, and adjust the phase of the two bridge circuits. This is a method in which the time for flowing current to the primary side of the switching transformer is varied by controlling.

  In this phase shift full bridge method, using the phase shift of each FET and the energy of the resonant coil, the charge stored in the parasitic capacitance of each FET is regenerated to the input side, and between the drain and source of the FET Switching loss is suppressed by moving the FET to the ON state after the potential is brought close to zero. On the other hand, when regenerating the charge stored in the parasitic capacitance of each FET, the parasitic diode in the FET or the free wheel diode connected in antiparallel with the FET until the next FET turns on. It is necessary to keep a current flowing through the resonance coil, and it is necessary to store energy capable of maintaining this current in the resonance coil. For this reason, when the resonant coil is small, when the load current is reduced, the switching current is reduced and zero voltage switching cannot be maintained, and a very large switching loss occurs.

  In other words, a full-bridge type DC / DC converter circuit with high input voltage and high output power is constructed using MOSFETs made of GaN or SiC that have low on-resistance, high breakdown voltage, high current and high-speed switching. In this case, it is effective to apply a phase shift full bridge method capable of zero voltage switching. However, in this phase shift full bridge method DC / DC converter circuit, zero voltage switching is possible even in light load conditions close to no load. In order to maintain and suppress the switching loss, a very large resonance coil is required, and there is a disadvantage that the power supply circuit becomes large.

  Therefore, for example, by monitoring the load current of the DC power supply device, when the load current is large, the switching frequency is increased, and when the load current is small, the switching frequency is decreased to increase the current flowing through the resonance coil, thereby increasing the load fluctuation range. A technology that suppresses switching loss by maintaining zero-voltage switching even in a large-sized device is disclosed (for example, Patent Document 1).

JP 2010-172146 A

  However, in the configuration shown in Patent Document 1, since the switching frequency is lowered when the output current is small, it is necessary to perform a design corresponding to the lowest switching frequency. For this reason, there is a problem in that individual components such as an output choke coil, a switching transformer, and a capacitor inserted in the input / output are increased, which is an obstacle to reducing the size and weight of the device.

  Furthermore, when the load current is close to the rated load, the switching frequency is sufficiently high, so individual components such as the output choke coil and capacitor occupy a larger and larger volume than necessary for the switching frequency. It becomes. In addition, there is a problem that the efficiency cannot be increased depending on the magnitude of the load current, such as an increase in conduction loss compared to the case of using a small component adapted to a high switching frequency.

  The present invention has been made in view of the above, and has a simple circuit configuration, can maintain zero voltage switching without being affected by load fluctuations, reduce switching loss, and is highly efficient, small and light. It is another object of the present invention to provide a DC power supply device that can be realized at low cost.

In order to solve the above-described problems and achieve the object, a DC power supply according to the present invention is a DC power supply that converts an input DC voltage into a DC voltage that can be used in a load device, and the input DC voltage is applied to the DC power supply. An input capacitor, a switching circuit configured by full-bridge connection of a plurality of FETs, a transformer having a primary side winding and a secondary side winding, and the primary side winding between the outputs of the switching circuit. A resonant coil connected via a line, a synchronous rectifier circuit having a plurality of FETs for synchronous rectification, a current detection circuit for detecting a switching current flowing in the switching circuit, and a phase of a drive signal of each FET Based on the switching current, the phase control circuit turns on the FET with the parasitic diode of each FET turned on. Zero voltage control for controlling the synchronous rectification FET so that a short-circuit loop current flows in the secondary winding when the switching current is insufficient with respect to a current lower limit value at which zero voltage switching can be achieved. The synchronous rectifier circuit includes a first synchronous rectification FET having a drain terminal connected to one terminal of the secondary winding, and a drain connected to the other terminal of the secondary winding. A second synchronous rectification FET to which a terminal is connected; a first output choke coil having one end connected to one terminal of the secondary winding; and one end to the other terminal of the secondary winding. Is connected to a connection point of the second output choke coil to which the other output choke coil is connected, the other end of the first output choke coil, and the other end of the second output choke coil. The source terminal of the FET and the second An output capacitor having the other end connected to a connection point with the source terminal of the rectifying FET, the zero voltage control circuit calculates an insufficient current with respect to the current lower limit value, and an inductance value of the resonance coil, Simultaneous on-time in one switching period of the first synchronous rectification FET and the second synchronous rectification FET required to compensate for the shortage current based on the leakage inductance value of the transformer and the input DC voltage And the on-timing of the first synchronous rectification FET and the second synchronous rectification FET are advanced by an amount corresponding to the simultaneous on-time, so that the first synchronous rectification FET and the second synchronous rectification use FET is characterized Rukoto provided a period in which are turned on simultaneously.

  According to the present invention, since the zero voltage switching of the FET constituting the switching circuit can be realized even in a state where the load current is small, the DC power supply device capable of converting the power efficiently without being affected by the load fluctuation is miniaturized. There is an effect that it can be realized at a low weight and at a low cost.

FIG. 1 is a diagram of a configuration example of the DC power supply device according to the first embodiment. FIG. 2 is a block diagram for explaining a detailed operation of the DC power supply device according to the first embodiment. FIG. 3 is a diagram illustrating waveforms of respective parts in the initial state of the DC power supply device according to the first embodiment. FIG. 4 is a diagram illustrating each part waveform during rated load operation in which the output current of the DC power supply device according to the first embodiment is maximized. FIG. 5 is a diagram illustrating waveforms at various parts during a light load operation in which the output current of the DC power supply device according to the first embodiment is close to no load. FIG. 6 is a diagram of a configuration example of the DC power supply device according to the second embodiment. FIG. 7 is a diagram illustrating each part waveform during rated load operation in which the output current of the DC power supply device according to the second embodiment is maximized. FIG. 8 is a diagram illustrating the waveforms of each part during light load operation in which the output current of the DC power supply device according to the second embodiment is close to no load. FIG. 9 is a diagram of a configuration example of the DC power supply device according to the third embodiment. FIG. 10 is a diagram illustrating each part waveform during light load operation in which the output current of the DC power supply device according to the third embodiment is close to no load.

  A DC power supply device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

  FIG. 1 is a diagram of a configuration example of the DC power supply device according to the first embodiment. As shown in FIG. 1, a DC power supply device 100 according to a first embodiment converts a DC voltage input from a DC power supply 1 into a DC voltage that can be used by a load device 13, and includes an input capacitor 2, switching A circuit 3, a resonance coil 4, a transformer 5, a synchronous rectification circuit 20, a current detection circuit 11, a phase control circuit 12, and a zero voltage control circuit 14 are provided.

  In FIG. 1, a DC power source 1 is a DC voltage source obtained after full-wave rectification of an AC voltage of a three-phase generator used as a primary power source in a ship or aircraft power system, for example. The output voltage of the DC power supply 1 is, for example, about 600 Vdc for a ship having an AC440Vrms delta-connected generator, and about 270Vdc for an aircraft having an AC115Vrms star-connected generator.

  The input capacitor 2 is for smoothing the output voltage of the DC power source 1 and for stably supplying a rectangular wave ripple current that flows when the switching circuit 3 in the subsequent stage is switched.

  The switching circuit 3 is a full-bridge switching circuit in which the FETs 21 and 22 are bridge-connected, the FETs 23 and 24 are bridge-connected, and the two bridge circuits are connected in parallel. The midpoint is connected to one terminal of the primary side winding 5-1 of the transformer 5 via the resonance coil 4, and the midpoint of the other bridge circuit is the other side of the primary side winding 5-1 of the transformer 5. Connected to the terminal. The FETs 21 to 24 constituting the switching circuit 3 are repeatedly turned on and off at different phases with the same on / off ratio.

  The synchronous rectification circuit 20 includes a first synchronous rectification FET 6, a second synchronous rectification FET 7, a first output choke coil 8, a second output choke coil 9, and an output capacitor 10.

  The secondary winding 5-2 of the transformer 5 has one terminal connected to the one terminal of the output capacitor 10 via the first output choke coil 8 and the other terminal connected to the one terminal of the output capacitor 10 via the second output choke coil 9. It is connected. The secondary winding 5-2 of the transformer 5 has one terminal connected to the drain terminal of the first synchronous rectification FET 6 and the other terminal connected to the drain terminal of the second synchronous rectification FET 7. The connection point of the source terminals of the synchronous rectification FETs 6 and 7 is connected to the other terminal of the output capacitor 10. A load device 13 is connected to the output capacitor 10 in parallel.

  The current detection circuit 11 detects a current flowing in the switching circuit 3 (hereinafter referred to as “switching current”) and outputs the current to the phase control circuit 12 and the zero voltage control circuit 14.

  The phase control circuit 12 receives the voltage across the output capacitor 10 and the switching current detected by the current detection circuit 11, and the FETs 21 to 24 constituting the switching circuit 3 so that the voltage across the output capacitor 10 is always constant. Is controlling the phase. The zero voltage control circuit 14 will be described later.

  In the present embodiment, it is assumed that the load device 13 is arbitrarily changed from a light load state, which can be said to be a substantially no-load state, to a rated load state where the output current is maximum.

  In the DC power supply device 100 according to the present embodiment, the four FETs 21 to 24 connected to the primary winding 5-1 of the transformer 5 are alternately turned on / off while changing the phase. Thus, the time width of the voltage applied to the primary side winding 5-1 of the transformer 5 is controlled, and according to the winding ratio between the primary side winding 5-1 and the secondary side winding 5-2. This is configured as a so-called phase shift full bridge type DC / DC converter circuit that generates voltage and current in the secondary winding 5-2 to transmit electric power.

  In the phase-shift full-bridge DC / DC converter circuit, the resonance coil 4 connected in series to the primary side of the transformer 5 delays the current that flows when the FETs 21 to 24 are switched, and the voltage applied to the FETs 21 to 24. The switching loss is reduced by shifting the timing of the current, and the energy stored by the current flowing in the resonance coil 4 is used to store the parasitic capacitance of each FET 21-24 via the parasitic diode of each FET 21-24. It has a function of regenerating the electric charge to the input capacitor 2 while the FETs 21 to 24 are turned off. Also, by turning on the FETs 21 to 24 while the parasitic diodes of the FETs 21 to 24 are turned on and current flows, and the potential difference between the drain and source of the FETs 21 to 24 is equal to the ON voltage of the parasitic diodes. Achieve zero voltage switching that eliminates voltage and current overlap. By performing such an operation, even when a very large amount of electric power is output, loss can be suppressed, and highly efficient power conversion is realized.

  Next, the operation of the DC power supply circuit 100 according to the first embodiment will be described with reference to FIGS. FIG. 2 is a block diagram for explaining a detailed operation of the DC power supply device according to the first embodiment.

  In the example shown in FIG. 2, the internal elements of the FETs 21 to 24 are illustrated. Here, the internal elements of the FETs 22 and 23, which will be described in detail in the following description, are described with reference numerals.

  The FET 22 includes, as internal elements, a parasitic diode 25 connected in antiparallel to the FET 22, a parasitic gate resistance (RB) 26 connected to the gate of the FET 22, and a parasitic resistance (RGS) existing between the gate and source of the FET 22. 27, parasitic capacitance (CGS) 28 existing between the gate and source of the FET 22, parasitic capacitance (CGD) 29 existing between the drain and gate of the FET 22, and parasitic capacitance (CDS) 30 existing between the drain and source of the FET 22. have.

  The FET 23 has, as internal elements, a parasitic diode 31 connected in antiparallel to the FET 23, a parasitic gate resistance (RB) 32 connected to the gate of the FET 23, and a parasitic resistance existing between the gate and source of the FET 23. (RGS) 33, parasitic capacitance (CGS) 34 existing between the gate and source of FET 23, parasitic capacitance (CGD) 35 existing between the drain and gate of FET 23, and parasitic capacitance (CDS existing between the drain and source of FET 23) 36). In the example illustrated in FIG. 2, an example in which the drive signals of the FETs 21 to 24 output from the phase control circuit 12 are input to the FETs 21 to 24 via the drive circuit is illustrated.

  FIG. 3 is a diagram illustrating waveforms of respective parts in the initial state of the DC power supply device according to the first embodiment. FIG. 4 is a diagram showing waveforms at various parts during rated load operation in which the output current of the DC power supply device according to the first embodiment is maximized. FIG. 5 is a diagram illustrating waveforms of each part during light load operation in which the output current of the DC power supply device according to the first embodiment is close to no load.

  Each of FIGS. 3 to 5 (a) shows a gate voltage waveform to the FET 21, each of FIGS. 3 to 5 (b) shows a gate voltage waveform to the FET 22, and FIGS. 3 to 5 (c) of FIG. 3 to 5D show the gate voltage waveform to the FET 24. FIG. Each of FIGS. 3 to 5 (e) shows a primary voltage waveform of the transformer 5, each of FIGS. 3 to 5 (f) shows a waveform of a current flowing through the resonance coil 4, and each of FIGS. 3 to 5 (g). Shows the drive signal waveform of the synchronous rectification FET 7, and FIGS. 3 to 5 (h) each show the drive signal waveform of the synchronous rectification FET 6. As shown in FIGS. 3 to 5, a dead time is provided between the ON period of the FET 21 and the ON period of the FET 22, and between the ON period of the FET 23 and the ON period of the FET 24. 3 prevents a short-circuit current from flowing.

  Here, in order to facilitate understanding of the operations of the switching circuit 3, the phase control circuit 12, and the resonance coil 4, details will be described with reference to FIGS. 2 and 3. 2 indicates a path of a current flowing in the period A in which the ON periods of the FETs 21 and 24 overlap in one switching cycle, and a one-dot chain line arrow in FIG. 2 indicates that the FET 21 is off. 2 shows the path of the regenerative current of the parasitic capacitances 29 and 30 of the FET 22 that flows during the period B1, and the two-dot chain arrow shown in FIG. Show.

  The FET 21 and the FET 22 operate with a phase difference of 180 °, and the FET 23 and the FET 24 operate similarly with a phase difference of 180 °. In the initial state immediately after the start of the DC power supply device 100, as shown in FIG. 3, the FET 21 and the FET 23 switch in the same phase (see FIGS. 3A to 3D), and the FETs 6 and 7 stop. (See FIGS. 3 (g) and 3 (h)). At this time, no current flows through the resonance coil 4 (see FIG. 3F), and no primary voltage is generated in the transformer 5 (see FIG. 3E).

  Thereafter, the phases of the FET 21 and the FET 22 are gradually delayed. When the ON period of the FET 21 and the ON period of the FET 24 overlap, a current flows in the resonance coil 4 as shown in FIGS. 4 and 5 (FIG. 4, 5 (f)). The voltage is applied to the primary winding 5-1 of the transformer 5 (see FIGS. 4 and 5 (e)).

  During rated load operation at which the output current of the DC power supply device 100 is maximum, as shown in FIG. 4, the first synchronous rectification FET 6 and the second synchronous rectification FET 7 are controlled in synchronization with the FETs 21 and 22 being turned off. In addition, by providing a time in which the ON period of the first synchronous rectification FET 6 and the ON period of the second synchronous rectification FET 7 overlap, it is possible to achieve zero voltage switching. Hereinafter, an operation when zero voltage switching is achieved in FIG. 4 will be described.

  In one switching cycle, in a period A (see FIG. 4) in which the ON periods of the FETs 21 and 24 overlap, a current flows along a path indicated by a broken-line arrow in FIG. As a result, a voltage is applied to the primary winding 5-1 of the transformer 5.

  In the period B1 (see FIG. 4) in which the FET 21 is turned off and only the FET 24 is turned on, the current is flowing in the resonance coil 4 in the period A and is stored in the parasitic capacitors 29 and 30 of the FET 22. The electric charge is discharged, a current flows toward the energized FET 24 via the primary coil 5-1 of the resonance coil 4 and the transformer 5, and a loop current flows along a path indicated by a one-dot chain line arrow in FIG.

  At this time, the charges stored in the parasitic capacitances 29 and 30 of the FET 22 are discharged to the GND through the primary winding 5-1 of the transformer 5, and thus are stored in the parasitic capacitances 29 and 30 of the FET 22. The energy due to the electric charge is transmitted to the secondary winding 5-2 of the transformer 5.

  When all the charges stored in the parasitic capacitors 29 and 30 of the FET 22 are discharged, a current flows through the parasitic diode 25 of the FET 22. As a result, the drain-source voltage of the FET 22 becomes equal to the on-voltage of the parasitic diode 25. By turning on the FET 22 in this state, zero voltage switching of the FET 22 is achieved.

  In the period B2 (see FIG. 4) in which both the FETs 21 and 24 are off, current flows from the FET 22 through the primary winding of the resonance coil 4 and the transformer 5 and current flows to the resonance coil 4 in the period A. The electric charge stored in the parasitic capacitances 35 and 36 of the FET 23 is discharged by the electromotive force generated by the, and merges with the current flowing from the FET 22 via the primary coil 5-1 of the resonant coil 4 and the transformer 5. A current flows in the direction of, and a current flows along a path indicated by a two-dot chain line arrow in FIG.

  At this time, the charges stored in the parasitic capacitances 35 and 36 of the FET 23 are regenerated to the input capacitor 2.

  When all the charges stored in the parasitic capacitors 35 and 36 of the FET 23 are discharged, a current flows through the parasitic diode 31 of the FET 23. As a result, the drain-source voltage of the FET 23 becomes equal to the on-voltage of the parasitic diode 31. By turning on the FET 23 in this state, zero voltage switching of the FET 23 is achieved.

  Thereafter, by controlling the FETs 22 and 23 in the same manner, zero voltage switching of the FETs 21 and 24 is achieved, and the switching loss of the switching circuit 3 can be suppressed.

  Here, in order to achieve the zero voltage switching of each of the FETs 21 to 24 as described above, energy is required to charge and discharge each parasitic capacitance and keep each parasitic diode in an on state.

  For this reason, when the output current of the DC power supply device 100 is light load operation close to no load, as shown by a broken line in FIG. 5, the current flowing through the resonance coil 4 during the off period of each of the FETs 21 to 24 is reduced. The FET is turned on in a state where the on-state of the 24 parasitic diodes is not maintained, or in a state where the charges of the parasitic capacitances of the FETs 21 to 24 are not discharged, that is, the zero voltage switching of the FETs 21 to 24 cannot be achieved. A large switching loss will occur.

  In order to achieve zero voltage switching of each of the FETs 21 to 24 in a state where the output current of the DC power supply device 100 is small, a method of increasing the inductance value of the resonance coil 4 can be considered. Even when the output current increases, a large choke coil is required so that the resonance coil 4 does not saturate, which is an obstacle to reducing the size and weight. Alternatively, a method of increasing the stored energy by increasing the output current of the DC power supply device 100 is conceivable, but in this case, it is necessary to provide a load other than the load device 13 to flow the current, and power is consumed wastefully. And the efficiency deteriorates.

  Therefore, in the present embodiment, when the output current of the DC power supply device 100 is small and zero voltage switching cannot be achieved, the on-timing of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 is set to the FETs 21 and 22. A zero voltage control circuit 14 that can achieve zero voltage switching is provided by causing a short-circuit loop current to flow through the secondary winding 5-2 earlier than the off timing. Hereinafter, the operation of the zero voltage control circuit 14 will be described.

  The zero voltage control circuit 14 monitors the switching current detected by the current detection circuit 11, calculates an insufficient current with respect to the current lower limit value at which zero voltage switching can be achieved, and determines the inductance value of the resonance coil 4 and the leakage inductance of the transformer 5. Based on the value and the input DC voltage, the simultaneous on-time (Ton) in one switching period of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 necessary to compensate for the above-described insufficient current is calculated, The on-timing of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 is advanced by this simultaneous on-time (Ton).

  More specifically, when the switching current detected by the current detection circuit 11 is smaller than the current lower limit value capable of achieving zero voltage switching, the FET 21 is turned off when the switching current is equal to or higher than the current lower limit value. The first synchronous rectification FET 6 that is turned on synchronously is turned on earlier by Ton than the OFF timing of the FET 21. As a result, as shown in FIG. 5, a time is provided in which the ON period of the first synchronous rectification FET 6 and the ON period of the second synchronous rectification FET 7 overlap in one switching cycle.

  Thus, by providing a time in which the ON period of the first synchronous rectification FET 6 and the ON period of the second synchronous rectification FET 7 overlap in one switching cycle, the secondary winding 5-2 of the transformer 5; A short-circuit loop current indicated by a solid line arrow in FIG. 2 flows through the first synchronous rectification FET 6 and the second synchronous rectification FET 7, and the current flowing through the resonance coil 4 increases accordingly (FIG. 5 (f ), The energy stored in the resonance coil 4 is supplemented, and the zero voltage switching of the FETs 22 and 23 can be maintained.

  Similarly, the second synchronous rectification FET 7 that is turned on in synchronization with the turn-off of the FET 22 when the switching current is equal to or greater than the current lower limit value is turned on earlier than Ton by the FET 22 by turning on the FET 21, 24. Zero voltage switching can be maintained.

  Here, a mechanism in which zero voltage switching cannot be maintained and a switching loss occurs will be described. When the output current of the DC power supply device 100 decreases and the switching current flowing through the switching circuit 3 decreases, the energy stored in the resonance coil 4 in the period A shown in FIG. 5 is proportional to the square of the current value of the switching current. Decrease.

  At this time, when the FET 21 is turned off and no voltage is applied to the primary winding 5-1 of the transformer 5 (transition from the period A to the period B shown in FIG. 5), it is indicated by a broken line arrow in FIG. When the current path shifts to the current path indicated by the one-dot chain line arrow in FIG. 2, the energy of the resonance coil 4 becomes insufficient, and the current can continue to flow through the current path indicated by the one-dot chain line arrow in FIG. Or the current cannot be kept flowing in the current path indicated by the two-dot chain line arrow in FIG. 2, and charges remain in the parasitic capacitors 29 and 30 of the FET 22 and the parasitic capacitors 35 and 36 of the FET 23. Alternatively, the FETs 22 and 23 are turned on in a state where an input voltage is applied between the drains and sources of the FETs 22 and 23, that is, zero voltage switching cannot be achieved. So that the Chingurosu occurs.

  In the DC power supply device 100 according to the present embodiment, as described above, the deficiency with respect to the current lower limit value of the switching current that can achieve zero voltage switching is calculated, and the deficiency necessary to compensate for the deficiency of this switching current is calculated. The simultaneous on-time (Ton) of one synchronous rectification FET 6 and the second synchronous rectification FET 7 in one switching cycle is calculated, and the on-timing of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 is calculated as follows: The first synchronous rectification FET 6 and the second synchronous rectification FET 7 are simultaneously turned on earlier by the simultaneous on-time (Ton), thereby forcibly causing the secondary winding 5-2 of the transformer 5 to short circuit loop current. To increase the current flowing through the resonance coil 4 (see FIG. 5F). As a result, a regenerative current flows through each FET 21 to 24, in order to maintain zero voltage switching at the timing when each FET 21 to 24 is turned off in one switching cycle, that is, at the transition from the period A to the period B shown in FIG. Sufficient energy is stored in the resonance coil 4.

  As described above, according to the direct-current power supply device of the first embodiment, the current lower limit value that can achieve zero voltage switching that turns on each FET while the parasitic diode of each FET constituting the switching circuit is turned on is achieved. When the switching current flowing through the switching circuit is insufficient, zero voltage can be obtained by flowing a regenerative current through each FET using the electromotive force generated in the resonance coil by flowing a short-circuit loop current through the secondary winding. Since zero voltage control is implemented to realize switching, zero voltage switching can be maintained even during light load operation close to no load without using a large choke coil, and it is not affected by load fluctuations Since switching loss can be reduced, a DC power supply that can be realized with high efficiency, small size, light weight and low cost is obtained. It is possible.

  More specifically, a shortage current for the lower limit of the current that can achieve zero voltage switching is calculated, and a first step for compensating for the shortage current is based on the inductance value of the resonant coil, the leakage inductance value of the transformer, and the input DC voltage. The simultaneous ON time in one switching period of one synchronous rectification FET and the second synchronous rectification FET is calculated, and the ON timing of the first synchronous rectification FET and the second synchronous rectification FET is determined as the simultaneous ON time. A zero voltage control circuit that achieves zero voltage switching by causing a short-circuit loop current to flow through the secondary winding by simultaneously turning on the first synchronous rectification FET and the second synchronous rectification FET earlier by the amount of time Therefore, it can be realized with a simple circuit configuration without greatly changing the circuit configuration from the conventional configuration. In the first embodiment described above, for convenience of explanation, as a definition of zero voltage switching, a parasitic diode inside each FET is turned on, and each FET is turned on while a current is flowing through the parasitic diode. However, zero voltage switching can be achieved even if a freewheeling diode is connected in antiparallel with each FET and each FET is turned on while the freewheeling diode is on and current is flowing through the freewheeling diode. Needless to say. The same applies to the following second and third embodiments.

Embodiment 2. FIG.
FIG. 6 is a diagram of a configuration example of the DC power supply device according to the second embodiment. In addition, the same code | symbol is attached | subjected to the component which is the same as that of Embodiment 1, or equivalent, and the detailed description is abbreviate | omitted.

  As shown in FIG. 6, in the DC power supply device 100a according to the second embodiment, the transformer 5a includes a first secondary winding 5-2a and a second secondary winding 5-2b. A full-bridge transformer in which a pair of secondary windings are connected by a center tap is provided.

  In addition to the configuration described in the first embodiment, the synchronous rectification circuit 20a includes a first drive circuit 15 that drives the first synchronous rectification FET 6 and a second drive that drives the second synchronous rectification FET 7. And a circuit 16.

  One terminal of the first secondary winding 5-2a of the transformer 5a is connected to the source terminal of the first synchronous rectification FET 6. One terminal of the second secondary winding 5-2b of the transformer 5a is connected to the source terminal of the second synchronous rectification FET7. The drain terminal of the first synchronous rectification FET 6 and the drain terminal of the second synchronous rectification FET 7 are connected, and are connected to one terminal of the output capacitor 10 via the output choke coil 8. The connection point between the other terminal of the first secondary winding 5-2a of the transformer 5a and the other terminal of the second secondary winding 5-2b is connected to the other terminal of the output capacitor 10. It is connected. A load device 13 is connected to the output capacitor 10 in parallel.

  In the configuration of the present embodiment shown in FIG. 6, when the FETs 21 and 24 are on, the first synchronous rectification FET 6 is turned on to pass a current through the first secondary winding 5-2a. When the FETs 22 and 23 are turned on, the second synchronous rectification FET 7 is turned on and a current is passed through the second secondary winding 5-2b to perform power conversion.

  In the configuration shown in FIG. 6, since the source terminals of both the first synchronous rectification FET 6 and the second synchronous rectification FET 7 are in a floating state, a drive signal based on the source potential is required. For this reason, the first drive circuit 15 and the second drive circuit 16 generate drive signals for the first synchronous rectification FET 6 and the second synchronous rectification FET 7 based on the signal from the zero voltage control circuit 14. Yes. Electric charges are stored in the output capacitor 10 by the on / off control of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 by this drive signal. The electric charge stored in the output capacitor 10 is operated to be regenerated to the primary winding 5-1 of the transformer 5a.

  Also in the configuration of the present embodiment shown in FIG. 6, by performing the zero voltage control similar to that of the first embodiment, the switching circuit 3 is provided even during light load operation where the output current of the DC power supply device 100a is close to no load. It is possible to maintain zero voltage switching of each of the FETs 21 to 24 to be configured. The operation of the DC power supply circuit 100a according to the first embodiment will be described below with reference to FIGS.

  FIG. 7 is a diagram illustrating each part waveform during rated load operation in which the output current of the DC power supply device according to the second embodiment is maximized. FIG. 8 is a diagram illustrating the waveforms of the respective parts during light load operation in which the output current of the DC power supply device according to the second embodiment is close to no load.

  7 and 8 (a) show the gate voltage waveform to the FET 21, FIGS. 7 and 8 (b) show the gate voltage waveform to the FET 22, and FIGS. 7 and 8 (c) to the FET 23. FIG. 7 and 8D show the gate voltage waveform to the FET 24. FIG. FIGS. 7 and 8 (e) show the primary voltage waveform of the transformer 5a. FIGS. 7 and 8 (f) show the current waveform flowing through the resonance coil 4. FIGS. Shows the drive signal waveform of the synchronous rectification FET 7, and FIGS. 7 and 8 (h) each show the drive signal waveform of the synchronous rectification FET 6. As shown in FIGS. 7 and 8, dead times are provided between the ON period of the FET 21 and the ON period of the FET 22, and between the ON period of the FET 23 and the ON period of the FET 24, and the respective ON periods overlap to each other. 3 prevents a short-circuit current from flowing.

  The FET 21 and the FET 22 operate with a phase difference of 180 °, and the FET 23 and the FET 24 operate similarly with a phase difference of 180 °. When the ON period of the FET 21 and the ON period of the FET 24 overlap, as shown in FIGS. 7 and 8, a current flows through the resonance coil 4 (see FIGS. 7 and 8 (f)), and the primary side winding 5- A voltage is applied to 1 (see FIGS. 7 and 8 (e)).

  At the rated load operation in which the output current of the DC power supply device 100a is maximum, as shown in FIG. 7, the second synchronous rectification FET 7 is turned on in synchronization with the FET 21 being turned off, and the second synchronous rectifying FET 7 is turned on in synchronization with the FET 22 being turned off. Zero voltage switching can be achieved by turning on one synchronous rectification FET 6.

  At the time of light load operation where the output current of the DC power supply device 100a is close to no load, the zero voltage control circuit 14 monitors the switching current detected by the current detection circuit 11, and lacks the current lower limit value that can achieve zero voltage switching. Based on the inductance value of the resonance coil 4, the leakage inductance value of the transformer 5a, and the input DC voltage, the first synchronous rectification FET 6 and the second synchronous rectification necessary to compensate for the above-described insufficient current are calculated. The simultaneous on-time (Ton) in one switching period of the FET for FET 7 is calculated, and the on-timing of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 is advanced by this simultaneous on-time (Ton).

  More specifically, when the switching current detected by the current detection circuit 11 is smaller than the current lower limit value capable of achieving zero voltage switching, the FET 21 is turned off when the switching current is equal to or higher than the current lower limit value. The first synchronous rectification FET 6 that is turned on synchronously is turned on earlier by Ton than the OFF timing of the FET 21. As a result, as shown in FIG. 5, a time is provided in which the ON period of the first synchronous rectification FET 6 and the ON period of the second synchronous rectification FET 7 overlap in one switching cycle.

  In this way, by providing a time in which the ON periods of the synchronous rectification FETs 6 and 7 overlap, a short-circuit loop current flows through the secondary windings 5-2a and 5-2b of the transformer 5a and the FETs 6 and 7, Along with this, the current flowing through the resonance coil 4 increases (solid line in FIG. 8 (f)), and the energy stored in the resonance coil 4 is supplemented, and the zero voltage switching of the FETs 22 and 23 can be maintained.

  Similarly, the second synchronous rectification FET 7 that is turned on in synchronization with the turn-off of the FET 22 when the switching current is equal to or greater than the current lower limit value is turned on earlier than Ton by the FET 22 by turning on the FET 21, 24. Zero voltage switching can be maintained.

  With the above-described operation, at the timing when each FET 21 to 24 is turned off in one switching cycle, that is, at the transition from the period A to the period B shown in FIG. It becomes a stored state.

  As described above, according to the direct-current power supply device of the second embodiment, two sets of secondary side windings composed of the first secondary side winding and the second secondary side winding are formed by the center tap. Even in the configuration including the connected full-bridge transformer, as in the first embodiment, the undercurrent relative to the current lower limit value at which zero voltage switching can be achieved is calculated, the inductance value of the resonance coil, the leakage inductance value of the transformer, And calculating the simultaneous on-time in one switching period of the first synchronous rectification FET and the second synchronous rectification FET for compensating for the undercurrent based on the input DC voltage, and the first synchronous rectification FET and The first synchronous rectification FET and the second synchronous rectification FET can be turned on simultaneously by advancing the ON timing of the second synchronous rectification FET by this simultaneous ON time. Thus, a zero voltage control circuit that achieves zero voltage switching by supplying a short-circuit loop current to the secondary winding is provided, so that the circuit configuration is greatly changed from the conventional configuration without using a large choke coil. In addition, with a simple circuit configuration, zero voltage switching can be maintained even during light load operation close to no load, and switching loss can be reduced without being affected by load fluctuations. It is possible to obtain a DC power supply that is light and can be realized at low cost.

Embodiment 3 FIG.
When a DC power supply device having a relatively high output voltage and a large output current is realized by using the configuration of the first or second embodiment, a synchronous rectification FET having a high withstand voltage and a low on-resistance is required. . In this case, a plurality of synchronous rectification FETs may be connected in parallel to lower the on-resistance, but depending on the output current of the DC power supply, a plurality of synchronous rectification FETs may be connected in parallel. When the diode rectifier circuit is configured rather than connecting to lower the on-resistance, the voltage at the time of turning on becomes lower, and there are cases where higher efficiency and smaller size and weight can be achieved.

  FIG. 9 is a diagram of a configuration example of the DC power supply device according to the third embodiment. In addition, the same code | symbol is attached | subjected to the component which is the same as that of Embodiment 1, 2, or equivalent, and the detailed description is abbreviate | omitted.

  As shown in FIG. 9, in the DC power supply device 100b according to the third embodiment, as the transformer 5b, the first secondary winding 5-2a for output and the second secondary winding 5-2b are used. Two sets of secondary windings are connected by a center tap, and two sets of secondary windings consisting of a first secondary side auxiliary winding 5-3a and a second secondary side auxiliary winding 5-3b It has a full-bridge transformer with side auxiliary windings connected by a center tap.

  Further, in the configuration described in the second embodiment, instead of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 provided in the synchronous rectification circuit 20a, the first secondary winding 5- The first rectifier diode 17 that rectifies the output of 2a and the second rectifier diode 18 that rectifies the output of the second secondary winding 5-2b are configured as a diode rectifier circuit 40. The synchronous rectifier circuit 20b includes an auxiliary capacitor 19 that charges the outputs of the first secondary side auxiliary winding 5-3a and the second secondary side auxiliary winding 5-3b, and the first synchronous rectification FET 6. And a drive circuit 16 for driving the second synchronous rectification FET 7.

  One terminal of the first secondary winding 5-2a of the transformer 5b is connected to the anode terminal of the first rectifier diode 17. One terminal of the second secondary winding 5-2b of the transformer 5b is connected to the anode terminal of the second rectifier diode 18. The cathode terminal of the first rectifier diode 17 and the cathode terminal of the second rectifier diode 18 are connected, and are connected to one terminal of the output capacitor 10 via the output choke coil 8. The connection point between the other terminal of the first secondary winding 5-2a of the transformer 5b and the other terminal of the second secondary winding 5-2b is connected to the other terminal of the output capacitor 10. It is connected. A load device 13 is connected to the output capacitor 10 in parallel.

  One terminal of the first secondary auxiliary winding 5-3a of the transformer 5b is connected to the source terminal of the first synchronous rectification FET 6. One terminal of the second secondary auxiliary winding 5-3b of the transformer 5b is connected to the source terminal of the second synchronous rectification FET 7. The drain terminal of the first synchronous rectification FET 6 and the drain terminal of the second synchronous rectification FET 7 are connected, and are connected to one terminal of the auxiliary capacitor 19. The connection point between the other terminal of the first secondary auxiliary winding 5-3a of the transformer 5b and the other terminal of the first secondary auxiliary winding 5-3b is the other end of the auxiliary capacitor 19. Connected to the terminal.

  In the configuration shown in FIG. 9, since the source terminals of both the first synchronous rectification FET 6 and the second synchronous rectification FET 7 are floating as in the second embodiment, the drive signals are based on the source potential. is necessary. For this reason, the first drive circuit 15 and the second drive circuit 16 generate drive signals for the first synchronous rectification FET 6 and the second synchronous rectification FET 7 based on the signal from the zero voltage control circuit 14. Yes. By the on / off control of the first synchronous rectification FET 6 and the second synchronous rectification FET 7 by this drive signal, electric charge is stored in the auxiliary capacitor 19, and the electric charge stored in the auxiliary capacitor 19 is transferred to the transformer 5b. The primary winding 5-1 is operated to regenerate.

  FIG. 10 is a diagram illustrating each part waveform during light load operation in which the output current of the DC power supply device according to the third embodiment is close to no load.

  10A shows the gate voltage waveform to the FET 21, FIG. 10B shows the gate voltage waveform to the FET 22, FIG. 10C shows the gate voltage waveform to the FET 23, and FIG. (D) shows the gate voltage waveform to the FET 24. 10E shows the primary voltage waveform of the transformer 5b, FIG. 10F shows the current waveform flowing through the resonance coil 4, and FIG. 10G shows the drive signal for the synchronous rectification FET 7. The waveform is shown, and FIG. 10H shows the drive signal waveform of the synchronous rectification FET 6. As shown in FIG. 10, a dead time is provided between the ON period of the FET 21 and the ON period of the FET 22, and between the ON period of the FET 23 and the ON period of the FET 24. The short circuit current is prevented from flowing.

  The FET 21 and the FET 22 operate with a phase difference of 180 °, and the FET 23 and the FET 24 operate similarly with a phase difference of 180 °. When the ON period of the FET 21 and the ON period of the FET 24 overlap, as shown in FIG. 10, a current flows through the resonance coil 4 (see FIG. 10F), and a voltage is applied to the primary winding 5-1 of the transformer 5b. Applied (see FIG. 10E).

  At the time of light load operation where the output current of the DC power supply device 100b is close to no load, the zero voltage control circuit 14 monitors the switching current detected by the current detection circuit 11 and lacks the current lower limit value at which zero voltage switching can be achieved. Based on the inductance value of the resonance coil 4, the leakage inductance value of the transformer 5b, and the input DC voltage, the first synchronous rectification FET 6 and the second synchronous rectification necessary to compensate for the above-described insufficient current are calculated. The on-time (Ton) in one switching cycle of the FET 7 is calculated.

  In the configuration of the present embodiment shown in FIG. 9, both the FET 21 and the FET 24 are turned on and a positive voltage is applied to the primary winding 5-1 of the transformer 5b, and the primary side of the transformer 5b immediately before that. The first synchronous rectification FET 6 is turned on every (Ton / 2) time during a period in which no voltage is applied to the winding 5-1, and both the FET 22 and FET 23 are turned on, and the primary side winding of the transformer 5b. The second synchronous rectification is performed every (Ton / 2) time in a period in which a negative voltage is applied to 5-1 and a period in which no voltage is applied to the primary winding 5-1 of the transformer 5b immediately before that. The FET 7 is turned on.

  More specifically, for example, in one switching cycle, the FET 24 starts from a time earlier by (Ton / 2) time than the ON timing of the FET 24 (timing at which the positive voltage applied to the primary winding 5-1 rises). Until the ON timing (the timing at which the positive voltage applied to the primary winding 5-1 rises), and the OFF timing of the FET 21 (the positive voltage applied to the primary winding 5-1 falls). For the first synchronous rectification in a period from the time earlier than (Ton / 2) time to (off) timing of the FET 21 (timing at which the positive voltage applied to the primary winding 5-1 falls). The FET 6 is turned on. Further, in one switching cycle, the on-timing of the FET 23 (primary) from the time earlier by (Ton / 2) time than the on-timing of the FET 23 (timing at which the negative voltage applied to the primary winding 5-1 falls). Than the period until the negative voltage applied to the side winding 5-1 falls) and the OFF timing of the FET 22 (the timing when the negative voltage applied to the primary winding 5-1 rises). Ton / 2) The second synchronous rectification FET 7 is turned on during a period from the time earlier by the time to the OFF timing of the FET 22 (the timing at which the negative voltage applied to the primary winding 5-1 rises).

  As described above, the first synchronous rectification FET 6 is turned on for the period of (Ton / 2) during the period when both the FET 21 and the FET 24 are turned on and the positive voltage is applied to the primary winding 5-1 of the transformer 5b. The FET 22 and the FET 23 are both turned on, and the second synchronous rectification FET 7 is applied for (Ton / 2) time during a period in which a negative voltage is applied to the primary winding 5-1 of the transformer 5b. Is turned on, a short-circuit loop current flows through the first secondary side auxiliary winding 5-3a and the second secondary side auxiliary winding 5-3b of the transformer 5b. Increases to supplement the energy stored in the resonance coil 4.

  Further, both the FET 21 and the FET 24 are turned on, and no voltage is applied to the primary winding 5-1 of the transformer 5b immediately before the positive voltage is applied to the primary winding 5-1 of the transformer 5b. In the period, the first synchronous rectification FET 6 is turned on for (Ton / 2) time, both the FET 22 and FET 23 are turned on, and a negative voltage is applied to the primary winding 5-1 of the transformer 5b. The auxiliary capacitor 19 is turned on by turning on the second synchronous rectification FET 7 for (Ton / 2) time in a period in which no voltage is applied to the primary winding 5-1 of the transformer 5b immediately before the period. Can be regenerated to the input capacitor 2 via the first secondary side auxiliary winding 5-3a and the second secondary side auxiliary winding 5-3b of the transformer 5b.

  With the above-described operation, at the timing when each FET 21 to 24 is turned off in one switching cycle, that is, at the transition from the period A to the period B shown in FIG. It becomes a stored state.

  As described above, according to the DC power supply device of the third embodiment, two sets of secondary side windings including the first secondary winding for output and the second secondary winding for output are provided. A full-bridge transformer in which two sets of secondary side auxiliary windings composed of a first secondary side auxiliary winding and a second secondary side auxiliary winding are connected by a center tap, connected by a center tap. In the configuration, a first synchronization for compensating for the undercurrent based on the inductance value of the resonance coil, the leakage inductance value of the transformer, and the input DC voltage is calculated based on the current lower limit value at which zero voltage switching can be achieved. The ON time in one switching period of the rectifying FET and the second synchronous rectifying FET is calculated, and the first synchronous rectifying FET and the second synchronous rectifying FET are ON-controlled only by this ON time. Thus, the first and second secondary auxiliary windings and the second secondary auxiliary winding are provided with a zero voltage control circuit that achieves zero voltage switching by passing a short-circuit loop current. Similarly, it is possible to maintain zero voltage switching even in light load operation near no load with a simple circuit configuration without using a large choke coil and without greatly changing the circuit configuration from the conventional configuration. Since the switching loss can be reduced without being affected by the load fluctuation, a DC power supply device that can be realized with high efficiency, small size, light weight and low cost can be obtained.

  In addition, the synchronous rectification FET is turned on for each period (Ton / 2) of a period in which a voltage is applied to the primary winding of the transformer and a period in which no voltage is applied to the primary winding of the transformer. Since it did in this way, it can comprise with components with small current capacity, and it becomes possible to implement | achieve further size reduction, weight reduction, and cost reduction of a DC power supply device.

  Needless to say, the above-described embodiments can be appropriately combined depending on the situation. For example, the zero voltage control is performed by combining the configuration of the first or second embodiment and the configuration of the third embodiment. By performing the above, it becomes possible to obtain a DC power supply device with higher accuracy of higher efficiency.

  In the above-described embodiment, the zero voltage switching of each FET constituting the switching circuit can be maintained even during light load operation where the output current of the DC power supply device is close to no load. As each of the FETs to be configured, it is suitable for a configuration in which a FET using a WBG semiconductor formed of GaN, SiC, or diamond having a large parasitic capacitance between the drain and the source and between the drain and the gate as compared with the Si semiconductor, It is possible to more effectively reduce charge / discharge loss and switching loss due to the large parasitic capacitance.

  Moreover, the effect by using FET comprised by the WBG semiconductor demonstrated in embodiment mentioned above is not restricted to the effect mentioned above.

  For example, FETs composed of WBG semiconductors have a high withstand voltage and a high allowable current density, so that further miniaturization of the FETs is possible, and each of these FETs constituting a switching circuit has been miniaturized. By using the FET, the DC power supply can be further reduced in size.

  The configurations described in the above embodiments are examples of the configurations of the present invention, and can be combined with other known techniques, and a part of the configurations is omitted without departing from the gist of the present invention. Needless to say, it is possible to change the configuration.

  As described above, the DC power supply device according to the present invention can be reduced in price and size, and is useful as a DC power supply device that can convert an input DC voltage into a DC voltage that can be used in a load device with high efficiency. In particular, it is suitable as a DC power supply device used in a power supply system for in-vehicle use, ship use, or aircraft use.

  1 DC power supply, 2 input capacitor, 3 switching circuit, 4 resonance coil, 5 transformer, 5-1 primary side winding, 5-2 secondary side winding, 5-2a first secondary side winding, 5- 2b Second secondary side winding, 5-3a First secondary side auxiliary winding, 5-3b Second secondary side auxiliary winding, 6 Synchronous rectification FET (first synchronous rectification FET) , 7 FET for synchronous rectification (second synchronous rectification FET), 8 output choke coil (first output choke coil), 9 output choke coil (second output choke coil), 10 output capacitor, 11 current detection circuit , 12 phase control circuit, 13 load device, 14 zero voltage control circuit, 15 drive circuit (first drive circuit), 16 drive circuit (second drive circuit), 17 rectifier diode (first rectifier diode), 18 Rectifier diode (Second rectifier diode), 19 auxiliary capacitor, 20, 20a, 20b synchronous rectifier circuit, 21, 22, 23, 24 FET, 25 parasitic diode, 26 parasitic gate resistance (RB), 27 parasitic resistance (RGS), 28 parasitic Capacitance (CGS), 29 Parasitic capacitance (CGD), 30 Parasitic capacitance (CDS), 31 Parasitic diode, 32 Parasitic gate resistance (RB), 33 Parasitic resistance (RGS), 34 Parasitic capacitance (CGS), 35 Parasitic capacitance (CGD) 36, parasitic capacitance (CDS), 40 diode rectifier circuit, 100, 100a, 100b DC power supply.

Claims (7)

A DC power supply device that converts an input DC voltage into a DC voltage that can be used by a load device,
An input capacitor to which the input DC voltage is applied;
A switching circuit configured by full-bridge connection of a plurality of FETs;
A transformer having a primary winding and a secondary winding;
A resonant coil connected between the outputs of the switching circuit via the primary winding;
A synchronous rectification circuit having a plurality of synchronous rectification FETs;
A current detection circuit for detecting a switching current flowing in the switching circuit;
A phase control circuit for controlling the phase of the drive signal of each FET;
Based on the switching current, when the switching current is insufficient with respect to the current lower limit value at which the phase control circuit can achieve zero voltage switching that turns on the FET with the parasitic diode of each FET turned on And a zero voltage control circuit for controlling the synchronous rectification FET so that a short-circuit loop current flows in the secondary side winding,
The synchronous rectifier circuit is
A first synchronous rectification FET whose drain terminal is connected to one terminal of the secondary winding;
A second synchronous rectification FET whose drain terminal is connected to the other terminal of the secondary winding;
A first output choke coil having one end connected to one terminal of the secondary winding;
A second output choke coil having one end connected to the other terminal of the secondary winding;
One end is connected to a connection point between the other end of the first output choke coil and the other end of the second output choke coil, and the source terminal of the first synchronous rectification FET and the second synchronous rectification An output capacitor whose other end is connected to a connection point with the source terminal of the FET;
With
The zero voltage control circuit is
The first synchronous rectification necessary for compensating the shortage current is calculated based on the inductance value of the resonance coil, the leakage inductance value of the transformer, and the input DC voltage, based on the current lower limit value. The simultaneous on-time in one switching cycle of the FET and the second synchronous rectification FET is calculated, and the on-timing of the first synchronous rectification FET and the second synchronous rectification FET is set to the amount of the simultaneous on-time. only early and said first synchronous rectification FET and said second dc power supply you comprising providing a synchronization period rectification FET is turned on at the same time. A DC power supply device that converts an input DC voltage into a DC voltage that can be used by a load device,
An input capacitor to which the input DC voltage is applied;
A switching circuit configured by full-bridge connection of a plurality of FETs;
A transformer having a primary winding and a secondary winding;
A resonant coil connected between the outputs of the switching circuit via the primary winding;
A synchronous rectification circuit having a plurality of synchronous rectification FETs;
A current detection circuit for detecting a switching current flowing in the switching circuit;
A phase control circuit for controlling the phase of the drive signal of each FET;
Based on the switching current, when the switching current is insufficient with respect to the current lower limit value at which the phase control circuit can achieve zero voltage switching that turns on the FET with the parasitic diode of each FET turned on And a zero voltage control circuit for controlling the synchronous rectification FET so that a short-circuit loop current flows in the secondary side winding,
The secondary winding is composed of a first secondary winding and a second secondary winding to which a midpoint is connected,
The synchronous rectifier circuit is
A first synchronous rectification FET having a source terminal connected to one terminal of the first secondary winding;
A second synchronous rectification FET having a source terminal connected to one terminal of the second secondary winding;
An output choke coil having one end connected to a connection point between the drain terminal of the first synchronous rectification FET and the drain terminal of the second synchronous rectification FET;
One end is connected to the other end of the output choke coil, and the other end is connected to a connection point between the other terminal of the first secondary winding and the other terminal of the second secondary winding. An output capacitor
A first drive circuit for driving the first synchronous rectification FET;
A second drive circuit for driving the second synchronous rectification FET;
With
The zero voltage control circuit is
The first synchronous rectification necessary for compensating the shortage current is calculated based on the inductance value of the resonance coil, the leakage inductance value of the transformer, and the input DC voltage, based on the current lower limit value. The simultaneous on-time in one switching cycle of the FET and the second synchronous rectification FET is calculated, and the on-timing of the first synchronous rectification FET and the second synchronous rectification FET is set to the amount of the simultaneous on-time. only early and said first synchronous rectifier dc power supply you characterized in that FET and the second synchronous rectification FET to extend the period during which simultaneously turned on. A DC power supply device that converts an input DC voltage into a DC voltage that can be used by a load device,
An input capacitor to which the input DC voltage is applied;
A switching circuit configured by full-bridge connection of a plurality of FETs;
A transformer having a primary winding and a secondary winding;
A resonant coil connected between the outputs of the switching circuit via the primary winding;
A synchronous rectification circuit having a plurality of synchronous rectification FETs;
A current detection circuit for detecting a switching current flowing in the switching circuit;
A phase control circuit for controlling the phase of the drive signal of each FET;
Based on the switching current, when the switching current is insufficient with respect to the current lower limit value at which the phase control circuit can achieve zero voltage switching that turns on the FET with the parasitic diode of each FET turned on And a zero voltage control circuit for controlling the synchronous rectification FET so that a short-circuit loop current flows in the secondary side winding,
The secondary side winding includes a first secondary side winding and a second secondary side winding to which a middle point is connected, a first secondary side auxiliary winding and a second side winding to which a middle point is connected. 2 secondary side auxiliary windings,
The synchronous rectifier circuit is
A first rectifier diode having an anode terminal connected to one terminal of the first secondary winding;
A second rectifier diode having an anode terminal connected to one terminal of the second secondary winding;
An output choke coil having one end connected to a connection point between the cathode terminal of the first rectifier diode and the cathode terminal of the second rectifier diode;
One end is connected to the other end of the output choke coil, and the other end is at a midpoint where the other terminal of the first secondary winding and the other terminal of the second secondary winding are connected. An output capacitor to which
A first synchronous rectification FET having a source terminal connected to one terminal of the first secondary auxiliary winding;
A second synchronous rectification FET having a source terminal connected to one terminal of the second secondary auxiliary winding;
One end is connected to a connection point between the drain terminal of the first synchronous rectification FET and the drain terminal of the second synchronous rectification FET, and the other terminal of the first secondary winding and the second terminal A capacitor having the other end connected to a midpoint to which the other terminal of the secondary side winding is connected;
A first drive circuit for driving the first synchronous rectification FET;
A second drive circuit for driving the second synchronous rectification FET;
With
The zero voltage control circuit is
The first synchronous rectification necessary for compensating the shortage current is calculated based on the inductance value of the resonance coil, the leakage inductance value of the transformer, and the input DC voltage, based on the current lower limit value. Calculating an ON time in one switching period of the FET and the second synchronous rectification FET, and ON-controlling the first synchronous rectification FET and the second synchronous rectification FET for the ON time. dc power supply you characterized. The zero voltage control circuit is
The first synchronous rectification ½ each of the ON time in a period in which a positive voltage is applied to the primary winding and a period in which no voltage is applied to the primary winding just before The FET is turned on, and a period during which a negative voltage is applied to the primary side winding and a period during which no voltage is applied to the primary side winding immediately before, 4. The DC power supply device according to claim 3 , wherein two synchronous rectification FETs are turned on. The zero voltage control circuit is
A period from a time that is 1/2 of the on-time earlier than the timing at which the positive voltage applied to the primary winding rises to the timing at which the positive voltage applied to the primary winding rises; and The period from the time ½ earlier than the on-time than the timing when the positive voltage applied to the primary winding falls to the timing when the positive voltage applied to the primary winding falls, 1 synchronous rectification FET is turned on,
A period from a time ½ earlier than the on-time than the timing when the negative voltage applied to the primary winding falls to the timing when the negative voltage applied to the primary winding falls; and A period from a time that is 1/2 of the on-time earlier than the timing at which the negative voltage applied to the primary winding rises to the timing at which the negative voltage applied to the primary winding rises, 5. The DC power supply device according to claim 4 , wherein the two synchronous rectification FETs are turned on. FET constituting the switching circuit includes a DC power supply device according to any one of claims 1 5, characterized in that it is formed by a wide band gap semiconductor. The DC power supply device according to claim 6 , wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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