JP5922317B2 - 変換索引バッファ（ｔｌｂ）のための重複検査 - Google Patents

変換索引バッファ（ｔｌｂ）のための重複検査 Download PDF

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Publication number
JP5922317B2
JP5922317B2 JP2015552800A JP2015552800A JP5922317B2 JP 5922317 B2 JP5922317 B2 JP 5922317B2 JP 2015552800 A JP2015552800 A JP 2015552800A JP 2015552800 A JP2015552800 A JP 2015552800A JP 5922317 B2 JP5922317 B2 JP 5922317B2
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entry
input
page size
tlb
page
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JP2015552800A
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Japanese (ja)
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JP2016507096A (ja
JP2016507096A5 (enExample
Inventor
ベンクマハンティ、スレシュ・ケー．
プロンケ、エーリッヒ・ジェイ．
コドレスク、ルシアン
マホン、シェイン・エム．
トレイ、ラーフル・アール．
ハムダン、ファディ・エー．
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2015552800A 2013-01-15 2014-01-10 変換索引バッファ（ｔｌｂ）のための重複検査 Expired - Fee Related JP5922317B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/741,981 US9208102B2 (en) 2013-01-15 2013-01-15 Overlap checking for a translation lookaside buffer (TLB)
US13/741,981 2013-01-15
PCT/US2014/011027 WO2014113286A2 (en) 2013-01-15 2014-01-10 Overlap checking for a translation lookaside buffer (tlb)

Publications (3)

Publication Number Publication Date
JP2016507096A JP2016507096A (ja) 2016-03-07
JP2016507096A5 JP2016507096A5 (enExample) 2016-04-14
JP5922317B2 true JP5922317B2 (ja) 2016-05-24

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JP2015552800A Expired - Fee Related JP5922317B2 (ja) 2013-01-15 2014-01-10 変換索引バッファ（ｔｌｂ）のための重複検査

Country Status (6)

Country Link
US (1) US9208102B2 (enExample)
EP (1) EP2946297B1 (enExample)
JP (1) JP5922317B2 (enExample)
KR (1) KR101623465B1 (enExample)
CN (1) CN104885063B (enExample)
WO (1) WO2014113286A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2536205A (en) 2015-03-03 2016-09-14 Advanced Risc Mach Ltd Cache maintenance instruction
US10372618B2 (en) * 2016-10-14 2019-08-06 Arm Limited Apparatus and method for maintaining address translation data within an address translation cache
WO2018100363A1 (en) 2016-11-29 2018-06-07 Arm Limited Memory address translation
US10083126B2 (en) * 2016-12-06 2018-09-25 Arm Limited Apparatus and method for avoiding conflicting entries in a storage structure
US11106596B2 (en) * 2016-12-23 2021-08-31 Advanced Micro Devices, Inc. Configurable skewed associativity in a translation lookaside buffer
US10929308B2 (en) * 2017-11-22 2021-02-23 Arm Limited Performing maintenance operations
US10866904B2 (en) 2017-11-22 2020-12-15 Arm Limited Data storage for multiple data types
US10831673B2 (en) 2017-11-22 2020-11-10 Arm Limited Memory address translation
WO2023019537A1 (en) 2021-08-20 2023-02-23 Intel Corporation Apparatuses, methods, and systems for device translation lookaside buffer pre-translation instruction and extensions to input/output memory management unit protocols
KR20240131741A (ko) 2023-02-24 2024-09-02 삼성전자주식회사 중복된 리퀘스트를 관리하는 전자 장치 및 그 동작 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654790A (en) * 1983-11-28 1987-03-31 Amdahl Corporation Translation of virtual and real addresses to system addresses
JPH06202954A (ja) * 1992-12-28 1994-07-22 Fujitsu Ltd タグ比較回路及びこれを用いたトランスレーション・ルック・アサイド・バッファ
US5765209A (en) * 1993-09-23 1998-06-09 Hewlett-Packard Co. Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
JPH08329687A (ja) * 1995-06-05 1996-12-13 Hitachi Ltd 半導体集積回路
WO1996012231A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
US5630087A (en) 1994-11-02 1997-05-13 Sun Microsystems, Inc. Apparatus and method for efficient sharing of virtual memory translations
US6233652B1 (en) 1998-10-30 2001-05-15 Intel Corporation Translation lookaside buffer for multiple page sizes
US6560689B1 (en) 2000-03-31 2003-05-06 Intel Corporation TLB using region ID prevalidation
US6549997B2 (en) * 2001-03-16 2003-04-15 Fujitsu Limited Dynamic variable page size translation of addresses
US6643759B2 (en) * 2001-03-30 2003-11-04 Mips Technologies, Inc. Mechanism to extend computer memory protection schemes
US20070005932A1 (en) * 2005-06-29 2007-01-04 Intel Corporation Memory management in a multiprocessor system
US8195916B2 (en) 2009-03-04 2012-06-05 Qualcomm Incorporated Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode
US8635428B2 (en) 2009-12-09 2014-01-21 Oracle America, Inc. Preventing duplicate entries in a non-blocking TLB structure that supports multiple page sizes
JP5459006B2 (ja) 2010-03-24 2014-04-02 富士通株式会社 メモリ管理装置、メモリ管理方法及びメモリ管理プログラム
US20110295587A1 (en) 2010-06-01 2011-12-01 Eeckhout Lieven Methods and systems for simulating a processor

Also Published As

Publication number Publication date
US9208102B2 (en) 2015-12-08
EP2946297A2 (en) 2015-11-25
JP2016507096A (ja) 2016-03-07
CN104885063A (zh) 2015-09-02
EP2946297B1 (en) 2019-02-27
KR20150108361A (ko) 2015-09-25
KR101623465B1 (ko) 2016-05-23
WO2014113286A2 (en) 2014-07-24
CN104885063B (zh) 2018-01-02
US20140201494A1 (en) 2014-07-17
WO2014113286A3 (en) 2014-09-12

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