CN104885063B - 针对转译后备缓冲器(tlb)的重叠检查 - Google Patents

针对转译后备缓冲器(tlb)的重叠检查 Download PDF

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Publication number
CN104885063B
CN104885063B CN201480003984.7A CN201480003984A CN104885063B CN 104885063 B CN104885063 B CN 104885063B CN 201480003984 A CN201480003984 A CN 201480003984A CN 104885063 B CN104885063 B CN 104885063B
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China
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page
entry
input
size
tlb
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Expired - Fee Related
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CN201480003984.7A
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English (en)
Chinese (zh)
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CN104885063A (zh
Inventor
苏雷什·K·文库马汉提
埃里克·J·普隆德克
卢奇安·科德雷斯库
沙恩·M·马洪
拉胡尔·R·托莱
法迪·A·哈姆丹
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201480003984.7A 2013-01-15 2014-01-10 针对转译后备缓冲器(tlb)的重叠检查 Expired - Fee Related CN104885063B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/741,981 2013-01-15
US13/741,981 US9208102B2 (en) 2013-01-15 2013-01-15 Overlap checking for a translation lookaside buffer (TLB)
PCT/US2014/011027 WO2014113286A2 (en) 2013-01-15 2014-01-10 Overlap checking for a translation lookaside buffer (tlb)

Publications (2)

Publication Number Publication Date
CN104885063A CN104885063A (zh) 2015-09-02
CN104885063B true CN104885063B (zh) 2018-01-02

Family

ID=50030520

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480003984.7A Expired - Fee Related CN104885063B (zh) 2013-01-15 2014-01-10 针对转译后备缓冲器(tlb)的重叠检查

Country Status (6)

Country Link
US (1) US9208102B2 (enExample)
EP (1) EP2946297B1 (enExample)
JP (1) JP5922317B2 (enExample)
KR (1) KR101623465B1 (enExample)
CN (1) CN104885063B (enExample)
WO (1) WO2014113286A2 (enExample)

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GB2536205A (en) 2015-03-03 2016-09-14 Advanced Risc Mach Ltd Cache maintenance instruction
US10372618B2 (en) * 2016-10-14 2019-08-06 Arm Limited Apparatus and method for maintaining address translation data within an address translation cache
CN109983538B (zh) 2016-11-29 2023-06-16 Arm有限公司 存储地址转换
US10083126B2 (en) * 2016-12-06 2018-09-25 Arm Limited Apparatus and method for avoiding conflicting entries in a storage structure
US11106596B2 (en) * 2016-12-23 2021-08-31 Advanced Micro Devices, Inc. Configurable skewed associativity in a translation lookaside buffer
US10929308B2 (en) * 2017-11-22 2021-02-23 Arm Limited Performing maintenance operations
US10866904B2 (en) 2017-11-22 2020-12-15 Arm Limited Data storage for multiple data types
US10831673B2 (en) 2017-11-22 2020-11-10 Arm Limited Memory address translation
CN117355816A (zh) 2021-08-20 2024-01-05 英特尔公司 用于设备转译后备缓冲器预转译指令和对输入/输出存储器管理单元协议的扩展的装置、方法和系统
KR20240131741A (ko) 2023-02-24 2024-09-02 삼성전자주식회사 중복된 리퀘스트를 관리하는 전자 장치 및 그 동작 방법

Citations (3)

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US5765209A (en) * 1993-09-23 1998-06-09 Hewlett-Packard Co. Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
US6233652B1 (en) * 1998-10-30 2001-05-15 Intel Corporation Translation lookaside buffer for multiple page sizes
US6560689B1 (en) * 2000-03-31 2003-05-06 Intel Corporation TLB using region ID prevalidation

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US4654790A (en) * 1983-11-28 1987-03-31 Amdahl Corporation Translation of virtual and real addresses to system addresses
JPH06202954A (ja) * 1992-12-28 1994-07-22 Fujitsu Ltd タグ比較回路及びこれを用いたトランスレーション・ルック・アサイド・バッファ
JPH08329687A (ja) * 1995-06-05 1996-12-13 Hitachi Ltd 半導体集積回路
WO1996012231A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
US5630087A (en) 1994-11-02 1997-05-13 Sun Microsystems, Inc. Apparatus and method for efficient sharing of virtual memory translations
US6549997B2 (en) * 2001-03-16 2003-04-15 Fujitsu Limited Dynamic variable page size translation of addresses
US6643759B2 (en) * 2001-03-30 2003-11-04 Mips Technologies, Inc. Mechanism to extend computer memory protection schemes
US20070005932A1 (en) * 2005-06-29 2007-01-04 Intel Corporation Memory management in a multiprocessor system
US8195916B2 (en) 2009-03-04 2012-06-05 Qualcomm Incorporated Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode
US8635428B2 (en) 2009-12-09 2014-01-21 Oracle America, Inc. Preventing duplicate entries in a non-blocking TLB structure that supports multiple page sizes
JP5459006B2 (ja) 2010-03-24 2014-04-02 富士通株式会社 メモリ管理装置、メモリ管理方法及びメモリ管理プログラム
US20110295587A1 (en) 2010-06-01 2011-12-01 Eeckhout Lieven Methods and systems for simulating a processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5765209A (en) * 1993-09-23 1998-06-09 Hewlett-Packard Co. Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
US6233652B1 (en) * 1998-10-30 2001-05-15 Intel Corporation Translation lookaside buffer for multiple page sizes
US6560689B1 (en) * 2000-03-31 2003-05-06 Intel Corporation TLB using region ID prevalidation

Also Published As

Publication number Publication date
WO2014113286A3 (en) 2014-09-12
US9208102B2 (en) 2015-12-08
CN104885063A (zh) 2015-09-02
US20140201494A1 (en) 2014-07-17
KR101623465B1 (ko) 2016-05-23
JP2016507096A (ja) 2016-03-07
JP5922317B2 (ja) 2016-05-24
EP2946297A2 (en) 2015-11-25
KR20150108361A (ko) 2015-09-25
EP2946297B1 (en) 2019-02-27
WO2014113286A2 (en) 2014-07-24

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