JP5920081B2 - Asynchronous correlation operation circuit - Google Patents

Description

  The present invention relates to an asynchronous correlation calculation circuit that performs correlation calculation asynchronously.

  As a positioning system using a positioning satellite signal, GPS (Global Positioning System) is widely known, and is used in a GPS receiver built in a mobile phone, a car navigation device, or the like. In GPS, position calculation calculation is performed to obtain position coordinates and clock errors of the position calculation device based on information such as positions of a plurality of GPS satellites and pseudo distances from each GPS satellite to the GPS receiver.

  A GPS satellite signal transmitted from a GPS satellite is modulated with a spread code different for each GPS satellite called a C / A (Coarse and Acquisition) code. In order to capture a GPS satellite signal from a weak received signal, the GPS receiver performs a correlation operation between the received signal and a replica code simulating a C / A code and captures the GPS satellite signal.

  For example, Patent Document 1 discloses a correlation operation between an input signal and a replica code by arranging a product-sum operation unit that performs a product-sum operation on an input signal and a replica code in parallel. A correlation calculation device is disclosed.

JP 2011-15159 A

  In recent years, there has been a demand for power saving of a GPS receiver in order to reduce the size of an electronic device in which the GPS receiver is built and to realize a long-time drive by a battery. Among the GPS receivers, the correlation calculation circuit has a high operating rate and high power consumption, and thus power saving of the correlation calculation circuit is desired.

  If so-called deep sub-micron semiconductor technology is used, it is possible to reduce power consumption and increase the speed of correlation calculation to some extent by reducing the voltage. However, since the conventional correlation calculation circuit is designed based on the synchronous design method and requires a clock, there are naturally limitations in reducing power consumption and increasing the calculation speed. For example, in order to realize high-speed operation, it is necessary to increase the frequency of the clock for driving the correlation operation circuit or to make the circuit parallel, in which case the clock frequency and the circuit are parallelized. There is a problem that the power consumption increases in proportion to the frequency of.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to propose a new correlation calculation circuit capable of realizing high-speed calculation while saving power.

  A first mode for solving the above-described problem is a first two-line encoding unit that performs two-line encoding on first series data that is a series of M-bit (M ≧ 1) first data. A first data supply unit that supplies first data to be used for the next calculation every time the calculation is completed, and a second line data that is a series of 1-bit second data. And a second data supply unit that supplies second data to be used for the next calculation every time the calculation is completed, and an addition result storage unit that stores the addition result Output from the first data supply unit to the output value of the third two-line encoding unit and a third two-line encoding unit that performs two-line encoding of the storage value of the addition result storage unit Asynchronous full adder that adds and outputs a value with a sign corresponding to the output value from the second data supply unit, and the asynchronous full adder And 2-wire decoder which decodes the output value of the 2-wire code is output to the addition result storage unit with an asynchronous correlation calculation circuit with.

  According to the first mode, the first series data is two-line encoded by the first two-line encoding unit included in the first data supply unit. In addition, the second series data is two-line encoded by the second two-line encoding unit included in the second data supply unit. The first data supply unit supplies the first data to be used for the next calculation to the asynchronous full adder every time the operation of the asynchronous full adder is completed, and the second data supply unit Each time the operation of the adder is completed, the second data to be used for the next operation is supplied to the asynchronous full adder. The asynchronous full adder adds the output value from the first data supply unit to the value obtained by two-line encoding the stored value of the addition result with a code corresponding to the output value from the second data supply unit. Output.

  Since the asynchronous full adder is configured to input 2-line encoded data, the asynchronous full adder can reliably detect the arrival of valid data and perform an operation. In the asynchronous full adder, an operation for adding the first data to the latest addition result of the asynchronous full adder is performed. In this case, if the sign of the second data is positive, the first data is added (that is, added), and if the sign of the second data is negative, the sign of the first data is inverted and added. By inserting (that is, subtracting), the correlation calculation can be performed correctly.

  In the asynchronous correlation circuit of this form, all circuits are driven by a global signal (clock), so unlike the synchronous circuit that follows the worst case scenario where the overall performance is determined by the slowest circuit, only the necessary circuit is required each time. Since the average case scenario that operates in an event-driven manner is followed, the degree of parallelism can be increased by a circuit block having a relatively small circuit granularity, so that a high-speed circuit operation can be realized as the entire correlation operation circuit. In addition, CMOS (Complementary Metal Oxide Semiconductor) logic consumes power proportional to the total number of switching, but since no semantically unnecessary switching operation is performed, significant power reduction can be realized.

  Further, as a second form, in the asynchronous correlation arithmetic circuit according to the first form, the first data supply unit stores the first data corresponding to each of the first data. The second data supply unit has a second data register group for storing the second data corresponding to each of the second data, and the first two-line code And the first data line corresponding to the first data register constituting the first data register group, and the first data line that encodes the first data stored in the first data register. An encoder, and the second two-line encoder is associated with each of the second data registers constituting the second data register group and stored in the second data register. 2nd line encoding of 2 data The first data supply unit has a first selection unit that selects the first two-line encoder corresponding to the first data to be subjected to the next calculation. The second data supply unit constitutes an asynchronous correlation calculation circuit having a second selection unit that selects the second two-line encoder corresponding to the second data to be subjected to the next calculation. It is good to do.

  According to the second mode, the first data supply unit has the first data register group, and the first data is stored in the first data register constituting the first data register group. , Stored in the corresponding first data register. In addition, a first two-line encoder is provided in association with each first data register constituting the first data register group. For this reason, the first selection unit selects the first two-line encoder corresponding to the first data to be subjected to the next calculation, whereby the first two-line corresponding to the first data is selected. Two-line encoding is performed by the encoder and supplied to the asynchronous full adder. The same applies to the second data.

  Further, as a third mode, in the asynchronous correlation operation circuit according to the second mode, the first selection unit sets a read token register stage that communicates with each other by a four-phase handshaking protocol to each of the first data. A read register mechanism provided in association with a read token configured to circulate through the read token register stage, wherein each time the asynchronous full adder completes the operation, the read token is transferred to the next read token register. A first read register mechanism that moves to the stage, and selects the first two-line encoder corresponding to the first data to be subjected to the next operation based on the read token; The selection unit provides a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the second data. A read register mechanism configured such that a read token circulates through the read token register stage, and the read token is moved to the next read token register stage each time the operation of the asynchronous full adder is completed. Forming an asynchronous correlation arithmetic circuit having two read register mechanisms and selecting the second two-line encoder corresponding to the second data to be subjected to the next operation based on the read token It is good.

According to the third aspect, the read register mechanism is configured so that the read token circulates in the read token register stage, and the read token is read to the next stage every time the operation of the asynchronous full adder is completed. In the first read register mechanism for moving to the token register stage, the read token is moved to the next read token register stage and corresponds to the first data to be used for the next operation based on the read token. By selecting the first two-line encoder, the first data to be used for the next calculation can be easily selected. Further, in this first read register mechanism, the read token register stages communicate with each other using a four-phase handshaking protocol, so that the read token register stages have no inconsistency after grasping the operation state of each other. Circuit operation can be realized. In this case, each read token register stage returns to the original state in the process of the read token transitioning.
The same applies to the second read register mechanism.

As a fourth mode, in the asynchronous correlation operation circuit of the second mode, the asynchronous full adder adds 2 ^K pieces (K is an integer of 1 or more) of the first data (2 ^K − 1) A tournament type full adder group in which one asynchronous full adder is arranged in a tournament type, and the first selection unit includes a read token register stage that communicates with each other by a four-phase handshaking protocol. A read register mechanism provided in association with each first data and configured such that a read token circulates through the read token register stage, wherein each read token register stage is an operation target of the asynchronous full adder 2 associated with the ^K first of said first two-wire encoder corresponding to the data, the asynchronous full adder unit reading operation for reading the token of the next every complete the Tokunre of Having a first read register mechanism for moving the register stages, the first two-wire encoder corresponding to the next 2 to Kyosu the calculation of the ^K of said first data based on the read token The second selection unit provides a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the second data, and a read token circulates through the read token register stage. A read register mechanism configured as described above, wherein each read token register stage is associated with the second two-line encoder corresponding to 2 ^K second data which is a counterpart of a correlation operation. And a second read register mechanism for moving the read token to the next read token register stage each time the operation of the asynchronous full adder is completed, and based on the read token Select the second two-wire encoder for the following 2 ^K pieces should Kyosu the operation of the second data, among the tournament-type full adder group, the asynchronous full adder respective lowermost Is the output value of the first 2-line encoder related to the first data of one of the two first data to be calculated, and the first value related to the other first data. An asynchronous correlation calculation circuit that adds an output value of a two-line encoder with a code corresponding to an output value of the second two-line encoder related to the two second data serving as a counterpart of a correlation calculation; It may be configured.

According to the fourth embodiment, a tournament-type all-in which (2 ^K −1) asynchronous full adders for adding 2 ^K (K is an integer of 1 or more) first data are arranged in the tournament type. An adder group is configured. In this case, similarly to the third embodiment, by using a so-called token passing system, 2 ^K pieces of first data and second data to be used for the next calculation can be easily transferred to the asynchronous full adder. It becomes possible to supply. In this case, depending on the sign of the second data that is the counterpart of the correlation calculation, two first data are added when the lowest asynchronous full adder in the tournament type full adder group performs the calculation. Instead, it needs to be subtracted. Therefore, each of the lowest asynchronous full adders in the tournament-type full adder group outputs the first 2-line encoder related to the first data of one of the two first data to be added. The output value of the first two-line encoder related to the other first data is the output value of the second two-line encoder related to the two second data that are the counterparts of the correlation calculation. Are added with a sign corresponding to.

  Further, as a fifth form, in the asynchronous correlation operation circuit of the second form, the write token is configured so that the write token circulates through the write token register stage communicating with each other by the four-phase handshaking protocol. A register mechanism for sequentially moving a write token to a next write token register stage and storing the first data in the first data register based on the write token; The write register mechanism is configured such that the write token circulates between the register mechanism for writing and the write token register stage communicating with each other by a four-phase handshaking protocol. And sequentially storing the second data in the second data register based on the write token. A write register mechanism, it is also possible to configure the asynchronous correlation calculation circuit with.

According to the fifth aspect, the write token is sequentially moved to the next write token register stage, and the first data is stored in the corresponding first data register based on the write token. By using this write register mechanism, it is possible to easily write the first data to the first data register. Also, in this first write register mechanism, the write register stages communicate with each other using a four-phase handshaking protocol, so that the write token register stages understand each other's operating state, Circuit operations without contradiction can be realized. In this case, each write register stage returns to the original state in the process of transition of the write token.
The same applies to the second write register mechanism.

As a sixth form, the second data supply unit in the asynchronous correlation calculation circuit of the first form generates the second series data having a length of 2 ^L −1 (L is an integer of 3 or more). An asynchronous data generation circuit, and the asynchronous data generation circuit includes an L-stage first data register unit configured by sandwiching a 1-bit data register unit between a 2-line decoder and a 2-line encoder (L- 1) A first linear feedback shift register circuit in which a first exclusive OR operation circuit in a stage is connected in a linear feedback manner and a 1-bit data register unit are sandwiched between a 2-line decoder and a 2-line encoder. A second linear feedback shift register circuit in which an L-stage second data register unit and an (L-1) -stage second exclusive OR operation circuit are connected in a linear feedback manner; and the first linear feedback system. A coupling unit that couples an output value from the register circuit and an output value from the second linear feedback shift register circuit, and a two-wire encoder of the first data register unit and the second The second 2-wire encoder is configured by a 2-wire encoder of the data register unit, and the first linear feedback shift register circuit includes a first initial value of each of the first data register units, The first exclusive OR operation circuit that executes the exclusive OR operation can be set, and the second linear feedback shift register circuit includes a second data register unit that includes a second data register unit. An asynchronous correlation operation circuit configured to be able to set the initial value and the second exclusive OR operation circuit for executing the exclusive OR operation may be configured.

According to the sixth aspect, the second data supply unit includes the asynchronous data generation circuit that generates the second series data having a length of 2 ^L −1 (L is an integer of 3 or more). This asynchronous data generation circuit includes an L-stage data register section configured by sandwiching a 1-bit data register section between a 2-line decoder and a 2-line encoder, and an (L-1) -stage exclusive OR operation circuit. The second series data is generated by combining two linear feedback shift register circuits connected by linear feedback, and combining output values from the respective linear feedback shift register circuits. Since the second two-line encoder is constituted by the two-line encoder of the first data register unit and the two-line encoder of the second data register unit, the second data constituting the second series data is configured. The data of 2 is two-line encoded and supplied to the asynchronous full adder. Each linear feedback shift register circuit is configured so that an initial value of each data register unit and an exclusive OR operation circuit for executing an exclusive OR operation can be set, and these settings are appropriately set. By doing so, the asynchronous data generation circuit can appropriately generate the second series data.

  In this case, as in the seventh embodiment, the second data supply unit in the asynchronous correlation operation circuit of the sixth embodiment causes the first data corresponding to the second series data to be generated by the asynchronous data generation circuit. And the first exclusive OR operation circuit are set, and the second initial value and the second exclusive OR operation circuit are set according to the second series data. It is effective to configure an asynchronous correlation operation circuit having a setting unit.

  According to the seventh embodiment, the second data supply unit sets the first initial value and the first exclusive OR operation circuit according to the second series data to be generated by the asynchronous data generation circuit. And a setting unit that sets the second initial value and the second exclusive OR operation circuit according to the second series data. As a result, even when there are a plurality of different series data as the second series data, the initial value and the exclusive OR operation circuit are set according to the series data to be generated, so that the desired first 2 series data can be generated by the asynchronous data generation circuit.

  Further, as an eighth aspect, in the asynchronous correlation arithmetic circuit according to any one of the first to seventh aspects, the first series data is series data obtained by sampling a received signal from a satellite in time series, The second series data is series data obtained by sampling the satellite replica code in time series, and constitutes an asynchronous correlation operation circuit that is an asynchronous circuit for calculating a correlation value between the received signal and the replica code. It is good.

  According to the eighth embodiment, it is possible to realize an asynchronous correlation calculation circuit that performs a correlation calculation between a received signal from a satellite and a replica code.

The block diagram which shows an example of a function structure of a GPS receiver. The figure which shows an example of the circuit structure of a 1st asynchronous correlation calculating circuit. The figure which shows an example of the circuit structure of an asynchronous full addition part. Explanatory drawing of the register mechanism for writing of the received data and the register mechanism for reading in the 1st asynchronous correlation calculating circuit. FIG. 3 is an explanatory diagram of a replica data write register mechanism and a read register mechanism in the first asynchronous correlation operation circuit. Explanatory drawing of a structure and operation | movement of a register mechanism. Explanatory drawing of operation | movement of the register mechanism for reading. Explanatory drawing of operation | movement of the register mechanism for reading. Explanatory drawing of the four-phase handshaking in the register mechanism for reading. Explanatory drawing of operation | movement of the register mechanism for writing. Explanatory drawing of operation | movement of the register mechanism for writing. The figure which shows an example of the circuit structure of a 2nd asynchronous correlation calculating circuit. FIG. 10 is an explanatory diagram of a reception data reading register mechanism in a second asynchronous correlation calculation circuit. Explanatory drawing of supply of replica data in the 3rd asynchronous correlation calculating circuit. Explanatory drawing of the replica data reading register | resistor mechanism in a 3rd asynchronous correlation calculating circuit. The figure which shows an example of the circuit structure of a 4th asynchronous correlation calculating circuit. The figure which shows an example of a circuit structure of an asynchronous replica data generation circuit. The figure which shows an example of a circuit structure of an exclusive OR operation circuit. A truth table relating to the operation of the exclusive OR operation circuit. The figure which shows an example of the data structure of the data for a setting.

  Hereinafter, an example of a preferred embodiment to which the present invention is applied will be described with reference to the drawings. The present embodiment is an embodiment to which GPS, which is a kind of satellite positioning system, is applied. Of course, the form to which the present invention can be applied is not limited to the embodiment described below.

  FIG. 1 is a block diagram illustrating an example of a functional configuration of a GPS receiver 1 which is a type of satellite signal receiving apparatus that receives GPS satellite signals. The GPS receiver 1 is a device configured to capture a GPS satellite signal from an RF (Radio Frequency) signal received by a GPS antenna (not shown) and calculate the position using the captured GPS satellite signal. .

  The GPS receiver 1 includes an RF receiving circuit unit 10 and a baseband processing circuit unit 20. The RF receiving circuit unit 10 and the baseband processing circuit unit 20 can be manufactured as separate LSIs (Large Scale Integration) or can be manufactured as one chip.

  The RF receiving circuit unit 10 receives an RF signal output from the GPS antenna, and performs A / D conversion by sampling the received signal (analog signal) at a given sampling time interval. And a reception signal is output as reception sequence data.

  In the present embodiment, description will be made assuming that N received signals for 1 millisecond are sampled to obtain N received data D1 to DN. Further, the description will be made assuming that the received data D1 to DN are converted into M-bit (M ≧ 1) digital data by quantization. In the present embodiment, the received data number is described using “i”. That is, “Di” means the i-th received data. The received data corresponds to the first data.

  The baseband processing circuit unit 20 acquires a GPS satellite signal by performing carrier wave removal, correlation calculation, and the like on the reception sequence data output from the RF reception circuit unit 10. Then, the position and clock error are calculated using time information and satellite orbit information extracted from the captured GPS satellite signal.

  In the present embodiment, the baseband processing circuit unit 20 includes an asynchronous correlation calculation circuit 100, a replica code generation unit 200, a processing unit 300, and a storage unit 400 as main components.

  Asynchronous correlation calculation circuit 100 performs correlation calculation between reception sequence data as first sequence data output from RF reception circuit unit 10 and replica code as second sequence data generated by replica code generation unit 200. Is an asynchronous correlation operation circuit. The configuration and operation of the asynchronous correlation calculation circuit 100 will be described in detail in the first to fourth embodiments.

  The replica code generation unit 200 is a circuit that generates a replica code that is a pseudo code that simulates a C / A code that is a spreading code of a GPS satellite signal. The replica code generation unit 200 generates a replica code related to the GPS satellite to which the PRN number is assigned according to the PRN number (satellite number) output from the processing unit 300. The replica code generation unit 200 includes an oscillator such as a code NCO (Numerical Controlled Oscillator).

  In this embodiment, the replica code is sampled at the same sampling rate as the received signal. Specifically, the replica code for 1 millisecond is sampled into N replica data C1 to CN as many as the received data. In this embodiment, the number of replica data is expressed using “j”. That is, “Cj” means the j-th replica data. Replica data is represented by 1 bit of “0” or “1”. Replica data corresponds to second data.

  The processing unit 300 is a control device and an arithmetic device that collectively control each functional unit of the baseband processing circuit unit 20, and includes a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). Is done.

  The processing unit 300 includes, as main functional units related to the present embodiment, an operation completion detection unit 310, a reception data write control unit 320, a reception data read control unit 330, a replica data write control unit 340, a replica A data read control unit 350. These functional units will be described later.

  The storage unit 400 stores a system program of the baseband processing circuit unit 20, various programs for realizing various functions such as a satellite acquisition / tracking control function, and a position calculation function, data, and the like. In addition, it has a work area for temporarily storing data being processed and results of various processes.

1. 1. First embodiment 1-1. Configuration of Asynchronous Correlation Operation Circuit FIG. 2 is a diagram illustrating an example of a circuit configuration of the first asynchronous correlation operation circuit 100A in the first embodiment. In the drawings to be referred to below, the flow of data that has been subjected to two-line coding is indicated by a bold line to distinguish it from data that has not been two-line coded.

  The first asynchronous correlation calculation circuit 100A includes a reception data supply unit 110, a replica data supply unit 120, an asynchronous full addition unit 150, a two-line decoding unit 160, an addition result storage unit 170, and an addition result two-line code. And a conversion unit 180.

  The reception data supply unit 110 uses the reception sequence data output from the RF reception circuit unit 10 for the next calculation every time the operation of the asynchronous full addition unit 150 is completed among the M-bit reception data sampled in time series. A data supply unit that supplies received data to be transmitted. The reception data supply unit 110 includes a reception data storage unit 110A, a reception data 2-wire encoding unit 110B, and a reception data selection unit 110C.

  The reception data storage unit 110 </ b> A is a storage circuit that stores M-bit reception data constituting the reception sequence data output from the RF reception circuit unit 10. In the present embodiment, the reception data storage unit 110A includes a reception data register group that stores the reception data corresponding to each reception data.

  The reception data 2-line encoding unit 110B performs 2-line encoding on the reception data output from the reception data storage unit 110A according to the 2-line encoding method. In the present embodiment, the reception data two-line encoding unit 110B is configured to have a two-line encoder corresponding to each of the reception data registers constituting the reception data storage unit 110A. Received data 2-line encoding section 110B corresponds to a first 2-line encoding section.

  Received data selecting section 110C has a received data reading register mechanism that moves the read token to the next read token register stage each time the operation of asynchronous full adder 150 is completed. The reception data is sequentially supplied to the asynchronous full adder 150 by selecting the reception data 2-wire encoder corresponding to the reception data to be subjected to the calculation.

  The replica data supply unit 120 completes the operation of the asynchronous full adder 150 for the replica data to be used for the next operation among the 1-bit replica data obtained by sampling the replica code output from the replica code generation unit 200 in time series. This is a data supply unit that is supplied every time. The replica data supply unit 120 includes a replica data storage unit 120A, a replica data 2-wire encoding unit 120B, and a replica data selection unit 120C.

  The replica data storage unit 120A is a storage device that stores replica data constituting the replica code output from the replica code generation unit 200. In the present embodiment, the replica data storage unit 120A is configured to include a replica data register group that stores the replica data corresponding to each replica data.

  The replica data 2-line encoding unit 120B is an encoding unit that performs 2-line encoding on the replica data output from the replica data storage unit 120A according to the 2-line encoding method. In the present embodiment, the replica data two-line encoding unit 120B includes a two-line encoder corresponding to each replica data register constituting the replica data storage unit 120A. The replica data 2-line encoding unit 120B corresponds to a second 2-line encoding unit.

  The replica data selection unit 120C has a replica data read register mechanism that moves the read token to the next read token register stage every time the operation of the asynchronous full adder is completed. Then, by selecting a replica data 2-wire encoder corresponding to replica data to be subjected to the next calculation based on the read token, the asynchronous full adder 150 is made to supply replica data sequentially.

Table 1 shows a truth table of the two-line coding method.

  The two-line encoding method is a method for expressing 1-bit data b using two signal line pairs “(b_1, b_0)”. “B — 1” corresponds to a positive signal line, and “b — 0” corresponds to a negative signal line. A state in which “(b — 1, b — 0)” is “(0, 0)” is called “Null”, and is used to separate data. The state “(0, 1)” represents “0”, and the state “(1, 0)” represents “1”. The state “(1, 1)” is called Inhibit, which is an illegal value that cannot be taken in operation.

  In the asynchronous circuit, data input / output between circuit blocks is performed using data that has been two-line encoded in accordance with this two-line encoding method. Data input / output is performed using the valid codeword “1” or “0”. The invalid code word “Null” is used at the time of non-calculation or for delimiting between data. If the same valid codeword is transmitted continuously, the data side cannot be identified on the receiving side, so valid codewords and invalid codewords are transmitted alternately to identify valid codewords. It is possible.

  Asynchronous full adder 150 adds the output value from reception data supply unit 110 to the output value of addition result two-line encoding unit 180 with a code corresponding to the output value from replica data supply unit 120 and outputs the result. . Asynchronous full adder 150 includes first input port X, second input port Y, carry input port Cin, and output port Z.

Reception data “(Di_1, Di_0)” that has been two-line encoded by the reception data two-line encoding unit 110B is input to the first input port X.
The product-sum operation value “(A_1, A_0)” of the asynchronous full adder 150 that has been two-line encoded by the addition result two-line encoder 180 is fed back to the second input port Y.
The carry input port Cin receives replica data “(Cj_1, Cj_0)” that has been two-line encoded by the replica data two-line encoding unit 120B.

  Each received data Di is M-bit data. On the other hand, the replica data Cj is 1-bit data. Asynchronous full adder 150 uses 1-bit replica data Cj as a carry input, and adds received data Di to the latest product-sum operation value A of asynchronous full adder 150 with a code corresponding to replica data Cj. By sequentially supplying the received data Di and the replica data Cj to the asynchronous full adder 150, the asynchronous full adder 150 performs a product-sum operation on the received data Di and the replica data Cj.

  The 2-line decoding unit 160 decodes the product-sum operation value A output from the asynchronous full addition unit 150 according to the 2-line encoding method. Asynchronous full adder 150 performs an operation using a 2-line encoded bit value, and the operation result is also 2-line encoded, so that product-sum operation value A is decoded according to the truth table of Table 1. Then, the result is output to the addition result storage unit 170.

  The addition result storage unit 170 is a storage circuit that stores the product-sum operation value A decoded by the two-wire decoding unit 160, and is configured as an accumulator, for example. The product-sum operation value A stored in the addition result storage unit 170 is output to the processing unit 300 and also output to the addition result two-line encoding unit 180 as feedback.

  The addition result two-line encoding unit 180 is a two-line encoder that performs two-line encoding on the product-sum operation value A input from the addition result storage unit 170. The two-line encoded product-sum operation value A is input to the second input port Y of the asynchronous full adder 150. The addition result 2-line encoding unit 180 corresponds to a third 2-line encoding unit.

When the shift amount of the replica data with respect to the received data is “k”, the correlation value “Corr (k)” calculated in the asynchronous full adder 150 is given by the following equation (1).

For example, when the shift amount of replica data is set to zero (k = 0), the correlation value “Corr (0)” calculated by the asynchronous full adder 150 is given by the following equation (2).

  Each time processing completion detector 310 detects that operation of asynchronous full adder 150 has been completed, processing unit 300 receives received data to be used for the next operation of received data by received data read control unit 330. Are sequentially read out from the reception data register, and the reception data is output from the reception data 2-wire encoding unit 110B. At the same time, the replica data read control unit 350 performs control to sequentially read from the replica data register the replica data to be used for the next calculation of the replica data, and the replica data two-line encoding unit The replica data is output from 120B.

  For example, the calculation completion detection unit 310 detects the completion of the calculation by the asynchronous full addition unit 150 based on a change in the product-sum calculation value A output from the addition result storage unit 170. That is, it is determined that one new calculation has been completed in the asynchronous full adder 150 because the product-sum operation value A stored in the addition result storage unit 170 has changed from the previous value.

1-2. Configuration of Asynchronous Full Adder FIG. 3 is a diagram illustrating an example of a circuit configuration of the asynchronous full adder 150. The asynchronous full adder 150 includes a logical NOT circuit 151, a selection circuit 153, and a full adder 155.

  The logical negation circuit 151 is a circuit that logically negates the two-line encoded reception data input from the reception data two-line encoding unit 110 </ b> B, and outputs a logical negation result to the selection circuit 153.

  The selection circuit 153 generates a logical negation by the logical negation circuit 151 based on the reception data output from the reception data 2-line encoding unit 110B based on the 2-line encoded replica data input from the replica data 2-line encoding unit 120B. It is a circuit that alternatively selects the received data. The selection circuit 153 outputs the selected received data to the full adder 155.

  When the input replica data Cj is “0”, the selection circuit 153 selects the reception data output from the reception data 2-line encoding unit 110 </ b> B and outputs it to the full adder 155. On the other hand, when the input replica data Cj is “1”, the logically negated received data output from the logical negation circuit 151 is selected and output to the full adder 155.

  In the logical negation circuit 151, the one's complement of the received data is calculated. When “1” of the replica data is added to the calculation result, the two's complement of the received data is obtained. Subtraction is realized by adding the 2's complement of the reduction number to the reduced number. In this case, the subtraction is the received data Di, and the subtracted number is the product-sum operation value A. Therefore, when the replica data Cj is “1”, the full adder 155 adds (ie, subtracts) the received data Di to the latest product-sum operation value A with the sign inverted. On the other hand, when the replica data Cj is “0”, the full adder 155 adds the received data Di as it is without inverting the sign to the latest product-sum operation value A.

  That is, the asynchronous full adder 150 adds or subtracts the received data Di to the product-sum operation value A based on whether the replica data Cj is “0” or “1” based on the two's complement expression. It can be said that.

1-3. Configuration of Register Mechanism Each time the calculation completion detection unit 310 detects the completion of the calculation of the asynchronous full addition unit 150, the reception data selection unit 110C sequentially switches the reception data to be used for the next calculation among the reception series data. A reception data reading register mechanism is provided as a mechanism for selection. In addition, the replica data selection unit 120C sequentially switches and selects the replica data to be used for the next calculation in the replica code every time the calculation completion detection unit 310 detects the completion of the calculation of the asynchronous full addition unit 150. As a mechanism, a replica data reading register mechanism is provided.

The reception data read register mechanism is provided with a read token register stage that communicates with each other according to the four-phase handshaking protocol in association with each received data, and the read token is configured to circulate through the read token register stage. It is a register mechanism. The received data read register mechanism moves the read token to the next read token register stage every time the operation of the asynchronous full adder 150 is completed. Then, the reception data 2-line encoder corresponding to the reception data to be subjected to the next calculation is selected based on the read token to supply the 2-line encoded reception data to the asynchronous full adder 150.
The same applies to the replica data read register mechanism.

  Further, the first asynchronous correlation operation circuit 100A includes a reception data write register mechanism as a mechanism for realizing writing of reception data to the reception data register. In addition, a replica data writing register mechanism is provided as a mechanism for realizing writing of replica data to the replica data register.

The reception data write register mechanism is a write register mechanism in which a write token register stage that communicates with each other by a four-phase handshaking protocol is associated with each reception data register. It is a mechanism that sequentially moves to the write token register stage of the stage and stores received data in a corresponding received data register based on the write token.
The same applies to the replica data writing register mechanism.

1-3-1. FIG. 4 is a schematic configuration diagram of a received data reading register mechanism and a received data writing register mechanism related to reading and writing of received data.
The reception data storage unit 110A includes reception data registers Rd1 to RdN for storing reception data D1 to DN, respectively. The reception data 2-line encoding unit 110B includes reception data 2-line encoders Ed1 to EdN associated with the reception data registers Rd1 to RdN on a one-to-one basis. From the reception data registers Rd1 to RdN, the stored reception data is output to the corresponding reception data 2-line encoders Ed1 to EdN as needed. The reception data selection unit 110C includes a reception data reading register mechanism as a mechanism for selecting a reception data 2-wire encoder corresponding to reception data to be subjected to the next calculation.

(1) Received data read register mechanism The received data read register mechanism is configured by annularly connecting N read token register stages Sd1 to SdN respectively connected to the received data 2-wire encoders Ed1 to EdN. The Since the read token register stages Sd1 to SdN are connected in a ring shape, the read token circulates through the read token register stage. That is, the read token moves (transitions) sequentially from the read token register stage from Sd1, reaches SdN, and then returns to Wd1 again. The reception data read register mechanism moves the read token between the read token register stages, and sequentially switches the access rights to the reception data 2-line encoders Ed1 to EdN, thereby receiving the reception data 2-line encoder Ed1. This is a mechanism for causing the asynchronous full adder 150 to output received data that has been subjected to two-line encoding from .about.EdN.

  Since the operation of the read register mechanism will be described in detail later, a procedure until the reception data 2-wire encoder executes 2-wire encoding will be briefly described here. Receiving data read control unit 330 receives the detection completion of asynchronous full adder 150 by calculation completion detection unit 310, and outputs read request signal Get to the read token register stage holding the read token. The read token register stage that has input the read request signal Get outputs a two-line encoding instruction signal Send to the reception data two-line encoder to which it is connected, and receives the reception data output from the corresponding reception data register. The received data 2-line encoder is subjected to 2-line encoding and output.

  For example, in FIG. 4, the read token is held by the read token register stage Sd2 (Sd2 is shown by a double circle). Therefore, the received data read control unit 330 outputs a read request signal Get to the read token register stage Sd2 (see solid line arrow). Then, the read token register stage Sd2 outputs a 2-line encoding instruction signal Send to the reception data 2-line encoder Ed2 (see solid line arrow). In response to this, the reception data 2-line encoder Ed2 performs 2-line encoding on the reception data D2 output from the reception data register Rd2 (see the thick solid arrow).

(2) Write register mechanism The receive data write register mechanism is configured by annularly connecting N write token register stages Wd1 to WdN respectively connected to the receive data registers Rd1 to RdN. Since the write token register stages Wd1 to WdN are connected in a ring shape, the write token circulates through the write token register stage. That is, the write token moves (transitions) sequentially from the write token register stage from Wd1, reaches WdN, and then returns to Wd1 again. The reception data write register mechanism moves the write token between the write token register stages, and switches the access right to the reception data registers Rd1 to RdN, whereby the reception data registers Rd1 to RdN receive data. This is a mechanism for sequentially realizing writing.

  The reception data write control unit 320 outputs a write request signal Put to the write token register stage holding the write token. In response to this, the write token register stage outputs the capture instruction signal Wr to the reception data register of the connection destination, thereby causing the reception data register of the corresponding number to be captured.

  For example, in FIG. 4, the write token is held in the write token register stage Wd3 (Wd3 is indicated by a double circle). Therefore, the received data write control unit 320 outputs the write request signal Put to the write token register stage Wd3 (see solid line arrow). In response to this, the write token register stage Wd3 outputs a capture instruction signal Wr to the reception data register Rd3 (see solid line arrow), and causes the reception data register Rd3 to capture reception data D3 (see solid line arrow). .

1-3-2. FIG. 5 illustrates the configuration of a register mechanism for replica data.
The replica data storage unit 120A has a replica data register group that stores the replica data corresponding to each of the replica data C1 to CN. The replica data register group includes N replica data registers Rc1 to RcN. Further, the replica data 2-line encoder 120B includes replica data 2-line encoders Ec1 to EcN corresponding to the replica data registers constituting the replica data register group. The replica data selection unit 120C includes a replica data read register mechanism as a mechanism for selecting a replica data 2-wire encoder corresponding to replica data to be subjected to the next operation.

  The replica data read register mechanism is configured by annularly connecting N read token register stages Sc1 to ScN connected to the replica data 2-line encoders Ec1 to EcN, respectively. The replica data write register mechanism is configured by annularly connecting N write token register stages Wc1 to WcN connected to the replica data registers Rc1 to RcN, respectively.

  The operations of the replica data reading register mechanism and the replica data writing register mechanism are the same as the operations of the reception data reading register mechanism and the reception data writing register mechanism described in FIG. However, the control mechanism of the register mechanism is different, the replica data read register mechanism is controlled by the replica data read control unit 350, and the replica data write register mechanism is controlled by the replica data write control unit 340.

1-3-3. Specific Configuration and Operation of Register Mechanism Next, the configuration and operation of the above-described read register mechanism and write register mechanism will be described in detail. The configuration and operation of these register mechanisms are the same for both the received data register mechanism and the replica data register mechanism. For this reason, a generalized description will be given here. That is, the register mechanism for reading data and the register mechanism for reading replica data are comprehensively used as a register mechanism for reading, and the register mechanism for writing the received data and the register mechanism for writing replica data are comprehensively used as a register mechanism for writing. explain.

  FIG. 6 (1) is an overall configuration diagram of the write register mechanism and the read register mechanism, and FIG. 6 (2) focuses on the nth write token register stage and read token register stage. It is a circuit block diagram. The register stage is generalized, the write token register stage is expressed as “Wn = W1 to WN”, and the read token register stage is expressed as “Sn = S1 to SN”. Further, a data register for storing data is generalized and expressed as “Rn = R1 to RN”, and a two-line encoder that encodes data into two lines is generalized and expressed as “En = E1 to EN”. .

  As shown in FIG. 6A, two adjacent write token register stages of the write register mechanism are connected by two signal lines. In addition, the signal lines are folded at the write token register stages W1 and WN located at the end portions. Each write token register stage W1-WN is connected to a data register R1-RN, respectively.

  Similarly, two adjacent read token register stages of the read register mechanism are connected by two signal lines. In addition, the signal lines are folded at the read token register stages S1 and SN located at the end portions. However, each read token register stage S1 to SN is connected to a two-line encoder E1 to EN, respectively.

  As shown in FIG. 6B, the write token register stage and the read token register stage include an AND element P1, a negative input type AND element P2, a C element Q1, and a negative output type C element Q2, respectively. Are connected to each other.

The C element is a logic element known as a Muller C element, and its truth table is shown in Table 2.

  As shown in Table 2, the C element is an element that outputs “0” when both inputs become “0” and outputs “1” when both inputs become “1”. It has a storage element inside and keeps the previous value while the two inputs are different, and does not change the output.

  Next, signals used in the write register mechanism will be described. The register stage on the start point side of the arrow representing the signal line is defined as the upstream register stage, and the register stage on the end point side of the arrow is defined as the downstream register stage.

  In the write register mechanism shown in FIG. 6 (2), “lcPut” and “rcPut” are signals for transmitting the upper signal line of the write register mechanism, and indicate that the write token transfer mode is set. (Hereinafter referred to as “write token transfer mode signal”). “LcPut” indicates a signal from the upstream write token register stage, and “rcPut” indicates a signal to the downstream write token register stage. When these write token transfer mode signals are asserted, the write token transfer mode is turned ON, and when negated, it is turned OFF.

  “RdPut” and “ldPut” are signals transmitted through the lower signal line of the write register mechanism, and are signals (hereinafter referred to as “write token transfer signals”) indicating that the write token is transferred. ). “RdPut” is a signal from the upstream write token register stage, and “ldPut” is a signal to the downstream write token register stage. These write token transfer signals are signals for transferring the write token to the next write token register stage.

  “Put” is a write request signal from the write control unit, and “ackPut” is a write authentication signal for the write control unit. In the reception data write register mechanism, the reception data write control unit 320 is a write control unit, and in the replica data write register mechanism, the replica data write control unit 340 is a write control unit. “Wr” is a data take-in instruction signal output from the write token register stage to the connected data register.

  Similarly, signals used in the read register mechanism will be described. In the circuit of FIG. 6 (2), “lcGet” and “rcGet” are signals transmitted on the lower signal line of the read register mechanism, and signals indicating the transfer mode of the read token (hereinafter, “ This is referred to as a “read token transfer mode signal”. “LcGet” is a signal from the upstream read token register stage. “RcGet” is a signal to the downstream read token register stage. When these read token transfer mode signals are asserted, the read token transfer mode is turned ON, and when it is negated, it is turned OFF.

  “RdGet” and “ldGet” are signals that are transmitted through the upper signal line of the read register mechanism, and are signals that represent transfer of a read token (hereinafter referred to as “read token transfer signal”). “RdGet” is a signal from the upstream read token register stage. “LdGet” is a signal to the downstream read token register stage. These read token transfer signals are signals for transferring the read token to the next read token register stage.

  “Get” is a read request signal from the read control unit, and “ackGet” is a read authentication signal for the read control unit. In the received data read register mechanism, the received data read control unit 330 is a read control unit, and in the replica data read register mechanism, the replica data read control unit 350 is a write control unit. “Send” is a 2-line encoding instruction signal output from the write token register stage to the connected 2-line encoder.

  Next, the operation of each register mechanism will be described. The operations of the write register mechanism and the read register mechanism are similar to each other. If the operation of one register mechanism is described, the operation of the other register mechanism is obvious. Therefore, here, description will be given focusing on the operation of the read register mechanism.

  7 and 8 are explanatory diagrams of the operation of the read register mechanism. 7 and 8, signal lines related to signals that are asserted and are in an active state are indicated by thick solid lines, and signal lines that are related to signals that are negated and are in an inactive state are indicated by normal solid lines. It is shown. In addition, the signal whose value has changed is indicated by surrounding the value with a rectangle.

  In the initial state, as shown in FIG. 7A, lcGet, rcGet, rdGet, ldGet, and Get are “0” for all the read token register stages. In this case, the output of each logic element is as shown in FIG.

  Next, in order to shift to the read token transfer mode, lcGet of the read token register stage SN is asserted starting from the read token register stage SN. Then, the output of the AND element P2 changes to “1”, and accordingly, rcGet for the downstream read token register stage is asserted.

  As described above, the read token register stage is connected by the two signal lines. Therefore, when rcGet of the most upstream read token register stage SN is asserted, all lcGet and rcGet up to the most downstream read token register stage S1 are asserted. That is, when rcGet of the read token register stage SN is asserted, lcGet of the read token register stage S (N−1) immediately below it is asserted. Then, rcGet of the read token register stage S (N−1) is asserted.

  By repeating this, lcGet of the most downstream read token register stage S1 is asserted, and rcGet is asserted. This means that the read register mechanism has shifted to the transfer mode for transferring the read token. This state is the state shown in FIG.

  From here, the read tokens are transferred in order from the read token register stages S1 to SN. In the read token register stage S1, the signal line is folded. Therefore, when rcGet of the read token register stage S1 is asserted, rdGet requesting the read token register stage S1 to transfer the read token is asserted. This means that the read token has moved to the read token register stage S1. This state is the state shown in FIG.

  The read control unit asserts Get to cause the read token register stage S1 holding the read token to read data. Then, the output of the C element Q1 changes from “0” to “1”, thereby asserting the two-line encoding instruction signal Send to the two-line encoder. As a result, the 2-line encoder E1 performs 2-line encoding of the data output from the data register, and the 2-line encoded data is output to the asynchronous full adder 150.

  Further, ackGet is asserted when Get is asserted. Further, rcGet is negated when the output of the AND element P1 changes from “1” to “0”. This state is the state shown in FIG.

  As rcGet is negated, rdGet that is looped back and input to the read token register stage S1 is negated. This state is the state shown in FIG.

  The read controller that has received the read authentication signal from the read token register stage S1 negates the read request signal Get for the read token register stage S1. Then, the output of the C element Q1 changes from “1” to “0”, and accordingly, the two-line encoding instruction signal Send is negated. Thereby, the two-line encoding of data in the two-line encoder is stopped.

  Accordingly, ackGet is negated. Further, when the output of the AND element P2 changes from “0” to “1”, ldGet is asserted. This means that the read token is transferred to the next read token register stage S2. This state is the state shown in FIG.

  By the procedure so far, the operation related to reading of data in the read token register stage S1 is completed. When the read token is transferred to the next read token register stage S2 in FIG. 8 (3), the data reading in the read token register stage S2 is performed in the same procedure. By repeating this procedure up to the read token register stage SN, data is read sequentially from the read token register stage S1, and the 2-line encoded data is sequentially supplied to the asynchronous full adder 150. .

  When the correlation calculation for one time by the asynchronous full adder 150 is completed, the replica data reading start position is shifted by one, and the replica data is sequentially read again and supplied to the asynchronous full adder 150. Correlation calculation with the received signal can be performed by shifting the phase of the code. In this case, in the initial state, the read token register stage for storing the read token may be shifted by one, and the read token may be controlled to move in order starting from the read token register stage.

  FIG. 9 is an explanatory diagram of communication by four-phase handshaking in the read register mechanism, in which the transition of each signal is illustrated in time series. First, when lcGet is asserted, rcGet is asserted (state shown in FIG. 7 (2)), and accordingly, rdGet is asserted (state shown in FIG. 7 (3)). When Get is asserted in this state, Send is asserted (state shown in FIG. 8 (1)).

  When Send is asserted, rcGet is negated, and rdGet is negated accordingly (state (2) in FIG. 8). When Get is negated in this state, Send is negated and ldGet is asserted (state shown in FIG. 8 (3)).

  Adjacent read token register stages communicate with each other using a four-phase handshaking protocol. In other words, in response to the assertion of the read token transfer mode signal rcGet, a certain read token register stage (hereinafter referred to as “request source read token register stage”) is one downstream read token register stage (hereinafter “ When the read token transfer mode signal rdGet is asserted as a request to the request destination read token register stage, the request destination read token register stage uses the read token transfer mode signal rcGet as an acknowledge to the request source read token register stage. To negate. Upon receiving the negation of the read token transfer mode signal rcGet, the request source read token register stage negates the read token transfer signal rdGet for the request destination read token register stage.

  That is, when the transmitting side asserts a request signal between adjacent read token register stages, the receiving side asserts an acknowledge signal in response to the assertion. Then, the transmitting side negates the request signal, and the receiving side negates the acknowledge signal in response to this. Therefore, the read token register stages communicate with each other using a four-phase handshaking protocol.

  10 and 11 illustrate the operation procedure in the write register mechanism. As described above, the operation of the write register mechanism is in accordance with the operation of the read register mechanism. Based on the operation of the read register mechanism described with reference to FIGS. The operation of can be similarly derived. Therefore, detailed description of the operation of the write register mechanism will be omitted by performing illustration only.

1-4. Effect In the first asynchronous correlation operation circuit 100A, the asynchronous full adder 150 is configured to input 2-line encoded data, so that the asynchronous full adder 150 reliably detects the arrival of valid data. Thus, it becomes possible to perform the calculation. The asynchronous full adder 150 performs an operation of adding received data to the latest addition result of the asynchronous full adder 150. In this case, if the sign of the replica data that is the counterpart of the correlation calculation is positive, the received data is added (ie, added), and if the sign of the replica data that is the counterpart of the correlation calculation is negative, the sign of the received data is By inverting and adding (that is, subtracting), the correlation calculation between the received signal and the replica code can be performed correctly.

  The first asynchronous correlation arithmetic circuit 100A does not require a synchronization mechanism such as a clock for driving the correlation arithmetic circuit, and can operate only in a circuit block to which data is exchanged in principle, and thus can operate at high speed. In addition, power consumption can be reduced. In general, in a complementary metal oxide semiconductor (CMOS) circuit, power consumption is proportional to the total number of switching transistors within a certain time. However, in the first asynchronous correlation arithmetic circuit 100A, only the transistors necessary for the operation are switched, so that the total number of switching can be minimized. This leads to a reduction in power consumption.

  Further, in the first asynchronous correlation operation circuit 100A, the input mechanism and the output mechanism to the storage unit for received data and replica data are realized by a write register mechanism and a read register mechanism. The received data and the replica data are written in the data registers corresponding to each one-to-one before the calculation, and are sequentially supplied from the data register for each calculation using a token passing system. With this configuration, energy reduction and phase shift for data supply are realized.

  More specifically, when data is supplied by a shift register method that has been generally used in the past, it is necessary to move the data itself, so that the total number of switching of transistors becomes enormous. However, in the token passing method of this embodiment, it is not necessary to move the data itself, and only the token needs to be moved. Therefore, the total number of switching of the transistor is greatly reduced, the coherent noise is greatly reduced, and the power consumption is greatly reduced. Reduction can be realized.

  In the GPS receiver, in order to detect the code phase of the received signal, the correlation calculation between the received signal and the replica code is performed by shifting the phase of the received signal or the replica code. In the asynchronous correlation operation circuit according to the present embodiment, for either one of the reception data reading register mechanism and the replica data reading register mechanism, the initial storage position of the read token is shifted and the data reading start position is shifted, thereby simplifying. A phase shift can be realized.

  In addition to these, in the first asynchronous correlation arithmetic circuit 100A, the clock skew caused by the propagation delay of the clock signal, the wiring delay of the circuit, etc., the clock of the correlation arithmetic circuit and the baseband processing circuit unit 20 Problems that may arise when a correlation operation circuit is designed by a synchronous design method, such as a synchronization problem due to a difference in frequency with the clock of the main circuit and a portability problem of a correlation operation circuit derived therefrom, can be avoided.

2. Second Embodiment Asynchronous correlation calculation circuit according to the second embodiment includes (2 ^K −1) asynchronous full adders in which an asynchronous full adder adds 2 ^K (K is an integer of 1 or more) received data. Is a configuration having a tournament type full adder group arranged in a tournament type.

  In the first asynchronous correlation operation circuit 100A described in the first embodiment, the received data Di and the replica data Cj are input to the asynchronous full adder one by one and the operation of adding to the latest product-sum operation value A is repeated. Thus, the correlation value given by equation (1) was calculated. However, this method requires many calculation steps until a correlation value is finally obtained. Therefore, by multiplying the reception data Di and the replica data Cj in parallel and adding the multiplication values, the calculation steps until the correlation value is obtained are reduced, and the calculation processing time is shortened. Plan.

2-1. Configuration of Asynchronous Correlation Operation Circuit FIG. 12 is a diagram illustrating an example of a circuit configuration of the second asynchronous correlation operation circuit 100B in the second embodiment. Here, a case where the second asynchronous correlation calculation circuit 100B is configured with “K = 2” will be described as an example. The same components as those in the first asynchronous correlation calculation circuit 100A are denoted by the same reference numerals and the description thereof is omitted.

  In FIG. 12, the received data storage unit 110A and the received data 2-line encoding unit 110B, and the replica data storage unit 120A and the replica data 2-line encoding unit 120B are not shown for the sake of simplicity. That is, the reception data Di and the replica data Cj that have been two-line encoded by the two-line encoder are illustrated as being supplied to the second asynchronous correlation calculation circuit 100B.

  The second asynchronous correlation calculation circuit 100B includes a tournament-type full adder group 250, an asynchronous full adder 150, a two-line decoder 160, an addition result storage unit 170, and an addition result two-line encoder 180. It is configured.

The tournament type full adder group 250 includes three asynchronous full adders, a first asynchronous full adder 251 to a third asynchronous full adder 253. Specifically, the tournament-type full adder group 250 includes “(2 ² −1) = 3” asynchronous full adders that add “2 ² = 4” received data in a tournament type. Composed. That is, the first asynchronous full adder 251 and the second asynchronous full adder 252 are arranged in the lower stage, and the third asynchronous full adder 253 is arranged in the upper stage. The configuration of these asynchronous full adders is the same as that of the asynchronous full adder 150 described with reference to FIG.

  In the tournament-type full adder group 250, the asynchronous full adders 251 and 252 which are the lowest level asynchronous full adders receive the received data 2-line code related to one received data of the two received data to be added. In accordance with the output value of the replica data 2-line encoding unit related to the two replica data that is the counterpart of the correlation operation, the output value of the receiving unit corresponding to the other reception data Add by sign.

  Specifically, in the first asynchronous full adder 251, the reception data D <b> 1 that has been two-line encoded by the reception data two-line encoder is input to the first input port X. The second input port Y receives the reception data D2 that has been two-line encoded by the reception data two-line encoding unit. The carry input port Cin receives an exclusive OR of the replica data C1 and C2 that are two-line encoded by the replica data two-line encoding unit.

  In the first asynchronous full adder 251, the replica data C1 and C2 become the two replica data of the counterpart of the correlation calculation. When the exclusive OR of the replica data C1 and C2 is “0”, the reception data D1 is added to the reception data D2 as it is. On the other hand, when the exclusive OR of the replica data C1 and C2 is “1”, the received data D1 is inverted in sign and added (ie, subtracted) to the received data D2.

  In the second asynchronous full adder 252, similarly to the first asynchronous full adder 251, the two-line encoded received data D3 and D4 are replica data that are two replica data that are counterparts of the correlation calculation. Addition is performed with a sign corresponding to the exclusive OR of C3 and C4. That is, when the exclusive OR of the replica data C3 and C4 is “0”, the reception data D3 is added to the reception data D4 as it is. On the other hand, when the exclusive OR of the replica data C3 and C4 is “1”, the received data D3 is inverted in sign and added (that is, subtracted) to the received data D4.

  When the phase shift amount of the replica code is set to zero (k = 0), an arithmetic expression for obtaining a correlation value is given by Expression (2). In this case, the first asynchronous full adder 251 calculates the product-sum value of the first term and the second term on the right side of Equation (2), and the product-sum operation value A1 is the third asynchronous full adder. Is output to H.253. The second asynchronous full adder 252 calculates the product sum value of the third term and the fourth term on the right side of the expression (2), and the product sum operation value A2 is calculated as the third asynchronous full adder 253. Is output.

  In the third asynchronous full adder 253, the product-sum operation value A1 of the first asynchronous full adder 251 is input to the first input port X, and the second asynchronous input to the second input port Y is the second asynchronous full adder 253. The product-sum operation value A2 of the full adder 252 is input. Further, an exclusive OR of the replica data C1 and C3 is input to the carry input port Cin. Then, the product-sum operation values A1 and A2 are added with a code corresponding to the exclusive OR of the replica data C1 and C3, and the product-sum operation value A3 as the addition result is output to the asynchronous full adder 150. .

  In the asynchronous full adder 150, the product-sum operation value A3 of the third asynchronous full adder 253 is input to the first input port X, and the addition result two-line encoding unit is input to the second input port Y. The latest product-sum operation value A4 output from 180 is input. The replica data C1 is input to the carry input port Cin. Then, the product-sum operation values A3 and A4 are added with a code corresponding to the replica data C1, and the addition result is output to the 2-wire code decoding unit 160.

2-2. Configuration of Reading Register Mechanism In the second asynchronous correlation operation circuit 100B of FIG. 12, every time the operation of the asynchronous full adder 150 is completed, 2 ^K received data to be used for the next operation are selected and the tournament It is necessary to supply the type full adder group 250. Therefore, as in the first embodiment, the second asynchronous correlation operation circuit is provided with a received data reading register mechanism in which read token register stages communicating with each other by a four-phase handshaking protocol are associated with each received data. 100B is provided. In this case, each read token register stage is configured to be associated with a reception data 2-line encoder corresponding to 2 ^K reception data to be calculated by the asynchronous full adder.

  FIG. 13 is a diagram illustrating a configuration example of the received data reading register mechanism in the case of “K = 2”. This received data reading register mechanism is configured such that four received data are simultaneously encoded in two lines with one read token and supplied to the tournament type full adder group 250.

  Specifically, the read data read register mechanism is configured to have “L = N / 4” read token register stages Sd1 to SdL. Each read token register stage is connected to four 2-wire encoders corresponding to data registers related to four consecutive received data. However, four connection destinations are selected in order of time series of received data so that the two-line encoders of connection destinations do not overlap between adjacent read token register stages.

  More specifically, the read token register stage Sd1 is connected to reception data 2-line encoders Ed1 to Ed4 corresponding to the reception data registers Rd1 to Rd4. The next read token register stage Sd2 is connected to reception data 2-line encoders Ed5 to Ed8 corresponding to reception data registers Rd5 to Rd8. The same applies hereinafter.

  In this case, each read token register stage outputs a two-wire encoding instruction signal Send simultaneously to the four reception data two-wire encoders to be connected, thereby corresponding to four consecutive reception data. The two-line encoder performs two-line encoding and supplies the result to the tournament type full adder group 250. The example of FIG. 13 shows a state in which the read token register stage Sd1 indicated by a double circle outputs a two-line encoding instruction signal Send as indicated by a solid line to the reception data two-line encoders Ed1 to Ed4. ing.

Similarly, for replica data, every time the operation of the asynchronous full adder is completed, “2 ² = 4” replica data to be used for the next operation is selected and supplied to the tournament type full adder group 250. There is a need. Therefore, although not shown, similar to the received data reading register mechanism of FIG. 13, the replica data reading register mechanism configured to include “L = N / 4” read token register stages Sc1 to ScL. May be configured.

The reception data reading register mechanism provided in the second asynchronous correlation calculation circuit 100B communicates with each other by a four-phase handshaking protocol, similarly to the reception data reading register mechanism provided in the first asynchronous correlation calculation circuit 100A. This is a read register mechanism in which a matching read token register stage is provided in association with each received data. In this register mechanism, each read token register stage is associated with a received data 2-wire encoder corresponding to 2 ^K received data to be operated by the tournament type full adder group, and the operation of the asynchronous full adder is performed. Each time it is completed, the read token is moved to the next read token register stage. In addition, a received data 2-line encoder corresponding to 2 ^K received data to be used for the next calculation is selected based on the read token, and the received data is 2-line encoded in the selected received data 2-line encoder. Let
The same applies to the replica data read register mechanism.

3. Third Embodiment In the third embodiment, a plurality of second asynchronous correlation calculation circuits described in the second embodiment are arranged, the phases of the replica codes are shifted from each other, and the correlation is made to each second asynchronous correlation calculation circuit. It is embodiment which applied the structure which performs a calculation in parallel.

As a specific example, a case will be described in which correlation calculation is performed by arranging four second asynchronous correlation calculation circuits 100B in the case of “K = 2” described in FIG. In this case, “2 ² = 4” received data and replica data are supplied to each of the four second asynchronous correlation calculation circuits 100B to cause the tournament type full adder group 250 to perform calculation. .

  The reception data Di is controlled so that the same data is supplied to the four second asynchronous correlation calculation circuits 100B in one calculation. That is, in the first calculation, the received data D1 to D4 are simultaneously supplied to each second asynchronous correlation calculation circuit 100B, and in the second calculation, each second asynchronous correlation calculation circuit 100B is supplied. On the other hand, the reception data D5 to D8 are supplied simultaneously. In the same manner, reception data is supplied in a time series of four pieces up to reception data DN.

  As a mechanism for realizing the supply of such reception data, the reception data reading register mechanism shown in FIG. 13 can be applied. That is, the reception data reading register mechanism shown in FIG. 13 may be provided in association with each of the four second asynchronous correlation arithmetic circuits 100B, and the reception data may be read by the token passing method.

  On the other hand, with respect to the replica data Cj, control is performed so that the four second asynchronous correlation calculation circuits 100B are respectively supplied with four data with the reading start position shifted by one. This is because the phase of the replica code is shifted to cause the four second asynchronous correlation calculation circuits 100B to perform correlation calculations at different phases.

  FIG. 14 is an explanatory diagram of supply of replica data in this case. For convenience, the description will be made by assigning numbers “A to D” to the four second asynchronous correlation arithmetic circuits 100B. FIG. 14 shows a table in which the number of the second asynchronous correlation calculation circuit is associated with the replica data supplied to each second asynchronous correlation calculation circuit. The hatched portion in the replica data column indicates a replica data set supplied in one operation. Further, the number written at the beginning of the replica data set indicates the number of the calculation, and the alphabet written at the end indicates the number of the second asynchronous correlation calculation circuit.

  According to this table, in the first calculation, the asynchronous correlation calculation circuit A is supplied with replica data C1 to C4, the asynchronous correlation calculation circuit B is supplied with replica data C2 to C5, and the asynchronous correlation calculation circuit C Is supplied with replica data C3 to C6, and the asynchronous correlation calculation circuit D is supplied with replica data C4 to C7.

  In the second calculation, replica data C5 to C8 are supplied to the asynchronous correlation calculation circuit A, replica data C6 to C9 are supplied to the asynchronous correlation calculation circuit B, and replica data C7 to C7 are supplied to the asynchronous correlation calculation circuit C. C10 is supplied, and the asynchronous correlation calculation circuit D is supplied with replica data C8 to C11. The same applies hereinafter.

  FIG. 15 is a configuration diagram of a replica data reading register mechanism which is a register mechanism for realizing the supply of the replica data. FIGS. 15 (1) to (4) illustrate the configuration of the replica data reading register mechanism provided in each of the asynchronous correlation arithmetic circuits A to D of FIG.

  These replica data read register mechanisms are configured such that four replica data are simultaneously two-line encoded with one read token. Each replica data read register mechanism has “L = N / 4” read token register stages Sc1 to ScL.

  Each read token register stage is connected to four two-line encoders corresponding to data registers related to four consecutive replica data. However, four connection destinations are selected in order of time series of replica data so that the two-line encoders of connection destinations do not overlap between adjacent read token register stages.

  The difference between the asynchronous correlation arithmetic circuits A to D is that the replica data 2-line encoders Ec to which the read token register stages Sc1 to ScL are connected are shifted one by one. For example, paying attention to the read token register stage Sc1, the asynchronous correlation arithmetic circuit A is connected to the two-line encoders Ec1 to Ec4, whereas the asynchronous correlation arithmetic circuit B is connected to the two-line encoders Ec2 to Ec5. Has been. The asynchronous correlation calculation circuit C is connected to the two-line encoders Ec3 to Ec6, and the asynchronous correlation calculation circuit D is connected to the two-line encoders Ec4 to Ec7.

  By constructing the replica data read token register stage in this way, each asynchronous correlation operation circuit A to D shifts the read start position one by one to cause the replica data to be two-line encoded, and the tournament type full adder group It becomes possible to use for the calculation in.

4). Fourth Embodiment The fourth embodiment is an embodiment in which an asynchronous circuit that generates replica data is provided in an asynchronous correlation operation circuit.

  The C / A code modulated into the GPS satellite signal is a pseudo-random noise code with a repetition period of 1 ms using 1023 chips as one PN frame, and is a code unique to each GPS satellite. This C / A code is known as a gold series code (gold code). The gold code can be generated by combining two M sequences having equal periods and preferred pairs. In this embodiment, based on this principle, an asynchronous circuit that generates two-line encoded replica data is realized.

FIG. 16 is a diagram illustrating an example of a circuit configuration of a fourth asynchronous correlation arithmetic circuit 100D in the fourth embodiment. The large configuration of the fourth asynchronous correlation calculation circuit 100D is the same as that of the first asynchronous correlation calculation circuit 100A. The difference is that the replica data supply unit 120 includes an asynchronous replica data generation circuit 130 and a setting unit 140. The asynchronous replica data generation circuit 130 is a circuit that generates replica data having the same length 1023 (= 2 ¹⁰ −1) as the code length of the C / A code.

  FIG. 17 is a diagram illustrating an example of a circuit configuration of the asynchronous replica data generation circuit 130. The asynchronous replica data generation circuit 130 includes a first linear feedback shift register circuit 131, a second linear feedback shift register circuit 132, and a coupling unit 133.

  The first linear feedback shift register circuit 131 includes a 10-stage (= L-stage) first data register section 131A and a 9-stage (= (L-1) -stage) first exclusive OR operation circuit 131B. Is a circuit formed by linear feedback connection. Similarly, the second linear feedback shift register circuit 132 includes a second data register unit 132A having 10 stages (= L stages) and a second exclusive OR operation having 9 stages (= (L−1) stages). This is a circuit formed by linear feedback connection with the circuit 132B.

  The first data register unit 131A and the second data register unit 132A are each configured by sandwiching a 1-bit data register unit between a 2-line decoder and a 2-line encoder. The two-line encoder of the first data register unit 131A and the two-line encoder of the second data register unit 132A constitute the replica data two-line encoder 120B described in the first embodiment.

  The 1-bit data register unit can be constituted by, for example, a 1-bit data register. That is, a 1-bit data register is sandwiched between a 2-line decoder and a 2-line encoder to constitute a data register unit. In this case, the 1-bit data register unit stores 1-bit data that has been 2-line decoded by the 2-line decoder. Then, the 1-bit data output from the 1-bit data register unit is 2-line encoded by the 2-line encoder and output to the data register unit in the next stage.

  In the figure, the 1-bit data register part constituting the data register part is represented as “BRn”, the 2-wire decoder is represented as “Dn”, and the 2-wire encoder is represented as “En”. “N = 1 to 10” indicates the number of the data register section. Further, (1) is added to the end of the 1-bit data register unit, the 2-wire decoder, and the 2-wire encoder that constitute the first data register unit 131A, and the 1-bit data register unit 132A that constitutes the second data register unit 132A. The bit data register unit, 2-line decoder, and 2-line encoder are distinguished from each other by adding (2) at the end.

  In the present embodiment, the 1-bit data register unit constituting the first data register unit 131A and the second data register unit 132A is illustrated and described as being configured by a single 1-bit data register. However, instead of this, for example, a 1-bit data register unit may be configured by connecting two stages of 1-bit data registers having different drive signal phases. This is a mechanism for avoiding racing, which is a particular problem in asynchronous circuits.

  The two-line decoder constituting the data register unit performs two-line decoding on the two-line encoded 1-bit data output from the two-line encoder constituting the preceding data register unit, and the decoding result is 1 Output to the bit data register section. Also, the 2-wire encoder constituting the data register unit outputs from the 1-bit data register unit when the 2-line encoding start signal Send that instructs the start of 2-line encoding of data is input from the setting unit 140. The two-line encoding of 1-bit data is started, and the data shift operation is performed asynchronously.

Each linear feedback shift register circuit is configured such that an initial value of each data register unit and an exclusive OR operation circuit for executing an exclusive OR operation can be set by the setting unit 140. Specifically, with respect to the first linear feedback shift register circuit 131, initial values B1 (1) to B10 of the 1-bit data register units BR1 (1) to BR10 (1) constituting the first data register unit 131A, respectively. (1) is set by the setting unit 140. In addition, circuit setting values Pass1 (1) to Pass9 (1) are respectively output by the setting unit 140 to the first exclusive OR operation circuits EXOR1 (1) to EXOR9 (1), and this circuit setting value Pass1 ( 1) to Pass9 (1) set whether or not the first exclusive OR operation circuits EXOR1 (1) to EXOR9 (1) execute the exclusive OR operation.
The same applies to the second linear feedback shift register circuit 132.

  The first exclusive OR operation circuit 131B and the second exclusive OR operation circuit 132B are provided on the data line of the feedback loop that feeds back the output from the most downstream data register unit (the tenth data register unit). Each is provided so as to be interposed between adjacent data register sections.

  In the figure, the exclusive OR operation circuit is expressed as “EXORm”. “M = 1 to 9” indicates the number of the exclusive OR operation circuit. Further, the first exclusive OR operation circuit 131B is distinguished by adding (1) at the end and (2) at the end of the second exclusive OR operation circuit 132B. .

  FIG. 18 is a diagram illustrating an example of a circuit configuration of the first exclusive OR operation circuit 131B and the second exclusive OR operation circuit 132B. These exclusive OR operation circuits 131B and 132B are logic circuits that have a plurality of logic elements and perform exclusive OR operation by inputting 2-line encoded data. The input data In is input from the preceding exclusive OR operation circuit to the exclusive OR operation circuits 131B and 132B. Further, the output of the data register unit having the same number as that of the exclusive OR circuit is input as tap data Tap. Further, the circuit setting value Pass is input from the setting unit 140 to the exclusive OR operation circuit, and whether or not the exclusive OR operation between the input data In and the tap data Tap is executed based on the circuit setting value Pass. Is controlled.

  FIG. 19 is a truth table relating to the operation of the exclusive OR operation circuit. When the circuit setting value Pass is “0” (Pass = 0), the exclusive OR operation of the input data In and the tap data Tap is not executed (that is, the tap data Tap is ignored), and the input data In As output data Out (Out = In). On the other hand, when the circuit set value Pass is “1” (Pass = 1), an exclusive OR operation between the tap data Tap and the input data In is executed, and the operation result is set as output data Out (Out = In xor Tap).

  This means that an exclusive OR operation location is determined by the circuit setting value Pass. In other words, the linear feedback shift register circuit of the present embodiment is provided with a nine-stage exclusive OR operation circuit, but the exclusive OR operation of the input data In and the tap data Tap is performed on all of these. It is not executed by the exclusive OR operation circuit, but only by an exclusive OR operation circuit necessary for generating replica data.

  The combining unit 133 includes a two-line encoded output value output from the first linear feedback shift register circuit 131, and a two-line encoded output value output from the second linear feedback shift register circuit 132. Calculate the exclusive OR of. Then, the calculation result is output to the asynchronous full adder 150 as two-line encoded replica data.

  The setting unit 140 sets the initial value of the first data register 131A and the first exclusive OR operation circuit 131B according to the replica code to be generated by the asynchronous replica data generation circuit 130, and according to the replica code. The initial value of the second data register 132A and the second exclusive OR operation circuit 132B are set. The setting unit 140 outputs a two-line encoding start signal Send to the two-line encoder of the data register unit configuring each linear feedback shift register circuit.

  FIG. 20 is a diagram illustrating an example of a data configuration of the setting data 141 used by the setting unit 140 for performing the above setting. The setting data 141 includes a PRN number (replica ID) 141A, a first setting value 141B related to the first linear feedback shift register circuit 131, and a second setting related to the second linear feedback shift register circuit 132. The value 141C is determined in association with it.

  The first set value 141B includes a 10-bit initial value b (1) (= b1 (1) to b10 (1)) for the first data register unit 131A and a first exclusive OR operation circuit 131B. 9-bit circuit setting value Pass (1) (= Pass1 (1) to Pass9 (1)) is defined. The second set value 141C includes a 10-bit initial value b (2) (= b1 (2) to b10 (2)) for the second data register unit 132A and a first exclusive OR operation. A 9-bit circuit setting value Pass (2) (= Pass1 (2) to Pass9 (2)) for the circuit 131B is determined.

  The setting unit 140 converts the first setting value 141B and the second setting value 141C corresponding to the PRN number 141A output from the processing unit 300 into the first linear feedback shift register circuit 131 and the second linear feedback shift, respectively. Output to the register circuit 132.

  The series data generated by the first linear feedback shift register circuit 131 includes an initial value set in each of the first data register units 131A and a first exclusive OR operation circuit that executes an exclusive OR operation. It is uniquely determined by 131B. The same applies to the second linear feedback shift register circuit 132. For this reason, initial values and circuit setting values for the two linear feedback shift register circuits are determined in advance for each PRN number (replica ID), and an initial value corresponding to the PRN number of the GPS satellite to be captured (capture target satellite). Then, by outputting the circuit setting value to the asynchronous replica data generation circuit 130, it is possible to cause the asynchronous replica data generation circuit 130 to generate replica data related to the capture target satellite.

5. Modifications Embodiments to which the present invention can be applied are not limited to the above-described embodiments, and can be changed as appropriate without departing from the spirit of the present invention. Hereinafter, modified examples will be described.

5-1. First series data and second series data In the above embodiment, the first series data is described as a reception signal received from a GPS satellite signal, and the second series data is described as a replica code. The types of the first series data and the second series data are not limited to these.

  In a system that performs data communication using the CDMA (Code Division Multiple Access) system, transmission data is spread-modulated using a spread code on the transmitter side, and the spread-modulated data is despread on the receiver side to demodulate the transmission data. To do. In despreading, since it is necessary to know the phase of the spread code of the received signal, a correlation operation between the received signal and the pseudo spread code is required. Therefore, the present invention can also be applied to communication systems other than the satellite positioning system, and the first sequence data and the second sequence data can be appropriately selected according to the applied communication system.

5-2. Parallelization of First Asynchronous Correlation Arithmetic Circuits Similar to the third embodiment, a plurality of first asynchronous correlation arithmetic circuits 100A described in the first embodiment are arranged, and each of the first asynchronous correlation arithmetic circuits 100A is arranged. Alternatively, the phase of the replica code may be shifted so that the correlation calculation is performed in parallel.

5-3. Register Mechanism In the above embodiment, the register mechanism for reading data (received data and replica data) has been described as being configured by circularly connecting the read token register stages. It is only an example. For example, a read register mechanism may be configured by connecting read token register stages in a bus type or a star type, and any structure may be used as long as the read token circulates in the read token register stage.
The same applies to the write register mechanism.

  In the above embodiment, the data register (received data and replica data) writing register mechanism has been described as having a one-to-one correspondence between the data register and the write token register stage. However, a plurality of (for example, four) data registers may be associated with one write token register stage, and data may be written to a plurality of data registers simultaneously with one write token.

5-4. Asynchronous Data Generation Circuit The asynchronous data generation circuit of the present invention is not limited to being applied to a circuit that generates replica data, but can of course be applied to circuits that generate other gold series data. For example, if gold series data with a length of “31 = 2 ⁵ −1” is generated, a 5-stage (= L-stage) data register unit and a 4-stage (= (L-1) -stage) exclusive are used. It is only necessary to provide two linear feedback shift register circuits in which a logical sum operation circuit and linear feedback connection are provided, and to configure the asynchronous data generation circuit so as to combine these output values.

5-5. Application Example The asynchronous correlation calculation circuit of the present embodiment can be arranged in various receivers and used for correlation calculation. Also, various electronic devices such as a mobile phone, a car navigation device, a portable navigation device, a personal computer, a PDA (Personal Digital Assistance), a pedometer, and a wristwatch are assumed as electronic devices including such a receiver. It is possible.

5-6. Satellite positioning system In the above embodiment, the embodiment in which GPS is applied as the satellite positioning system has been described. However, WAAS (Wide Area Augmentation System), QZSS (Quasi Zenith Satellite System), GLONASS (GLObal NAvigation Satellite System), Of course, other satellite positioning systems such as GALILEO may be used.

  DESCRIPTION OF SYMBOLS 1 GPS receiver, 10 RF receiving circuit part, 20 Baseband processing circuit part, 100A 1st asynchronous correlation arithmetic circuit, 100B 2nd asynchronous correlation arithmetic circuit, 100D 4th asynchronous correlation arithmetic circuit, 110 Reception data supply part 110A reception data storage unit, 110B reception data 2-line encoding unit, 110C reception data selection unit, 120 replica data supply unit, 120A replica data storage unit, 120B replica data 2-line encoding unit, 120C replica data selection unit, 130 Asynchronous replica data generation circuit, 140 setting unit, 150 asynchronous full addition unit, 160 2-line decoding unit, 170 addition result storage unit, 180 addition result 2-line encoding unit, 200 replica code generation unit, 300 processing unit, 400 storage unit

Claims (8)

It has a first two-line encoding unit that two-line encodes first series data consisting of a first data series of M bits (M ≧ 1), and is used for the next calculation every time the calculation is completed. A first data supply unit for supplying first data to be
2nd data which has the 2nd 2 line coding part which carries out 2 line coding of the 2nd series data which consist of the 1-bit 2nd data series, and should be used for the next operation whenever an operation is completed A second data supply unit for supplying
An addition result storage unit for storing the addition result;
A third two-line encoding unit for two-line encoding the stored value of the addition result storage unit;
Asynchronous all output by adding the output value from the first data supply unit to the output value of the third two-line encoding unit with a code corresponding to the output value from the second data supply unit. An adder;
A 2-line decoding unit that decodes an output value of the 2-line code by the asynchronous full addition unit and outputs the decoded value to the addition result storage unit;
Asynchronous correlation operation circuit. The first data supply unit includes a first data register group that stores the first data corresponding to each of the first data;
The second data supply unit includes a second data register group that stores the second data corresponding to each of the second data,
The first two-line encoding unit is associated with each of the first data registers constituting the first data register group, and the first data stored in the first data register is two-line encoded. A first two-wire encoder
The second two-line encoding unit is associated with each of the second data registers constituting the second data register group, and the second data stored in the second data register is two-line encoded. A second two-wire encoder
The first data supply unit includes a first selection unit that selects the first two-line encoder corresponding to the first data to be subjected to the next calculation;
The second data supply unit includes a second selection unit that selects the second two-line encoder corresponding to second data to be subjected to the next calculation.
The asynchronous correlation calculation circuit according to claim 1. The first selection unit is configured to provide a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the first data, and a read token circulates through the read token register stage. And a first read register mechanism for moving the read token to the next read token register stage each time the operation of the asynchronous full adder is completed. Based on the first two-line encoder corresponding to the first data to be subjected to the next operation,
The second selection unit is configured to provide a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the second data, and a read token circulates through the read token register stage. And a second read register mechanism that moves the read token to the next read token register stage each time the operation of the asynchronous full adder is completed. Selecting the second 2-line encoder corresponding to the second data to be subjected to the next operation based on
The asynchronous correlation calculation circuit according to claim 2. The asynchronous full adder is a tournament type full adder in which 2 ^K (2 ^K −1) asynchronous full adders that add 2 ^K pieces (K is an integer of 1 or more) are arranged in a tournament type. Has a group of vessels,
The first selection unit is configured to provide a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the first data, and a read token circulates through the read token register stage. In the read register mechanism, each read token register stage is associated with the first two-line encoder corresponding to 2 ^K first data to be calculated by the asynchronous full adder. And a first read register mechanism that moves the read token to the next read token register stage each time the operation of the asynchronous full adder is completed, and is to be used for the next calculation based on the read token. Selecting the first two-line encoder corresponding to the ^K first data;
The second selection unit is configured to provide a read token register stage that communicates with each other by a four-phase handshaking protocol in association with each of the second data, and a read token circulates through the read token register stage. In the read register mechanism, each read token register stage is associated with the second 2-line encoder corresponding to 2 ^K second data which is a counterpart of the correlation operation, and the asynchronous A second read register mechanism for moving the read token to the next read token register stage each time the operation of the full adder is completed, and 2 ^K pieces to be used for the next calculation based on the read token Selecting the second 2-line encoder corresponding to the second data;
In the tournament-type full adder group, each of the asynchronous full adders in the lowermost stage has the first two-line code related to the first data of one of the two first data to be calculated. The output value of the first two-line encoder related to the other first data is used as the output value of the second encoder, and the second two-line related to the two second data serving as counterparts of the correlation calculation Add with a code according to the output value of the encoder,
The asynchronous correlation calculation circuit according to claim 2. A write register mechanism configured such that a write token circulates through a write token register stage communicating with each other by a four-phase handshaking protocol, wherein the write token is transferred to the next write token register stage. A first write register mechanism that sequentially moves and stores the first data in the first data register based on the write token;
A write register mechanism configured such that a write token circulates through a write token register stage communicating with each other by a four-phase handshaking protocol, wherein the write token is transferred to the next write token register stage. A second write register mechanism that sequentially moves and stores the second data in the second data register based on the write token;
The asynchronous correlation calculation circuit according to claim 2, comprising: The second data supply unit includes an asynchronous data generation circuit that generates the second series data having a length of 2 ^L −1 (L is an integer of 3 or more),
The asynchronous data generation circuit includes:
An L-stage first data register section configured by sandwiching a 1-bit data register section between a 2-line decoder and a 2-line encoder and an (L-1) -stage first exclusive OR operation circuit are linearly arranged. A first linear feedback shift register circuit in feedback connection;
An L-stage second data register section composed of a 1-bit data register section sandwiched between a two-line decoder and a two-line encoder and a (L-1) -stage second exclusive OR operation circuit are linearly arranged. A second linear feedback shift register circuit in feedback connection;
A coupling unit coupling an output value from the first linear feedback shift register circuit and an output value from the second linear feedback shift register circuit;
Have
The second 2-line encoder is configured by the 2-line encoder of the first data register unit and the 2-line encoder of the second data register unit,
The first linear feedback shift register circuit can set a first initial value of each of the first data register units and the first exclusive OR operation circuit for executing an exclusive OR operation. Composed of
The second linear feedback shift register circuit can set a second initial value of each of the second data register units and the second exclusive OR operation circuit for executing an exclusive OR operation. Configured
The asynchronous correlation calculation circuit according to claim 1. The second data supply unit sets the first initial value and the first exclusive OR circuit according to the second series data to be generated by the asynchronous data generation circuit, and A setting unit configured to set the second initial value and the second exclusive OR operation circuit according to second series data;
The asynchronous correlation calculation circuit according to claim 6. The first series data is series data obtained by sampling a received signal from a satellite in time series,
The second series data is series data obtained by sampling the replica code of the satellite in time series,
An asynchronous circuit that calculates a correlation value between the received signal and the replica code.
The asynchronous correlation calculation circuit according to claim 1.

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