CN114489567A - Parallel pseudo-random code generator and method - Google Patents

Parallel pseudo-random code generator and method Download PDF

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CN114489567A
CN114489567A CN202111593821.7A CN202111593821A CN114489567A CN 114489567 A CN114489567 A CN 114489567A CN 202111593821 A CN202111593821 A CN 202111593821A CN 114489567 A CN114489567 A CN 114489567A
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registers
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鲁郁
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Nuo Ling Technology Ltd Co ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/33—Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS

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Abstract

The invention provides a parallel pseudorandom code generator and a method, wherein the generator comprises a G1 register group, a G1 updating parallel circuit, a G2 register group, a G2 updating parallel circuit and a logic operation unit. The invention increases the number of the linear shift registers, simultaneously increases the updating logic from conventional single-path output to parallel multi-path output, and uses a plurality of pseudo code chip signals obtained by the calculation of the parallel pseudo code calculating unit to update the multi-path linear shift register unit to realize parallel updating, thereby realizing the parallel generation of a plurality of feedback bits in a single clock period and realizing the parallel output of N pseudo code chips. Compared with the conventional pseudo code generating circuit, the invention can complete all the chip outputs in one pseudo code period at 1/N of the original clock frequency. The scheme of the invention can obviously reduce power consumption and reduce the time sequence requirement on clock frequency in design on the basis of not increasing cost and not reducing performance.

Description

Parallel pseudo-random code generator and method
Technical Field
The invention belongs to the field of satellite positioning, and particularly relates to a parallel pseudorandom code generator and a method.
Background
The pseudo-random code generator inside the satellite positioning receiver is generally realized by a generating circuit of a linear feedback register, and the structure of the pseudo-random code generator serially generates a full-period pseudo-random code by a working clock driving feedback register circuit and a necessary logic operation unit, so that the baseband processing of acquisition, tracking and the like of a positioning signal transmitted by a satellite is realized. In a conventional pseudo code generator unit, only one pseudo code chip signal component is generated each time, and then the signal component is fed back to a first register unit of a linear shift register through a single-path feedback circuit, so that serial updating is realized, and the efficiency is low. Due to the need of technical development, in the implementation of a baseband circuit of a satellite positioning receiver, a faster operation speed, a shorter processing time, and a lower circuit power consumption are needed, but the prior art cannot meet the requirement.
Disclosure of Invention
In order to solve the above problems, the present invention discloses a pseudo random code generator circuit unit capable of providing parallel pseudo code signals and a method for generating the parallel pseudo code signals. The invention adopts a parallel pseudo code computing unit and a corresponding multivariate linear feedback register updating unit to combine with control logic, and can realize the output of a plurality of pseudo-random code chip signals in a driving clock.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a parallel pseudo-random code generator comprises a G1 register group, a G1 updating parallel circuit, a G2 register group, a G2 updating parallel circuit and a logic operation unit, wherein the G1 register group and the G2 register group respectively comprise 2N linear feedback registers; the 1 st to N registers in the G1 register group are electrically connected with the G1 updating parallel circuit, and the respective register values are input into the G1 updating parallel circuit for operation; the 1 st to N th registers of G1 are connected to the N +1 st to 2N th registers of G1 one by one, and the values of the respective registers are updated to the N +1 st to 2N th registers; the 1 st to N registers of G1 are connected to the logic operation unit to output the G1 sequence to the logic operation unit; g1 updates the parallel circuit to generate N linear feedback bits to update the value of 1 st to N registers; the 1 st to N registers in the G2 register group are electrically connected with the G2 updating parallel circuit, and the respective register values are input into the G2 updating parallel circuit for operation; the 1 st to N th registers of G2 are connected to the N +1 st to 2N th registers of G2 one by one, and the values of the respective registers are updated to the N +1 st to 2N th registers; the 1 st to N registers of G2 are connected to the logic operation unit to output the G2 sequence to the logic operation unit; g2 updates the parallel circuit to generate N linear feedback bits to update the value of 1 st to N registers; and the logic operation unit is used for performing modulo two addition operation on the N bits in the G1 sequence and the N bits in the G2 sequence to obtain N output bits and outputting the N output bits.
Further, when N is 10, G1 updates the logic in parallel as follows:
Figure BDA0003429989940000021
Figure BDA0003429989940000022
Figure BDA0003429989940000023
Figure BDA0003429989940000024
Figure BDA0003429989940000025
Figure BDA0003429989940000026
Figure BDA0003429989940000027
Figure BDA0003429989940000028
Figure BDA0003429989940000029
Figure BDA00034299899400000210
the G2 parallel update logic is as follows:
Figure BDA00034299899400000211
Figure BDA00034299899400000212
Figure BDA00034299899400000213
Figure BDA00034299899400000214
Figure BDA00034299899400000215
Figure BDA00034299899400000216
Figure BDA00034299899400000217
Figure BDA00034299899400000218
Figure BDA00034299899400000219
Figure BDA00034299899400000220
the logic operation unit outputs the C/A code of the GPS.
Further, when N is 11, G1 updates the logic in parallel as follows:
Figure BDA00034299899400000221
Figure BDA00034299899400000222
Figure BDA00034299899400000223
Figure BDA00034299899400000224
Figure BDA00034299899400000225
Figure BDA00034299899400000226
Figure BDA00034299899400000227
Figure BDA00034299899400000228
Figure BDA00034299899400000229
Figure BDA00034299899400000230
Figure BDA00034299899400000231
the G2 parallel update logic is as follows:
Figure BDA00034299899400000232
Figure BDA00034299899400000233
Figure BDA00034299899400000234
Figure BDA00034299899400000235
Figure BDA00034299899400000236
Figure BDA00034299899400000237
Figure BDA0003429989940000031
Figure BDA0003429989940000032
Figure BDA0003429989940000033
Figure BDA0003429989940000034
Figure BDA0003429989940000035
and the logic operation unit outputs a pseudo-random code of the Beidou.
Further, when N is 9, a pseudo random code of Glonass is generated.
Further, the logic operation unit is an exclusive or operation unit.
The invention also provides a parallel pseudo-random code generating method, which comprises the following steps:
setting a G1 linear feedback register group and a G2 linear feedback register group to initial values based on a reset signal;
step two, each clock signal generates N linear feedback values which are respectively sent to G1 and G2 register groups; the two register groups simultaneously perform the following operations: updating the (N + 1) -2N register values by using the (1) -N register values, and then respectively updating the (1) -N linear feedback register values of the group by using N linear feedback bits generated by two groups of parallel updating circuits;
step three, when each clock signal arrives, performing modulo two addition on the G1 sequence and the G2 sequence respectively output by the 1 st to N registers of the two groups of register groups to obtain N output bits and then outputting the N output bits;
and step four, finishing the output of all PRN chips after all CNT/N clocks, wherein CNT is the cycle number of the pseudo-random code.
Further, the initial value in the first step is set by the following method: 2N registers of the G1 register bank are set to be 0, and 2N registers of the G2 register bank are set to be initial phases;
further, in the first step, the initial phase is calculated by the PRN number.
The invention has the beneficial effects that:
1. the invention increases the number of the linear shift registers, simultaneously increases the updating logic from conventional single-path output to parallel multi-path output, and uses a plurality of pseudo code chip signals obtained by the calculation of the parallel pseudo code calculating unit to update the multi-path linear shift register unit to realize parallel updating, thereby realizing the parallel generation of a plurality of feedback bits in a single clock period and realizing the parallel output of N pseudo code chips.
2. Compared with the conventional pseudo code generating circuit, the pseudo code generating circuit can reduce N times of the original clock frequency, namely 1/N of the original clock frequency can complete all chip outputs in one pseudo code period. If the time length is the same, the driving clock of the invention only needs 1/N of the original clock.
3. The scheme of the invention can obviously reduce power consumption and reduce the time sequence requirement on clock frequency in design on the basis of not increasing cost and not reducing performance.
4. The scheme of the invention is suitable for all satellite positioning systems and terminal equipment thereof which utilize a linear shift register structure to generate pseudo-random codes, and the specific implementation forms include but are not limited to GNSS positioning terminals, chips and software receivers. Meanwhile, the scheme is easy to expand into a multi-frequency and multi-mode satellite positioning system, and requirements for the design difficulty and the power consumption of the multi-frequency and multi-mode satellite positioning system can be lowered.
Drawings
Fig. 1 is a schematic structural diagram of a parallel pseudo-random code generator for generating a gps c/a code according to an embodiment of the present invention.
Fig. 2 is a logic diagram of a G1 parallel refresh circuit according to a first embodiment of the present invention.
Fig. 3 is a logic diagram of a G2 parallel refresh circuit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a parallel pseudorandom code generator for generating a pseudorandom code of the big dipper in the second embodiment of the present invention.
Fig. 5 is a logic diagram of a G1 parallel refresh circuit according to a second embodiment of the present invention.
Fig. 6 is a logic diagram of a G2 parallel refresh circuit according to a second embodiment of the present invention.
Detailed Description
The technical solutions provided by the present invention will be described in detail below with reference to specific examples, and it should be understood that the following specific embodiments are only illustrative of the present invention and are not intended to limit the scope of the present invention.
The first embodiment is as follows:
this example is an example of a method for generating C/a codes for GPS using the present invention. As shown in fig. 1, the parallel pseudo-random code generator provided by the present invention includes a G1 register set, a G1 updated parallel circuit, a G2 register set, a G2 updated parallel circuit, and a modulo two addition (exclusive or) logic operation unit, wherein the G1 register set and the G2 register set each include 2N linear feedback registers, and for the C/a code of GPS, N is 10, that is, the G1 register set and the G2 register set each include 20 registers.
In FIG. 1, the G1 register set includes
Figure BDA0003429989940000041
Wherein
Figure BDA0003429989940000042
The registers are electrically connected to the G1 refresh parallel circuit, and the respective register values are inputted to the G1 refresh parallel circuit to be operated, and at the same time,
Figure BDA0003429989940000043
registers are connected one by one to
Figure BDA0003429989940000044
Register to be
Figure BDA0003429989940000045
Register value is updated to
Figure BDA0003429989940000046
Registers, i.e.
Figure BDA0003429989940000047
Register value is updated to
Figure BDA0003429989940000048
A register is provided to store a plurality of data,
Figure BDA0003429989940000049
register value is updated to
Figure BDA00034299899400000410
Register …… and so on. In addition to this, the present invention is,
Figure BDA00034299899400000411
the values in the registers are output as a sequence of G1 to a modulo two addition (exclusive or) logic unit. G1 update parallel circuit generates 10 linear feedback bit updates in parallel
Figure BDA00034299899400000412
The value in the register. The G2 register set includes
Figure BDA00034299899400000413
Wherein
Figure BDA00034299899400000414
The registers are electrically connected to the G2 refresh parallel circuit, and the respective register values are inputted to the G2 refresh parallel circuit to be operated, and at the same time,
Figure BDA00034299899400000415
registers are connected one by one to
Figure BDA00034299899400000416
Register to be
Figure BDA00034299899400000417
Register value is updated to
Figure BDA00034299899400000418
A register. In addition to this, the present invention is,
Figure BDA00034299899400000419
the values in the registers are output as a sequence of G2 to a modulo two addition (exclusive or) logic unit. G1 update parallel circuit 10 linear feedback bit updates
Figure BDA00034299899400000420
The value in the register. The modulo two addition (exclusive OR) logic operation unit performs modulo two addition operation on 10 bits in the G1 sequence and 10 bits in the G2 sequence to obtain 10 output bits, and then the 10 output bits are outputAnd (6) discharging.
The logic of the G1 parallel update circuit is shown in FIG. 2, which comprises 10 modulo two addition (XOR) logic units, wherein the first modulo two addition (XOR) logic unit is used to calculate the register
Figure BDA00034299899400000423
Value of (2) and updated value
Figure BDA00034299899400000422
Get the updated value
Figure BDA00034299899400000421
The second modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000426
Value of (2) and updated value
Figure BDA00034299899400000425
Get the updated value
Figure BDA00034299899400000424
The third modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA0003429989940000051
Value of (2) and updated value
Figure BDA00034299899400000524
Get the updated value
Figure BDA00034299899400000522
The fourth modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000526
Value of (2) and updated value
Figure BDA00034299899400000525
Get the updated value
Figure BDA00034299899400000523
The fifth modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000527
Value of (2) and updated value
Figure BDA00034299899400000528
Get the updated value
Figure BDA00034299899400000529
The sixth modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000531
Value of (2) and updated value
Figure BDA00034299899400000532
Get the updated value
Figure BDA00034299899400000530
The seventh modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000534
Value of (2) and updated value
Figure BDA00034299899400000533
Get the updated value
Figure BDA00034299899400000535
The eighth modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000538
Value and register of
Figure BDA00034299899400000537
To obtain an updated value
Figure BDA00034299899400000536
Ninth mould two plusXOR logic operation unit for calculating register
Figure BDA00034299899400000539
Value and register of
Figure BDA00034299899400000540
To obtain an updated value
Figure BDA00034299899400000541
The tenth modulo two addition (XOR) logic operation unit is used for calculating the register
Figure BDA00034299899400000543
Value and register of
Figure BDA00034299899400000544
To obtain an updated value
Figure BDA00034299899400000542
Figure BDA00034299899400000542
10 linear feedback bits generated in parallel
Figure BDA00034299899400000545
Updating
Figure BDA00034299899400000546
The value in the register. Formulating the G1 parallel update logic as follows:
Figure BDA0003429989940000052
Figure BDA0003429989940000053
Figure BDA0003429989940000054
Figure BDA0003429989940000055
Figure BDA0003429989940000056
Figure BDA0003429989940000057
Figure BDA0003429989940000058
Figure BDA0003429989940000059
Figure BDA00034299899400000510
Figure BDA00034299899400000511
the logic of the G1 parallel update circuit is shown in FIG. 3, and the formula for the G2 parallel update logic is as follows:
Figure BDA00034299899400000512
Figure BDA00034299899400000513
Figure BDA00034299899400000514
Figure BDA00034299899400000515
Figure BDA00034299899400000516
Figure BDA00034299899400000517
Figure BDA00034299899400000518
Figure BDA00034299899400000519
Figure BDA00034299899400000520
Figure BDA00034299899400000521
the parallel pseudo-random code generator in this example works as follows:
1) the reset signal sets the initial values of the G1 and G2 linear feedback register groups, each group of linear feedback register groups is 20(2N), wherein 20 registers of G1 are set to 0, and 20 registers of G2 are set to initial phases, and specific initialization values are calculated by software according to a PRN number (pseudo random noise code).
2) When the driving clock comes, each clock signal will generate N linear feedback values (bit values) which are respectively sent to the G1 and G2 register groups. The two register groups simultaneously perform the following operations:
control circuit for a motor vehicle
Figure BDA0003429989940000061
Register value update of
Figure BDA0003429989940000062
Then updated with 10 linear feedback bits generated by the G1 parallel update circuit
Figure BDA0003429989940000063
Linear feedback register values. The way in which the G1 updates the 10 linear feedback values generated by the circuit in parallel has been calculated is illustrated in fig. 2.
At the same time, for control circuits
Figure BDA0003429989940000064
Register value update of
Figure BDA0003429989940000065
Then updated with 10 linear feedback bits generated by the G1 parallel update circuit
Figure BDA0003429989940000066
Linear feedback register values. The way in which the G2 updates the 10 linear feedback values generated by the circuit in parallel has been calculated is illustrated in fig. 3.
3) Performing modulo-two addition on 10 bits of G1 and G2 at the arrival time of each clock signal to obtain 10 output bits, and then outputting the 10 output bits;
4) the output of all PRN chips is completed after all CNT/N clocks. Here, CNT is the cycle number of the pseudo random code, and for GPS, CNT is 1023 and N is 10.
It can be seen from the above process that the conventional pseudo code generating circuit needs CNT clocks to obtain all pseudo random chip outputs, and the present invention can complete all chip outputs only by 1/N of the original clock number. If the time lengths are the same, the driving clock of the invention only needs 1/N times of the original clock, and the design difficulty of power consumption index, time sequence synthesis and the like can be obviously reduced in the design fields of high-speed chips and the like.
Example two:
this example is another example of the method of the present invention for generating the pseudo random code of big dipper. As shown in fig. 4, the parallel pseudo-random code generator provided in this embodiment includes a G1 register bank, a G1 updated parallel circuit, a G2 register bank, a G2 updated parallel circuit, and a modulo two addition (exclusive or) logic operation unit, where the G1 register bank and the G2 register bank each include 2N linear feedback registers, and for the pseudo-random code of beidou, N is 11, that is, the G1 register bank and the G2 register bank each include 22 registers.
In FIG. 4, the G1 register set contains
Figure BDA0003429989940000067
Wherein
Figure BDA0003429989940000068
The registers are electrically connected to the G1 refresh parallel circuit, and the respective register values are inputted to the G1 refresh parallel circuit to be operated, and at the same time,
Figure BDA0003429989940000069
registers are connected one by one to
Figure BDA00034299899400000610
Register to be
Figure BDA00034299899400000611
Register value is updated to
Figure BDA00034299899400000612
Registers, i.e.
Figure BDA00034299899400000613
Register value is updated to
Figure BDA00034299899400000614
A register is provided to store a plurality of data,
Figure BDA00034299899400000615
register value is updated to
Figure BDA00034299899400000616
DepositingAnd so on for the device … …. In addition, in the case of the present invention,
Figure BDA00034299899400000617
the values in the registers are output as a sequence of G1 to a modulo two addition (exclusive or) logic unit. G1 update parallel circuit generates 11 linear feedback bit updates in parallel
Figure BDA00034299899400000618
The value in the register. The G2 register set includes
Figure BDA00034299899400000619
Wherein
Figure BDA00034299899400000620
The registers are electrically connected to the G2 refresh parallel circuit, and the respective register values are input to the G2 refresh parallel circuit to be operated, and at the same time,
Figure BDA00034299899400000621
registers are connected one by one to
Figure BDA00034299899400000622
Register to be
Figure BDA00034299899400000623
Register value is updated to
Figure BDA00034299899400000624
A register. In addition to this, the present invention is,
Figure BDA00034299899400000625
the values in the registers are output as a sequence of G2 to a modulo two addition (exclusive or) logic unit. G1 update parallel circuit 11 linear feedback bit updates
Figure BDA00034299899400000626
The value in the register. The modulo two addition (exclusive OR) logic operation unit performs modulo two addition operation on 11 bits in the G1 sequence and 11 bits in the G2 sequence to obtain 11 output bitsAnd then outputting.
The logic of the G1 parallel update circuit is shown in fig. 5, which includes 11 modulo two addition (exclusive or) logic operation units, and the G1 parallel update logic for beidou expressed by a formula is as follows:
Figure BDA0003429989940000071
Figure BDA0003429989940000072
Figure BDA0003429989940000073
Figure BDA0003429989940000074
Figure BDA0003429989940000075
Figure BDA0003429989940000076
Figure BDA0003429989940000077
Figure BDA0003429989940000078
Figure BDA0003429989940000079
Figure BDA00034299899400000710
Figure BDA00034299899400000711
the logic of the G2 parallel update circuit is shown in FIG. 6, and the formula is used to express the G2 parallel update logic as follows:
Figure BDA00034299899400000712
Figure BDA00034299899400000713
Figure BDA00034299899400000714
Figure BDA00034299899400000715
Figure BDA00034299899400000716
Figure BDA00034299899400000717
Figure BDA00034299899400000718
Figure BDA00034299899400000719
Figure BDA00034299899400000720
Figure BDA00034299899400000721
Figure BDA00034299899400000722
the parallel pseudo-random code generator in this example works as follows:
1) the reset signal correspondingly sets the initial values of the G1 and G2 linear feedback register groups, each group of linear feedback register groups is 22(2N), wherein 22 registers of G1 are set to be 0, 22 registers of G2 are set to be initial phases, and specific initialization values are calculated by software according to PRN numbers.
2) When the driving clock comes, each clock signal will generate N linear feedback values (bit values) which are respectively sent to the G1 and G2 register groups. The two register groups simultaneously perform the following operations:
for control circuits
Figure BDA00034299899400000723
Register value update of
Figure BDA00034299899400000724
Then updated with 11 linear feedback bits generated by the G1 parallel update circuit
Figure BDA00034299899400000725
Linear feedback register values. The way in which the G1 parallel updates the 11 linear feedback values generated by the circuit has been calculated is illustrated in fig. 5.
At the same time, for control circuits
Figure BDA00034299899400000726
Register value update of
Figure BDA00034299899400000727
Of a register, howeverThen using 11 linear feedback bits generated by G1 parallel update circuit to update
Figure BDA00034299899400000728
Linear feedback register values. The way in which the G2 parallel updates the 11 linear feedback values generated by the circuit has been calculated is illustrated in fig. 6.
3) Performing modulo two addition on 11 bits of G1 and G2 at each arrival time of the clock signal to obtain 11 output bits, and outputting the output bits;
4) the output of all PRN chips is completed after all CNT/N clocks. Here, CNT is the number of cycles of the pseudo random code, and for big dipper CNT is 2046 and N is 11.
The invention can generate N pseudo code chip signals in a working clock in a multi-path parallel mode by performing multi-element expansion on a single pseudo code computing unit of the traditional pseudo code generator, thereby improving the parallel output capability of the pseudo code chips, completing the generation of the full-period pseudo code chips on the working frequency of 1/N of the original working clock frequency, reducing the driving clock of the baseband processing circuit to the original 1/N, and having great significance for the design of a low-power consumption system. Where N is the parallelism and is related to the amount of increase in the linear shift register. Except that in the first embodiment, N is 10 for the C/a code of GPS, and in the second embodiment, N is 11 for the pseudo random code of beidou; for the Glonass pseudorandom code, N is 9.
It should be noted that the above-mentioned contents only illustrate the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and it is obvious to those skilled in the art that several modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations fall within the protection scope of the claims of the present invention.

Claims (8)

1. A parallel pseudorandom code generator characterized by: the circuit comprises a G1 register group, a G1 updating parallel circuit, a G2 register group, a G2 updating parallel circuit and a logic operation unit, wherein the G1 register group and the G2 register group respectively comprise 2N linear feedback registers;
the 1 st to N registers in the G1 register group are electrically connected with the G1 updating parallel circuit, and the respective register values are input into the G1 updating parallel circuit for operation; the 1 st to N th registers of G1 are connected to the N +1 st to 2N th registers of G1 one by one, and the values of the respective registers are updated to the N +1 st to 2N th registers; the 1 st to N th registers of G1 are connected to the logical operation unit to output the G1 sequence to the logical operation unit; g1 updates the parallel circuit to generate N linear feedback bits to update the value of 1 st to N registers; the 1 st to N registers in the G2 register group are electrically connected with the G2 updating parallel circuit, and the respective register values are input into the G2 updating parallel circuit for operation; the 1 st to N th registers of G2 are connected to the N +1 st to 2N th registers of G2 one by one, and the values of the respective registers are updated to the N +1 st to 2N th registers; the 1 st to N registers of G2 are connected to the logic operation unit to output the G2 sequence to the logic operation unit; g2 updates the parallel circuit to generate N linear feedback bits to update the value of 1 st to N registers; and the logic operation unit is used for performing modulo two addition operation on the N bits in the G1 sequence and the N bits in the G2 sequence to obtain N output bits and outputting the N output bits.
2. The parallel pseudorandom code generator of claim 1, wherein: when N is 10, G1 updates the logic in parallel as follows:
Figure FDA0003429989930000011
Figure FDA0003429989930000012
Figure FDA0003429989930000013
Figure FDA0003429989930000014
Figure FDA0003429989930000015
Figure FDA0003429989930000016
Figure FDA0003429989930000017
Figure FDA0003429989930000018
Figure FDA0003429989930000019
Figure FDA00034299899300000110
the G2 parallel update logic is as follows:
Figure FDA00034299899300000111
Figure FDA00034299899300000112
Figure FDA00034299899300000113
Figure FDA00034299899300000114
Figure FDA00034299899300000115
Figure FDA00034299899300000116
Figure FDA00034299899300000117
Figure FDA00034299899300000118
Figure FDA00034299899300000119
Figure FDA00034299899300000120
the logic operation unit outputs the C/A code of the GPS.
3. The parallel pseudorandom code generator of claim 1, wherein: when N is 11, G1 updates the logic in parallel as follows:
Figure FDA0003429989930000021
Figure FDA0003429989930000022
Figure FDA0003429989930000023
Figure FDA0003429989930000024
Figure FDA0003429989930000025
Figure FDA0003429989930000026
Figure FDA0003429989930000027
Figure FDA0003429989930000028
Figure FDA0003429989930000029
Figure FDA00034299899300000210
Figure FDA00034299899300000211
the G2 parallel update logic is as follows:
Figure FDA00034299899300000212
Figure FDA00034299899300000213
Figure FDA00034299899300000214
Figure FDA00034299899300000215
Figure FDA00034299899300000216
Figure FDA00034299899300000217
Figure FDA00034299899300000218
Figure FDA00034299899300000219
Figure FDA00034299899300000220
Figure FDA00034299899300000221
Figure FDA00034299899300000222
and the logic operation unit outputs a pseudo-random code of the Beidou.
4. The parallel pseudorandom code generator of claim 1, wherein: when N is 9, a pseudo random code of Glonass is generated.
5. The parallel pseudorandom code generator of claim 1, wherein: the logic operation unit is an exclusive-or operation unit.
6. A method for generating parallel pseudorandom codes, comprising the steps of:
setting a G1 linear feedback register group and a G2 linear feedback register group to initial values based on a reset signal;
step two, generating N linear feedback values by each clock signal and respectively sending the linear feedback values into G1 and G2 register groups; the two register groups simultaneously perform the following operations: updating the (N + 1) -2N register values by using the (1) -N register values, and then respectively updating the (1) -N linear feedback register values of the group by using N linear feedback bits generated by two groups of parallel updating circuits;
step three, when each clock signal arrives, performing modulo two addition on the G1 sequence and the G2 sequence respectively output by the 1 st to N registers of the two groups of register groups to obtain N output bits and then outputting the N output bits;
and step four, finishing the output of all PRN chips after all CNT/N clocks, wherein CNT is the cycle number of the pseudo-random code.
7. The method of claim 6, wherein the initial value in step one is set by: the 2N registers of the G1 register set are set to 0, and the 2N registers of the G2 register set are set to initial phase.
8. The method of claim 7, wherein the initial phase is computed from the PRN number in step one.
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