CN112698364A - Compatible modern GNSS signal ranging code generation method - Google Patents
Compatible modern GNSS signal ranging code generation method Download PDFInfo
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- CN112698364A CN112698364A CN202011436153.2A CN202011436153A CN112698364A CN 112698364 A CN112698364 A CN 112698364A CN 202011436153 A CN202011436153 A CN 202011436153A CN 112698364 A CN112698364 A CN 112698364A
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- 238000012545 processing Methods 0.000 claims abstract description 4
- 238000013461 design Methods 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 5
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- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/37—Hardware or software details of the signal processing chain
Abstract
The invention discloses a compatible modern GNSS signal ranging code generation method, which comprises the following steps: storing the L sequence, the phase difference, the truncation point and the ranging code to a CPU (central processing unit) end; writing initialization configuration is carried out on Ram according to the storage content of the CPU end; performing read operation on Ram; if the Ram is stored as an L sequence, inputting the L sequence into a digital circuit end, and generating a pilot branch ranging code and a data branch ranging code through a time division multiplexing calculation unit; and if the stored Ram is the ranging code, outputting the pilot branch ranging code and the data branch ranging code. The invention transplants the generation of Weil code to the digital circuit end and generates the required pilot frequency branch distance measuring code and data branch distance measuring code in a time division multiplexing mode, thereby reducing the calculation amount of the CPU end and saving the storage resource.
Description
Technical Field
The invention relates to the field of satellite navigation positioning, in particular to a compatible modern GNSS signal ranging code generation method.
Background
The Beidou third navigation system B1C signal, the GPS navigation system modernization L1C signal and the Galileo navigation system E1 signal are new system modernization signals, and the distance measurement code generation method is different from the traditional Gold code generation method, wherein the B1C signal and the L1C signal are generated in a Weil code truncation mode, and the E1 signal is Ram code. The pilot branch and data branch ranging code period for the B1C and L1C signals is 10ms, the chip length is 10230 chips, the pilot branch and data branch ranging code period for E1 is 4ms, and the chip length is 4092 chips. The code loop and the carrier loop of the signals B1C, L1C and E1 track a pilot branch, and a data branch is used for demodulating messages. The method comprises the steps that a distance measuring code of a data branch and a distance measuring code of a pilot branch need to be generated in one channel at the same time, and the conventional method is that the distance measuring code of the pilot branch and the distance measuring code of the data branch are stored in Ram at a digital circuit end and then output in an inquiry mode; by configuring different ranging codes, one channel can be compatible with ranging code output of three signals, and the conventional method for generating the ranging codes is shown in fig. 1. In the method, each channel occupies 20460bits of storage resources, and if the number of tracking channels is 64, the storage resources at the end of a digital circuit with 64 multiplied by 20460bits are occupied.
Another disadvantage is that since the B1C and L1C signal ranging codes are generated by way of Weil code truncation, the Weil codes are generated as L sequences, and if the L sequences are stored at the CPU, the Weil codes of the corresponding satellites need to be calculated each time before the channel is opened, which may greatly occupy CPU computing resources; if the CPU end stores each satellite ranging code, a large amount of storage resources of the CPU are occupied.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a compatible modern GNSS signal ranging code generation method.
The purpose of the invention is realized by the following technical scheme:
a compatible modern GNSS signal ranging code generation method comprises the following steps:
storing the L sequence, the phase difference, the truncation point and the ranging code to a CPU (central processing unit) end;
writing initialization configuration is carried out on Ram according to the storage content of the CPU end;
performing read operation on Ram;
if the Ram is stored as an L sequence, inputting the L sequence into a digital circuit end, and generating a pilot branch ranging code and a data branch ranging code through a time division multiplexing calculation unit;
if the stored Ram is the ranging code, outputting the pilot branch ranging code and the data branch ranging code;
the design of the time division multiplexing calculation unit comprises the following steps:
determining the time period between every two code clocks of the time division multiplexing calculation unit according to the code rate of the ranging code corresponding to the L sequence and the working rate of the system clock;
at the time of counting the value 0, adding the phase difference of the pilot frequency branch as a read address on the basis of the chip counting value; outputting a corresponding L sequence value Lp _ w from the Ram;
counting the value at 1 moment, adding the phase difference of the pilot branch and an intercept point on the basis of a chip counting value, then taking a module of the byte length of the L sequence, and taking the module value as a read address; outputting a corresponding L sequence value Lp _ wp from the Ram;
at the moment of counting the value of 2, exclusive OR is carried out on Lp _ w and Lp _ wp to obtain a pilot frequency branch ranging code; meanwhile, on the basis of the chip count value, adding a data branch phase difference as a read address, and outputting a corresponding L sequence value Ld _ w from Ram;
at the moment of counting value 3, adding the phase difference of the data branches and the interception point on the basis of a chip counting value, then taking a module of the byte length of the L sequence, taking the module value as a read address, and outputting a corresponding L sequence value Ld _ wp from Ram;
and when the count value is 4, exclusive-OR is carried out on Ld _ w and Ld _ wp to obtain a data branch ranging code, and the next time period is entered.
Further, the L sequence includes 10243bitsL sequence and 10223bitsL sequence.
Further, the 10243bitsL sequence is used for generating a ranging code of the B1C signal; the 10223bitsL sequence is used to generate the ranging code for the L1C signal.
Further, the ranging code is 8184bits ranging code for generating the ranging code of the E1 signal.
Further, the Ram is 10243bits in total, and the Ram comprises a first part and a second part.
Further, the first part has a storage length of 4096bits, and the storage content is a pilot branch ranging code.
Further, the storage length of the second part is 6147bits, and the storage content is the data branch ranging code.
The invention has the beneficial effects that: the invention transplants the generation of Weil code to the digital circuit end and generates the required pilot frequency branch distance measuring code and data branch distance measuring code in a time division multiplexing mode, thereby reducing the calculation amount of the CPU end and saving the storage resource.
Drawings
Fig. 1 is a block diagram of a conventional method for generating ranging codes.
Fig. 2 is a schematic diagram of a ranging code generation method according to the present invention.
FIG. 3 is a timing diagram illustrating the generation of B1C signal ranging codes according to the present invention.
FIG. 4 is a diagram illustrating E1 signal ranging code generation according to the present invention.
Detailed Description
In order to more clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings.
Embodiment 1, as shown in fig. 2, is a process for generating a B1C signal ranging code, and includes the following steps:
storing an L sequence, a phase difference and an interception point required by generating a B1C signal ranging code to a CPU (central processing unit);
writing initialization configuration is carried out on Ram according to the storage content of the CPU end;
performing read operation on Ram;
inputting the L sequence into a time division multiplexing calculation unit to generate a pilot branch ranging code and a data branch ranging code.
The capacity of the Ram is 10243bits, and the length of the L sequence of the B1C signal ranging code is 10243 bits.
The Ram is divided into two parts, the first part is 4096bits, the second part is 6147bits, the storage content of the first part is pilot branch ranging codes, and the storage content of the second part is data branch ranging codes.
After the L sequence is input into the time division multiplexing calculation unit, the process of generating the pilot branch ranging code and the data branch ranging code comprises the following steps:
the code rate of the B1C signal is 1.023MHz, the system clock works at 62MHz, therefore, 60 clocks exist between two code reading intervals and are represented by counters 0-59, and the timing diagram is shown in FIG. 3;
1) at the time of counting value 0, adding a pilot frequency branch phase difference (w) as a read address on the basis of a chip counting value, and outputting a corresponding L sequence value Lp _ w at the time of counting value 1 Ram;
2) at the moment of counting value 1, adding the phase difference of the pilot branch and an intercept point (w + p) on the basis of a chip counting value, then performing modulus operation on 10243, taking the modulus value as a read address, and outputting a corresponding L sequence value Lp _ wp at the moment of counting value 2 Ram;
3) and when the count value is 2, exclusive OR is carried out on Lp _ w and Lp _ wp, and the pilot frequency branch ranging code is obtained. Meanwhile, at the moment, on the basis of the chip counting value, adding a data branch phase difference (w) as a reading address, and outputting a corresponding L sequence value Ld _ w at the counting value 3 moment Ram;
4) at the moment of counting value 3, adding (w + p) the phase difference of the data branches and the intercept point on the basis of the chip counting value, then performing modulus on 10243, taking the modulus as a read address, and outputting a corresponding L-sequence value Ld _ wp at the moment of counting value 4 Ram;
5) and at the moment of counting the value 4, exclusive OR is carried out on Ld _ w and Ld _ wp, and the data branch ranging code is obtained.
The L1C signal ranging code generation mode is the same as the B1C signal ranging code, the length of an L sequence required by generating the L1C signal ranging code is 10223bits, the Ram storage size meets the requirement, and the program multiplexing mode is the same.
Embodiment 2, as shown in fig. 4, a method for generating E1 signal ranging codes includes the following steps:
storing the E1 signal ranging code to the CPU end;
writing initialization configuration is carried out on Ram according to the storage content of the CPU end;
performing read operation on Ram;
and outputting the pilot branch ranging code and the data branch ranging code.
The method for generating the pilot branch ranging code and the data branch ranging code comprises the following steps:
1) at the time of counting value 0, taking the chip counting value as a reading address, and outputting an E1 signal pilot frequency branch ranging code at the time of counting value 1 Ram;
2) at the time of count value 1, the chip count value is shifted up by 4096 as a read address, and at the time of count value 2, Ram, the data branch ranging code is output.
The code rate of the E1 signal is 1.023MHz, the code length is 4092 chips, the period is 4ms, the E1 signal ranging code is defined through an ICD interface file, and the E1 signal ranging code can only be realized in a table look-up mode.
The invention only needs 10243bits at each channel digital circuit end. If the number of tracking channels is 64, the storage resources of 64 × 10243bits are occupied. Meanwhile, the CPU only needs to store the L sequence, the phase difference (w), the truncation point (p) and the E1 signal ranging code; for B1C, L1C, then there is no need to store the ranging code for each satellite; the conventional method is that Weil code generation is realized at a CPU end, and the Weil code generation is transplanted to a digital circuit end to realize, so that the calculated amount of the CPU end and the storage resource of the CPU end are reduced; the conventional method occupies two Ram with 10230bits, and the invention only needs to store 10243bit L sequence at most in a time division multiplexing mode, thereby saving nearly half of storage resources at the digital circuit end.
The invention transplants the generation of Weil code to the digital circuit end and generates the required pilot frequency branch distance measuring code and data branch distance measuring code in a time division multiplexing mode, thereby reducing the calculation amount of the CPU end and saving the storage resource.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A compatible modern GNSS signal ranging code generation method is characterized by comprising the following steps:
storing the L sequence, the phase difference, the truncation point and the ranging code to a CPU (central processing unit) end;
writing initialization configuration is carried out on Ram according to the storage content of the CPU end;
performing read operation on Ram;
if the Ram is stored as an L sequence, inputting the L sequence into a digital circuit end, and generating a pilot branch ranging code and a data branch ranging code through a time division multiplexing calculation unit;
if the stored Ram is the ranging code, outputting the pilot branch ranging code and the data branch ranging code;
the design of the time division multiplexing calculation unit comprises the following steps:
determining the time period between every two code clocks of the time division multiplexing calculation unit according to the code rate of the ranging code corresponding to the L sequence and the working rate of the system clock;
at the time of counting the value 0, adding the phase difference of the pilot frequency branch as a read address on the basis of the chip counting value; outputting a corresponding L sequence value Lp _ w from the Ram;
counting the value at 1 moment, adding the phase difference of the pilot branch and an intercept point on the basis of a chip counting value, then taking a module of the byte length of the L sequence, and taking the module value as a read address; outputting a corresponding L sequence value Lp _ wp from the Ram;
at the moment of counting the value of 2, exclusive OR is carried out on Lp _ w and Lp _ wp to obtain a pilot frequency branch ranging code; meanwhile, on the basis of the chip count value, adding a data branch phase difference as a read address, and outputting a corresponding L sequence value Ld _ w from Ram;
at the moment of counting value 3, adding the phase difference of the data branches and the interception point on the basis of a chip counting value, then taking a module of the byte length of the L sequence, taking the module value as a read address, and outputting a corresponding L sequence value Ld _ wp from Ram;
and when the count value is 4, exclusive-OR is carried out on Ld _ w and Ld _ wp to obtain a data branch ranging code, and the next time period is entered.
2. The method as claimed in claim 1, wherein the L sequence comprises 10243bits L sequence and 10223bits L sequence.
3. The method as claimed in claim 2, wherein the 10243bitsL sequence is used to generate ranging codes of B1C signals; the 10223bitsL sequence is used to generate the ranging code for the L1C signal.
4. The method as claimed in claim 2, wherein the ranging code is 8184bits ranging code for generating the ranging code of E1 signal.
5. The method as claimed in claim 1, wherein the Ram is 10243bits in total, and the Ram comprises a first part and a second part.
6. The method as claimed in claim 5, wherein the first part has a length of 4096bits and the stored contents are pilot branch ranging codes.
7. The method as claimed in claim 5, wherein the length of the second part is 6147bits, and the content of the second part is data branch ranging code.
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| CN113391331A (en) * | 2021-06-23 | 2021-09-14 | 湖南国科微电子股份有限公司 | Ranging code acquisition method and device, electronic equipment and storage medium |
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