CN1697366B - Controllable method for generating chaos cipher sequence of natural number, and core of digit chip - Google Patents
Controllable method for generating chaos cipher sequence of natural number, and core of digit chip Download PDFInfo
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- CN1697366B CN1697366B CN 200510074598 CN200510074598A CN1697366B CN 1697366 B CN1697366 B CN 1697366B CN 200510074598 CN200510074598 CN 200510074598 CN 200510074598 A CN200510074598 A CN 200510074598A CN 1697366 B CN1697366 B CN 1697366B
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Abstract
A controllable method for generating chaos cipher sequence of natural number, and core of digit chip at first generates controllable sequence of natural number by a natural number iterative calculation method, and generates controllable chaos sequence of natural number by period continuation extending arithmetic, and based on above, further generates chaos long sequence of natural number adopting more than three chaos sequence of natural number to operate binary system multiplication (XOR) scrambling calculation, and achieves chaos sequence of natural number generator core of digit chip by adopting hardware language. The method of the invention has sensitivity to initial value, and integrates advantage of simple chaos technology code arithmetic and natural number calculation, which can be widely used for information security such as spectrum spread and data encoding, security communication etc.
Description
Technical field:
The invention belongs to the ciphering sequence production method and the digit chip nuclear technology of message area information security, be specifically related to a kind of controllable method for generating chaos cipher sequence of natural number and core of digit chip.
Background technology:
Along with the development of mobile communication, radio communication, embedded system and digit chip product more and more are used widely, and corresponding information security more and more obtains paying attention to.Shannon has proved that for once a key is an overall safety, promptly changes encryption key rather than fixed key in ciphering process at any time, adopts the stream cipher of random sequence just in time can realize this cipher mode.Adopting the key of stream cipher is the generation and the transmission of sequence.If a spot of parametric representation sequence is adopted in research, then the transmission of sequence just needs only and transmits this a spot of parameter, and adopts sequential value as each encrypted secret key, thereby conveniently realizes safety encipher communication.Real random sequence can not obtain, and generally adopts pseudo random sequence.In information communication and information encryption, pseudo random sequence has widely to be used.
Chaos sequence has pseudo-random characteristics, and statistical property with white noise responsive to initial condition.Chaos sequence based on infinite precision has easy generation, but processor requirement is had the floating-point disposal ability.Adopt the chaos iteration of limited precision to make that the chaos sequence cycle short, lost the pseudo-random characteristics of chaos.
In embedded system or in the digit chip, because to handling the ability and the speed limit of floating number, a kind of suitable chaos of special demands is calculated alternative manner, this algorithm adopts integer or natural number to carry out iterative computation, avoid floating-point operation, be fit to the characteristics of bit arithmetic.Invent this type of natural number method for generating chaos sequence, will encrypt the simple and convenient safe means that provide for the information security of embedded digital products such as mobile communication, radio communication.The natural number method for generating chaos sequence is examined now with the silicon intellectual property chip, can be made things convenient for other digital system integrated.
Summary of the invention:
In order to study natural number computing or the digitalization operation that a kind of suitable embedded environment or digit chip are handled, produce the natural number chaos sequence, the purpose of this invention is to provide a kind of controllable method for generating chaos cipher sequence of natural number and core of digit chip, it has at first proposed a kind of computational methods of natural number iteration, and then realize the natural number chaos sequence on this basis, and finish the silicon nuclear of method for generating chaos cipher sequence of natural number.
In order to realize the foregoing invention purpose, the technical solution adopted in the present invention:
The controllable method for generating chaos cipher sequence of natural number that the present invention proposes may further comprise the steps:
1. adopt the iteration of the class chaos sequence formula realization sequence of natural numbers of natural number iteration:, derived the natural number iteration formula of limited precision by the iteration of infinite precision according to the iterative formula of dynamic system Logistic mapping.The controlled sequence of natural numbers alternative manner of variable byte number is to adopt the following formula of shape:
, a=2 wherein
8q-1, and q=2,3..., the byte number that expression is got; The span of sequence of natural numbers is by the value decision of parameter a or q: z
k∈ (0,2a)=(0,2
8q), k=0 wherein, 1,2 ..., when w=1, then become the single step iteration formula:
By three parameters: initial value z
0, q and step-length w just determined whole sequence of natural numbers.In embedded system or digit chip processing, according to selected w, the initial value z that is got
0And q, only carry out multiplication z
k* z
k, supplement (is negate number-z
k 2), the displacement (promptly divided by
And z
kMultiply by 4 operation 4z
k), addition
Computing just can iterative computation obtain whole sequence of natural numbers
2. adopt the method for periodic extension expansion to make the null value in the sequence iteration disappear:, to occur stopping phenomenons such as iteration in the iteration because the limited precision that natural number is represented causes iteration gained sequence period to shorten.The present invention proposes the method for periodic extension expansion, the value that promptly adopts the value in nonzero value district to replace the null value district occurring continues iteration:
Wherein k is the sequence number of sequence, and k ∈ [1, T
n]; T
nMaximum length for the continuous nonzero value of chaos sequence; H is the cycle period preface of sequence, h=0, and 1,2 ...
3. adopt the scrambling of the sequence of natural numbers more than three to obtain the natural number chaos sequence: in order to prolong sequence period, the present invention has adopted three above sequence of natural numbers to carry out the synchronous binary position and has taken advantage of scrambling.A plurality of sequence of natural numbers { p
i(k) | p
i(k)=z
k, sequence numbering: i 〉=3; K=0,1,2 ... take advantage of by binary digit and to obtain new natural number chaos sequence after the scrambling:
P wherein
1(k), p
2(k), p
3(k) ... be the sequence that is produced by above-mentioned 1,2 steps, p (k) is controlled chaos cipher sequence of natural number.By selected byte parameter q and each sequence of natural numbers initial parameter z of adjustment control
0(z
01, z
02, z
03...) and step-length w (w
1, w
2, w
3...) w (w
1, w
2, w
3...) just can obtain different natural number class chaos sequences.
This natural number method for generating chaos sequence can be by 16, and 32 convenient realizations of embedded system also can conveniently be realized by digit chip hardware.
The present invention has further proposed a kind of for realizing the core of digit chip of above-mentioned natural number method for generating chaos sequence, and chip has adopted hardware description language to realize above-mentioned natural number method for generating chaos sequence.Its composition comprises mixed pure simple sequence generator module of three periodic extension natural number classes and clock three XOR gate modules.Periodic extension natural number class chaos simple sequence generator module is wherein formed and is comprised natural number iteration module, clocked register and data selector again.Natural number iteration module is wherein finished
Computing; Clocked register is finished the preservation to presetting on the clock edge; Data selector is finished the output of non-zero.Clock three XOR gate finish and export the XOR results of three input data on the clock edge.This chip nuclear has three data input port A, B, C (respectively in order to input z
01, z
02, z
03Three initial values) and output port Z (in order to output p (k)), three control ports are respectively clocks (CLK), preset (SET), zero clearing port (CLR).This chip is endorsed to reset primary iteration value (z by presetting end (SET)
01, z
02, z
03), can pass through clear terminal (CLR) and remove iterative value.By changing three initial value (z
01, z
02, z
03) the different natural number chaos sequence of acquisition.Output sequence has sensitiveness to parameter change.
The invention has the beneficial effects as follows:
1, the class chaos sequence formula of employing natural number iteration has reduced the complicated requirement of processor or digit chip processing floating-point.Adopt simple operations such as multiplication, supplement, displacement, addition can realize the iteration of sequence of natural numbers.The scope of number of iterations is by parameter adjustment.Determined whole sequence of iterations by initial value control.This alternative manner has the characteristics to the initial value sensitivity.
2, adopt the method for periodic extension expansion to make the null value in the sequence iteration disappear.Thereby this method makes the natural number sequence of iterations long arbitrarily, and the iteration that has overcome in the limited precision iterative stops phenomenon.Means are provided for producing sequence.
3, adopt the sequence of natural numbers more than three to carry out scrambling.Natural numerical order train value more than three is carried out the binary system XOR synchronously, obtain new natural number chaos sequence value.It is few that this method has parameter, safe characteristics.
4, Fa Ming natural number chaos sequence core of digit chip both can adopt CPLD/FPGA realize to form digit chip, also can be easily and the large scale digital system integration.
Description of drawings:
Accompanying drawing 2 is the sequence results (figure (a) and (b), (c), initial parameter is respectively 9,10,11) of natural number iteration cycle continuation and the effect illustration of the natural chaos sequence after three sequence scramblings (figure (d)) thereof.
Accompanying drawing 3 calculates length to 10 for adopting periodic extension scramble sequence shown in Figure 2
5The illustration of gained chaos sequence (initial parameter is respectively 9,10,11).
Accompanying drawing 5 is that the inside of accompanying drawing 4 described chip nuclears is formed, and is made up of three identical myiterate and a my3xor module.A myiterate module is seen accompanying drawing 6.My3xor is clock three XOR gate, finishes the XOR of three input signals on the clock edge.
Accompanying drawing 6 is that the inside of a myiterate module is formed, and is made up of con_reg, iterate and three modules of comp again.Con_reg wherein is a clocked register, when set is effective to the preservation of preset value; Iterate wherein adopts computings such as multiplication, supplement, displacement, addition to realize the iteration formula:
Function; Comp wherein is a data comparator, as din[0..15]=0 the time, dout[0..15] output dkep[0:15] value, otherwise dout[0..15] output din[0..15] value.
Embodiment:
Referring to Fig. 1, the inventive method can be schemed to embody thus: this method is to count parameter by presetting initial natural, and promptly several 2, the initial natural of several 1, the initial natural of initial natural is several 3 among Fig. 1, and band generation natural number chaos sequence 11 change under synchronizing clock signals 6 effects.When enabling preset signal 4, make natural parameter 1,2 or 3 at the beginning of can changing, next clock after preset signal 4 removes begins to carry out interative computation according to new initial value 1,2,3 again, produces new chaos sequence 11.When enabling reset signal 5, the output 11 of natural number chaos sequence algorithm becomes null value.Owing to contain periodic extension, natural number chaos generator 7,8,9 null value can not occur.By the combination of different initial natural parameters 1,2,3, just can obtain different chaos cipher sequence of natural number 11, and the change of 11 pairs of initial parameters of sequence 1,2,3 has sensitiveness.
Fig. 5 is the specific implementation of Fig. 1.Form by three identical myiterate and a my3xor module.A myiterate module is seen accompanying drawing 6.My3xor is clock three XOR gate, finishes the XOR of three input signals on the clock edge.Accompanying drawing 6 is that the inside of a myiterate module is formed, and is made up of con_reg, iterate and three modules of comp again.Con_reg wherein is a clocked register, when set is effective to the preservation of preset value; Iterate wherein adopts computings such as multiplication, supplement, displacement, addition to realize the iteration formula:
Function; Comp wherein is a data comparator, as din[0..15]=0 the time, dout[0..15] output dkep[0:15] value, otherwise dout[0..15] output din[0..15] value.
It is as follows that embedded 16bits integer chaotic encipher series production method based on periodic extension is described (behavioral scaling is whole to be described):
(1) sets initial parameter z
0(z
01, z
02, z
03) (be among Fig. 11,2,3), w (w
1, w
2, w
3), j=1, and the sequence length n that asks;
(2) if the j==n algorithm finishes; Otherwise
Continue;
(3) make i=0; (annotate: following (4)～(11) step calculates and finishes among Fig. 17,8,9)
(4) make that z (1) is z (1)=z
0iK=1;
(5) as if k==w,
Change (9); Otherwise
Continue;
(6) calculate: z (j-1) moves to left 2
T1;
(7) calculate: z (j-1) * z (j-1) also moves to right 14
T2;
(8) calculate:
K=k+1 changes (5)
(9) calculate:
(10) periodic extension is judged:
A. if p
i(j)=0 or 65536, record T
n, put periodic extension sign signal=1; Otherwise clear periodic extension sign signal=0; Continue b;
B. as if signal=1, then
(11) i=i+1, if i ≠ 3, commentaries on classics (4), otherwise continue the step (12) down;
(12)
(annotate: this step finishes among Fig. 1 10,11)
(13) change step (2).
Adopt hardware description language in EDA (Electronic Design Automation), to carry out comprehensively having produced silicon nuclear above-mentioned algorithm.And carry out functional simulation.
The illustration that obtains according to above-mentioned algorithm (4)～(11) step such as Fig. 2 (a), Fig. 2 (b), Fig. 2 (c); The illustration that step (12) obtains is as 2 (d) and Fig. 3.Fig. 4 is the chip nuclear symbol of the above-mentioned algorithm that adopts hardware description language and realize in EDA.Fig. 7 is this algorithm chip kernel function analogous diagram.
Claims (2)
1. controllable method for generating chaos cipher sequence of natural number said method comprising the steps of:
(1) the iteration formula of controlled chaos cipher sequence of natural number is:
Integer a=2 wherein
8q-1, and integer q=2,3..., the byte number that expression is got, w is a step parameter, k=0,1,2 ..., expression is by the serial number of the value z of formula calculating, z
kAnd z
K+wBe respectively substitution formula value and calculated value, z
0Be initial integer value; The value of controlled chaos cipher sequence of natural number has determined scope by the value of parameter a or q: z
k∈ (0,2a)=(0,2
8q), z
kBe integer value; By three parameters: initial value z
0, q and step-length w just determined controlled chaos cipher sequence of natural number;
(2) get different parameters z by step (1)
0, q and w, produce integer sequence { z
k, adopt the method for periodic extension expansion to make the null value in the sequence iteration disappear: the sequence of employing area of non-zero regions is carried out periodic extension and is expanded the null value zone that covers in the iteration, obtains long sequence of natural numbers, that is:
Wherein m is the sequence number of sequence, and m ∈ [1, T
n]; H is the cycle period preface of sequence, h=0, and 1,2, T
nFor sequence repeatedly with the maximum length of continuous area of non-zero regions;
(3) adopt the controlled chaos cipher sequence of natural number of step (2) generation more than three: p
1(k)={ z
K1, p
2(k)={ z
K2, p
3(k)={ z
K3..., obtain new controlled chaos cipher sequence of natural number by scrambling: promptly:
P (k) is new controlled chaos cipher sequence of natural number, by selected byte parameter q and each sequence of natural numbers initial parameter z of adjustment control
0(z
01, z
02, z
03...) and step-length w (w
1, w
2, w
3...) just can obtain different controlled chaos cipher sequence of natural number.
2. core of digit chip of realizing the described controllable method for generating chaos cipher sequence of natural number of claim 1, it is characterized in that: core of digit chip adopts hardware description language to realize the described controllable method for generating chaos cipher sequence of natural number of claim 1, and it comprises three controlled chaos cipher sequence of natural number generator modules of periodic extension and clock three XOR gate modules;
Controlled chaos cipher sequence of natural number generator module wherein comprises natural number iteration module, clocked register and data selector again; Natural number iteration module is wherein finished
Computing; Clocked register is finished the preservation to presetting on the clock edge; Data selector is finished the output of non-zero;
Clock three XOR gate modules finish and export the XOR results of three input data on the clock edge;
This chip nuclear has three data input ports, an output port and three control ports, and three control ports are respectively clock, preset, the zero clearing port.
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| CN 200510074598 CN1697366B (en) | 2005-01-18 | 2005-05-30 | Controllable method for generating chaos cipher sequence of natural number, and core of digit chip |
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| CN101022331B (en) * | 2006-02-16 | 2010-11-10 | 刘粉林 | Chaos encrypting method based on carrier |
| CN101090312B (en) * | 2007-05-24 | 2011-12-14 | 华中科技大学 | Improved speech code flow enciphering Improved speech code flow enciphering method |
| CN104062939A (en) * | 2013-03-20 | 2014-09-24 | 王少夫 | Numerically-controlled machine tool ball-feeding screw system chaotic phenomenon elimination method |
| CN103490845B (en) * | 2013-09-16 | 2015-09-30 | 哈尔滨工程大学 | Based on Adaptive MPEG I Coding System Based on Structure Segmentation generation device and the method for weighting process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1359211A (en) * | 2002-01-10 | 2002-07-17 | 张红雨 | Chaotic encipher series generator |
| CN1556602A (en) * | 2003-12-31 | 2004-12-22 | 华中科技大学 | Chaotic cipher production method under limited precision |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1359211A (en) * | 2002-01-10 | 2002-07-17 | 张红雨 | Chaotic encipher series generator |
| CN1556602A (en) * | 2003-12-31 | 2004-12-22 | 华中科技大学 | Chaotic cipher production method under limited precision |
Non-Patent Citations (2)
| Title |
|---|
| 胡文立，王玫.Logistic数字混沌序列的性能分析.桂林电子工业学院学报21 1.2001,21(1),26-29. |
| 胡文立，王玫.Logistic数字混沌序列的性能分析.桂林电子工业学院学报21 1.2001,21(1),26-29. * |
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