JP5929583B2 - Asynchronous maximum N value detection circuit and satellite signal acquisition device - Google Patents

Description

  The present invention relates to a circuit for detecting a maximum N value asynchronously.

  Conventionally, a circuit for detecting a maximum value from input data is known. For example, Patent Document 1 discloses a detection circuit for detecting a maximum value from input data. This maximum value detection circuit compares the data supplied from the external system every clock and the data stored in the register, and updates and stores the data with the larger value in the register. The maximum value of the data is detected.

JP 2004-73735 A

  The conventionally known maximum value detection circuit as described above is a synchronous detection circuit designed based on a synchronous design technique. That is, the circuit blocks constituting the detection circuit are designed to operate in synchronization with the clock signal.

  However, such a synchronous circuit has a problem that a large current of the clock signal and a problem of clock skew occur. In addition, there are other problems peculiar to a synchronous circuit, such as a high speed circuit operation exceeding the clock frequency cannot be expected or the power consumption of the entire circuit increases in proportion to the clock frequency.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to achieve high-speed operation while achieving power saving, and the highest value is the highest value among input data. The object is to propose a new circuit capable of detecting N (maximum N values) data.

  A first form for solving the above-described problem is that N (N ≧ 2) registers and N pieces of data corresponding to each of the registers are subjected to two-line encoding and output. A two-line encoder and (N-1) selection circuits are configured in a tournament type, and a tournament type selection for selecting the minimum output data from the output data of the N two-line encoders A circuit, an input data 2-line encoder that encodes and outputs given input data, an output data of the input data 2-line encoder, and a minimum output selected by the tournament type selection circuit When the output data of the input data 2-wire encoder is larger as a result of the comparison by the comparator comparing the magnitude of the data and the comparator, the storage contents of the register for storing the minimum output data are stored. Input data 2-wire code A control circuit that performs control to rewrite the output data of the encoder, and when M (M ≧ N) input data are sequentially input to the input data 2-wire encoder, of the M input data, An asynchronous maximum N-value detection circuit characterized in that upper N pieces of data are stored in the register.

  According to the first mode, data stored in N (N ≧ 2) registers are two-line encoded by the corresponding N two-line encoders. The tournament type selection circuit selects the minimum output data from the output data of the N two-wire encoders. By configuring (N-1) selection circuits in a tournament type, it is possible to easily select the minimum data among the data stored in the register.

  On the other hand, given input data is two-line encoded by the input data two-line encoder, the output data of the input data two-line encoder, the minimum output data selected by the tournament type selection circuit, Are compared by a comparator. When the output data of the input data 2-line encoder is larger as a result of the comparison by the comparator, the storage contents of the register storing the minimum output data are rewritten to the output data of the input data 2-line encoder. Control is performed by a control circuit. In this case, when M pieces (M ≧ N) of input data are sequentially input to the input data 2-line encoder, the top N pieces of data having the highest value as the highest order among the M pieces of input data are registered. Stored in Therefore, with the above configuration, it is possible to detect data of the maximum N values among the M pieces of input data.

  The maximum N value detection circuit of this embodiment is an asynchronous circuit. When the maximum N value detection circuit is configured by the synchronous design method, all circuits are driven by the clock signal, so that the worst case scenario in which the overall performance is determined by the slowest circuit is followed. However, the maximum N value detection circuit of this embodiment is an asynchronous detection circuit that employs a two-wire encoding method, and follows the average case scenario in which only necessary circuits are operated in an event-driven manner. High-speed circuit operation can be realized as the entire detection circuit. Further, since no clock signal is required, the power consumption of the entire circuit can be reduced.

  As a second form, the control circuit in the asynchronous maximum N value detection circuit of the first form stores the minimum output data based on the selection results of the (N−1) selection circuits. An asynchronous maximum N value detection circuit for determining which register to perform may be configured.

  According to the second embodiment, the control circuit can easily and appropriately determine the register storing the minimum output data by referring to the selection results of the (N−1) selection circuits. .

  As a third mode, in the asynchronous maximum N-value detection circuit according to the first or second mode, an absolute value of data stored in the register is calculated between the register and the 2-wire encoder. Then, an asynchronous maximum N value detection circuit further comprising N absolute value calculators to be output to the 2-wire encoder may be configured.

  According to the third embodiment, the absolute value calculator is provided between the register and the two-line encoder so that the absolute value of the data stored in the register is two-line encoded and supplied to the tournament type selection circuit. Is done. Thereby, in the tournament type selection circuit, the data having the minimum absolute value among the data stored in the register is selected. As a result, it is possible to store in the register the top N pieces of data having the highest absolute value among the M pieces of input data.

  As a fourth mode, in the asynchronous maximum N-value detection circuit according to any one of the first to third modes, the two-line encoder and the input data two-line encoder are instructed to operate from an external system. The control circuit executes a two-wire encoding operation according to the signal, and the control circuit outputs a control operation completion signal to the external system, and communication with the external system related to the operation instruction signal and the control operation completion signal is performed in four phases. An asynchronous maximum N value detection circuit characterized by being realized by a handshaking protocol may be configured.

  According to the fourth embodiment, the 2-wire encoder and the input data 2-wire encoder execute the 2-wire encoding operation in accordance with the operation instruction signal from the external system. Further, the control circuit outputs a control operation completion signal to the external system. In this embodiment, the communication with the external system related to the operation instruction signal and the control operation completion signal is realized by the four-phase handshaking protocol. Therefore, after grasping the operation state between the control circuit and the external system, It is possible to realize a circuit operation without contradiction.

  Further, as a fifth embodiment, a correlation calculation circuit that performs correlation calculation between a received signal that has received a satellite signal and a replica code, and data of a correlation value by the correlation calculation circuit is used as the input data. A satellite signal acquisition device comprising: the asynchronous maximum N value detection circuit according to any one of claims 1 to 3; and a capture unit that captures the satellite signal using data stored in a register of the asynchronous maximum N value detection circuit. It may be configured.

  According to the fifth embodiment, the correlation calculation circuit calculates the correlation between the received signal that has received the satellite signal and the replica code. Then, the correlation value data from the correlation calculation circuit is input as input data to the asynchronous maximum N value detection circuit of the above-described form. This makes it possible to detect the maximum N value of the correlation value data. The capturing unit can capture the satellite signal by using the data stored in the register of the asynchronous maximum N value detection circuit, that is, the correlation value of the detected maximum N value.

The block diagram which shows an example of a function structure of a GPS receiver. The figure which shows an example of a circuit structure of an asynchronous maximum N value detection circuit. The flowchart which shows the flow of a satellite signal acquisition process. The figure which shows an example of a circuit structure of an asynchronous absolute value maximum N value detection circuit.

  Hereinafter, an example of a preferred embodiment to which the present invention is applied will be described with reference to the drawings. The present embodiment is an embodiment in which the present invention is applied to a GPS receiver which is a kind of satellite positioning system. Of course, the form to which the present invention can be applied is not limited to the embodiment described below.

  A GPS satellite signal transmitted from a GPS satellite is modulated with a spread code different for each GPS satellite called a C / A (Coarse and Acquisition) code. In order to capture a GPS satellite signal from a weak received signal, the GPS receiver performs a correlation operation between the received signal and a replica code simulating a C / A code and captures the GPS satellite signal. Then, using the captured GPS satellite signal, for example, position calculation using a pseudorange is performed to calculate the position of the GPS receiver.

1. GPS Receiver FIG. 1 is a block diagram showing an example of a functional configuration of a GPS receiver 1 which is a kind of satellite signal receiver. The GPS receiver 1 is a device configured to capture a GPS satellite signal from an RF (Radio Frequency) signal received by a GPS antenna (not shown) and calculate the position using the captured GPS satellite signal. . In this embodiment, the GPS receiver 1 functions as a satellite signal capturing device that captures a GPS satellite signal by performing a correlation operation between a received signal of the GPS satellite signal and a replica code.

  The GPS receiver 1 includes an RF receiving circuit unit 10 and a baseband processing circuit unit 20. The RF receiving circuit unit 10 and the baseband processing circuit unit 20 can be manufactured as separate LSIs (Large Scale Integration) or can be manufactured as one chip.

  The RF receiving circuit unit 10 receives an RF signal output from the GPS antenna, and performs A / D conversion by sampling the received signal (analog signal) at a given sampling time interval. And outputs a received signal as digitized received data to the baseband processing circuit unit.

  The baseband processing circuit unit 20 acquires a GPS satellite signal by performing carrier wave removal, correlation calculation, and the like on the reception data output from the RF receiving circuit unit 10. Then, the position and clock error are calculated using time information and satellite orbit information extracted from the captured GPS satellite signal.

  In this embodiment, the baseband processing circuit unit 20 includes, as main components, a replica code generation unit 50, a correlation calculation circuit 100, an asynchronous maximum N value detection circuit 200, a processing unit 300, and a storage unit 400. It is configured.

  The replica code generation unit 50 is a circuit that generates a replica code that is a pseudo code that simulates a C / A (Coarse and Acquisition) code that is a spreading code of a GPS satellite signal. The replica code generation unit 50 generates a replica code related to the GPS satellite to which the PRN number is assigned according to the instructed phase shift amount according to the PRN number (satellite number) output from the processing unit 300 and the replica phase shift amount. To the correlation calculation circuit 100. The replica code generation unit 50 includes an oscillator such as a code NCO (Numerical Controlled Oscillator).

  The correlation calculation circuit 100 is a circuit unit that performs a correlation calculation between the reception signal output from the RF reception circuit unit 10 and the replica code output from the replica code generation unit 50, and includes a plurality of correlation calculation units 110 (110− 1, 110-2, 110-3,...) And a memory unit 120. The reason why the plurality of correlation calculation sections 110 are provided is to perform the correlation calculation between the received signal and the replica code in parallel by changing the phase of the replica code. This means that a plurality of channels for capturing satellite signals are provided.

  Each correlation calculation unit 110 performs a correlation calculation between the reception signal output from the RF reception circuit unit 10 and the replica code output from the replica code generation unit 50. Then, the correlation power value obtained as a result is output to the memory unit 120.

  The memory unit 120 is a storage circuit that stores the correlation power value (Power) calculated by the correlation calculation unit 110. The memory unit 120 outputs the correlation power values (Power) one by one to the asynchronous maximum N value detection circuit 200 according to the output control signal from the processing unit 300. In the present embodiment, it is assumed that M correlation power values (Power [1] to Power [M]) are sequentially supplied to the asynchronous maximum N value detection circuit 200.

  The asynchronous maximum N value detection circuit 200 has the highest N correlation powers with the maximum value being the highest among the M correlation power values (Power [1] to Power [M]) sequentially supplied from the memory unit 120. Detect value. However, N ≧ 2 and M ≧ N.

  The asynchronous maximum N value detection circuit 200 receives a two-line encoding operation instruction signal (Put) and a reset signal (Reset) from the processing unit 300. Also, the asynchronous maximum N value detection circuit 200 outputs N correlation power values and a control operation completion signal (Done) to the processing unit 300 in descending order. The configuration and operation of the asynchronous maximum N value detection circuit 200 will be described later in detail.

  The processing unit 300 is a control device and an arithmetic device that collectively control each functional unit of the baseband processing circuit unit 20, and includes a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). Is done.

  The processing unit 300 includes a correlation calculation control unit 310, a detection circuit control unit 320, and a satellite signal acquisition unit 330 as main functional units related to the present embodiment. In the present embodiment, the processing unit 300 functions as an external system that performs communication with the asynchronous maximum N value detection circuit 200.

  The storage unit 400 stores a system program of the baseband processing circuit unit 20, various programs for realizing various functions such as a satellite capturing / tracking function and a position calculating function, data, and the like. In addition, it has a work area for temporarily storing data being processed and results of various processes.

2. Asynchronous Maximum N Value Detection Circuit FIG. 2 is a diagram illustrating an example of a circuit configuration of the asynchronous maximum N value detection circuit 200. In the drawings to be referred to below, the flow of data that has been subjected to two-line coding is indicated by a bold line to distinguish it from data that has not been two-line coded. Here, as a simple example, the number of registers is four (N = 4), and an asynchronous maximum four-correlation power value detection circuit that detects the upper four correlation power values among the M correlation power values. Illustrated and described as a configuration.

  The asynchronous maximum N value detection circuit 200 includes four (= N) registers Reg of the first register Reg1 to the fourth register Reg4, and the first two-line encoder Enc1 to the fourth two-line encoding. The four-wire encoder Enc, the tournament type selection circuit TS, the input data two-wire encoder Enc0, the input data comparator Comp0, and the control circuit Ctrl.

  In the first register Reg1 to the fourth register Reg4, four pieces of data are stored in order from the maximum value among the correlation power values. These registers Reg capture the correlation power value (Power) transmitted on the data bus according to the capture instruction signals Wr1 to Wr4 output from the control circuit Ctrl. The stored contents of these registers Reg are reset in accordance with a reset signal (Reset) output from the processing unit 300.

  The first two-line encoder Enc1 to the fourth two-line encoder Enc4 correspond to each of the first register Reg1 to the fourth register Reg4, and store the data stored in the register Reg in two lines. Encode and output to the tournament type selection circuit TS. These two-line encoders Enc perform two-line encoding on the data stored in the corresponding register Reg according to the two-line encoding operation instruction signal Put output from the processing unit 300, and output the data.

Table 1 shows a truth table of the two-line coding method.

  The two-line encoding method is a method for expressing 1-bit data b using two signal line pairs “(b_1, b_0)”. “B — 1” corresponds to a positive signal line, and “b — 0” corresponds to a negative signal line.

  In the two-line coding method, the data b takes either “1” or “0” that is a valid codeword or “Null” that is an invalid codeword. By two-line coding, “0”, which is an effective codeword, is converted to “(0, 1)”, and “1”, which is an effective codeword, is converted to “(1, 0)”. An invalid code word “Null” is converted to “(0, 0)”. “(1, 1)” is called “Inhibit” and is an illegal value that cannot be taken in operation.

  In an asynchronous circuit, data is input / output between circuit blocks using a bit value that has been two-line encoded in accordance with this two-line encoding method. Data input / output is performed using the valid codeword “1” or “0”. The invalid code word “Null” is used when not operating or for separating data. If the same valid codeword is transmitted continuously, the data side cannot be identified on the receiving side, so valid codewords and invalid codewords are transmitted alternately to identify valid codewords. It is possible.

  The tournament type selection circuit TS is configured by arranging three (= N−1) selection circuits S1 to S3 in a tournament type. Specifically, the first selection circuit S1 that inputs data from the first 2-line encoder Enc1 and the second 2-line encoder Enc2, the third 2-line encoder Enc3, and the fourth The configuration includes three selection circuits S including a second selection circuit S2 for inputting data from the two-line encoder Enc4 and a third selection circuit S3 provided at the uppermost stage.

  Each selection circuit S includes a comparator Comp and a multiplexer MUX. That is, the first selection circuit S1 includes a first comparator Comp1 and a first multiplexer MUX1, and the second selection circuit S2 includes a second comparator Comp2 and a second multiplexer MUX2. The third selection circuit S3 includes a third comparator Comp3 and a third multiplexer MUX3.

  The comparator Comp is a circuit element that compares the value of the input 2-line encoded data, and is known as a comparator. The comparator Comp compares the magnitudes of the two data, compares the comparison operation completion signal CDone indicating that the comparison operation has been completed, and the comparison result signal Cp indicating the result of the magnitude comparison, the corresponding multiplexer MUX, and the control Output to the circuit Ctrl. At this time, the comparator Comp performs two-line encoding of the signal and outputs it.

  For example, the comparison operation completion signal CDone is “0” when the comparison is not completed and “1” when the comparison is completed. When the comparison is completed, the completion of the comparison operation is notified to the multiplexer MUX and the control circuit Ctrl by outputting (1, 0) obtained by 2-line encoding “1”.

  The comparison result signal Cp is, for example, when the data transmitted through the left data line in the drawing is smaller than the data transmitted through the right data line for each combination of two data input to the comparator. “1” is output to “1”, and “0” is output in the opposite case. For example, the first comparator Comp1 sets the comparison result signal Cp to “1” when the data input from the first two-line encoder Enc1 is smaller than the data input from the second two-line encoder Enc2. ", And (1, 0) obtained by two-line coding this is output. In the opposite case, the comparison result signal Cp is set to “0” and (0, 1) obtained by two-line coding this is output. The same applies to the second comparator Comp2 and the third comparator Comp3.

  The comparison between the comparison operation completion signal CDone and the comparison result signal Cp can be realized by sandwiching an invalid code word Null. That is, in the two-line coding method, valid data can be identified by alternately transmitting valid code words and invalid code words. Therefore, after the comparison operation completion signal CDone (1, 0) is output, (0, 0) corresponding to “Null” is output after the invalid code, and then (0, 1) or (1 , 0) is output, the signal receiving side can identify two types of signals.

  The multiplexer MUX is a circuit that alternatively selects and outputs two pieces of 2-line encoded data input to the multiplexer MUX according to the comparison result signal Cp output from the corresponding comparator Comp. In the present embodiment, the multiplexer MUX selects the data having the smaller value from the two data according to the comparison result signal Cp and outputs it to the subsequent stage.

  In the first selection circuit S1, the magnitudes of the two-line encoded data in the first two-line encoder Enc1 and the second two-line encoder Enc2 are compared, and the smaller value of the data is compared. Is output to the third selection circuit S3. In the second selection circuit S2, the magnitudes of the two-line encoded data in the third two-line encoder Enc3 and the fourth two-line encoder Enc4 are compared, and the smaller value of the data is compared. Is output to the third selection circuit S3. In the third selection circuit S3, the two-line encoded data output from the first selection circuit S1 is compared with the two-line encoded data output from the second selection circuit S2. The data having the smaller value is output to the input data comparator Comp0.

  As a result, the data output from the third selection circuit S3 is the smallest value among the data stored in the four registers Reg1 to Reg4. The data output from the third selection circuit S3 is referred to as “most selected data”.

  The input data 2-line encoder Enc0 uses M correlation power values (Power [1] to Power [M]) supplied from the memory unit 120 as input data, and performs 2-line encoding on the input data. From the memory unit 120, the output of the correlation power value is controlled one by one in accordance with the control of the processing unit 300. The input data 2-line encoder Enc0 performs 2-line encoding on the correlation power value supplied from the memory unit 120 in accordance with the 2-line encoding operation instruction signal Put output from the processing unit 300, and outputs the correlation power value.

  The input data comparator Comp0 is a combination of the 2-line encoded correlation power value data output from the input data 2-line encoder Enc0 and the 2-line encoded data output from the third multiplexer MUX3. Compare large and small. Then, similarly to the first comparator Comp1 to the third comparator Comp3, the two-line encoded comparison operation completion signal CDone0 and the comparison result signal Cp0 are output to the control circuit Ctrl. For example, the input data comparator Comp0 is configured to output “1” to the control circuit Ctrl as the comparison result signal Cp0 when the input data is smaller than the most significant selection data, and “0” in the opposite case. Yes.

  Among the correlation power values encoded in two lines, the data value of the positive line is put on the data bus connected in parallel to the first register Reg1 to the fourth register Reg4. According to the truth table of Table 1, the data value “0” is converted to (0, 1) by two-line encoding, and the data value “1” is converted to (1, 0) by two-line encoding. . That is, the bit value of the affirmative line in the data subjected to the two-line encoding is the same as the bit value before the two-line encoding. Actually, the correlation power value is expressed not by 1 bit but by a plurality of bits, but when each bit value is 2-line encoded, the bit value of the positive line does not change, so in this embodiment it is 2-line encoded. The circuit is configured such that the data value of the positive line among the correlated power values is transmitted to the register Reg.

  Instead of configuring the circuit in this way, a two-line decoder may be provided on the data bus connecting the input data two-line encoder Enc0 and the register Reg. That is, the circuit is configured such that the correlation power value that has been two-line encoded by the input data two-line encoder Enc0 is two-line decoded by the two-line decoder, and the two-line decoded data is written to the register Reg. It is good.

  The control circuit Ctrl is a control unit that comprehensively controls the asynchronous maximum N-value detection circuit 200, and includes a two-line decoder Dec for decoding two-line encoded data. The two-line decoder Dec receives the two-line encoded comparison operation completion signal CDone and the comparison result signal Cp output from the first comparator Comp1 to the third comparator Comp3 and the input data comparator Comp0, respectively. Decrypt. Then, based on the comparison result signal Cp subjected to the two-line decoding, it is controlled whether or not the contents of the register Reg are rewritten with input data.

  Specifically, the control circuit Ctrl determines a register Reg in which data having the smallest value among the four registers Reg is stored, based on the comparison result signal Cp input from each comparator Comp. That is, the register Reg that stores the minimum output data is determined based on the selection results of the three (= N−1) selection circuits S1 to S3. When the comparison result signal Cp0 input from the input data comparator Comp0 indicates that the output data of the input data 2-line encoder Enc0 is larger, the capture instruction signal Wr is output to the register Reg. Thus, control is performed to rewrite the storage contents of the register for storing the minimum output data to the output data of the input data 2-line encoder Enc0.

  Since the purpose is to detect the four correlation power values in descending order, the contents of the register Reg need to be rewritten sequentially with the data having the largest value. Therefore, when the input data is larger than the highest-order selection data, the control circuit Ctrl sends a fetch instruction signal Wr to the register Reg in order to rewrite the contents of the register Reg storing the highest-order selection data with the input data. And the input data on the data bus is controlled to be taken into the register Reg.

3. Processing Flow FIG. 3 is a flowchart showing a flow of satellite signal acquisition processing executed by the processing unit 300. The processing unit 300 executes this satellite signal acquisition process according to the program stored in the storage unit.

  First, the correlation calculation control unit 310 controls the correlation calculation by the correlation calculation circuit 100 (step A1). Specifically, the PRN number of the GPS satellite to be captured (hereinafter referred to as “capture target satellite”) is output to the replica code generation unit 50 and the phase shift amount of the replica code is instructed. Then, each correlation calculation unit 110 constituting the correlation calculation circuit 100 is caused to perform correlation calculation between the received signal and the replica code with different replica code phases. Note that a search in the frequency direction is also required when capturing the satellite signal. In this case, the search frequency can be determined by estimating an approximate value of the Doppler frequency.

  Next, the detection circuit control unit 320 starts control related to the detection of the correlation power value in the asynchronous maximum N value detection circuit 200. Specifically, the detection circuit control unit 320 outputs the correlation power value output control signal to the memory unit 120, thereby controlling the output of one correlation power value to the asynchronous maximum N value detection circuit 200 (step A3). .

  Next, the detection circuit control unit 320 asserts the 2-wire encoding operation instruction signal Put (step A5). In response to this, the first two-line encoder Enc1 to the fourth two-line encoder Enc4 of the asynchronous maximum N-value detection circuit 200 receive the data stored in the first register Reg1 to the fourth register Reg4. Are two-line encoded. The input data 2-line encoder Enc0 performs 2-line encoding on the correlation power value supplied from the memory unit 120.

  Next, the detection circuit control unit 320 waits until the control operation completion signal Done of the control circuit Ctrl of the asynchronous maximum N value detection circuit 200 is asserted (step A7; No), and determines that it is asserted (step A7). Yes), the two-line encoding operation instruction signal Put is negated (step A9). In response, the first 2-line encoder Enc1 to the fourth 2-line encoder Enc4 and the input data 2-line encoder Enc0 stop executing the 2-line encoding. In response to the negation of the 2-wire encoding operation instruction signal Put, the control circuit Ctrl negates the control operation completion signal Done.

  In the present embodiment, communication is realized between the processing unit 300 and the control circuit Ctrl using a four-phase handshaking protocol using the 2-wire encoding operation instruction signal Put and the control operation completion signal Done. Specifically, when the processing unit 300 asserts the 2-wire encoding operation instruction signal Put, the control circuit Ctrl executes a control operation related to rewriting of input data. When the control operation is completed, the control circuit Ctrl asserts a control operation completion signal Done. In response to the control circuit Ctrl asserting the control operation completion signal Done, the processing unit 300 negates the two-line encoding operation instruction signal Put. The control circuit Ctrl negates the control operation completion signal Done in response to the processing unit 300 negating the two-line encoding operation instruction signal Put.

  Next, the detection circuit control unit 320 determines whether or not the control operation by the control circuit Ctrl is completed for all the correlation power values (step A11). If it is determined that the control operation is not yet completed (step A11; No) ), And returns to Step A3. If it is determined that the process has been completed (step A11; Yes), the correlation power value is read from the register Reg of the asynchronous maximum N value detection circuit 200 (step A13).

  Thereafter, the satellite signal acquisition unit 330 performs satellite signal acquisition determination (step A15). Specifically, for example, an average value of correlation power values read from each register Reg is calculated. When the average value of the calculated correlation power values exceeds a predetermined threshold value, it is determined that the satellite signal has been successfully captured from the capture target satellite. Then, the code phase is determined based on the correlation power value read from each register Reg.

  Finally, the detection circuit control unit 320 performs control to reset the stored contents of the register Reg by outputting a reset signal (Reset) to the asynchronous maximum N value detection circuit 200 (step A17), and then performs satellite signal acquisition processing. Exit.

4). Operation In the asynchronous maximum N value detection circuit 200, data stored in N (N ≧ 2) registers Reg are subjected to two-line encoding by the corresponding N two-line encoders Enc. The tournament type selection circuit TS selects the minimum output data from the output data of the N two-wire encoders Enc. On the other hand, the correlation power value calculated by the correlation calculation circuit 100 performing correlation calculation is stored in the memory unit 120, and the correlation power value is detected from the memory unit 120 by one asynchronous maximum N value according to the control of the processing unit 300. It is output to the circuit 200.

  In the asynchronous maximum N value detection circuit 200, the input correlation power value is two-line encoded by the input data two-line encoder Enc0. Then, the input data comparator Comp0 compares the output data of the input data 2-line encoder Enc0 with the minimum output data selected by the tournament type selection circuit TS. If the output data of the input data 2-line encoder Enc0 is larger as a result of the comparison by the input data comparator Comp0, the stored contents of the register Reg for storing the minimum output data are stored in the input data 2-line encoder. Control for rewriting the output data of Enc0 is performed by the control circuit Ctrl. In this case, when M (M ≧ N) correlation power values are sequentially input to the input data 2-line encoder Enc0, the top N of the M correlation power values having the highest value as the highest order. Are stored in the register Reg. Therefore, with the above configuration, the maximum N value among the M correlation power values can be detected.

  The maximum N value detection circuit of this embodiment is a detection circuit configured by an asynchronous design method. When the maximum N-value correlated power value detection circuit is configured by the synchronous design method, each circuit that configures the maximum N-value detection circuit by a clock signal of a clock (for example, TCXO (Temperature Compensated Crystal Oscillator)) provided in the GPS receiver 1 Will drive the worst case scenario where the slowest circuit determines the overall performance. However, the maximum N value detection circuit of this embodiment is an asynchronous detection circuit that employs a two-wire encoding method, and follows the average case scenario in which only necessary circuits are operated in an event-driven manner. High-speed circuit operation can be realized as the entire detection circuit. In addition, since no clock is required, it is possible to save power as a whole circuit, and to avoid problems such as clock skew caused by clock signal propagation delay and circuit wiring delay. Can do.

5. Modifications Embodiments to which the present invention can be applied are not limited to the above-described embodiments, and can be changed as appropriate without departing from the spirit of the present invention. Hereinafter, modified examples will be described.

5-1. Application Example The asynchronous maximum N value detection circuit of the present invention can be used by being incorporated in a satellite signal capturing device as described in the above embodiment, or by being installed in various devices or electronic devices. is there. For example, the asynchronous maximum N value detection circuit of the present invention may be incorporated in an image processing device that performs image processing or a sound processing device that performs sound processing.

  For example, when performing filtering processing (for example, feature extraction processing or smoothing processing) on an input image in an image processing apparatus, for example, for the purpose of examining the distribution of luminance values as preprocessing, the luminance value data of each pixel is used. The maximum N value may be detected as input data.

  In addition, a receiver that receives a signal modulated by a QAM (Quadrature Amplitude Modulation) modulation method, for example, is not a receiver that receives a signal modulated by a Binary Phase Shift Keying (BPSK) modulation method such as GPS. The asynchronous maximum N value detection circuit of the invention may be incorporated. In this case, the complex correlation value calculated by the complex correlator provided in the reception device and the power value calculated using the real part and the imaginary part of the complex correlation value are used as input data, and the above embodiment is applied. It is possible to detect the maximum N value in the same manner as in FIG.

5-2. Maximum N Value Detection of Absolute Value FIG. 4 is a diagram illustrating an example of a circuit configuration of the asynchronous absolute value maximum N value detection circuit 220 in a modification. As in the detection circuit illustrated in FIG. 2, the case where the number of registers Reg is four will be described as an example (N = 4).

  In this asynchronous absolute value maximum N value detection circuit 220, the absolute value of the data stored in the register Reg is calculated between the register Reg and the two-line encoder Enc, and is output to the two-line encoder. (= N) absolute value calculators Abs are provided. That is, the first absolute value calculators Abs1 to fourth absolute value calculation for calculating the absolute value of the data stored in the register Reg in association with each of the first register Reg1 to the fourth register Reg4. A container Abs4 is provided.

  Unlike the asynchronous maximum N value detection circuit described in FIG. 2, the input data comparator Comp0 includes an absolute value output data obtained by calculating the absolute value of the output data of the input data 2-wire encoder Enc0, and a tournament type selection circuit. The size is compared with the minimum output data selected by TS. This is because the absolute value of the minimum output data selected by the tournament type selection circuit TS is calculated by the absolute value calculator Abs provided in the preceding stage, so that the absolute values are compared with each other. This is necessary. In this case, in the register Reg, the upper four data having the highest absolute value among the M input data as the highest order are stored in the register Reg.

  When this asynchronous maximum N value detection circuit is applied to the GPS receiver 1 in the above embodiment, for example, the upper predetermined number of correlation values are detected from those having a large absolute value of correlation values calculated by the correlation calculation unit. Can be used for applications.

5-3. Minimum N Value Detection Circuit In the above embodiment, an embodiment of a detection circuit that detects the top N data out of M input data has been described. However, the same circuit configuration as in FIG. Of course, it is possible to realize a detection circuit (asynchronous minimum N value detection circuit) that detects lower N pieces of data having the lowest minimum value. In addition, a detection circuit (asynchronous absolute minimum N value detection circuit) for detecting lower N pieces of data with the lowest absolute value among M pieces of input data is realized by the same circuit configuration as FIG. It goes without saying that it is possible.

5-4. Number of Registers and Tournament Type Selection Circuit In the above embodiment, the number of registers N is four (N = 4), but this is only an example. For example, N may be two or more (N ≧ 2). In this case, it is possible to freely determine how the selection circuits are arranged and formed to form the tournament type selection circuit.

5-5. Electronic Device The satellite signal capturing device described in the above embodiment is mounted on various electronic devices such as a portable telephone, a car navigation device, a portable navigation device, a personal computer, a PDA (Personal Digital Assistance), a pedometer, and a wristwatch. It is possible to use it.

5-6. In the above embodiment, GPS is applied as the satellite positioning system. However, satellite positioning such as WAAS (Wide Area Augmentation System), QZSS (Quasi Zenith Satellite System), GLONASS (GLObal NAvigation Satellite System), and GALILEO is used. Of course, the system may be applied.

  DESCRIPTION OF SYMBOLS 1 GPS receiver, 10 RF receiving circuit part, 20 Baseband processing circuit part, 50 Replica code production | generation part, 100 Correlation calculating circuit, 110 Correlation calculating part, 120 Memory part, 200 Asynchronous maximum N value detection circuit, 220 Asynchronous absolute value Maximum N value detection circuit, 300 processing unit, 310 correlation calculation control unit, 320 detection circuit control unit, 330 satellite signal acquisition unit, 400 storage unit

Claims (5)

N (N ≧ 2) registers;
Corresponding to each of the registers, N two-line encoders that output the data stored in the register by two-line encoding;
(N-1) tournament-type selection circuits configured to select tournament-type selection circuits and select the minimum output data from the output data of the N two-wire encoders;
An input data 2-line encoder for 2-line encoding and outputting given input data;
A comparator that compares the output data of the input data 2-wire encoder with the minimum output data selected by the tournament type selection circuit;
As a result of the comparison by the comparator, when the output data of the input data 2-wire encoder is larger, the storage content of the register for storing the minimum output data is used as the output data of the input data 2-wire encoder. A control circuit for performing rewrite control, and
When M (M ≧ N) input data are sequentially input to the input data 2-wire encoder, the upper N data of the M input data are stored in the register. An asynchronous maximum N value detection circuit characterized by the above. The control circuit determines a register for storing the minimum output data based on a selection result of each of the (N-1) selection circuits.
The asynchronous maximum N value detection circuit according to claim 1. Provided between the register and the two-line encoder, further comprising N absolute value calculators that calculate the absolute value of the data stored in the register and output to the two-line encoder;
The asynchronous maximum N value detection circuit according to claim 1 or 2. The 2-wire encoder and the input data 2-wire encoder execute a 2-wire encoding operation in accordance with an operation instruction signal from an external system,
The control circuit outputs a control operation completion signal to the external system;
The asynchronous maximum according to any one of claims 1 to 3, wherein communication with the external system related to the operation instruction signal and the control operation completion signal is realized by a four-phase handshaking protocol. N value detection circuit. A correlation operation circuit for performing a correlation operation between the received signal and the replica code received from the satellite signal;
Asynchronous maximum N value detection circuit according to any one of claims 1 to 4, wherein the correlation value data obtained by the correlation calculation circuit is used as the input data.
A capturing unit that captures the satellite signal using data stored in a register of the asynchronous maximum N value detection circuit;
A satellite signal acquisition device.

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