JP5914559B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which functional parts having functions such as a modulator and a laser are mounted on a semiconductor chip, and a manufacturing method thereof.

  With the progress of ultra-high-speed optical fiber transmission in recent years, there is a need for a technology that realizes a high-density optical integrated circuit, an optical semiconductor chip based on a semiconductor such as InP, and an optical semiconductor using these as a module Module is realized.

  In order to reduce the size of the optical semiconductor chip, it is important to realize a low loss and a small bending radius. As a waveguide structure that realizes a small bending radius, a high mesa structure as shown in FIG. 1 is known (see Non-Patent Document 1). In FIG. 1, the lower cladding layer 102 is made of an InP substrate, the core layer 103 is made of InGaAsP, and the upper cladding layer 104 is made of InP. This high-mesa waveguide is obtained by etching both sides of the waveguide deeper than the core layer 103, and the optical confinement in the in-plane direction of the substrate includes the lower clad layer 102, the core layer 103, and the upper clad layer 104 described above. This is done by the difference in refractive index between the constituent medium and air. Since the waveguide width w shown in FIG. 1 is a single mode condition of about 1.0 to 3.0 μm, those values are generally used.

  Non-Patent Document 2 is an example in which an optical semiconductor chip is realized with a high mesa structure using an InP substrate (prior art document). FIG. 1 shows a waveguide cross section in a passive region where no voltage is applied to the waveguide. The layer structure is as follows. A semi-insulating (SI) -InP substrate 101 is used, and an n-type lower cladding layer (n-InP) 102 and an undoped multiple quantum well (i-MQW) core layer are sequentially formed on the substrate from the substrate surface. 103, the upper cladding layer 104 is grown. The upper cladding layer 104 may be a non-doped InP (i-InP) layer, a p-InP layer laminated on an i-InP layer, or an n-InP layer on an i-InP layer. A stacked layer or a stacked layer of a thin p-InP layer on an i-InP layer and a stacked layer of an n-InP layer may also be used.

  These have a high mesa structure as shown in FIG. 1 by a fine processing technique using photolithography. This high mesa structure is protected by embedding the left and right sides of the high mesa structure using an insulating polymer 105 or the like. At this time, the polymer 105 is required to cover at least the left and right sides of the waveguide, but may be thinly deposited on the waveguide.

  FIG. 2 shows a cross-sectional view of an active region waveguide structure for applying a voltage to the waveguide. Since the polymer 105 used here is insulating, the electrode 106 is provided after removing the polymer immediately above the waveguide. The ground electrodes 107 and 108 are provided on the lower cladding layer 102. Even in this case, the waveguide is protected by the polymer 105.

  FIG. 3 is a top view of the optical semiconductor chip. The figure shows an example of a semiconductor Mach-Zehnder modulator, which is an input high-mesa waveguide 111, an output high-mesa waveguide 112, a 1-input 2-output duplexer 113, and a 2-input 1-output multiplexer 114. , High mesa waveguides 115 and 116 are provided. The high mesa waveguides 115 and 116 are provided with electrodes (signal electrodes S) 117 and ground electrodes (ground electrodes G) 119, 120, and 121 on the high mesa waveguides 115 and 116, and voltage is applied using these electrodes. Can be applied. As is apparent from the figure, an optical integrated circuit usually has both a region (active region R2) where a voltage (or current) is applied and a region (passive region R1) where no voltage is applied (passive region R1). R1 can have the configuration of the waveguide cross section shown in FIG. 1, and the active region R2 can have the configuration of the waveguide cross section shown in FIG. Some optical integrated circuits, such as wavelength filters and arrayed waveguide gratings, are all composed of a passive region.

  As described above, by embedding and protecting the high mesa structure with a polymer or the like, it is possible to suppress the deterioration of the optical characteristics and the destruction of the high mesa structure due to the adhesion of foreign matter to the core layer wall surface. As the polymer, for example, benzocyclobutene (BCB) resin is used. Since the BCB resin has good characteristics such as a low dielectric constant and high heat resistance, the capacitance (parasitic capacitance) of the semiconductor chip can be reduced. As a result, the semiconductor optical chip can be operated at high speed. As the BCB resin, for example, divinyltetramethylsiloxane-bisbenzocyclobutene (DVS-bisBCB) in which 20 to 30 atomic percent of Si atoms are combined is desirable. Moreover, as a BCB resin, the carbosilane compound and siloxane compound containing Si may be sufficient. The thickness of the BCB resin region is, for example, 2 μm or more and 6 μm or less.

Y. Shibata et al., “Reflection characteristics and cascadability of a multi-mode interference 3 dB coupler”, Optoelectronics IEE Proceedings, Vol. 149, No. 5-6, Oct-Dec 2002, pp. 217-221. H. Yagi et al., “Low driving voltage InP-based Mach-Zehnder modulators for compact 128 Gb / s DP-QPSK module”, 2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR) WK2-2 Hideki Yagi et al. “1.3 Gam AlGaInAs / InP Ridge Waveguide Laser Using BCB Planarization Process”, July 2009 SEI Technical Review No. 175, pp. 120-123.

  FIG. 4 shows how the semiconductor element (semiconductor chip) 1 is mounted. When mounting the semiconductor chip 1 as a module, it is mounted on a pedestal called a carrier 4 together with a high-frequency wiring board and an optical coupling component (such as a lens), so that mounting with high positional accuracy is required. In order to perform mounting with high positional accuracy, the chuck jig 3 having the pushing-in area 31 formed convexly around the adsorbing area is used (FIG. 4A). First, the semiconductor chip 1 is sucked and supported by the jig 3 (FIG. 4B). At this time, the region 31 to be pushed in is adjusted so as to be located in a region where the functional element 2 on the semiconductor chip 1 is not present. The solder 5 is sandwiched between the semiconductor chip 1 and the carrier 4, and after the solder 5 is heated, the region without the functional element 2 on the surface of the semiconductor chip 1 is pushed into the carrier 4 side by the pushing region 31 of the jig 3. (FIG. 4 (c)). For fixing the semiconductor chip 1 to the carrier 4, AuSn (gold tin) solder 5 or the like is used.

  However, in order to realize further high-density integration, it is expected that the area to be pushed in on the surface of the semiconductor chip 1 is also reduced. However, if the area is too small, the clearance between the jig 3 and the functional element 2 to be pushed in is reduced. There was a possibility that the functional element 2 could be damaged due to contact with it.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device capable of ensuring mounting reliability while realizing high-density integration, and manufacture of the semiconductor device Is to provide a method.

The above object the present invention for solving the includes a semi-conductor chip, a functional element circuit mounted on the semiconductor chip surface, in the same semiconductor chip surface on the front Symbol functional element circuit is mounted face, and the Bei example a plurality of struts provided at a position other than the functional element circuit, wherein the semiconductor chip is in a state of mounting the functional element circuit, pushed to the carrier side via a plurality of struts by jig the is configured to interface with the carrier, said plurality of struts, the when the semiconductor chip is pushed, the functional element circuit formed higher than the height of the functional element circuit so as not to damage the posts 2 The longitudinal elastic modulus of the lower strut on the semiconductor chip side is smaller than the longitudinal elastic modulus of the upper strut .

Moreover, this invention for solving said subject is a manufacturing method of a semiconductor device including the process of producing a semiconductor device, and the process of installing the produced semiconductor device in a carrier, Comprising: Production of the said semiconductor device The process includes a step of sequentially growing a lower clad layer, a core layer, and an upper clad layer on a semi-insulating substrate, and etching the lower clad layer, the core layer, and the upper clad layer to form a high mesa. A step of forming a waveguide, and a step of applying a constituent material of a lower layer of the support column to the upper surface and the etched region of the upper clad layer, wherein the support column has a two-layer structure, and the lower layer on the semiconductor chip side longitudinal elastic modulus of the struts is, a step is less than the longitudinal elastic coefficient of the upper strut, a step of applying, to leave a portion of the strut, to reduce the thickness of the coated layer, before And forming a constituent material of the upper strut portion of the strut, and in the step of placing the semiconductor device described above created in the carrier, to adsorb supporting the semiconductor device by a jig, the semiconductor chip of the semiconductor device When the semiconductor chip is pushed into the carrier side, the semiconductor chip of the semiconductor device is pushed to join the carrier to the carrier side through the support with the jig in a state where the functional element circuit on the semiconductor surface is mounted , the semiconductor chip is not in contact with the functional element circuit portions, only contact posts.

It is a figure which shows the waveguide (passive part) of a high mesa structure. It is a figure which shows the waveguide (active part) of a high mesa structure. It is the figure which looked at the optical integrated circuit from the top. It is a figure explaining the mounting process of the conventional semiconductor device. It is a figure which shows the structural example of the semiconductor device of this embodiment. It is a figure which shows the mounting method of the semiconductor chip of this embodiment. It is a figure which shows the specific structural example of this embodiment. It is a figure explaining the phase change amount by the optical waveguide with respect to the shortest distance between an optical waveguide and a support | pillar. It is a figure for demonstrating the failure rate of the support | pillar at the time of pushing in with respect to the area / height of a support | pillar upper surface. It is a figure which shows the failure rate of the support | pillar at the time of pushing in with respect to dielectric material layer thickness. It is a figure which shows the manufacturing process of the semiconductor device of this embodiment.

  Hereinafter, embodiments of the present invention will be described in detail.

  FIG. 5 is a diagram showing a basic configuration of a semiconductor device having the support structure of this embodiment. The semiconductor device according to the present embodiment includes an InP substrate, a dielectric layer such as benzocyclobutene (BCB) or polyimide, and a metal layer (for example, Au) used as high-speed electrical wiring or DC electrical wiring. As shown in FIG. 5, the functional element unit 22 such as a modulator or a laser is installed at the center of the semiconductor chip 2, and the columns 21 are installed at the four corners of the semiconductor chip 2. In FIG. 5A, the columns 21 are installed at the four corners, but the four columns are not necessarily four. The support column 21 can be manufactured at the same time as the functional element portion 22 and can have a two-layer (BCB, Au) structure as shown in FIG.

  FIG. 6 shows a process for installing a semiconductor device on a carrier. First, the semiconductor chip 2 on which the functional element unit 22 is mounted is vacuum chucked by the chuck jig 32. Only the pillars 21 at the four corners contact the jig, and the semiconductor chip 2 is fixed. Thereafter, the carrier 4 on which the solder 5 such as gold tin is placed is heated to near the melting point of the solder 5 to melt the solder 5, and then the semiconductor chip 2 is pressed to fix the semiconductor chip 2 to the carrier 4.

  FIG. 7A shows a configuration example (four support columns) of the semiconductor chip 2 when the functional element unit is an IQ modulator. The figure shows a configuration in which four Mach-Zehnder type optical modulators are arranged in parallel, and a waveguide 23 and an electrode 24 are provided in the functional element portion. A part of the wiring 25 is also shown in FIG. In this configuration example, the semiconductor chip 2 is provided with four support columns 21 around the waveguide 23, the electrode 24, the wiring 25, and the like constituting the functional element unit.

The shape of the column 21 was 100 (W) × 100 (D) × 6 (H) μm, Au thickness: 3 μm, and dielectric layer thickness: 3 μm. The semiconductor chip 2 was 15 (W) × 3 (D) × 0.45 (H) mm on an InP platform. The failure rate at the time of fixing to the carrier was 0.01% for the semiconductor chip of the present invention and 5% for the conventional semiconductor chip, and the yield was successfully improved.
FIG. 7B shows a configuration example (six columns) of the semiconductor chip 2 of the semiconductor DFB laser array (6ch). The figure shows a configuration in which six DFB (distributed feedback) lasers are arranged in parallel and coupled by a 6-input 1-output optical multiplexer, and a waveguide or electrode is connected to the functional element section. Have. In this configuration example, the semiconductor chip 2 is provided with six struts 21 around a waveguide, an electrode, a laser array 26, and the like that constitute a functional element unit.
The shape of the column 21 was 80 (W) × 90 (D) × 4 (H) μm, Au thickness: 2 μm, and dielectric layer thickness: 2 μm. The semiconductor chip 2 was 4 (W) × 1 (D) × 0.30 (H) mm on the InP platform. The failure rate at the time of fixing to the carrier was 0.01% for the semiconductor chip of the present invention and 6% for the conventional semiconductor chip, so that the yield was significantly improved.
In the above description, an example of an IQ modulator and an example of a DFB laser array have been described as functional elements, but the functional elements are not limited to these. Any device having an electrode or a waveguide, such as an electric field modulator integrated semiconductor laser array, a semiconductor optical amplifier array, a wavelength conversion element array, or an array of light receiving elements, may be used. Further, it may be a passive device such as an arrayed waveguide grating, and it may have only a waveguide without an electrode.

  In addition, there is a concern about the influence of stress when the support is installed in the vicinity of the optical waveguide when the support is installed. FIG. 8 shows the influence of stress when a support is installed in the vicinity of the optical waveguide. FIG. 8A shows the shortest distance (D) between the optical waveguide and the support, and FIG. Each phase change amount with respect to the shortest distance (D) between the waveguide and the support and the area / chip area (R) that cannot be installed by the installation of the support are shown. It is shown that the smaller the R (area that cannot be installed by the installation of the support column / chip area) is, the more integration is possible, and the larger the phase change amount due to the optical waveguide is, the more integration is possible. Has been. FIG. 8B shows that D = 50 to 200 μm is desirable when the phase change requirement is 3 ° or less and the R requirement is 3%.

  Also, depending on the ratio of the area and height of the upper surface of the column, the failure rate of the column during push-in changes for reasons of strength. FIG. 9 shows the relationship of the failure rate of the support column during pressing with respect to the area / height (μm) of the upper surface of the support column. Each of the three lines represents a failure rate in the case of a triangle (A), a rectangle (B), and a circle (C). As can be seen from the figure, the failure rate increases as the area / height of the upper surface of the column decreases. When the allowable value of the failure rate is 0.01% or less, the area / height of the upper surface of the support is desirably 400 μm or less. In addition, since the failure rate hardly changes at 10000 μm or more, it is desirable to make this value or less from the viewpoint of integration. As for the shape of the rectangular circuit or the square chip, the square can efficiently take up an area.

  Further, it is preferable that the longitudinal elastic modulus of the lower layer of the strut having the two-layer structure is smaller than the longitudinal elastic modulus of the upper layer. Metals have a very high longitudinal elastic modulus (Young's modulus) of several tens to several hundreds of GPa, and when deposited directly on a semiconductor that is a brittle material, there is a concern that the semiconductor chip may be damaged by impact during pressing. Therefore, the impact can be reduced by inserting a resin-based dielectric material having a low longitudinal elastic modulus of about several GPa between the InP substrate and the metal layer. Note that the two-layer strut is manufactured at the same time as the functional element portion, and has the advantage that the number of steps does not increase. For example, when the functional element circuit has an optical waveguide for propagating light, the lower layer of the two-layer structure of the support is made of the same constituent material as the layer that embeds the side surface of the optical waveguide. The upper layer is made of the same constituent material as the electrode of the functional element circuit having the electrode.

  FIG. 10 is a diagram showing a failure rate at the time of indentation with respect to the dielectric layer thickness. The failure rate is high when the dielectric layer is not thick or thin. On the other hand, if the thickness of the dielectric layer is too large, the low strength of the dielectric layer affects, and conversely the failure rate increases. Therefore, when the required failure rate is 0.01%, the dielectric layer thickness is desirably 2 to 10 μm.

  In addition, by including a magnetic material (iron oxide, chromium oxide, cobalt, ferrite, etc.) in the pillar constituent material, it is possible to lift the semiconductor chip by magnetic force and improve the mounting accuracy on the carrier. Compared with the case of using a vacuum chuck, the stress applied to the semiconductor chip is also reduced, and there is an effect of reducing warpage. The mounting position accuracy can be improved by one digit (position accuracy 0.2 μm or less) or more compared to the chuck in vacuum.

  Next, a method for producing a semiconductor device having the above configuration will be described. This method is a manufacturing method of a semiconductor device including a step of creating a semiconductor device and a step of installing the created semiconductor device on a carrier, and the step of creating the semiconductor device is performed on a semi-insulating substrate, A step of sequentially growing a crystal of a lower clad layer, a core layer, and an upper clad layer; a step of etching the lower clad layer, the core layer, and the upper clad layer to form a high mesa waveguide; A step of applying a constituent material of the lower layer of the pillar to the upper surface and the etched region of the cladding layer, a step of reducing the thickness of the applied layer while leaving the portion of the pillar, and an upper layer of the pillar in the portion of the pillar Forming the component material, and mounting the prepared semiconductor device on a carrier. And, when pressed against the carrier, the jig does not contact the functional element circuit portion of the semiconductor surface, characterized in that it only contacts the post.

FIG. 11 is a diagram illustrating a process for creating a support column. As an example, a case where a modulator is created will be described. FIG. 11A shows epitaxial growth, in which a lower cladding layer 102, a core layer 103, and an upper cladding layer 104 are grown on a semi-insulating (SI) InP substrate 101. In FIG. 11B, the high mesa waveguide H is formed by the photolithography technique and the etching technique. As shown in FIG. 11C, the BCB 105 is applied by a spinner to protect the high mesa waveguide. Subsequently, the BCB 105 is processed as shown in FIG. (See Non-Patent Reference 3). As the processing of the BCB 105, a photosensitive BCB is applied, and the BCB is left as it is only in the column portion by photolithography and CF ₄ / O ₂ reactive ion etching (RIE), and the BCB 105 is thinned in the remaining portion. . Further, using the same technique, in the active region of the optical functional element, as shown in FIG. 11 (f), after performing drilling to remove the BCB 105 (which is an insulator) from the portion where the electrode 106 is provided, the electrode 106. A ground electrode 108 is formed. At this time, the upper layer (Au) 121 of the support is also formed at the same time. At the same time, as shown in FIG. 11E, the upper layer (Au) 121 of the support can be formed even in the passive region of the optical functional element in which no electrode is formed.

  Here, the description has been given on the assumption that the pillars are formed in both the active region and the passive region, but the pillars are not necessarily required in both. For example, in the example of FIG. 7A, the support column exists only in the passive region where there is no electrode.

  According to the semiconductor device of this embodiment, it is possible to avoid the contact between the jig to be pushed in and the circuit portion by forming the support structure in the area where the functional circuit on the surface of the semiconductor chip is not present, and to perform stable mounting. Furthermore, by using a material having a low longitudinal elastic modulus for a part of the support column, it is possible to absorb the impact during pressing and prevent the semiconductor chip from being damaged. Further, by using a magnetic material-containing support and a magnet material pushing jig, the semiconductor chip can be lifted easily and with high precision, and the chip can be fixed with high precision.

2 Semiconductor chip 21 Support 22 Functional element 23 Waveguide 24 Electrode 25 Wiring 26 Laser array 3, 32 Jig for chuck 4 Carrier 5 Solder 101 Semi-insulating (SI) InP substrate 102 Lower cladding layer 103 Core layer 104 Upper cladding layer 105 BCB
106 Electrode 107, 108 Ground electrode 121 Upper layer of support (Au)

Claims (7)

A semi-conductor chip,
A functional element circuit mounted on the semiconductor chip surface;
E Bei a plurality of struts disposed in the same semiconductor chip surface on the front Symbol functional element circuit is mounted face and at a position other than the functional element circuit,
The semiconductor chip is configured to be joined to the carrier by being pushed to the carrier side through the plurality of pillars by a jig in a state where the functional element circuit is mounted,
The plurality of pillars are formed higher than the height of the functional element circuit so that the functional element circuit is not damaged when the semiconductor chip is pushed in ,
2. The semiconductor device according to claim 1, wherein the strut has a two-layer structure, and a longitudinal elastic modulus of a lower strut on the semiconductor chip side is smaller than a longitudinal elastic modulus of an upper strut . 2. The semiconductor device according to claim 1, wherein a ratio (area / height) between an area of an upper surface of the support column and a height of the support column is 400 to 10,000 μm. Having an optical waveguide wherein the functional element circuit that propagates light, the semiconductor device according to claim 1 or 2 shortest distance between said optical waveguide and said post is characterized in that it is a 50 to 200 [mu] m. 4. The semiconductor device according to claim 3 , wherein a lower layer of the two-layer structure of the support is made of the same constituent material as a layer embedded in a side surface of the optical waveguide. The functional element circuit has an electrode layer on the ones of the two-layer structure of the strut, a semiconductor according be composed of the same constituent material as the electrode of claims 2, wherein the one of the four device. The semiconductor device according to any of claims 1 5, characterized in that it contains the magnetic material constituting the strut. A step of creating a semiconductor device according to claims 1 6, a method of manufacturing a semiconductor device including the step of placing the semiconductor device created in the carrier,
The step of creating the semiconductor device includes:
A step of sequentially growing a lower clad layer, a core layer, and an upper clad layer on a semi-insulating substrate;
Etching the lower cladding layer, the core layer, and the upper cladding layer to form a high mesa waveguide;
A step of applying a constituent material of a lower layer of the pillar to the upper surface and etched region of the upper cladding layer, wherein the pillar has a two-layer structure, and the longitudinal elastic modulus of the lower pillar on the semiconductor chip side is an upper layer Applying step smaller than the longitudinal elastic modulus of the support of
Leaving the portion of the column and reducing the thickness of the applied layer;
Forming a constituent material of the upper layer of the pillar in the portion of the pillar, and
In the step of placing the created semiconductor device on a carrier, the semiconductor device is sucked and supported by a jig, and when the semiconductor chip of the semiconductor device is pushed into the carrier side, the semiconductor chip of the semiconductor device In a state where the functional element circuit is mounted, the jig is pushed by the jig so as to join the carrier to the carrier side through the support, and the semiconductor chip does not contact the functional element circuit part, but only contacts the support. A method for manufacturing a semiconductor device.

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