JP2014219442A - Semiconductor optical element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor optical element manufacturing method capable of suppressing an increase in contact resistance while improving adhesiveness of an insulating layer to a buried resin region.SOLUTION: A method of manufacturing a semiconductor optical element 50 comprises: steps S1 to S3 of preparing a substrate product P having a semiconductor mesa 9; a step S4 of forming a semiconductor protection film 11 covering the semiconductor mesa 9; a step S5 of forming a buried resin region 12; a step S6 of etching the buried resin region 12, and forming an opening A for exposing the semiconductor protection film 11 in the buried resin region 12; a step S7 of exposing an upper surface 9b of the semiconductor mesa 9 from the opening A; a step S8 of forming an ohmic metallic film 15p by evaporation and liftoff methods; and a step S9 of forming a polymer protection film 16 by a sputtering method.

Description

  The present invention relates to a method for manufacturing a semiconductor optical device.

  An embedded semiconductor optical device such as an optical modulator in which a semiconductor mesa for an optical waveguide is embedded with a resin such as benzocyclobutene (BCB) is known.

  Patent Document 1 describes a waveguide type optical element. In the manufacturing process of the waveguide type optical element, an etching groove (stripe groove) for forming the ridge waveguide is provided on both sides of the ridge waveguide, and then a protective layer covering the ridge waveguide and the etching groove is formed. . Then, the etching groove is filled with polyimide resin.

JP-A-8-220358

  When manufacturing a buried type semiconductor optical device, for example, after forming a buried resin region in which a semiconductor mesa is buried, an opening exposing the upper surface of the semiconductor mesa is formed in the buried resin region. Then, an insulating layer is formed on the upper surface of the embedded resin region, on the side surface of the opening, and on the upper surface exposed in the opening. Then, after an opening exposing the upper surface of the semiconductor mesa is formed in the insulating layer, an electrode extending from the upper surface of the semiconductor mesa to the upper surface of the embedded resin region is formed.

  Here, in the formation of the insulating layer, a film forming method that can improve the adhesion of the insulating layer to the embedded resin region is used. According to this film forming method, the contact resistance may be increased because the upper surface of the semiconductor mesa on which the insulating layer is formed is damaged.

  An object of the present invention is to provide a method of manufacturing a semiconductor optical device capable of suppressing an increase in contact resistance while improving the adhesion of an insulating layer to a buried resin region.

  The present invention includes a step of preparing a substrate product having a semiconductor mesa for an optical waveguide, a step of forming a first insulating film covering a side surface of the semiconductor mesa and an upper surface of the semiconductor mesa, and a first insulating film. Later, a resin is applied to the substrate product to form a buried resin region that embeds the side surface and the top surface, and a first opening that exposes the first insulating film on the top surface by etching the buried resin region on the top surface is formed. Forming the buried resin region; removing the first insulating film in the first opening by etching to expose the upper surface of the semiconductor mesa; and forming an ohmic metal film on the upper surface of the semiconductor mesa exposed in the first opening And forming a second insulating film that covers the upper surface of the embedded resin region, the side wall surface of the first opening, and the ohmic metal film by a sputtering method.

  In this manufacturing method, since the second insulating film is formed on the buried resin region by sputtering, the adhesion of the second insulating film to the buried resin region can be improved. In this manufacturing method, when the second insulating layer is formed, since the upper surface of the semiconductor mesa is covered with the ohmic metal film, the upper surface of the semiconductor mesa is protected from damage caused by sputtering. Therefore, an increase in contact resistance can be suppressed while improving the adhesion of the insulating layer to the embedded resin region.

  The embedded resin region is made of benzocyclobutene, and the second insulating film is made of an insulating material containing silicon. When the second insulating film made of an insulating material containing silicon is formed on the buried resin region made of benzocyclobutene by using the sputtering method, the adhesion of the second insulating film to the buried resin region can be improved. it can.

  In the step of forming the first insulating film, the first insulating film is formed by chemical vapor deposition. According to this method, it is possible to suppress damage to the upper surface of the semiconductor mesa when forming the first insulating film.

  The ohmic metal film is made of a material containing gold. According to the ohmic metal film made of a metal material containing gold, damage to the ohmic metal film due to the formation of the second insulating film can be suppressed.

  A step of etching the second insulating film on the ohmic metal film to form a second opening in the second insulating film to expose the ohmic metal film; and an ohmic in which the barrier metal film containing titanium is exposed to the second opening. A step of forming on the metal film, and a step of forming a bonding pad on the barrier metal film. A barrier metal layer is formed on the second insulating film, and further a bonding pad is formed on the barrier metal layer. Therefore, the bonding pad is bonded to the buried resin region via the barrier metal layer and the second insulating film. ing. Since the barrier metal layer is made of a metal material containing titanium, the bonding strength of the metal layer to the second insulating film can be increased. Accordingly, peeling of the barrier metal layer from the second insulating film is suppressed, so that the workability of bonding to the bonding pad can be improved.

  The width of the first opening is larger than the total width obtained by adding the thickness of the first insulating film formed on both side surfaces of the semiconductor mesa to the width of the semiconductor mesa. Since the entire upper surface of the semiconductor mesa is exposed from the first opening, an ohmic metal film can be formed on the entire upper surface of the semiconductor mesa. Therefore, an increase in contact resistance can be further suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor optical element which can suppress the increase in contact resistance is improved, improving the adhesiveness of the insulating layer with respect to a buried resin area | region.

FIG. 1 is a diagram showing main steps of a method for manufacturing a semiconductor optical device. FIG. 2 is a diagram for explaining the main steps of the method for manufacturing a semiconductor optical device. FIG. 3 is a diagram for explaining the main steps of the method for manufacturing a semiconductor optical device. FIG. 4 is a diagram for explaining the main steps of the method for manufacturing a semiconductor optical device. FIG. 5 is a diagram for explaining the main steps of the method for manufacturing a semiconductor optical device. FIG. 6 is a diagram for explaining the main steps of the method for manufacturing a semiconductor optical device. FIG. 7 is a perspective view showing an end face of the structure of the semiconductor element before being formed into chips. FIG. 8 is a plan view of the Mach-Zehnder optical modulator. FIG. 9 is a diagram illustrating main steps of a method for manufacturing a semiconductor optical device according to a comparative example. FIG. 10 is a perspective view of the end surface showing the structure of the semiconductor optical device according to the comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram showing main steps of a method for manufacturing a semiconductor optical device. 2-6 is a figure for demonstrating the main processes of the manufacturing method of a semiconductor optical element.

  As shown in FIG. 2A, a semiconductor substrate 1 having a front surface 1a and a back surface 1b is prepared. The semiconductor substrate 1 is made of an n-type III-V group semiconductor, for example, an n-type InP substrate. Then, on the surface 1a of the semiconductor substrate 1, the buffer layer 2, the core layer 3, the upper clad layer 4, and the contact layer 6 are grown in this order to form an epitaxial multilayer E (semiconductor layer growth step S1 (FIG. 1)). reference)).

  Here, the buffer layer 2 is a III-V group compound semiconductor of the first conductivity type, and is made of, for example, n-type InP. The core layer 3 is an undoped III-V group compound semiconductor and includes, for example, a well layer made of AlGaInAs and a barrier layer made of AlInAs. The upper cladding layer 4 is a second conductivity type III-V group compound semiconductor, and is made of, for example, p-type InP. The contact layer 6 is a second conductivity type III-V group compound semiconductor, and is made of, for example, p-type InGaAsP or p-type InGaAs.

As shown in FIG. 2B, an etching mask 7 is formed on the contact layer 6 (mask formation step S2 (see FIG. 1)). The etching mask 7 is preferably composed of an insulating film such as SiO ₂ formed by a thermal CVD method, for example, and has an opening 7a corresponding to the groove 8 (see part (c) of FIG. 2). Such an etching mask 7 is formed by forming an insulating film on the contact layer 6 and then etching the insulating film by a general photolithography method.

  As shown in part (c) of FIG. 2, the epitaxial stack E and the semiconductor substrate 1 are etched using the etching mask 7. By this etching, a groove 8 penetrating the contact layer 6, the upper cladding layer 4, the core layer 3, and the buffer layer 2 is formed, and a semiconductor mesa 9 for an optical waveguide is formed (semiconductor mesa forming step S3 (FIG. 1))). The optical waveguide has an optical waveguide direction along the direction in which the semiconductor mesa 9 extends. By this step S3, the substrate product P having the semiconductor mesa 9 is obtained.

  In step S3, for example, a dry etching method using HI gas is preferably used. According to the dry etching method, the semiconductor mesa 9 having the high verticality and the smooth side surface 9a is formed, and the light propagation characteristic can be improved. In particular, when each layer constituting the epitaxial stack E is made of an InP-based semiconductor as in this embodiment, it is more preferable to use an inductively coupled plasma etching (ICP-RIE) method. In this step S3, the width W1 of the semiconductor mesa 9 in the direction orthogonal to the optical waveguide direction is, for example, not less than 1 μm and not more than 2 μm. Further, the height H1 of the semiconductor mesa 9, that is, the depth of the groove 8 is, for example, 3 μm or more and 4 μm or less.

As shown in FIG. 2D, a semiconductor protective film (first insulating film) 11 is formed by chemical vapor deposition (CVD) (first insulating film forming step S4 (see FIG. 1)). . The semiconductor protective film 11 is made of, for example, an insulating material having a thickness of 0.1 μm to 0.3 μm, such as SiO ₂ , SiON, or SiN. The semiconductor protective film 11 is formed on the side surface 9 a and the upper surface 9 b of the semiconductor mesa 9 and covers the semiconductor mesa 9. The semiconductor protective film 11 covers the side wall surface 8 a and the bottom surface 8 b of the groove 8 and the top surface 6 a of the contact layer 6.

  As shown in FIG. 3A, the embedded resin region 12 is formed (embedded resin region forming step S5 (see FIG. 1)). A resin for the buried resin region 12 is applied on the semiconductor protective film 11 by a spin coating method. Benzocyclobutene (BCB) is preferably used for the resin. For example, photosensitive resin such as polyimide or AL polymer manufactured by Asahi Glass Co., Ltd. may be used as the resin.

  The height H3 of the embedded resin region 12 in the groove 8 is larger than the height H1 of the semiconductor mesa 9. In this case, the height H3 of the upper surface 12a of the embedded resin region 12 with respect to the upper surface 9b of the semiconductor mesa 9 is preferably 2 μm or more, and the upper limit is, for example, 3 μm. The side surface 9a of the semiconductor mesa 9 is embedded by the embedded resin region 12 having the flat upper surface 12a.

As shown in part (b) of FIG. 3, an opening (first opening) A is formed in a portion of the embedded resin region 12 on the semiconductor mesa 9 (embedded resin region etching step S6 (see FIG. 1)). The opening A exposes the semiconductor protective film 11 formed on the semiconductor mesa 9, and the opening A is formed by, for example, a dry etching method using CF ₄ or O ₂ gas. In forming the opening A, the etching depth of the opening A is controlled by the etching time. The etching in step S6 is performed until the upper surface 9b of the semiconductor mesa 9 is exposed from the opening A. Further, overetching may be performed by the thickness of the semiconductor protective film 11 formed on the upper surface 9 b of the semiconductor mesa 9.

  The opening A is defined using the width W1 of the semiconductor mesa 9. That is, the width W2 of the opening A in the direction orthogonal to the optical waveguide direction is formed to be slightly larger than the width W1 of the semiconductor mesa 9 in the direction. More specifically, the width W2 of the opening A is larger than the total width obtained by adding the thickness t1 of the semiconductor protective film 11 formed on both side surfaces 9a of the semiconductor mesa 9 to the width W1 of the semiconductor mesa 9.

  In step S6, simultaneously with the formation of the opening A, the embedded resin region 12 in the region Y is etched to form the opening B. The opening B has a width W3 in a direction orthogonal to the scribe direction, for example, 100 μm.

As shown in FIG. 3C, the semiconductor protective film 11 on the semiconductor mesa 9 is removed by etching to expose the upper surface 9b of the semiconductor mesa 9 in the opening A (first insulating film etching step). S7 (see FIG. 1)). In this step S7, for example, a dry etching method using CF ₄ gas is used. At least the upper surface 9b of the semiconductor mesa 9 is exposed in the opening A after performing the step 7, and the end surfaces 11a of the semiconductor protective films 11 on both sides on the side surface 9a of the semiconductor mesa 9 are formed.

  Subsequently, an ohmic metal film 15p that is in ohmic contact with the contact layer 6 is formed on the semiconductor mesa 9 (ohmic metal film forming step S8 (see FIG. 1)). First, as shown in FIG. 4A, a mask 13 for lift-off is formed (step S8a). The mask 13 is a positive resist, and a two-layer resist method is used for forming the mask 13. The mask 13 is formed on the upper surface 12a of the embedded resin region 12, the side wall surface A1 of the opening A, and the side wall surface B1 and the bottom surface B2 of the opening B. More specifically, the mask 13 is formed between the upper surface 12a and the bottom surface A2 of the opening A on the side wall surface A1 of the opening A. The edge 13a of the mask 13 is formed inside the opening A. The mask 13 having such a shape can be obtained by controlling the pattern shape and the exposure time for forming the mask 13.

  As shown in FIG. 4B, a metal film 15 is formed on the semiconductor mesa 9 and the resist 13 by, for example, a vapor deposition method (step S8b). The metal film 15 includes a metal film 15a formed on the entire bottom surface A2 of the opening A including the upper surface 9b of the semiconductor mesa 9, and a metal film 15b formed on the mask 13 on the upper surface 12a of the embedded resin region 12. Contains. Here, the bottom surface A <b> 2 of the opening A includes the upper surface 9 b of the semiconductor mesa 9 and the end surface 11 a of the semiconductor protective film 11.

  The bottom surface A2 may further include a bottom surface 12c of the embedded resin region 12. The ohmic metal layer 15p provided on the bottom surface A2 includes a protruding portion S that protrudes outward from the semiconductor protective layer 11 in the width W1 direction of the semiconductor mesa 9.

  The metal film 15 has a configuration in which an Au film, a Zn film, and an Au film are stacked in this order (Au / Zn / Au), and the Au film and the Zn film are formed by vapor deposition. The metal film 15 may have a configuration (Ti / Pt / Au) in which a Ti film, a Pt film, and an Au film are stacked in this order.

  As shown in FIG. 4C, unnecessary portions of the metal film 15 are removed by a lift-off method (step S8c). The unnecessary portion is the metal film 15 b on the embedded resin region 12.

  Through the above steps S8a to S8c, the ohmic metal film 15p is formed in contact with the entire upper surface 9b of the semiconductor mesa 9, the end surface 11a of the semiconductor protective film 11, and the upper surface 12c of the embedded resin region 12 (ohmic). Metal film forming step S8 (see FIG. 1)).

  Here, in the opening A, a step of about 2 μm to 3 μm corresponding to the height H4 of the embedded resin region 12 in the region Y is formed. In order to form the ohmic metal film 15p on at least the upper surface 9b of the semiconductor mesa 9 by the vapor deposition method and the lift-off method as in steps S8a to S8c, a resist 13 having a height equal to or higher than the height H4 (for example, 3-4 μm) is required. In addition, when the width W2 of the opening A is equal to the width W1 of the semiconductor mesa 9 (1 μm to 2 μm), the acceptance ratio is increased and high overlay accuracy is required. In this embodiment, the width W2 of the opening A is made larger than the width W1 of the semiconductor mesa 9, and the pattern is formed wider than the width W1 of the semiconductor mesa 9.

As shown in FIG. 5A, a polymer protective film (second insulating film) 16 that protects the embedded resin region 12 is formed (second insulating film forming step S9 (see FIG. 1)). Similar to the semiconductor protective film 11, the polymer protective film 16 is made of an insulating material having a thickness of 0.1 μm to 0.4 μm, such as SiO ₂ , SiON, or SiN. The polymer protective film 16 is formed in contact with the upper surface 12a of the embedded resin region 12, the ohmic metal film 15p exposed from the opening A, and the semiconductor protective film 11 exposed from the opening B.

  In the opening A, a step of about 2 μm to 3 μm corresponding to the height H4 of the embedded resin region 12 in the region Y is formed. For this reason, in forming the polymer protective film 16, it is required to apply a film forming method that has good adhesion to the resin material forming the embedded resin region 12 and good step coverage. As a film forming method that satisfies such conditions, a sputtering method is applied in step S9.

  In addition, since the polymer protective film 16 is formed after the ohmic metal film 15p is formed (step S8), the ohmic metal film 15p is embedded in the embedded resin region 12 by the protruding portion S outside the upper surface 9b of the semiconductor mesa 9. And the second polymer protective film 16 and the semiconductor protective film 11 and the second polymer protective film 16.

As shown in part (b) of FIG. 5, the polymer protective film 16 is etched to form an opening C (second opening) as a contact hole in the polymer protective film 16 on the semiconductor mesa 9. For forming the opening C, for example, a dry etching method using CF ₄ gas is used. From the opening C, the ohmic metal film 15p on the semiconductor mesa 9 is exposed (contact hole forming step S10 (see FIG. 1)).

  In step S <b> 10, the width W <b> 4 of the opening C in the direction orthogonal to the optical waveguide direction may be wider than the width W <b> 1 of the semiconductor mesa 9. This is because the width W5 of the ohmic metal film 15p is larger than the width W1 of the semiconductor mesa 9, and the semiconductor protective film 11 and the embedded resin region 12 on the side surface 9a of the semiconductor mesa 9 are not over-etched.

  As shown in FIG. 5C, a barrier metal film 17 is formed (barrier metal film forming step S11 (see FIG. 1)). The barrier metal film 17 is formed on a surface including the upper surface 16a of the polymer protective film 16 and the ohmic metal film 15p exposed from the openings A and C. In this step S11, a Ti (titanium) film is first formed, a Pt film is formed thereon, an Au film is further formed thereon, and a Ti / Pt / Au film is formed. For example, vapor deposition or sputtering is used to form these metal films. The barrier metal film 17 may be a TiW / Au film in which an Au film is formed on a TiW film.

  As shown in FIG. 6A, a bonding pad 18 is formed on the barrier metal film 17 (bonding pad forming step S12 (see FIG. 1)). The bonding pad 18 includes a portion formed in the opening A and a portion formed on the region Y between the groove 8 and the opening B. In this step S12, the bonding pad 18 is formed on the barrier metal film 17 by, for example, Au plating. Then, as shown in FIG. 6B, the portion of the barrier metal film 17 exposed from the bonding pad 18 is removed by etching.

  As shown in part (c) of FIG. 6, in the semiconductor protective film 11 and the polymer protective film 16, a portion on the scribe line, that is, a portion formed on the contact layer 6 exposed in the opening B is etched, for example. (Element isolation groove forming step S13 (see FIG. 1)).

  As shown in FIG. 6D, an ohmic metal film 19 that is a cathode electrode is formed on the back surface 1b of the semiconductor substrate 1 (ohmic metal film forming step S14 (see FIG. 1)). The ohmic metal film 19 is an AuGe / Au film in which an Au film is formed on an AuGe film. For forming these metal films, for example, a vapor deposition method or a sputtering method is used. The AuGe film of the ohmic metal film 19 formed by this step S14 makes ohmic contact with the semiconductor substrate 1. The ohmic metal film 19 may be an AuGe / Ti / Pt / Au film in which an AuGe film is formed and a Ti film, a Pt film, and an Au film are sequentially formed thereon.

  Then, after the ohmic metal film 19 is formed, a portion of the ohmic metal film 19 formed immediately below the opening B of the embedded resin region 12 is removed by etching to form an opening D. Finally, the semiconductor substrate 1 is cut along the openings B and D, which are scribe lines (element cutting step S15 (see FIG. 1)). By performing the above steps S1 to S15, the semiconductor light modulation device is completed. .

  Next, the structure of the waveguide type semiconductor optical device obtained by the above steps S1 to S15 will be described. FIG. 7 is a perspective view showing an end face of the structure of the semiconductor element before being formed into chips. As shown in FIG. 7, the waveguide type semiconductor optical device 50 is a semiconductor optical modulation device.

  The semiconductor optical device 50 includes a semiconductor mesa 9 including the semiconductor substrate 1. The semiconductor substrate 1 functions as a support substrate for maintaining the mechanical strength of the semiconductor optical device 50. A buffer layer 2 is provided on the semiconductor substrate 1.

  The buffer layer 2 has a function of improving the crystallinity of the core layer 3. A core layer 3 is provided on the buffer layer 2. The core layer 3 includes a multiple quantum well structure (MQW) in which a plurality of well layers and barrier layers are alternately stacked. The core layer 3 may have a quantum well structure in which one well layer is sandwiched between upper and lower barrier layers, or may be a layer made of a single semiconductor material. An upper clad layer 4 is provided on the core layer 3. The upper clad layer 4 functions as a clad for confining the light guided through the core layer 3 in the core layer 3. A contact layer 6 is provided on the upper cladding layer 4. The contact layer 6 is provided for ohmic contact with the electrode.

  As described above, the semiconductor mesa 9 includes a part of the semiconductor substrate 1, the buffer layer 2, the core layer 3, the upper cladding layer 4, and the contact layer 6.

  The semiconductor optical device 50 has a groove 8 that is a trench. The groove 8 is provided to form a stripe-shaped semiconductor mesa 9 constituting the optical waveguide in the region X. The groove 8 extends along the optical waveguide direction G. The groove 8 is formed by etching that penetrates the contact layer 6, the upper cladding layer 4, the core layer 3, and the buffer layer 2, and the bottom surface thereof is constituted by the semiconductor substrate 1. The inner wall of the groove 8 constitutes a side surface 9 a of the semiconductor mesa 9 for the optical waveguide in the region X. In the semiconductor mesa 9, light is mainly guided through the core layer 3. The semiconductor mesa 9 confines light in the left-right direction due to the difference in refractive index between the side surface 9 a and the outside, and confines light in the vertical direction due to the difference in refractive index between the upper cladding layer 4 and the buffer layer 2 and the core layer 3.

  The semiconductor protective film 11 is for insulating and protecting a semiconductor region such as the semiconductor mesa 9 from the outside. In order to allow contact between the contact layer 6 of the semiconductor mesa 9 and the anode electrode structure 21, the semiconductor protective layer 11 on the upper surface 9b of the semiconductor mesa 9 is removed.

  The embedded resin region 12 is for embedding the side surface 9a of the semiconductor mesa 9 and providing a bonding pad 18 of the anode electrode structure 21 described later. Since the side surface 9a of the semiconductor mesa 9 is embedded by the embedded resin region 12, the formation of a metal layer on the side surface 9a is avoided, and scattering and absorption of light propagating through the optical waveguide are suppressed. Further, the buried resin region 12 is formed thicker than the depth H1 of the groove 8 in order to reduce stray capacitance due to the bonding pad 18 and suppress deterioration of the high-frequency characteristics of the element (FIG. 3A). Section).

  The embedded resin region 12 has two openings A and B. The opening A is formed on the semiconductor mesa 9 of the embedded resin region 12 and in a region on the semiconductor substrate 1 that will be a light modulation section 66 (see FIG. 8) described later. In the opening A, an ohmic metal film 15p, a barrier metal film 17, and a bonding pad 18 are disposed. The opening B functions as a scribe line when the semiconductor optical device 50 is chipped.

  The polymer protective film 16 is for protecting the embedded resin region 12 and preventing moisture absorption from the upper surface 12 a of the embedded resin region 12. An opening C is provided in the polymer protective film 16 on the semiconductor mesa 9.

  The anode electrode structure 21 is provided from the upper surface 9 b of the semiconductor mesa 9 to the upper surface 16 a of the polymer protective film 16. The anode electrode structure 21 of this embodiment includes an ohmic metal film 15p, a barrier metal film 17, and a bonding pad 18.

  The ohmic metal film 15 p is provided on the entire bottom surface of the opening A of the embedded resin region 12 including the upper surface 9 b of the semiconductor mesa 9. When the AuZn film of the ohmic metal film 15p and the contact layer 6 of the semiconductor mesa 9 are in contact with each other, the anode electrode structure 21 and the contact layer 6 are in ohmic contact. A part of the ohmic metal film 15 p is electrically connected to the barrier metal film 17 through the opening C of the polymer protective film 16.

  The barrier metal film 17 is in contact with the polymer protective film 16 on the embedded resin region 12. The Ti film of the barrier metal film 17 and the polymer protective film 16 are in contact with each other, so that the bonding strength (adhesion) between the barrier metal film 17 and the polymer protective film 16 is enhanced. The bonding pad 18 is a portion to which a bonding wire that electrically connects the anode electrode structure 21 and an external circuit is bonded.

  The cathode electrode structure 22 includes an ohmic metal film 19 provided on the back surface 1 b of the semiconductor substrate 1. In addition, on the back surface 1 b of the semiconductor substrate 1, an opening D for cutting the semiconductor substrate 1 is provided immediately below the opening B of the embedded resin region 12.

  Next, a Mach-Zehnder optical modulator 60 that is an example of the above-described waveguide-type semiconductor optical device 50 will be described. The Mach-Zehnder optical modulator 60 is an apparatus for constructing an optical communication network, and is a semiconductor optical device that changes the light intensity of transmitted light by controlling the phase of light using an electrical signal.

  FIG. 8 is a plan view of the Mach-Zehnder optical modulator 60. As shown in FIG. 8, the Mach-Zehnder optical modulator 60 includes couplers 61 and 62 that are so-called multimode interference waveguides (MMI) for processing signal light. The coupler 61 branches the signal light into two branched lights, and the coupler 62 combines the branched lights that have undergone predetermined processing to generate a new signal light.

  Signal light is incident on the coupler 61 through the optical waveguides 62a and 62b. The branched light emitted from the coupler 61 enters the coupler 61 through the optical waveguides 63a and 63b. The signal light emitted from the coupler 61 is emitted to the outside through the optical waveguides 64a and 64b.

  Here, between the coupler 61 and the coupler 62, an optical modulator 66 that changes the phase of one of the branched lights is provided. The light modulation unit 66 includes a p-electrode 66a provided on the optical waveguide 63a to which a DC voltage is applied and a p-electrode 66b to which an AC voltage is applied. In addition, the light modulation unit 66 includes a p-electrode 66c provided on the optical waveguide 63b to which a DC voltage is applied and a p-electrode 66d to which an AC voltage is applied. An n-electrode 66e is provided between the optical waveguide 63a and the optical waveguide 63b. In the light modulator 66, the phase of the signal light is controlled by controlling the voltage applied to the p electrodes 66a to 66d.

  Here, FIG. 7 is a cross section taken along the line VII-VII in FIG. 8. The optical waveguide 63a corresponds to the semiconductor mesa 9, and the anode electrode structure 21 corresponds to the p electrode 66a.

  Next, a method for manufacturing the semiconductor optical device 90 according to the comparative example will be described. FIG. 9 is a diagram showing the main steps of the method for manufacturing a semiconductor optical device according to the comparative example, and FIG. 10 is a perspective view of the end face showing the structure of the semiconductor optical device 90 according to the comparative example.

  As shown in FIG. 9A, after forming the opening A in the embedded resin region 12 (step S6), the semiconductor protective film 11 is etched to expose the upper surface 9b of the semiconductor mesa 9 (step S7). . The manufacturing method of the comparative example is performed through the same steps as the manufacturing method of the present embodiment until step S7. Subsequently, a polymer protective film 91 is formed by sputtering, and the polymer protective film 91 formed on the bottom of the opening A is etched to expose the upper surface 9b of the semiconductor mesa 9 (see the part (b) in FIG. 9). Next, an ohmic metal film 92 is formed on the bottom of the opening A including the upper surface 9b of the semiconductor mesa 9 by vapor deposition and lift-off (see part (c) of FIG. 9).

  Then, a barrier metal film 93 is formed on the ohmic metal film 92 and the polymer protective film 16 (see the part (d) in FIG. 9). Then, the semiconductor optical element 90 shown by FIG. 10 is manufactured by implementing process S11-S15 (refer FIG. 1) of this embodiment.

  According to the manufacturing method of the comparative example described above, since the polymer protective film 91 is formed on the upper surface 9b of the semiconductor mesa 9 by the sputtering method, the upper surface 9b of the semiconductor mesa 9 is damaged. Further, in the step of etching the semiconductor protective film 11 and the step of etching the polymer protective film 91, the upper surface 9b of the semiconductor mesa 9 is further damaged. Therefore, the contact layer 6 forming the upper surface 9b is increased in damage, which may increase the contact resistance.

  On the other hand, in the method of manufacturing the semiconductor optical device 50 according to the present embodiment, the ohmic metal film 15p is formed on the upper surface 9b of the semiconductor mesa 9 by using a vapor deposition method and a lift-off method with low damage to the semiconductor. Damage to the contact layer 6 during the 15p film formation can be reduced.

  In the method of manufacturing the semiconductor optical device 50 according to the present embodiment, when the polymer protective film 16 is formed, the upper surface 9b of the semiconductor mesa 9 is covered with the ohmic metal film 15p. The upper surface 9b of the semiconductor mesa 9 is not damaged by the film formation.

  Furthermore, in the method of manufacturing the semiconductor optical device 50 according to the present embodiment, when the polymer protective film 16 is etched, the upper surface 9b of the semiconductor mesa 9 is covered with the ohmic metal film 15p. The top surface 9b of the mesa 9 is not damaged. Therefore, the application of damage due to etching can be reduced once.

  Therefore, according to the method for manufacturing the semiconductor optical device 50 of the present embodiment, the damage given to the contact layer 6 in contact with the ohmic metal film 15p is reduced, so that an increase in contact resistance can be suppressed.

  Further, since the polymer protective film 16 made of an insulating material containing silicon is formed on the buried resin region 12 made of benzocyclobutene by sputtering, the adhesion of the polymer protective film 16 to the buried resin region 12 is improved. Can do. And since peeling of the polymer protective film 16 from the embedded resin region 12 is suppressed, the workability of bonding to the bonding pad 18 can be improved.

  Further, in the step S4 for forming the semiconductor protective film 11, the semiconductor protective film 11 is formed by the CVD method, so that damage to the upper surface 9b of the semiconductor mesa 9 during the formation of the semiconductor protective film 11 can be suppressed.

  In addition, since the ohmic metal film 15p is made of a material containing gold, damage to the ohmic metal film 15p due to the formation of the polymer protective film 16 can be suppressed.

  Further, since the entire upper surface 9b of the semiconductor mesa 9 is exposed from the opening A, the ohmic metal film 15p can be formed on the entire upper surface 9b of the semiconductor mesa 9. Therefore, an increase in contact resistance can be further suppressed.

  According to the method for manufacturing the semiconductor optical device 50 of the present embodiment, the anode electrode structure 21 can be easily formed on the upper surface 9 b of the semiconductor mesa 9 because the planarization is performed by the embedded resin region 12. Therefore, while solving the problem of increase in contact resistance, the high frequency characteristics are improved, and the wafer process can be made large in diameter, which is advantageous in manufacturing cost.

  Although the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist thereof.

  The semiconductor optical device manufactured by the manufacturing method of this embodiment has an anode-side electrode on the front surface side and a cathode-side electrode on the back surface side, but the semiconductor optical device has a cathode-side electrode on the front surface side. It is also possible to provide the anode side electrode on the back side.

In the description of the manufacturing method of the present embodiment, the semiconductor protective film 11 and the polymer protective film are exemplified by a structure made of SiO ₂ or SiN which is a dielectric insulating material. However, the semiconductor protective film 11 and the polymer protective film 16 are made of Si, The structure which consists of fluoride, an oxide, and nitride containing Al, Ti, etc. may be sufficient.

  In the manufacturing method of the present embodiment, a photoelectric conversion circuit may be formed on the semiconductor substrate 1. This photoelectric conversion circuit includes, for example, an InP-based electronic device such as a heterojunction bipolar transistor, a capacitor, and a resistance element.

  The manufacturing method of this embodiment may be applied to the manufacture of semiconductor lasers and light receiving elements in addition to the optical modulators described above.

  Although the manufacturing method of the present embodiment has been described by taking the case where the semiconductor mesa 9 is an optical waveguide extending in one direction as an example, the semiconductor mesa may be, for example, a cylindrical mesa structure assuming front surface incidence and back surface incidence. Good.

  The conductivity of the semiconductor substrate 1 may be a p-type semiconductor substrate or a semi-insulating semiconductor substrate doped with Fe. In the case of a semi-insulating semiconductor substrate, the cathode electrode is formed on the surface side of the semiconductor substrate.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 9 ... Semiconductor mesa, 11 ... Semiconductor protective film (1st insulating film), 12 ... Embedded resin area | region, 15p ... Ohmic metal film, 16 ... Polymer protective film (2nd insulating film), 17 ... Barrier metal Membrane, 18 ... bonding pad, 50 ... semiconductor optical device, 60 ... Mach-Zehnder optical modulator, A ... opening (first opening), B ... opening, C ... opening (second opening), P ... substrate product, S1 ... Semiconductor layer growth step, S2 ... Mask formation step, S3 ... Semiconductor mesa formation step, S4 ... First insulating film formation step, S5 ... Embedded resin region forming step, S6 ... Embedded resin region etching step, S7 ... First insulating film etching Step, S8 ... Ohmic metal film forming step, S9 ... Second insulating film forming step, S10 ... Contact hole forming step, S11 ... Barrier metal film forming step, S12 ... Bonding pad Forming step, S13 ... isolation groove forming step, S14 ... ohmic metal film forming step, S15 ... element cutting step.

Claims (6)

Preparing a substrate product having a semiconductor mesa for the optical waveguide;
Forming a first insulating film covering a side surface of the semiconductor mesa and an upper surface of the semiconductor mesa;
After forming the first insulating film, applying a resin to the substrate product to form a buried resin region that embeds the side surface and the upper surface;
Etching the embedded resin region on the upper surface to form a first opening in the embedded resin region to expose the first insulating film on the upper surface;
Removing the first insulating film in the first opening by etching to expose the upper surface of the semiconductor mesa;
Forming an ohmic metal film on the upper surface of the semiconductor mesa exposed in the first opening;
Forming a second insulating film covering the upper surface of the embedded resin region, the side wall surface of the first opening, and the ohmic metal film by a sputtering method. The embedded resin region is made of benzocyclobutene,
The method of manufacturing a semiconductor optical device according to claim 1, wherein the second insulating film is made of an insulating material containing silicon.   3. The method of manufacturing a semiconductor optical device according to claim 1, wherein in the step of forming the first insulating film, the first insulating film is formed by chemical vapor deposition.   The said ohmic metal film is a manufacturing method of the semiconductor optical element as described in any one of Claims 1-3 which consists of material containing gold | metal | money. Etching the second insulating film on the ohmic metal film to form a second opening in the second insulating film to expose the ohmic metal film;
Forming a barrier metal film containing titanium on the ohmic metal film exposed in the second opening;
Forming a bonding pad on the barrier metal film;
The manufacturing method of the semiconductor optical element as described in any one of Claims 1-4 which has these.   The width of the first opening is larger than the total width of the width of the semiconductor mesa plus the thickness of the first insulating film formed on both side surfaces of the semiconductor mesa. The manufacturing method of the semiconductor optical element of description.

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