JP5901373B2 - Noise removal circuit, semiconductor integrated device, and noise removal method - Google Patents

Description

  The present invention relates to a noise removal circuit capable of removing noise from an input signal, a semiconductor integrated device equipped with the noise removal circuit, and a noise removal method.

  In a digital circuit mounted on a semiconductor integrated device, particularly a flip-flop that resets asynchronously with respect to a clock signal (hereinafter referred to as FF), when noise is superimposed on an externally supplied input signal, In some cases, this noise causes resetting at an incorrect timing.

  Therefore, in order to prevent such a malfunction, a signal delay circuit has been proposed in which only the rising edge portion or the falling edge portion of the binary input signal is delayed (for example, (See FIG. 1 or FIG. 3 of Patent Document 1). For example, in the signal delay circuit shown in FIG. 3 of Patent Document 1, only the timing at which the input signal transitions from the logic level “0” to the state “1” is delayed by a predetermined delay period and output. According to such a configuration, the output is fixed at the logic level “0” regardless of the level of the input signal during the delay period described above. For example, the pulse level of the logic level “1” is applied to the input signal during this period. Even if the noise is superimposed, the influence of the pulse noise is not reflected on the output.

  Therefore, if the externally input reset signal subjected to the delay processing by the signal delay circuit is supplied to the reset terminal of the FF, it does not react to the pulsed noise superimposed on the input reset signal. Then, the reset can be performed by reacting only to the reset pulse having a stable logic level “1” thereafter.

  However, when such a signal delay circuit is used, the pulse width of the reset pulse is narrowed by the above-described delay period. Therefore, when the pulse width of the reset signal input externally becomes narrow to a degree slightly longer than the delay period due to noise or the like, or long noise with a pulse width slightly longer than this delay period is superimposed. In this case, there is a high possibility that a reset pulse having a shorter pulse width than the specified reset hold period is supplied to the FF. Therefore, at this time, there arises a problem that each FF cannot be reliably reset.

  Further, in the signal delay circuit described above (see, for example, FIG. 3 of Patent Document 1), since the power supply voltage is applied to the output line a via the capacitor 4, negative noise lower than the ground voltage is applied to the ground line. If they are superimposed, a malfunction occurs. That is, when such negative noise is superimposed on the ground line, a current flows instantaneously in the current path composed of the capacitor 4, the output line a, and the resistor 3, and the voltage on the output line a temporarily becomes logic. A malfunction occurs in which the state is inverted from the level “0” to the logic level “1”.

Japanese Patent Laid-Open No. 05-110396

  The present invention is a noise removal circuit that is not easily affected by noise superimposed on a power supply line and a ground line, and that can remove noise superimposed on the input signal without reducing the pulse width of the input signal. An object of the present invention is to provide a semiconductor integrated device and a noise removal method.

  A noise removal circuit according to the present invention is a noise removal circuit that performs a noise removal action on an input on / off signal having one of first and second levels, and includes a rising edge portion and a rising edge in the input on / off signal. A first delay circuit that generates a first delay signal obtained by delaying one of the falling edge portions over a predetermined period, and the other of the rising edge portion and the falling edge portion in the first delay signal is the predetermined period. A second delay circuit that generates a second delay signal delayed for a period of time, and as long as the first delay signal has the first level, captures and holds the second delay signal and outputs it as a noise removal signal, As long as the first delay signal has the second level, a latch that stops taking in the second delay signal and outputs the held content as the noise removal signal; Serial first and second delay signals both having a gate for controlling the latch in order to set the contents the retained as long as having the second level to the second level.

  The semiconductor integrated device according to the present invention is a semiconductor integrated device in which a noise removal circuit that performs a noise removal action on an input on / off signal having one of the first and second levels is formed. The noise removal circuit includes: a first delay circuit that generates a first delay signal obtained by delaying one of a rising edge portion and a falling edge portion of the input on / off signal over a predetermined period; and A second delay circuit that generates a second delay signal obtained by delaying the other of the rising edge portion and the falling edge portion over the predetermined period; and only when the first delay signal has the first level. The second delayed signal is captured and held and output as a noise removal signal, while the second delayed signal is captured only when the first delayed signal has the second level. A latch that stops and outputs the retained content as the noise removal signal; and when both the first and second delayed signals have the second level, the retained content is set to the second level. And a gate for controlling the latch.

  The noise removal method according to the present invention is a noise removal method for applying a noise removal action to an input on / off signal having one of the first and second levels, and a rising edge portion in the input on / off signal. And generating a first delayed signal obtained by delaying one of the falling edge portions for a predetermined period, and setting the other of the rising edge portion and the falling edge portion of the first delayed signal for the predetermined period. A delayed second delayed signal is generated, and as long as the first delayed signal has the first level, the second delayed signal is captured and held and output as a noise removal signal, while the first delayed signal is As long as the second level signal has the second level, the capturing of the second delay signal is stopped and the stored content is output as the noise removal signal. If having a second level set the contents described above held in the second level.

  The present invention generates, as a first delay signal, a signal obtained by delaying only a rising edge portion (or falling edge portion) of an input signal for a predetermined period, and subsequently a falling edge portion with respect to the first delay signal. A signal obtained by delaying only (or the rising edge) for a predetermined period is generated as the second delay signal. Here, when the first delay signal has the first level, the second delay signal is captured and held in the latch and output as a noise removal signal, while the first delay signal has the second level. Stops taking in the second delay signal by the latch and outputs the content held as described above as a noise removal signal. At this time, if both the first and second delay signals have the second level, the contents held in the latch are inverted.

  According to this configuration, noise superimposed on the input signal is removed, and a noise removal signal including a pulse having the same pulse width as the input pulse is obtained.

  Further, according to such a configuration, even if noise having a voltage higher than the power supply voltage is superimposed on the power supply line or negative noise lower than the ground voltage is superimposed on the ground line, the noise is accompanied. The voltage fluctuation section of the second delay signal is not taken into the latch.

  Therefore, according to the present invention, it is difficult to be affected by the noise superimposed on the power supply line and the ground line, and the noise superimposed on the input signal can be removed without reducing the pulse width of the input signal. It becomes.

1 is a circuit diagram showing an example of a noise removal circuit 10 formed on a semiconductor chip as a semiconductor integrated device according to the present invention. 3 is a time chart showing the internal operation of the noise removal circuit 10. FIG. 3 is a circuit diagram showing a rising delay circuit 1. 3 is a circuit diagram showing a falling delay circuit 3. FIG. 3 is a time chart showing a noise removal operation in the noise removal circuit 10. It is a time chart which shows the internal waveform of the noise removal circuit 10 when noise is superimposed on the power supply line VL. It is a time chart which shows the internal waveform of the noise removal circuit 10 when noise is superimposed on the ground line GL. 3 is a circuit diagram showing another example of the noise removal circuit 10. FIG. It is a time chart which shows the internal operation | movement of the noise removal circuit 10 shown in FIG.

  The present invention generates the first delayed signal (y, g) by delaying only one of the rising edge portion and the falling edge portion of the input signal for a predetermined period (TQ). A second delay signal (h, d) is generated by delaying only the other edge portion of the rising edge portion and the falling edge portion in one delay signal for a predetermined period. Here, only when the first delay signal has the first level, the second delay signal is captured and held and output as a noise removal signal, whereas when the first delay signal has the second level, the second delay signal has the second level. 2 The capture of the delayed signal is stopped, and the content held as described above is output as a noise removal signal (5, 8). At this time, if both the first and second delay signals have the second level, the held contents are inverted (4, 7).

  FIG. 1 is a circuit diagram showing a noise removing circuit 10 formed on a semiconductor chip as a semiconductor integrated device according to the present invention.

  In FIG. 1, a rising delay circuit 1 has a signal level from a logic level “0” to “1” with respect to a binary input signal having a logic level “1” or “0”. A first delay signal y is generated by delaying only a section (hereinafter referred to as a rising edge portion) transitioning to a corresponding level by a delay period TQ as shown in FIG.

  FIG. 3 is a circuit diagram showing an example of the internal configuration of the rising delay circuit 1.

  As shown in FIG. 3, this rising delay circuit 1 includes an inverter 11, a p-channel MOS (Metal Oxide Semiconductor) type transistor 12 as a first switching element, and an n-channel MOS type as a second switching element. It comprises a transistor 13, a resistor 14 and a capacitor 15. The inverter 11 supplies a signal obtained by inverting the logic level of the input signal to the gate terminals of the transistors 12 and 13. The power supply voltage VDD corresponding to the logic level “1” is applied to the source terminal of the transistor 12 via the power supply line VL, and one end of the resistor 14 is connected to the drain terminal. The other end of the resistor 14 is connected to the drain terminal of the transistor 13 via the output line L1. The ground voltage GND is applied to the source terminal of the transistor 13 via the ground line GL. In addition, one end of a capacitor 15 is connected to the output line L1, and a ground voltage GND is applied to the other end of the capacitor 15 via a ground line GL.

  In the configuration shown in FIG. 3, first, in a section where the signal level of the input signal transitions from a level corresponding to the logic level “1” to a level corresponding to the logic level “0” (hereinafter referred to as a falling edge portion), As the transistor 13 transitions from the off state to the on state, the ground voltage GND corresponding to the logic level “0” is applied to the output line L1. Therefore, during this period, as shown in FIG. 2, the delay signal y having the falling edge portion that transitions from the logic level “1” to the logic level “0” at substantially the same timing as the input signal is transferred to the buffer 2 via the output line L1. Is sent out. On the other hand, at the rising edge portion of the input signal, the transistor 12 transitions from the off state to the on state, so that the power supply voltage VDD corresponding to the logic level “1” is passed through the transistor 12 to the output line L1 via the resistor 14. Applied. However, the voltage on the output line L1 gradually rises with time and reaches the power supply voltage VDD by the CR integration circuit including the capacitor 15 connected to the output line L1 and the resistor 14 described above. Therefore, for the rising edge portion in the input signal, a delay signal y having a rising edge portion delayed by a delay period TQ as shown in FIG. 2 is generated, and this is sent to the buffer 2 via the output line L1. The However, when the period during which the power supply voltage VDD is applied to the output line L1 via the resistor 14 is shorter than the delay period TQ, the voltage on the output line L1 is used to determine “0” or “1” of the logic element. At this time, the delay signal y having the logic level “0” is sent to the buffer 2 via the output line L1. That is, when the pulse width of the pulse of the logic level “1” by the input signal is narrower than the delay period TQ, the rising delay circuit 1 makes this pulse noise, and the signal from which the noise is removed, that is, the logic level “ The delay signal y of “0” is transmitted.

  The buffer 2 supplies the delay signal y supplied from the rising delay circuit 1 as a delay signal g to each of the falling delay circuit 3, the OR gate 4, and the terminal G of the D latch 5.

  The falling delay circuit 3 generates a second delay signal h in which only the falling edge portion of the delay signal g described above is delayed by the delay period TQ as shown in FIG. 2 and supplies this to the buffer 6.

  FIG. 4 is a circuit diagram showing an example of the internal configuration of the falling delay circuit 3.

  As shown in FIG. 4, the falling delay circuit 3 includes an inverter 31, a p-channel MOS transistor 32 as a third switching element, an n-channel MOS transistor 33 as a fourth switching element, and a resistor 34. And a capacitor 35. The inverter 31 supplies a signal obtained by inverting the logic level of the delay signal g to the gate terminals of the transistors 32 and 33. The power supply voltage VDD corresponding to the logic level “1” is applied to the source terminal of the transistor 32 via the power supply line VL, and one end of the resistor 34 is connected to the drain terminal via the output line L2. Yes. The other end of the resistor 34 is connected to the drain terminal of the transistor 33. The ground voltage GND is applied to the source terminal of the transistor 33 via the ground line GL. Further, one end of a capacitor 35 is connected to the output line L2, and the ground voltage GND is applied to the other end of the capacitor 35 via the ground line GL.

  According to the configuration shown in FIG. 4, in the so-called rising edge portion where the delay signal g transits from the logic level “0” to the logic level “1”, the transistor 32 transits from the off state to the on state. The power supply voltage VDD corresponding to “1” is applied to the output line L2. Therefore, during this time, as shown in FIG. 2, the delay signal h that transitions from the logic level “0” to the logic level “1” at substantially the same timing as the delay signal g is sent to the buffer 6 via the output line L2. On the other hand, in the so-called rising edge portion where the delay signal g transits from the logic level “1” to the logic level “0”, the transistor 33 transits from the off state to the on state. A ground voltage GND corresponding to "0" is applied to the output line L2 via the resistor 34. However, the voltage on the output line L2 gradually decreases with time and reaches the ground voltage GND by the CR circuit including the capacitor 35 connected to the output line L2 and the resistor 34 described above. Therefore, a delayed signal h having a falling edge portion which is delayed by a delay period TQ as shown in FIG. 2 is generated for the falling edge portion in the delay signal g, and this is generated by the buffer 6 via the output line L2. Is sent out.

  Therefore, the delay signal h generated through the rising delay circuit 1 and the falling delay circuit 3 as described above is obtained by delaying the input signal having the pulse width TP as shown in FIG. 2 by the delay period TQ. .

  The buffer 6 supplies the delay signal h supplied from the falling delay circuit 3 to each of the OR gate 4 and the data terminal D of the D latch 5 as the delay signal d.

  The OR gate 4 as a gate element calculates the logical sum of the delay signal g and the delay signal d and supplies the logical sum result to the reset terminal R of the D latch 5 as the reset signal rn. That is, as shown in FIG. 2, the OR gate 4 is a logic that prompts the D latch 5 to perform a reset operation only when the delay signal g is at the logic level “0” and the delay signal d is at the logic level “0”. The reset signal rn of level “0” is supplied to the reset terminal R of the D latch 5.

  The D latch 5 is a so-called level sensitive latch and takes in the delay signal d supplied to the data terminal D while the delay signal g supplied to the terminal G is at the logic level “1” as shown in FIG. This is output as a noise removal signal. When the delay signal g supplied to the terminal G transitions from the logic level “1” to “0”, the D latch 5 immediately before transitioning to the logic level “0” as shown in FIG. The acquired value is held and output as a noise removal signal. Note that when the reset signal rn of the logic level “0” that prompts the reset operation is supplied to the reset terminal R, the D latch 5 forcibly changes the held contents to the state of the logic level “0”. Reset. That is, as a result of such reset, the D latch 5 outputs a noise removal signal obtained by inverting the held contents from the logic level “1” to the logic level “0” as shown in FIG.

  Below, the effect by the noise removal circuit 10 which has an above-described structure is demonstrated.

  First, according to the operation of the start-up delay circuit 1 of the noise elimination circuit 10, as shown in FIG. 2, from the leading edge of a pulse (hereinafter referred to as an input pulse) by an input signal to the time when the delay period TQ elapses. A section becomes a noise removal section.

  Therefore, when an input signal having noise whose pulse width of the input pulse is smaller than the delay period TQ as shown in FIG. 5 is supplied, the noise removal circuit 10 has a logic level “0” from which this noise is removed. Outputs a noise removal signal. On the other hand, when the pulse width of the input pulse is longer than the delay period TQ, the noise removal circuit 10 outputs a noise removal signal representing a pulse having the same pulse width TP as the input pulse as shown in FIG. That is, in the noise elimination circuit 10, the rising delay circuit 1 performs delay processing of the delay time TQ on the rising edge portion of the input pulse, and the falling delay circuit 3 further applies the delay time TQ on the falling edge portion of the pulse. By performing the delay process, a noise removal signal having a pulse with the same pulse width TP as the input pulse is generated as shown in FIG.

  Therefore, the noise removal circuit 10 can remove noise without narrowing the pulse width of the input pulse. Therefore, for example, if the noise removal circuit 10 is used for a reset signal, even if noise or a reset pulse having a pulse width slightly longer than the delay time TQ is supplied, a subsequent FF to be reset can be detected. A reset pulse that can be reliably reset is generated.

  Further, in the noise removal circuit 10, by providing the OR gate 4 and the D latch 5, the resistance to the following noise superimposed on the power supply line VL or the ground line GL is enhanced.

  FIG. 6 is a time chart showing an example of the internal operation of the noise removal circuit 10 when noise having a peak voltage VP higher than the power supply voltage VDD is superimposed on the power supply line VL.

  At this time, as shown in FIG. 6, while the rising delay circuit 1 and the falling delay circuit 3 are outputting the delay signal y and the delay signal h representing the pulse having the peak voltage corresponding to the logic level “1”, respectively. In addition, when the above noise is superimposed on the power supply line VL, the peak voltage of the pulse temporarily increases. In the digital circuit, all voltages higher than the voltage corresponding to the logic level “1” are determined to be the logic level “1”, so that the subsequent circuit does not malfunction due to this noise.

  However, as shown in FIG. 6, while the rising delay circuit 1 and the falling delay circuit 3 output the low voltage (0 volt) delay signal y and the delay signal h corresponding to the logic level “0”, respectively. When the noise as described above is superimposed on the power supply line VL, a positive voltage is applied to the output line L2 via the capacitor 35 of the falling delay circuit 3 as shown in FIG. Therefore, during this period, the falling delay circuit 3 outputs a delay signal h including a noise pulse NP having a positive voltage as shown in FIG. During this time, the rising delay circuit 1 continues to send the delay signal y corresponding to the logic level “0” without being affected by the noise superimposed on the power supply line VL because the transistor 12 is in the OFF state. ing. Therefore, although the delay signal d corresponding to the logic level “1” is supplied to the data terminal D of the D latch 5 due to the influence of noise as described above, the delay signal y having the logic level “0” is supplied to the terminal G during this period. Since it is supplied, the delay signal d having the logic level “1” accompanying noise is not taken into the D latch 5.

  Therefore, the D latch 5 sends out a noise removal signal from which the noise pulse NP is removed as shown in FIG.

  FIG. 7 is a time chart showing an example of the internal operation of the noise removal circuit 10 when noise having a peak voltage VN lower than the ground voltage GND is superimposed on the ground line VL.

  At this time, as shown in FIG. 7, while the rising delay circuit 1 and the falling delay circuit 3 are outputting the low voltage delay signal y and the delay signal h corresponding to the logic level “0”, respectively, When such negative polarity noise is superimposed on the ground line GL, a negative voltage section corresponding to this noise also occurs in the delay signal y. In the digital circuit, all the voltages lower than the voltage corresponding to the logic level “0” are determined to be the logic level “0”. Therefore, the subsequent circuit does not malfunction due to this noise.

  However, as shown in FIG. 7, while the falling delay circuit 3 outputs the low voltage (0 volt) delay signal h corresponding to the logic level “0”, the negative noise as described above is generated by the ground line GL. Is superimposed on the falling delay circuit 3, the following problems occur. That is, in the falling delay circuit 3, when a negative voltage due to the above-described noise is applied to the ground line GL, the current temporarily flows in the current path of the capacitor 35, the output line L2, the resistor 34, and the transistor 33 as shown in FIG. Thus, a current flows and a positive voltage is generated on the output line L2. Therefore, during this period, the falling delay circuit 3 outputs a delay signal h including a noise pulse NP having a positive voltage as shown in FIG. However, during this time, the rising delay circuit 1 sends out the delay signal y corresponding to the logic level “0”, so that the delay signal d corresponding to the logic level “1” is converted into the D latch 5 by the influence of the noise described above. The delay signal y having the logic level “0” is supplied to the terminal G during this period, so that the delay signal d having the logic level “1” due to noise is taken into the D latch 5. There is nothing.

  Therefore, the D latch 5 sends out a noise removal signal from which the noise pulse NP is removed as shown in FIG.

  As described above, according to the noise removal circuit 10 having the configuration shown in FIG. 1, even if noise is superimposed on the power supply line VL or the ground line GL, it is superimposed on the input signal without being affected by the noise. It is possible to transmit a noise removal signal from which the noise is removed.

  In the above-described embodiment, the noise removal circuit for the input signal having the logic level 1 as the input signal, i.e., the so-called high level significant input signal has been described. However, the noise removal for the low level significant input signal has been described. A circuit can be similarly constructed.

  FIG. 8 is a circuit diagram showing another configuration of the noise removal circuit 10 made in view of such points.

  In FIG. 8, the falling delay circuit 36 generates a first delay signal y in which only the falling edge portion of the input signal is delayed by the delay period TQ as shown in FIG. 9, and supplies this to the buffer 2. The falling delay circuit 36 has the same internal configuration as the falling delay circuit 3 as shown in FIG.

  The buffer 2 supplies the delay signal y supplied from the falling delay circuit 36 as a delay signal g to each of the rising delay circuit 16, the NAND gate 7, and the terminal G of the D latch 8.

  The rising delay circuit 16 generates a second delay signal h in which only the rising edge portion in the delay signal g is delayed by the delay period TQ as shown in FIG. 9 and supplies this to the buffer 6. The rising delay circuit 16 has the same internal configuration as the rising delay circuit 1 as shown in FIG.

  The delay signal h generated through the falling delay circuit 36 and the rising delay circuit 16 as described above is obtained by delaying the input signal having the pulse width TP as shown in FIG. 9 by the delay period TQ.

  The buffer 6 supplies the delay signal h supplied from the rising delay circuit 16 as a delay signal d to each of the NAND gate 7 and the data terminal D of the D latch 8.

  The NAND gate 7 serving as a gate element obtains an inverted logical product of the delay signal g and the delay signal d and supplies the result to the set terminal S of the D latch 8 as a reset signal rn. That is, as shown in FIG. 9, the NAND gate 7 is a logic that prompts the D latch 8 to perform a set operation only when the delay signal g is a logic level “1” and the delay signal d is a logic level “1”. The set signal rn of level “0” is supplied to the set terminal S of the D latch 8.

  The D latch 8 is a so-called level sensitive latch, and takes in the delay signal d supplied to the data terminal D while the delay signal g supplied to the terminal G is at the logic level “0” as shown in FIG. This is output as a noise removal signal. Here, when the delay signal g supplied to the terminal G transits from the logic level “0” to “1”, the D latch 8 immediately before transiting to the logic level “1” as shown in FIG. The acquired value is held and output as a noise removal signal. When the set signal rn of the logic level “0” for prompting the set operation is supplied to the set terminal S, the D latch 8 forcibly changes the held contents to the state of the logic level “1”. set. That is, by such a setting operation, the D latch 8 outputs a noise removal signal obtained by inverting the held contents from the logic level “0” to the logic level “1” as shown in FIG.

  In the noise elimination circuit 10 having the configuration shown in FIG. 8, due to the operation of the falling delay circuit 36, as shown in FIG. 9, there is a section from the falling edge of the input pulse by the input signal to the time when the delay period TQ elapses. It becomes a noise elimination section. Further, according to the configuration shown in FIG. 8, as in the case where the configuration shown in FIG. 1 is adopted, a noise removal signal having a pulse having the same pulse width TP as the input pulse as shown in FIG. 9 is generated.

  In short, as shown in FIG. 1 or FIG. 8, the noise removal circuit according to the present invention includes a first delay circuit (1, 36), a second delay circuit (3, 16), and a latch (5, 8). ) And the gate element (4, 7).

  At this time, the first delay circuit (1, 36) has a rising edge portion and a falling edge portion of the input on / off signal having one of the first and second levels (logic levels 0, 1). A first delay signal (y) in which only one of them is delayed for a predetermined period is generated. The second delay circuit (3, 16) generates a second delay signal (h) obtained by delaying only the other of the rising edge portion and the falling edge portion of the first delay signal for a predetermined period. The latches (5, 8) capture and hold the second delay signal as long as the first delay signal has the first level (logic level 0 or 1) and output it as a noise removal signal, while As long as the delay signal has a second level different from the first level, the capture of the second delay signal is stopped, and the held content is output as a noise removal signal. When both the first and second delay signals have the second level, the gate (4, 7) controls the latch to set the held content to the second level.

1, 16 Rising delay circuit 3, 36 Falling delay circuit 4 OR gate 5, 8 D latch 7 NAND gate

Claims (7)

A noise removing circuit that performs a noise removing action on an input on / off signal having one of first and second levels,
A first delay circuit that generates a first delay signal obtained by delaying one of a rising edge portion and a falling edge portion in the input on / off signal over a predetermined period;
A second delay circuit for generating a second delay signal obtained by delaying the other of the rising edge portion and the falling edge portion of the first delay signal over the predetermined period;
As long as the first delay signal has the first level, the second delay signal is captured and held and output as a noise removal signal, while the second delay signal has the second level as long as the first delay signal has the second level. A latch that stops the capture and outputs the held content as the noise removal signal;
And a gate for controlling the latch to set the held content to the second level as long as both the first and second delay signals have the second level. The first level is higher than the second level;
The first delay circuit is a signal obtained by delaying only the rising edge portion in the input on / off signal for the predetermined period, and is the first delay signal.
2. The noise removal circuit according to claim 1, wherein the second delay circuit uses, as the second delay signal, a signal obtained by delaying only the falling edge portion of the first delay signal for the predetermined period. . The first delay circuit is turned on only when the input on / off signal has the first level and applies a power supply voltage to the first output line through a resistor, and the input on / off signal. The second switching element which is turned on only when the second level has the second level and applies the ground voltage to the first output line, and one terminal is connected to the first output line, and the other terminal And a first capacitor to which the ground voltage is applied,
The second delay circuit is turned on only when the first delay signal has the first level and applies the power supply voltage to the second output line, and the first delay signal A fourth switching element that is turned on only when having the second level and applies the ground voltage to the second output line via a resistor, and one terminal is connected to the second output line. A second capacitor to which the power supply voltage is applied to the other terminal,
The first delay circuit uses the voltage on the first output line as the first delay signal, and the second delay circuit uses the voltage on the second output line as the second delay signal. Item 3. A noise elimination circuit according to Item 2. The first level is lower than the second level;
The first delay circuit is a signal obtained by delaying only the falling edge portion of the input on / off signal over the predetermined period, as the first delay signal,
2. The noise removal circuit according to claim 1, wherein the second delay circuit uses, as the second delay signal, a signal obtained by delaying only the rising edge portion of the first delay signal for the predetermined period. The first delay circuit is turned on only when the input on / off signal has the second level and applies a power supply voltage to the first output line, and the input on / off signal is the first on / off signal. A second switching element that is turned on only when having a level and applies a ground voltage to the first output line through a resistor, and one terminal is connected to the first output line, and the other terminal And a first capacitor to which the power supply voltage is applied,
The second delay circuit is turned on only when the first delay signal has the second level and applies the power supply voltage to the second output line via a resistor, the third switching element, a fourth switching element 1 delayed signal to apply the ground voltage is only turned on before Symbol second output line when it has the first level, is one terminal connected to the second output line A second capacitor to which the ground voltage is applied to the other terminal,
The first delay circuit uses the voltage on the first output line as the first delay signal, and the second delay circuit uses the voltage on the second output line as the second delay signal. Item 5. The noise elimination circuit according to Item 4. A semiconductor integrated device in which a noise removal circuit that performs a noise removal action on an input on / off signal having one of first and second levels is formed,
The noise removing circuit is
A first delay circuit that generates a first delay signal obtained by delaying one of a rising edge portion and a falling edge portion in the input on / off signal over a predetermined period;
A second delay circuit for generating a second delay signal obtained by delaying the other of the rising edge portion and the falling edge portion of the first delay signal over the predetermined period;
Only when the first delay signal has the first level, the second delay signal is captured and held and output as a noise removal signal, while only when the first delay signal has the second level. A latch that stops capturing the second delay signal and outputs the held content as the noise removal signal;
And a gate for controlling the latch to set the held content to the second level when both the first and second delay signals have the second level. A noise removal method for applying a noise removal action to an input on / off signal having one of first and second levels,
While generating a first delayed signal in which one of the rising edge portion and the falling edge portion in the input on / off signal is delayed for a predetermined period, the rising edge portion and the falling edge portion in the first delayed signal are generated. A second delay signal obtained by delaying the other of the first delay period and the second delay period,
As long as the first delay signal has the first level, the second delay signal is captured and held and output as a noise removal signal, while the second delay signal has the second level as long as the first delay signal has the second level. To stop the capture and output the held content as the noise removal signal,
The noise removing method, wherein when both the first and second delay signals have the second level, the held content is set to the second level.

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