JPH03270313A - Noise eliminating circuit - Google Patents

Abstract

PURPOSE:To eliminate a noise component included in an input signal and to prevent the malfunction of an internal circuit by providing a coincidence detection means and a holding means outputting a held input signal only when the result of detection of the coincidence detection means shows discordance and outputting a delay signal when the result of detection of the coincidence detection means shows the coincidence on this noise eliminating circuit. CONSTITUTION:The noise eliminating circuit is provided with a coincidence detection means and a holding means outputting a held input signal only when the result of detection of the coincidence detection means shows discordance and outputting a delay signal when the result of detection of the coincidence detecting means shows the coincidence. That is, when the result of detection of the coincidence detecting means shows discordance, the held input signal before delay is outputted and when the result of detection of the coincidence detecting means shows the coincidence, the delay signal is outputted. Thus, when since the result of detection shows discordance and the held input signal before the delay is outputted, only noise components are eliminated. Thus, the malfunction of the internal circuit at a post-stage is prevented.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Example (1) Description of an example of the first invention ( 2) Description of other embodiments of the first invention (3) Description of one embodiment of the second invention Effects of the invention [Summary] Noise contained in the input signal provided at the signal input section between each circuit The purpose of the present invention is to provide a noise removal circuit that can remove noise components included in an input signal, and to provide a noise removal circuit that is shorter than the pulse width of the signal component of the input signal, and signal delay means for outputting a delayed signal by delaying the input signal by a delay time longer than the pulse width of the noise component in the input signal; and comparing the signal state of the input signal with the signal state of the delayed signal. , a coincidence detection means for detecting coincidence or mismatch of each signal state, and holding the input signal before delay for a period corresponding to the delay time of the signal delay means, and holding it only when the detection result of the coincidence detection means does not match. and holding means for outputting the delayed signal when the detection result of the coincidence detection means is a coincidence.

[Industrial application field]

The present invention relates to a noise removal circuit that is provided at a signal input section between circuits and removes noise contained in an input signal.

BACKGROUND ART In recent years, digital circuits such as microcomputers and memories are configured to operate by synchronizing timing in each circuit based on a reference pulse signal serving as a reference signal.

If spike noise is superimposed on such a reference pulse signal and input to various digital circuits, the spike noise will act as a reference signal and cause malfunctions. It is necessary to remove spike noise contained in the reference pulse signal input to the various circuits described above before inputting it, and a noise removal circuit for this purpose is required.

[Conventional technology]

Conventionally, this type of noise removal circuit is used in an address detection circuit (ATD circuit: Add+ess Ttr++5i).
jionDetcc+or) was shown in FIG. In the same figure, the ATD circuit has external signals A, A
1 is input, and the row address buffer 1.2 holds the input external signal A SA and the held external signal A O
This configuration includes a pulse generation circuit 3 that generates an ATD signal based on SA I, and outputs the ATD signal to an internal circuit 10 at a subsequent stage.

Based on the above configuration, the operation of the conventional ATD circuit will be explained with reference to FIG. FIG. 10 shows an operation timing chart of the conventional circuit. FIG. 10 (A) shows the input signal waveform in a normal case, and FIG. 10 (B) shows the input signal waveform in the case where spike noise is included.

When the input signal shown in FIG.
It will be generated as a D signal and output to the internal circuit 10.

In addition, when the human input signal shown in FIG.
A signal corresponding to the input signal at G is sent to the pulse generation circuit 3.
The signal is generated as an ATD signal and output. time t11
Since the input signal contains spike noise, the spike noise is removed based on a predetermined threshold.

However, if the spike noise exceeds this threshold level, the pulse generation circuit 3 treats it as a signal,
An ATD signal corresponding to the spike noise is output to the internal circuit.

[Problem to be solved by the invention]

Since the conventional ATD circuit is configured as described above, if a noise component is included at a level close to the signal component of the input signal (that is, signal strength equal to or higher than the threshold level), the normal signal component is detected. The problem is that spike noise is output to the subsequent internal circuit as the same input signal as the input signal, causing the internal circuit to malfunction.

The present invention was made to solve the above problems, and an object of the present invention is to propose a noise removal circuit that can remove noise components contained in an input signal.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the first invention.

In the figure, the noise removal circuit according to the first aspect of the present invention has a delay time that is shorter than the time corresponding to the pulse width of the signal component of the input signal and longer than the time corresponding to the pulse width of the noise component in the input signal. signal delay means for delaying the input signal and outputting a delayed signal; coincidence detection means for comparing the signal state of the input signal with the signal state of the delayed signal and detecting whether each signal state matches or mismatches; The input signal before the delay is held for a period corresponding to the delay time of the delay means, and the held input signal is output only when the detection result of the coincidence detection means is a mismatch, and when the detection result of the coincidence detection means is a match, the input signal is outputted. and a holding means for outputting the delayed signal.

Moreover, FIG. 2 shows a principle diagram of the second invention.

In the figure, the noise removal circuit according to the second aspect of the invention includes a signal edge detection means for detecting rising and falling signal edges of the signal components of the input signal, and a signal edge detection means for detecting the rising and falling signal edges of the signal components of the input signal, and a signal delay means for outputting a delayed signal by delaying the signal by a delay time shorter than the pulse width of the noise component in the input signal and longer than the time corresponding to the pulse width of the noise component in the input signal; and a signal delay means for delaying the signal before the rise of the input signal. an end adjacent portion invalidating means for invalidating and outputting the input signal to the signal delaying means during a period corresponding to the delay time and a period corresponding to the delay time of the signal delaying means after the fall of the input signal; compares the invalidated input signal with the delayed signal output from the signal delaying means and determines whether they match or not.
a coincidence detecting means for detecting a mismatch, and a coincidence detecting means for holding the input signal whose end adjacent portion before the delay is invalidated for a period corresponding to the delay time of the signal delaying means, and detecting the held input signal before the delay. and a holding means for outputting the delayed signal when the detection result of the coincidence detection means is a coincidence, and a holding means for outputting the delayed signal when the detection result of the coincidence detection means is a coincidence.

and the input signal, and based on the detection result, the input signal before delay is held for the delay time.

If the detection results do not match, the held input signal before delay is output, and if they match, the delayed signal is output. Therefore, if the input signal contains noise, the detection results do not match and the retained input signal before the delay is output, so only the noise component is removed, and the internal circuit of the subsequent stage prevent malfunction.

In the second invention, the rising and falling edges of the input signal are detected, and the punching force signal corresponding to the delay time of the signal delaying means is invalidated from each edge, and the portion adjacent to the edge is invalidated. By removing noise from the input signal in the same manner as in the first invention, it is possible to remove noise contained in all areas of the falling portion of the "L" level in the input signal.

[Effect]

In the first invention, the input signal is delayed by a predetermined delay time by the signal delay means, and the delayed signal [Embodiment] (1) Description of an embodiment of the first invention The first invention An example of this will be explained based on FIGS. 3 and 4. FIG. 3 shows a schematic overall configuration of an ATD circuit to which the circuit of this embodiment is connected, and FIG. 4 shows a logic circuit diagram of this embodiment.

In each of the above figures, the noise removal circuit according to this embodiment is based on the ATD output from the pulse generation circuit 3 of the ATD circuit.
a delay circuit 4 that delays the signal S1 by a delay time t; a coincidence circuit 7 that compares the ATD signal S1 with the delayed ATD signal S2 of the delay circuit 4 to detect a match; and the delay circuit 4.
A timing adjustment circuit 8 adjusts the delayed ATD signal S2 to synchronize it with the detection signal S5 of the coincidence circuit 7, and adjusts the adjusted ATD signal S3 output from the timing adjustment circuit 8 to the coincidence/mismatch detection signal of the coincidence circuit 7. This configuration includes a latch circuit 9 that holds the adjusted 5 ATD signal S3 based on S SS and outputs the held adjustment 5 ATD signal S3.

Each component of the circuit of this embodiment will be explained in more detail with reference to FIG.

In the figure, the delay circuit 4 is formed by connecting an even number of N07 circuits in series, and has a configuration in which the sum of delays caused by each N07 circuit is the delay time t.

The minus number circuit 7 is an EX-NOR circuit 71 that calculates the exclusive NOR of the ATD signal S1 and the delayed ATD signal S2.
and NOT which inverts the output of the EX-NOR circuit 71.
A circuit 72 is provided, and the EX-NOR circuit 71 and NOT
This is a configuration 5 in which a match/mismatch detection signal S 1S is output from the circuit 72.

The timing adjustment circuit 8 is formed of an N07 circuit and is configured to synchronize by adjusting a time (hereinafter referred to as adjustment time 1) corresponding to the signal delay time by the NOT circuit 72 of the minus number circuit 7.

The latch circuit 9 adjusts the timing adjustment circuit 8 based on the coincidence detection signal S5 output from the minus number circuit 7.
NMOS 91 that controls the input/output of the signal S3, and NMOS 91 that controls the input/output of the adjusted ATD signal S3 held on the drain side of the NMOS 91 based on the mismatch detection signal S4.
The configuration includes a MOS 92.

Next, the operation of this embodiment based on the above configuration will be explained with reference to FIG. FIG. 5 shows an operation timing chart of the circuit of this embodiment. In the figure, an ATD signal S1 is inputted from a pulse generation circuit to a delay circuit 4 and a minus number circuit 7, respectively. The delay circuit 4 delays the ATD signal S1 by delay time 1 (1=1=...t17) and outputs the delayed ATD signal S2 to the matching circuit 7.

The ATD signal S1 and the delayed ATD signal S2 are compared in the above-mentioned number circuit 7 to obtain an exclusive NOR condition, and when they do not match, a mismatch detection signal S4 is output, and when they match, a match detection signal S5 is output. Output. This - number circuit 7
is A in the interval of time t3, t8, t.
It is determined that the TD signal S1 and the delayed 6 ATD signal S2 are both at "L" level and match, and the coincidence detection signal S5 is outputted as "H", and the mismatch detection signal S4 is outputted as "L". Also, time 1
In the section 5613ゝ14 of Sl S11, both the ATD signal Sl and the delayed ATD signal S2 match at the "H" level, and as in the above case, the coincidence detection signal S5 is set to "H" and the mismatch detection signal S4 is set to "H". Output as "L". Furthermore, in the interval between 4712 and t15, since the signal level of the time 1.1.1 ATD signal S is different from that of the 1-delayed ATD signal S2, the coincidence detection signal S5 is set to "L", and the mismatch detection signal S4 is set to "L". Output as "H".

Each of the above mismatch and match detection signals S SS and 5 Adjustment ATD signal S3 is input to latch circuit 9.

This latch circuit 9, in the interval of time t-t3,
NMOS 92 by “L” level mismatch detection signal S4
turns off, and NMOS 91 turns on due to the "H" level match detection signal S5, and goes "L".
The level adjustment ATD signal S3 is output as an "L" level output signal.

In this state, the output of the NOT circuit 93 is at the "H" level, and this signal is output to the gate terminal of the PMO 394.
The PMOS 94 is turned off, and the connection point P is held at the 'L' level, which is the signal level of the adjusted ATD signal S3.

Also, in the section of time 1.1.1 5613, t14, NMOS 91 is in the ON state in the same way as above,
The NMOS 92 is turned off and outputs the "H" level adjusted ATD signal S3 as an "H" level output signal. In this state, an "H" level signal is held at the connection point P.

Furthermore, times 1, 17, t12, t, each of which has elapsed by delay time t from the above time 1.1.1 3 6 11゛t14,
15, the NMOS 91 is turned off by the “L” level match signal S5,
The NMOS 92 is turned on by the "H" level mismatch signal S4, and the signal level signal held at the connection point P before the delay time t is output. That is,
From time t4 to time t5 and from time t11 to time t12
, the “L” held at the connection point P
A level signal is output as an output signal S6.

Further, when the transition is from time t6 to time t7 and from time t14 to time t15, the "H" level signal held at the connection point P is output as the output signal S6.

Next, as shown in FIG. 5, if the ATD signal includes spike noise N1 at time t9,
This spike noise N1 is removed as follows. This spike noise N1 also appears in the delayed ATD signal S as a spike noise N2 at time t10, and the matched circuit 7 compares the ATD signal including each spike noise with the delayed ATD signal S2 to detect coincidence or mismatch.

This matching circuit 7 detects that at time 1.1, there is no signal that contains spike noise N SN of the level Hl10.
42 Outputs the coincidence detection signal S4 and at the same time at time t10't
At this point, a coincidence detection signal S5 containing spike noise N51, 1 N5□ of "L@ level" is output.

At the time t9, the spike noise N41 exists at the "H" level in the mismatch detection signal S14, and the match detection signal S5 maintains the "H" level.
Both NMOs 891 and 92 are in the ON state, but adjustment A
Since the TD signal S3 is at the "L" level, the output signal S6 at the "L" level is output.

Furthermore, since the mismatch detection signal S4 maintains the "L" level at the time when the "L" level spike noise N51 included in the coincidence detection signal S5 at the time t1o is input, each NMO 391°92 Both are in the OFF state, and an "L" level output signal S is output. Since the coincidence detection signal S5 maintains the "H" level at the time when the "H" level spike noise N42 included in the mismatch detection signal S4 at the time tlo is input, each NMOS 91.92 is Although it is in the ON state, since the adjusted ATD signal S3 is at the "L" level, an output signal at the "L" level is output.

Next, since the mismatch detection signal S4 maintains the "L" level at the time when the spike noise N52 of the °L" level included in the coincidence detection signal S5 at time t is input, each NMOS 91゜92 are both O
It becomes FF state and "H" included in the adjusted ATD signal S3
Level spike noise N is not output. Therefore,
The output signal S6 is output as an "L" level, and at this point, the spike noise N3 included in the adjusted ATD signal S is removed.

(2) Description of another embodiment of the first invention FIG. 6 shows a configuration diagram when the embodiment circuit shown in FIG. 4 is configured as a 0MO3 circuit. In the same figure, the circuit of this embodiment operates in the same manner as in the case described in FIG. 4, and the adjustment ATD
Remove spike noise N3 included in the signal.

Note that in each of the above embodiments, the delay circuit 4 is
Although the configuration includes an R circuit 71 and a NOT circuit 72,
It is also possible to adopt a configuration including an AND circuit and an N07 circuit that inverts the output of this circuit. In this case,
The output of the AND circuit becomes the coincidence detection signal S5, and the output of the N07 circuit becomes the mismatch detection signal S4, each of which is output to the latch circuit.

Further, in each of the above embodiments, the timing adjustment circuit 8 is provided, but the timing adjustment circuit may be omitted as long as each signal is synchronized in the latch circuit.

Further, although the above embodiments have been described with reference to the case where the present invention is applied to an ATD circuit, the present invention can also be applied to other input sections, sense amplifiers, etc.

(3) Description of one embodiment of the second invention Hereinafter, one embodiment of the second invention will be described based on FIG. 7.

FIG. 7 shows an overall schematic configuration diagram of an ATD circuit to which the circuit of this embodiment is connected.

In the figure, the noise removal circuit according to the present embodiment receives the ATD signal S1 outputted from the pulse generation circuit 3 of the ATD circuit as in the embodiment of the first invention described in FIG. 4. It includes a number circuit 7, a timing adjustment circuit 8, and a latch circuit 9, and in addition to the above configuration, it also includes a signal edge detection circuit 5 and an edge adjacent invalidation circuit 6 connected to the input side of the delay circuit 4. It is the composition.

The signal edge detection circuit 5 is an ATD of the pulse generation circuit 3.
The configuration is such that the rising edge and falling edge of the signal S are detected and an edge detection signal 511ASS1.8 is output.

The edge adjacent portion invalidating circuit 6 receives the edge detection signal $11AS.
S11B is input, a period corresponding to the delay time t of the delay circuit 4 before the rise of the ATD signal S1 (hatched portion in FIG. 8), and a period corresponding to the delay time t after the fall of the ATD signal S1 ( Each ATD signal S1 in the hatched part in FIG.
13 is output to the delay circuit 4 and the minus number circuit 7. The time tn from the input of the ATD signal Sl to the output of the ATD signal S13 is the time required for the arithmetic operation of the end adjacent portion invalidation circuit 6.

Next, the operation of this embodiment based on the above configuration will be explained with reference to FIG. FIG. 8 shows an operation timing chart of the circuit of this embodiment.

In the same figure, when an ATD signal S1 having only normal signal components is input, and when an ATD signal S1 having spike noise N at a portion other than the end delay time of the ATD signal signal S portion is input,
When a signal is input, the device operates in the same manner as the embodiment of the first invention, and the spike noise N1 is removed.

Furthermore, when the ATD signal S1 in which spike noises N11 and N12 are present within a delay time from the signal end of the signal component of the ATD signal S1 is input, it represents the rising part of the normal signal component of the ATD signal S1. The edge detection signal S 1 and the edge detection signal S 2 representing the falling portion of the rising edge 1A are detected by the signal edge detection circuit 5 . This signal edge detection circuit 5 compares the duration of the signal rising with a preset time,
Based on this comparison result, it is determined whether the signal end is a normal signal component or a spike noise signal end.

"edge detection signal representing the signal edge of this regular signal component"
11, 5118 is input to the end adjacent portion invalidating circuit 6,
The ATD signal S1 is invalidated during a period corresponding to the delay time before the rising edge of the edge detection signal S (hatched portion in FIG. 8) with reference to the edge detection signal S. AT at this point
The spike noises N and N included in the D signal S are removed.

II 12 In the above embodiment, the configuration is such that it is connected within the ATD circuit, but it may also be configured to be connected to another input section, a digital circuit such as a sense amplifier, or an analog circuit that requires a synchronizing signal.

〔Effect of the invention〕

As explained above, in the first invention, the input signal is delayed by a predetermined delay time by the signal delay means, the coincidence of the delayed signal and the input signal is detected, and when the detection result is a mismatch, outputs the input signal held before the delay, and also outputs the delayed signal if there is a match, so only the noise component is removed, preventing malfunction of the internal circuit in the subsequent stage. It has the effect of

In the second invention, the rising and falling edges of the input signal are detected, and a high-power signal corresponding to the delay time of the signal delaying means is invalidated from each edge, and the portion adjacent to the edge is invalidated. By removing noise from the input signal in the same way as in the first invention, it is possible to remove noise contained in all regions of the falling portion of the "L" level in the input signal.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the first invention, FIG. 2 is an explanatory diagram of the principle of the second invention, and FIG. 3 is an overall schematic configuration diagram of an ATD circuit to which an embodiment of the circuit of the first invention is connected. 4 is a block diagram of an embodiment of the first invention, FIG. 5 is an operation timing chart of the embodiment circuit shown in FIG. 4, FIG. 6 is a MO3 circuit block diagram of the embodiment circuit shown in FIG. 4, FIG. 7 is an overall schematic configuration diagram of an ATD circuit to which an embodiment circuit of the second invention is connected. FIG. 8 is an operation timing chart of the embodiment circuit shown in FIG. 7. FIG. 9 is an overall schematic configuration diagram of a conventional ATD circuit. 10 shows an operation timing chart of the circuit shown in FIG. 9. 1.2...Address buffer 3...Pulse generation circuit 4...Delay circuit 5...Signal end detection circuit 6...End adjacent portion invalidating circuit 7...-Number circuit 8...・Timing adjustment circuit 9...Latch circuit 10...Internal circuit

Claims (1)

[Claims] 1. The input signal is delayed by a delay time shorter than the time equivalent to the pulse width of the signal component of the input signal and longer than the time equivalent to the pulse width of the noise component in the input signal. a signal delay means for outputting a delayed signal; a coincidence detection means for comparing the signal state of the input signal with the signal state of the delayed signal and detecting coincidence or mismatch of each signal state; and a signal delay means corresponding to the delay time of the signal delay means. The input signal before the delay is held while the input signal is delayed, the held input signal is output only when the detection result of the coincidence detection means is a mismatch, and the delayed signal is outputted when the detection result of the coincidence detection means is a coincidence. A noise removal circuit comprising: a holding means. 2. Signal edge detection means for detecting rising and falling signal edges in the signal component of the input signal; and a signal edge detection means that is shorter than the pulse width of the signal component of the input signal and that is a noise component in the input signal. signal delay means for outputting a delayed signal by delaying the signal by a delay time longer than the time corresponding to the pulse width of the input signal; edge-adjacent section invalidating means for invalidating the input signal for a period corresponding to the delay time of the signal delaying means after the signal has fallen and outputting it to the signal delaying means; a coincidence detection means for comparing the delayed signal outputted from the means and detecting coincidence or mismatch; and a coincidence detecting means for detecting coincidence or mismatch by comparing with the delayed signal output from the means, and holding the input signal whose end adjacent portion before delay is invalidated for a period corresponding to the delay time of the signal delaying means. and holding means for outputting the held undelayed input signal only when the detection result of the coincidence detection means is a mismatch, and outputting the delayed signal when the detection result of the coincidence detection means is a coincidence. A noise removal circuit featuring: