JP5879925B2 - Semiconductor device and power consumption control method for semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a power consumption control method for the semiconductor device.

  As a means for reducing power consumption in a semiconductor device, a method of giving an instruction not to supply a clock to a processing circuit that does not operate is used. As another means for reducing power consumption, a method of stopping a clock supplied to the processing circuit according to the value of the enable signal input to the processing circuit is used.

  FIG. 9 is an explanatory diagram of conventional power saving control. For example, as shown in FIG. 9, the clock is supplied to the processing circuit 305 via the inverter 301, the clock gating circuit 302, and the inverters 303 and 304. A clock control signal is input from the clock control unit 300 to the clock gating circuit 302. The clock control unit 300 is realized by firmware or software, for example. For example, the clock control unit 300 identifies the processing circuit 305 that does not operate, and sets the clock control signal to the clock gating circuit 302 corresponding to the processing circuit 305 that does not operate to a low level. Thereby, the supply of the clock to the processing circuit 305 can be stopped.

  The header processing unit included in the packet transfer apparatus includes a plurality of packet processing circuits that perform packet processing. The circuit number determination circuit monitors the number of lines that perform communication and the amount of traffic that is input from the lines, and operates the packet processing circuit. It has been proposed to realize the power saving of the packet transfer apparatus by determining the presence or absence of the packet and shutting off the power and clock of the unnecessary packet processing circuit based on the determination result.

  Further, the communication interface circuit extracts packet data from the received signal, the communication interface control circuit generates and outputs an interrupt signal, and the network processor analyzes the packet data, and based on the analysis result, the packet data is hosted. When the interrupt control circuit receives an interrupt signal from the network processor, the interrupt control circuit activates the host processor when the interrupt signal is received from the network processor. In response to this, it has been proposed to execute packet data reception processing.

JP 2009-111707 A JP 2008-270918 A

  As described above, in the conventional means for reducing power consumption, the clock control circuit controls the supply and stop of the clock to the processing circuit. However, the means using the clock control circuit is effective in reducing power consumption for each large processing circuit, but it becomes difficult to apply to reducing power consumption as the processing circuit scale decreases.

  Specifically, when the system specifications of the semiconductor device are given at the time of designing the semiconductor device, the detailed design of the processing circuit with a small circuit scale in the processing circuit with a large circuit scale has not been completed. Therefore, at this stage, it is practically impossible to design the control means for supplying the clock for each small processing circuit. On the other hand, designing the clock supply control means after the detailed design of the small processing circuit is completed is a circuit design in two stages and cannot be employed. Also, if the clock control unit realized by firmware or software controls the clock supply for each small processing circuit, the processing in firmware or software may become complicated, and some errors may occur due to clock control. Becomes higher.

  In addition, when the clock supplied to the processing circuit is stopped in accordance with the value of the enable signal input to the processing circuit, the supply of the clock to the processing circuit can be stopped. However, in a clock tree that is a circuit that supplies a clock, it is not possible to stop the supply of the clock to the part corresponding to the processing circuit in which the supply of the clock is stopped in the clock tree. For this reason, the power consumption in the clock tree itself cannot be reduced.

  According to one aspect of the present invention, a semiconductor device capable of reducing power consumption by controlling clock supply is provided.

  According to one aspect, the disclosed semiconductor device includes a control unit and a clock supply unit. The control unit extracts, from the received packet, function information that is information recorded in the packet and is information that specifies processing to be performed. The clock supply unit performs processing to be specified by the extracted function information on the basis of the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when processing is performed. The clock is supplied to the processing circuit to which the clock is to be supplied when performing the above.

  According to one aspect of the disclosed semiconductor device, power supply can be reduced by controlling clock supply.

It is a figure which shows an example of a semiconductor device. It is a figure which shows an example of a processing circuit block. It is a figure which shows a part of processing circuit block. It is a figure which shows an example of a packet. It is explanatory drawing of the process in a power saving control part. It is explanatory drawing of the process in a power saving control part. It is explanatory drawing of power saving control. It is a figure which shows a power saving control sequence. It is explanatory drawing of the conventional power saving control.

  FIG. 1 is a diagram illustrating an example of a semiconductor device.

  The semiconductor device 100 includes at least one processing circuit block. Specifically, the semiconductor device 100 includes a processing circuit block 101 and a plurality of processing circuit blocks 102.

  The processing circuit block 101 is a circuit that is not included in the other processing circuit blocks 102. The processing circuit block 101 is an upper processing circuit block, and includes, for example, a processing circuit block 103 and a plurality of processing circuit blocks 104. In the processing circuit block 101, the packet 200 is actually received and processed by the lower processing circuit block 103 and used for clock control.

  The processing circuit block 102 is a circuit that is not included in the upper processing circuit block 101. The processing circuit block 102 receives and processes the packet 200, and generates and outputs a new packet 200 based on the processing result. Further, the processing circuit block 102 analyzes the packet 200 received by itself, and performs clock control of the own circuit, in other words, the processing circuit block 102 based on the analysis result. The processing circuit block 102 may include an analysis processing circuit block.

  The processing circuit block 103 is a circuit included in the upper processing circuit block 101. The processing circuit block 103 receives and processes the packet 200, and generates and outputs a new packet 200 based on the processing result. Further, the processing circuit block 103 analyzes the packet 200 received by itself, and performs clock control of the own circuit, in other words, the processing circuit block 103 based on the analysis result. The processing circuit block 103 may include an analysis processing circuit block.

  The processing circuit block 104 is a circuit included in the upper processing circuit block 101. The processing circuit block 104 does not receive the packet 200, but receives and processes the processing result of the packet 200 from the processing circuit block 103. Further, the processing circuit block 104 receives the analysis result of the packet 200 from the processing circuit block 103 or receives various signals for clock control, and performs clock control of the processing circuit block 104.

  Signals are transmitted and received by the packet 200 between the processing circuit block 101 or the processing circuit block 103 and the processing circuit block 102 and between the processing circuit block 102 and the processing circuit block 102. As described above, the processing circuit blocks 102 and 103 perform their own clock control based on the analysis result of the packet 200 received by the processing circuit blocks 102 and 103. Therefore, the packet 200 instructs the processing circuit blocks 102 and 103 that are the recipients of the packet 200 to supply a clock. Further, the packet 200 can include data to be processed.

  When distinguishing the processing circuit blocks 101 to 103, for example, the processing circuit block # 1 is referred to. When distinguishing the packet 200, it is referred to as packet # 1, for example.

  FIG. 2 is a diagram illustrating an example of a processing circuit block.

  The processing circuit block 103 includes a clock gating circuit 1, latch circuits 2 and 3, an internal processing circuit 4, and a power saving control unit 7. The internal processing circuit 4 includes a clock tree unit 5 and a processing circuit group 6. The power saving control unit 7 includes an OR gate circuit 8, a clock gating circuit 9, and an analysis control circuit 10. The processing circuit group 6 includes a plurality of processing circuits 61.

  The clock is input to the clock gating circuit 1, the latch circuit 3, the clock gating circuit 9 of the power saving control unit 7, and the clock tree unit 5. The clock is supplied from a clock supply source of the semiconductor device 100. The clock control signal is input to the clock gating circuit 1 and the latch circuit 3. The packet 200 is input to the latch circuit 2. The clock control signal and the packet 200 are transmitted and input from, for example, the processing circuit block 102 or 103 preceding the processing circuit block 103. As will be described later with reference to FIG. 4A, the packet 200 is transmitted and input in synchronization with the clock control signal.

  Therefore, the clock is always supplied to the clock gating circuit 1, the latch circuit 3, and the clock gating circuit 9. On the other hand, the clock is supplied to the latch circuit 2, the processing circuit group 6, and the analysis control circuit 10 only when the packet 200 and the clock control signal are received. Thereby, when the packet 200 is not received, the clock is supplied only to the circuit that processes the presence or absence of reception of the clock control signal and the packet 200, in other words, the minimum necessary circuit.

  A clock is always supplied to a part of the clock tree unit 5, specifically, only an inverter array 51 of FIG. On the other hand, the clock tree unit 5 other than the inverter array 51 is supplied with a clock only to the circuit that processes the packet 200 according to the control signal from the analysis control circuit 10 only when the packet 200 and the clock control signal are received. The Thereby, when the packet 200 is received, the clock is supplied only to the circuit that processes the packet 200 from the time when the packet 200 is received, in other words, the processing circuit 61 that should supply the clock when performing the processing. Is done.

  As the clock gating circuit 1, for example, a 2-input AND gate circuit is used. The clock gating circuit 1 receives a high-level clock control signal while the clock is supplied. As a result, the clock gating circuit 1 is opened, and the clock is supplied from the clock gating circuit 1 to the latch circuit 2.

  As a result, the latch circuit 2 receives the packet 200 whose transmission is started together with the clock control signal in synchronization with the clock. The latch circuit 2 outputs the received packet 200 to the processing circuit group 6 of the internal processing circuit 4 and the analysis control circuit 10 of the power saving control unit 7.

  The latch circuit 3 receives a high-level clock control signal while the clock is supplied. Accordingly, the latch circuit 3 outputs the received clock control signal to the OR gate circuit 8 of the power saving control unit 7.

  The OR gate circuit 8 receives the high level clock control signal and outputs the high level control signal to the clock gating circuit 9. At this time, a low-level control signal is input to the OR gate circuit 8 from the analysis control circuit 10 as will be described later.

  The clock gating circuit 9 receives a high-level control signal while the clock is supplied, and outputs the clock to the analysis control circuit 10. As a result, the analysis control circuit 10 receives the packet 200 in synchronization with the clock from which the supply is started, and starts analyzing the received packet 200. Before the clock from the clock gating circuit 9 is supplied, the analysis control circuit 10 consumes little power.

  The analysis control circuit 10 is a control unit that controls supply of a clock to the processing circuit group 6 by the clock tree unit 5. The analysis control circuit 10 analyzes the header of the packet 200 received from the latch circuit 2, performs control determination in the clock tree unit 5 based on the analysis result, and transfers to the clock tree unit 5 based on the determination result. The control instruction is performed.

  Specifically, the analysis control circuit 10 extracts function information by extracting a plurality of bits at a predetermined position of the header of the received packet 200 as analysis processing. The function information is information recorded in the packet 200 and is information that specifies a process to be functioned.

  The analysis control circuit 10 specifies the processing circuit 61 to which the clock is to be supplied based on the function information and the circuit information as the control determination process. The circuit information is information for specifying a processing circuit to which a clock is to be supplied when processing is performed. The processing circuit 61 to which a clock is to be supplied is a circuit to which a clock is to be supplied when performing the function to be performed specified by the function information.

  The circuit information is held in advance by the analysis control circuit 10. The analysis control circuit 10 holds processing and a processing circuit to which a clock is to be supplied as circuit information in association with each other. The analysis control circuit 10 generates a control signal for controlling the clock tree unit 5 based on the extracted function information and the held circuit information, and inputs the control signal to the clock tree unit 5.

  Specifically, the analysis control circuit 10 holds circuit information using, for example, a first holding unit and a second holding unit.

  The first holding unit holds processing to be performed in association with function information, in other words, information indicating the type of the packet 200 or information indicating the type of instruction. The first holding unit is, for example, a clock control determination table 12 described later with reference to FIG. As will be described later, the information indicating the type of the packet 200 or the information indicating the type of the command is, for example, a packet type ID. The process to be performed indicates, for example, a process to be performed when a clock control determination, in other words, a packet 200 having a corresponding packet type ID is received.

  The second holding unit holds the processing circuit 61 to be supplied with a clock when performing the process to be functioned in association with the process to be functioned. The second holding unit is, for example, a clock gating ID determination table 13 described later with reference to FIG. As will be described later, the process to be performed is the type of process. The processing circuit 61 to be supplied with the clock is actually held as the ID of the clock gating circuits 52 and 54 of the clock tree unit 5 to be opened to supply the clock, in other words, the gating ID. In other words, the second holding unit holds the gating IDs of the clock gating circuits 52 and 54 to be opened in order to supply the clock to the processing circuit 61 to which the clock is supplied in association with the process to be functioned. .

  The circuit information holding means in the analysis control circuit 10 is not limited to the first holding unit and the second holding unit. In the analysis control circuit 10, circuit information can be held by various holding means. For example, instead of the first holding unit and the second holding unit, a holding unit that obtains a process to be functioned based on function information and obtains a processing circuit 61 to supply a clock based on the process to be functioned is used. Anyway. In addition, holding means for obtaining the processing circuit 61 to which the clock should be supplied based on the function information may be used.

  The analysis control circuit 10 generates a control instruction based on the specified processing circuit 61 as a control instruction, and inputs the generated control instruction to the clock tree unit 5. The control instruction is a control signal for controlling the clock tree unit 5. In other words, the analysis control circuit 10 generates and outputs a control instruction corresponding to each of the clock gating circuits 52 and 54, and inputs each of the generated control instructions to each of the clock gating circuits 52 and 54. . Thereby, each of the clock gating circuits 52 and 54 is individually controlled. As a result, the clock can be supplied only to the processing circuit 61 to which the clock is to be supplied, and the power consumption can be reduced. Before the clock from the clock gating circuit 9 is supplied, the processing circuit group 6 consumes little power.

  The analysis control circuit 10 inputs a high-level control signal to the OR gate circuit 8 together with the output of the control instruction corresponding to each of the clock gating circuits 52 and 54.

  The clock tree unit 5 is a clock supply unit that supplies a clock to the processing circuit group 6. The clock tree unit 5 receives the control instruction from the analysis control circuit 10 and supplies the clock to the processing circuit 61 to which the clock is to be supplied, in other words, the specified processing circuit 61. As a result, the specified processing circuit 61 processes the packet 200 received from the latch circuit 2. The identified processing circuit 61 transmits a processing completion notification signal to the analysis control circuit 10.

  The analysis control circuit 10 receives the process completion notification signal from the processing circuit 61 and makes a process completion determination. Specifically, the analysis control circuit 10 receives the processing completion notification signal from the processing circuit 61 and inputs a low-level control signal to the OR gate circuit 8.

  At this time, the analysis control circuit 10 receives the processing completion notification signal from the processing circuit 61, generates a control instruction corresponding to each of the clock gating circuits 52 and 54, and outputs a clock to the processing circuit 61. May be stopped. Thereby, the supply of the clock to the processing circuit 61 can be stopped at an earlier timing. As a result, in the clock tree unit 5, the clock gating circuits 52 and 54 corresponding to the processing circuit 61 are closed, and as a result, all the clock gating circuits 52 and 54 are closed. Therefore, in the clock tree unit 5, only the inverter train 51 consumes power when the clock is supplied.

  On the other hand, when the transmission of the clock control signal is stopped, the clock control signal is set to the low level as shown in FIG. In other words, the clock gating circuit 1 receives the low level of the clock control signal. As a result, the clock gating circuit 1 is closed and the clock is not supplied from the clock gating circuit 1 to the latch circuit 2. As a result, the latch circuit 2 does not output the packet 200 to the processing circuit group 6 and the analysis control circuit 10. Thereby, the power consumption in the processing circuit group 6 can be reduced.

  The latch circuit 3 receives the low level of the clock control signal and outputs the received low level clock control signal to the OR gate circuit 8 of the power saving control unit 7. As a result, the OR gate circuit 8 outputs a low level signal to the clock gating circuit 9. As a result, the clock gating circuit 9 does not output a clock to the analysis control circuit 10. Thereby, the power consumption control unit 7, in other words, the power consumption in the analysis control circuit 10 can be reduced.

  The analysis control circuit 10 does not generate a control instruction when the packet 200 and the clock are not supplied. Specifically, the analysis control circuit 10 inputs a high level control signal to all the clock gating circuits 52 and 54. As a result, in the clock tree unit 5, all the clock gating circuits 52 and 54 are closed. Therefore, in the clock tree unit 5, only the inverter train 51 consumes power due to the supply of the clock. Thereby, power consumption in the clock tree unit 5 can be reduced. Therefore, the latch circuit 3 is a clock control circuit that restricts the supply of clocks to the analysis control circuit 10, the clock tree unit 5, and the processing circuit 61 before receiving the packet 200.

  In the semiconductor device 100, the trigger for operating the processing circuit 61 is often due to reception of the packet 200. A circuit that has not received the packet 200 does not actually need to operate and does not require a clock supply. Therefore, the clock tree unit 5 is controlled with the reception of the packet 200 as a trigger. For this reason, as will be described later, the packet 200 has information for controlling the clock itself. In other words, the packet 200 controls the processing circuit block 102 or 103 to which the packet 200 is transmitted to autonomously supply a necessary clock.

  Thereby, since the clock is not supplied to the processing circuit 61 until the packet 200 is received, the power consumption can be reduced. When the packet 200 is received, the power consumption can be reduced by operating only the processing circuit 61 that needs to supply a clock. In addition, the clock tree unit 5 is not supplied with a clock until the packet 200 is received, so that power consumption can be reduced. When the packet 200 is received, the clock tree unit 5 supplies the clock only to the path to the processing circuit 61 that needs to supply the clock, thereby reducing the power consumption.

  Instead of the analysis control circuit 10, a program for executing a process described later with reference to FIG. 8 is executed on a CPU (Central Processing Unit) so that the same process as the analysis control circuit 10 is performed. Also good.

  FIG. 3 is a diagram illustrating an example of the clock tree unit and the processing circuit group.

  The clock tree unit 5 includes a clock tree and clock gating circuits 52 and 54. The clock tree is a clock supply path that supplies a clock and branches in a tree shape. Specifically, the clock tree includes an inverter row 51, an inverter row 53 that branches from the inverter row 51 into a plurality, and an inverter row 55 that branches from the inverter row 53 into a plurality. The number of inverters included in the inverter rows 51, 53 and 55 is not limited to two.

  The clock gating circuits 52 and 54 are provided at the head of each of a plurality of paths branched at the branch point at each branch point of the clock tree. Specifically, the clock gating circuit 52 is provided on the clock supply source side of the inverter row 53 between the inverter row 51 and the plurality of inverter rows 53. The clock gating circuit 54 is provided on the clock supply source side of the inverter row 55 between the inverter row 53 and the plurality of inverter rows 55.

  The processing circuit group 6 includes, for example, six processing circuits 61. The number of processing circuits 61 is not limited to six. The processing performed by each processing circuit 61 is predetermined at the time of designing the semiconductor device 100. For example, the “processing circuit A” is the processing circuit 61 that performs the processing A. Each processing circuit 61 performs different processing, for example. A clock is supplied to each processing circuit 61 via different clock supply paths provided corresponding to each processing circuit 61. Note that one processing circuit 61 may perform a plurality of processes.

  The inverter train 51 is connected to a clock supply source. The clock supply path branches into three paths by an inverter string 53 connected to the inverter string 51 via a clock gating circuit 52. Further, the clock supply path is branched into two paths by the inverter array 55 connected to the inverter array 53 via the clock gating circuit 54. As a result, the clock tree branches to correspond to each of the six processing circuits 61 included in the processing circuit group 6, and the clock supply path is different to the six processing circuits 61 included in the processing circuit group 6. A clock is supplied by a route.

  A clock from a clock supply source is commonly input to one input terminal of three two-input AND gates which are the clock gating circuit 52 via an inverter array 51. Different control signals from the analysis control circuit 10 are input to the other input terminals of the three clock gating circuits 52, respectively. Thereby, the three clock gating circuits 52 are individually controlled.

  A clock from a clock supply source is input to one input terminal of six 2-input AND gates that are the clock gating circuit 54 via the inverter row 51, the clock gating circuit 52, and the inverter row 53. Different control signals from the analysis control circuit 10 are input to the other input terminals of the six clock gating circuits 54, respectively. Thereby, the six clock gating circuits 52 are individually controlled.

  A control signal from the analysis control circuit 10 is input to the other input terminal of the 2-input AND gate after being inverted by an inverter. Therefore, in FIG. 3, a “circle” representing an inverter is added to the other input terminal of the 2-input AND gate. In FIG. 3, the control signal lines from the analysis control circuit 10 to the respective clock gating circuits 52 are omitted.

  For example, as shown in FIG. 3, the gating IDs in the clock tree unit 5 are assigned to the clock gating circuits 52 and 54, respectively. The gating ID is identification information that uniquely identifies the clock gating circuit 52 or 54 in the clock tree unit 5.

  Since the clock gating circuit 52 is a first layer gate in the clock tree unit 5, it has a gating ID such as “1-X”. The clock gating circuit 52 has gating IDs “1-1”, “1-2”, and “1-3” in order from the left in FIG. In FIG. 3, the value of X is “1” to “3”, but is not limited thereto.

  Since the clock gating circuit 54 is a gate of the second hierarchy in the clock tree unit 5, it has a gating ID such as “2-XY”. In FIG. 3, the clock gating circuit 52 has gating IDs such as “1-1-1”, “1-1-2”, and “1-2-1” in order from the left. In FIG. 3, the value of Y is “1” to “2”, but is not limited thereto.

  For example, the clock gating circuit 52 having the gating ID “1-1” may be referred to as a clock gating circuit 1-1. For example, the clock gating circuit 54 having the gating ID “1-1-1” may be referred to as a clock gating circuit 1-1-1.

  For example, when the control signal from the analysis control circuit 10 to the clock gating circuit 52 is at a high level, a low level that is an inverted signal thereof is input to the clock gating circuit 52. As a result, the output of the clock gating circuit 52 is set to the low level regardless of the level of the signal from the inverter array 51. In other words, the clock gating circuit 52 is closed. Therefore, the clock is not supplied to the inverter array 53.

  When the control signal from the analysis control circuit 10 to the clock gating circuit 52 is at a low level, a high level that is an inverted signal thereof is input to the clock gating circuit 52. Thereby, the output of the clock gating circuit 52 depends on the level of the signal from the inverter array 51. In other words, the clock gating circuit 52 is opened. Therefore, the clock is supplied to the inverter array 53.

  FIG. 4 is a diagram illustrating an example of a packet.

  The packet 200 is transmitted in synchronization with the clock as shown in FIG. Therefore, the processing circuit blocks 102 and 103 are supplied with the packet 200 and a clock control signal that enables supply of a clock to the processing circuit blocks 102 and 103 during the reception period of the packet 200. The packet 200 is a unit for transmitting and receiving information between the processing circuit blocks 102 and 103 included in the semiconductor device 100. The packet 200 includes a header and packet data. The header is added to the head of the packet 200 and includes function information that is information for specifying a process to be functioned, as will be described later. The packet data is added to the next position of the header and includes data to be processed. Packet data may be omitted.

  The clock control signal is transmitted together with the packet 200 in synchronization with the clock. The clock control signal is transmitted only during the period during which the packet 200 is transmitted. Specifically, the clock control signal is set to, for example, a high level only during a period during which the packet 200 is transmitted. As a result, only during the period during which the packet 200 is transmitted, the clock is supplied to the processing circuit blocks 102 and 103 that receive the packet 200 to enable the operation. Therefore, the clock control signal is an enable signal for the processing circuit blocks 102 and 103.

  The packet 200 may be data or control information that has a predetermined format to be expressed and is transmitted / received between the processing circuit blocks 102 and 103. The packet 200 can take various formats.

  The length of the header transmission period and the length of the packet data transmission period in the packet 200 can take various values. Also, a header packet including a header and a data packet including packet data may be transmitted in parallel as different packets 200 using different communication lines, for example, at the same timing.

  As shown in FIG. 4B, the header of the packet 200 includes, for example, 8-bit data. The information “PKT type” indicating the type of the packet 200 is represented by 4 bits [7: 4] of the eighth to fifth bits of the header. 4 bits [3: 0] from the fourth bit to the first bit of the header represent information “instruction” indicating the type of instruction for processing the data included in the packet 200.

  Accordingly, the function information is information recorded in the header of the packet 200 and is information indicating the type of the packet 200 or information indicating the type of instruction for processing data included in the packet 200. As described above, the function information is identification information representing the type of processing determined according to the packet 200. In other words, the function information is a packet type ID representing the type of the packet 200. As the function information, either one or both of the information indicating the type of the packet 200 and the information indicating the type of the instruction for processing the data included in the packet 200 can be used. Determined.

  For example, as shown in FIG. 4C, when the value represented by 4 bits [7: 4] of the 8th to 5th bits of the header is “0”, the header includes a packet including itself. 200 represents the packet 200 for process A. The processing circuit 61 that performs the processing A is “processing circuit A” at the design time of the semiconductor device 100 in advance. Accordingly, when the processing circuit blocks 102 and 103 receive the header whose value represented by the 8th to 5th bits of 4 bits [7: 4] is “0”, it is included in the processing circuit blocks 102 and 103. The clock is supplied only to the processing circuit A.

  Also, for example, as shown in FIG. 4D, when the value represented by 4 bits [3: 0] of the 4th to 1st bits of the header is “0”, the header is included in the packet data. Indicates that the included data should be added. Among the processing circuits 61 included in the processing circuit blocks 102 and 103, for example, the processing circuit that performs the addition is “processing circuit A”, which is determined in advance at the time of designing the semiconductor device 100. Therefore, when the processing circuit blocks 102 and 103 receive a header whose value represented by 4 bits [3: 0] of the fourth bit to the first bit is “0”, the processing circuit blocks 102 and 103 are included in the processing circuit blocks 102 and 103. The clock is supplied only to the processing circuit A.

  FIG. 5A is an explanatory diagram of header information that is information included in the header of a packet.

  As shown in FIG. 5A, the header 11 of the packet 200 may include various control information in addition to the information described with reference to FIG. In FIG. 5A, various uses of control information are also shown. When the header 11 of the packet 200 includes various control information, the header of the packet 200 is actually 16 bits instead of 8 bits shown in FIG. 4B, for example. The header of the packet 200 may be 32 bits, 64 bits, or the like.

  As various control information, the header 11 of the packet 200 includes, for example, a clock supply control, a forced clock stop, and a forced clock stop ID in addition to the packet type ID, as shown in FIG. As described above, the packet type ID is expressed using 8 bits of a 16-bit header. The clock supply control, forced clock stop, and forced clock stop ID are expressed using the other 8 bits of the 16-bit header.

  The clock supply control is information indicating whether or not to control the clock supply. When the clock supply control is ON (high level), the analysis control circuit 10 controls the clock tree unit 5 to control the clock supply. When the clock supply control is OFF (low level), the control of the clock tree unit 5 by the analysis control circuit 10 is not performed, and a clock is always supplied.

  The control based on the clock supply control has priority over the control of the clock tree unit 5 based on the packet type ID by the analysis control circuit 10. For example, in the received packet 200, the packet type ID indicates that the clock is supplied to the processing circuit A. When the clock supply control is OFF, the analysis control circuit 10 is based on the OFF of the clock supply control. Thus, a clock is always supplied to the processing circuit A. Thereby, for example, the processing circuit 61 that needs to be operated at all times can be supplied with a clock at all times by transmitting the packet 200.

  The forced clock stop is information indicating that the clock supply is forcibly stopped or the stop is released. When the forced clock stop is ON (high level), the clock tree unit 5 is controlled by the analysis control circuit 10 and the supply of the clock is forcibly stopped. When the forced clock stop is OFF (low level), the analysis control circuit 10 releases the forced stop of the clock supply.

  The forced clock stop ID is identification information of a processing circuit that performs processing that should stop the supply of the clock or cancel the stop based on the forced clock stop. The forced clock stop ID is determined in advance for each of the processes A to F described above, for example. For the processing circuit 61 instructed by the forced clock stop ID, the supply of the clock is forcibly stopped or the stop is released.

  The control based on the forced clock stop has priority over the control of the clock tree unit 5 based on the clock supply control. Therefore, the control based on the forced clock stop has priority over the control of the clock tree unit 5 based on the packet type ID by the analysis control circuit 10. The control based on the forced clock stop may be performed regardless of the control of the clock tree unit 5 based on the clock supply control. Further, the control based on the forced clock stop may be performed regardless of the control of the clock tree unit 5 based on the packet type ID. In these cases, the forced clock stop and the clock supply control are set in the header of the packet 200 so as not to contradict each other.

  For example, in the received packet 200, when the clock supply control is OFF and the forced clock stop is ON, the analysis control circuit 10 sets the forced clock stop ON and the forced clock stop ID indicating the processing circuit A. Based on this, the supply of the clock to the processing circuit A is forcibly stopped. The processing circuit 61 to which the packet type ID represents the supply of the clock is irrelevant to the control based on the forced clock stop. As a result, for example, the supply of the clock to the processing circuit A that performs the processing A that becomes unnecessary after the design of the semiconductor device 100 can be stopped by transmitting the packet 200.

  FIG. 5B shows the clock control determination table 12.

  The clock control determination table 12 shows the correspondence between the packet type ID and the clock control determination. In other words, the clock control determination table 12 determines the clock control determination corresponding to the packet type ID for each packet type ID. The clock control determination indicates a process to be performed when a packet 200 having a corresponding packet type ID is received.

  For example, it is assumed that the values of the 8th to 5th bits [7: 4] of the header shown in FIG. 4C are “# 1”. Further, for example, it is predetermined that the packet # 1 whose packet type ID is “# 1” is to perform the process A and the process C. On the other hand, the packet type ID is described at a predetermined position inside the header of the packet 200. Therefore, by analyzing the received packet 200 and extracting the packet type ID, it is possible to know which processing circuit 61 should operate in order to process the received packet 200. Therefore, it is possible to know the processing circuit 61 to which a clock is to be supplied when performing processing. For example, when the extracted packet type ID is “# 1”, a clock may be supplied to the processing circuit A and the processing circuit C.

  The clock control determination table 12 may have a configuration other than the table format. The clock control determination table 12 is actually composed of a circuit that outputs a corresponding one or more processes, in other words, a processing circuit 61, with the packet type ID as an input. For example, the decoding circuit for clock control determination may decode the packet type ID and output the corresponding one or a plurality of processes, in other words, the processing circuit 61 from the holding circuit.

  FIG. 6A shows a clock gating ID determination table.

  The clock gating ID determination table 13 shows the correspondence between the processing circuit to which a clock is to be supplied when performing processing and the clock gating circuits 52 and 54 of the clock tree unit 5. In other words, the clock gating ID determination table 13 defines the clock gating circuits 52 and 54 of the clock tree unit 5 to be opened for supplying a clock for each type of processing. As described above, when the type of processing is determined, the processing circuit 61 to which a clock is to be supplied when performing processing is also determined.

  For example, in order to perform the processing A, it is required to supply a clock to the processing circuit A. Referring to FIG. 3, the clock is supplied to the processing circuit A through the inverter array 51, the clock gating circuit 1-1, the inverter array 53, and the clock gating circuit 1-1-1. In other words, in order to supply the clock to the processing circuit A, the clock gating circuit 1-1 and the clock gating circuit 1-1-1 may be opened. Accordingly, as indicated by “circle” in FIG. 6A, the clock gating circuits 52 and 54 whose gating IDs are “1-1” and “1-1-1” are opened in the process A. It is defined that

  The clock gating ID determination table 13 may have a configuration other than the table format. The clock gating ID determination table 13 is actually configured by a circuit that outputs the corresponding clock gating circuits 52 and 54 with the processing type as an input. For example, the decoding circuit for determining the clock gating ID may decode the processing type and output the corresponding clock gating circuits 52 and 54 from the holding circuit.

  FIG. 6B shows a logical sum of the determination results of the clock gating ID.

  For example, the analysis control circuit 10 extracts the packet type ID “# 3” by extracting a signal at a predetermined bit position in the header of the received packet 200. Then, based on the extracted packet type ID “# 3”, the analysis control circuit 10 determines processing A and processing F to be performed by the packet 200 as illustrated in FIG.

  Further, the analysis control circuit 10, based on the determined processing A, as shown in FIG. 6A, the clock gating circuit 1-1 and the clock gating circuit to be opened to supply the clock to the processing circuit A. 1-1-1. Further, the analysis control circuit 10, based on the determined processing F, as shown in FIG. 6A, the clock gating circuit 1-3 and the clock gating circuit to be opened to supply a clock to the processing circuit F. 1-3-2 is obtained. Then, the analysis control circuit 10 obtains the logical sum of the obtained clock gating circuits.

  As a result, the analysis control circuit 10 performs the processing A and the processing F by the received packet 200 as shown in FIG. 6B, so that the clock gating circuits 1-1, 1-3, 1-1. 1 and 1-3-2 are opened, a control instruction which is a signal for opening the clock gating circuits 1-1, 1-3, 1-1-1 and 1-3-2 is generated, and the clock is generated. Input to the tree part 5. Thus, the clocks can be supplied only to the processing circuit A and the processing circuit F, and the processing A and the processing F can be performed by the received packet 200. Further, in the clock tree unit 5, the clock is supplied only to the path for supplying the clock to the processing circuit A and the processing circuit F, and the clock is not supplied to the path other than the path for supplying the clock to the processing circuit A and the processing circuit F. Can be.

  FIG. 7 is an explanatory diagram of power saving control.

  FIG. 7 shows clock gating in the case where the clock is supplied to the processing circuits A and F and the clock is not supplied to the other processing circuits 61 as described above.

  In order to supply a clock to the processing circuit A, a low-level control signal is input to the clock gating circuit 1-1 and the clock gating circuit 1-1-1. As a result, the clock gating circuit 1-1 and the clock gating circuit 1-1-1 are opened as shown by the solid line in FIG. As a result, as indicated by a one-dot chain line in FIG. 7, the clock passes through the inverter train 51, the clock gating circuit 1-1, the inverter train 53, the clock gating circuit 1-1-1, and the inverter train 55. Input to the processing circuit A.

  In order to supply a clock to the processing circuit F, a low-level control signal is input to the clock gating circuit 1-3 and the clock gating circuit 1-3-2. As a result, the clock gating circuit 1-3 and the clock gating circuit 1-3-2 are opened as shown by being surrounded by a solid line in FIG. As a result, as shown by a one-dot chain line in FIG. 7, the clock passes through the inverter train 51, the clock gating circuit 1-3, the inverter train 53, the clock gating circuit 1-3-2, and the inverter train 55. Input to the processing circuit F.

  On the other hand, the processing circuit 61 other than the processing circuit A and the processing circuit F is not supplied with a clock. For this purpose, clock gating circuit 1-2, clock gating circuit 1-1-2, clock gating circuit 1-2-1, clock gating circuit 1-2-2, clock gating circuit 1-3 1, a high level control signal is input. As a result, these clock gating circuits are closed as shown by the dotted lines in FIG. As a result, no clock is supplied to the processing circuit B, the processing circuit C, the processing circuit D, and the processing circuit E. Thereby, the supply of the clock to the processing circuit 61 that does not process the packet 200 can be stopped.

  FIG. 8 is a diagram illustrating a power saving control sequence.

  When transmission of the clock control signal and the packet 200 is started from the processing circuit block 102 or 103 at the previous stage, the clock gating circuit 1 receives a high-level clock control signal in a state where the clock is supplied ( S1). Thereby, the clock gating circuit 1 is opened, and the clock is supplied from the clock gating circuit 1 to the latch circuit 2 (S2). As a result, the latch circuit 2 receives the packet 200 and outputs the received packet 200 to the processing circuit group 6 and the analysis control circuit 10 (S3). On the other hand, the latch circuit 3 receives the high-level clock control signal while the clock is supplied, and outputs the received clock control signal to the OR gate circuit 8 (S3).

  The OR gate circuit 8 outputs a high level control signal to the clock gating circuit 9 in accordance with the received high level clock control signal. The clock gating circuit 9 receives a high-level control signal while the clock is supplied, and outputs the clock to the analysis control circuit 10 (S4). As a result, the analysis control circuit 10 starts analyzing the received packet 200 in synchronization with the clock whose supply has been started.

  The analysis control circuit 10 analyzes the header of the packet 200 received from the latch circuit 2 (S5), performs control determination in the clock tree unit 5 based on the analysis result (S6), and based on the determination result. Then, a control instruction is given to the clock tree unit 5 (S7).

  Specifically, the analysis control circuit 10 extracts the function information from the packet 200 as the analysis process, and specifies the processing circuit 61 to which the clock is to be supplied based on the function information and the circuit information as the control determination process. As a control instruction, a control instruction is generated based on the specified processing circuit 61, and the generated control instruction is input to the clock tree unit 5. Thereby, each of the clock gating circuits 52 and 54 is controlled individually.

  In sequence S <b> 7, the analysis control circuit 10 inputs a high-level control signal to the OR gate circuit 8 together with outputs of control instructions corresponding to the clock gating circuits 52 and 54. Thereafter, the analysis control circuit 10 waits for reception of a processing completion notification signal from the processing circuit 61.

  The clock tree unit 5 receives the control instruction from the analysis control circuit 10 by the processing in the sequence S7, and supplies a clock to the processing circuit A as shown in FIG. 7, for example (S9). Thereby, the processing circuit A processes the packet 200 received from the latch circuit 2 by the processing in the sequence S3 (S10), and completes the processing (S11). In S <b> 11, the processing circuit A transmits a processing completion notification signal to the analysis control circuit 10.

  Further, the clock tree unit 5 receives a control instruction from the analysis control circuit 10 by the processing in the sequence S7, and supplies a clock to the processing circuit F as shown in FIG. 7, for example (S12). Thereby, the processing circuit F processes the packet 200 received from the latch circuit 2 by the processing in the sequence S3 (S13), and completes the processing (S14). In step S <b> 14, the processing circuit F transmits a processing completion notification signal to the analysis control circuit 10. For example, the sequence S9 and the sequence S12 are performed in parallel, and the sequence S10 and the sequence S13 are started in parallel. The sequence S11 and the sequence S14 may or may not be performed in parallel.

  By the processing in sequence S11 and sequence S14, the analysis control circuit 10 receives the processing completion notification signal from the processing circuit A and processing circuit F, and starts processing completion determination (S8). Specifically, the analysis control circuit 10 receives processing completion notification signals from the processing circuits A and F and inputs a low-level control signal to the OR gate circuit 8.

  Thereafter, the transmission of the clock control signal and the packet 200 from the processing circuit block 102 or 103 in the previous stage is stopped. Thereby, the clock gating circuit 1 receives the low level of the clock control signal. As a result, the clock gating circuit 1 is closed, the clock is not supplied from the clock gating circuit 1 to the latch circuit 2, and the latch circuit 2 does not output the packet 200 to the processing circuit group 6 and the analysis control circuit 10. .

  On the other hand, the latch circuit 3 receives the low level of the clock control signal and outputs the received low level clock control signal to the OR gate circuit 8. As a result, the OR gate circuit 8 outputs a low level signal to the clock gating circuit 9. As a result, the clock gating circuit 9 does not output a clock to the analysis control circuit 10.

  The analysis control circuit 10 does not generate a control instruction in a state where the packet 200 and the clock are not supplied. As a result, in the clock tree unit 5, all the clock gating circuits 52 and 54 are closed. Therefore, in the clock tree unit 5, only the inverter train 51 consumes power when the clock is supplied.

  As will be understood from the above description, the following embodiments are grasped.

(Additional remark 1) The control part which extracts the function information which is the information recorded on the said packet from the received packet, and is the information which specifies the process which should be functioned,
Based on the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when the processing is performed, the process to be performed specified by the extracted function information is performed. A processing circuit to which the clock is supplied when performing includes a clock supply unit that supplies the clock.

(Additional remark 2) The said control part associates and hold | maintains the said process and the processing circuit which should supply the said clock when performing the said process as said circuit information, and the said function information and said circuit information which were extracted are stored. Based on this, a control signal for controlling the clock supply unit is generated and input to the clock supply unit.

(Supplementary Note 3) The clock supply unit includes a clock tree that is a path for supplying the clock and branches in a tree shape, and each of a plurality of paths branched at the branch point at each branch point of the clock tree. Including a clock gating circuit provided at the beginning,
The semiconductor device according to appendix 2, wherein the control unit generates and inputs a control signal corresponding to each of the clock gating circuits.

(Supplementary Note 4) The function information is information recorded in a header of the packet, and is information indicating the type of the packet or information indicating a type of instruction for processing data included in the packet. The semiconductor device according to appendix 1, wherein:

(Additional remark 5) The said control part is linked | related with the process which should be made to function in relation to the 1st holding | maintenance process which hold | maintains the process which should be made to function in relation to the information which represents the information which represents the kind of the said packet, or the said instruction | command type, and the said process The semiconductor device according to appendix 4, wherein the circuit information is held by a second holding unit that holds a processing circuit to which the clock is to be supplied when processing to be performed is performed.

(Supplementary Note 6) The clock supply unit is a path for supplying the clock and branches in a tree shape, and each of a plurality of paths branched at the branch point at each branch point of the clock tree. Including a clock gating circuit provided at the beginning,
The second holding unit holds identification information indicating the clock gating circuit to be opened to supply a clock to the processing circuit to which the clock is supplied as the processing circuit to which the clock is supplied. The semiconductor device according to appendix 5.

(Supplementary Note 7) When the control unit supplies the clock to the processing circuit to which the clock is to be supplied, the control unit receives a processing completion notification signal from the processing circuit to which the clock is to be supplied, The semiconductor device according to appendix 1, wherein the supply of the clock to the processing circuit to be supplied is stopped.

(Supplementary Note 8) The semiconductor device further includes:
The semiconductor device according to appendix 1, further comprising: a clock control circuit that restricts the supply of the clock to the control unit, the clock supply unit, and the processing circuit before receiving the packet.

(Supplementary Note 9) The packet is information recorded in the packet, and includes information indicating whether to control the supply of the clock,
The control unit controls the clock to the processing circuit to which the clock is to be supplied, based on information indicating whether or not to control the supply of the clock prior to the control based on the function information. The semiconductor device according to appendix 1.

(Supplementary Note 10) The packet is information recorded in the packet, and includes information indicating that the supply of the clock is forcibly stopped,
The control unit forcibly stops the supply of the clock to the processing circuit to which the clock is to be supplied based on information indicating that the supply of the clock is forcibly stopped. A semiconductor device according to 1.

(Additional remark 11) The said packet contains the identification information of the processing circuit corresponding to the process which should stop the supply of the said clock based on the information which shows that the supply of the said clock is stopped forcibly,
The control unit forcibly supplies the clock to a processing circuit corresponding to a process that should stop the supply of the clock based on the information indicating that the supply of the clock is forcibly stopped and the identification information. The semiconductor device according to appendix 10, wherein the semiconductor device is stopped.

(Supplementary Note 12) The semiconductor device includes at least one processing circuit block including the control unit and the clock supply unit,
The supplementary note 1 is characterized in that the processing circuit block is supplied with the packet and a clock control signal that validates the supply of the clock to the processing circuit block during reception of the packet. Semiconductor device.

(Supplementary Note 13) A power consumption control method for a semiconductor device including a control unit, a clock supply unit, and a processing circuit,
The control unit extracts function information that is information recorded in the packet from the received packet and is information that specifies a process to be performed.
The clock supply unit is specified by the extracted function information based on the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when the processing is performed. A power consumption control method for a semiconductor device, characterized in that the clock is supplied to a processing circuit to which the clock is to be supplied when processing to be performed is performed.

(Supplementary Note 14) A power consumption control method for a semiconductor device including a control unit, a clock supply unit, and a processing circuit,
The semiconductor device power consumption control method, wherein the semiconductor device stops clock supply to the control unit, the clock supply unit, and the processing circuit until a packet is received.

DESCRIPTION OF SYMBOLS 1, 9 Clock gating circuit 2, 3 Latch circuit 4 Internal processing circuit 5 Clock tree part 6 Processing circuit group 7 Power saving control part 8 OR gate circuit 10 Analysis control circuit 51, 53, 55 Inverter train 52, 54 Clock gating Circuit 61 Processing circuit 100 Semiconductor device 101-104 Processing circuit block 200 Packet

Claims (8)

A control unit that extracts, from the received packet, function information that is information recorded in the packet and that specifies information to be processed;
Based on the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when the processing is performed, the process to be performed specified by the extracted function information is performed. A processing circuit to which the clock is supplied when performing includes a clock supply unit that supplies the clock. A semiconductor device for processing a received packet,
A processing circuit divided for each function of processing the packet;
Forming a path for supplying clocks by branching into a tree shape, and a clock tree for supplying clocks to the processing circuit;
A clock gating circuit provided at a branch point of the clock tree;
A semiconductor device comprising: a control unit that specifies a process to be functioned from the packet and controls the clock gating circuit based on the specified process . A control unit that extracts, from the received packet, function information that is information recorded in the packet and that specifies information to be processed;
Based on the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when the processing is performed, the process to be performed specified by the extracted function information is performed. A clock supply unit for supplying the clock to a processing circuit to which the clock is to be supplied when performing,
The control unit holds, as the circuit information, the processing and a processing circuit to which the clock is to be supplied when the processing is performed, and based on the extracted function information and the circuit information, A control signal for controlling the clock supply unit is generated and input to the clock supply unit,
The clock supply unit is provided at the head of each of a plurality of paths branched at the branch point in a clock tree that is a path for supplying the clock and branches in a tree shape, and at each branch point of the clock tree. Clock gating circuit
Wherein the control unit, the clock gating circuit semiconductors devices you characterized in that each generates a control signal corresponding input. The function information is information recorded in a header of the packet, and is information indicating a type of the packet or information indicating a type of an instruction for processing data included in the packet. The semiconductor device according to claim 3 . The control unit includes a first holding unit that holds the process to be functioned in association with information indicating the type of the packet or information indicating the type of instruction, and the process to be functioned in association with the process to be functioned The semiconductor device according to claim 4, wherein the circuit information is held by a second holding unit that holds a processing circuit to which the clock is to be supplied when performing the above. The semiconductor device includes at least one processing circuit block including the control unit and the clock supply unit,
The processing circuit block, and the packet to claim 3 clock control signal to enable the supply of said clock to said processing circuit block during the period of reception of the packet and is characterized in that the input The semiconductor device described. A power consumption control method for a semiconductor device including a control unit, a clock supply unit, and a processing circuit,
The control unit extracts function information that is information recorded in the packet from the received packet and is information that specifies a process to be performed.
The clock supply unit is specified by the extracted function information based on the extracted function information and circuit information that is information for specifying a processing circuit to which a clock is to be supplied when the processing is performed. A power consumption control method for a semiconductor device, characterized in that the clock is supplied to a processing circuit to which the clock is to be supplied when processing to be performed is performed. A control unit that extracts information recorded in the packet, which is information recorded in the packet and is information that specifies processing to be performed, from the received packet, the extracted function information, and a clock when performing the processing The processing circuit to which the clock is to be supplied when performing the process to be functioned specified by the extracted function information based on the circuit information that is information for specifying the processing circuit to which the clock is to be supplied. Each of a plurality of paths branched at the branch point at each of the branch points of the clock tree, and a clock tree branching in a tree shape, the path supplying the clock a clock supply unit including a clock gating circuit provided on the top a power consumption control method for a semiconductor device comprising a processing circuit
The control unit holds, as the circuit information, the processing and a processing circuit to which the clock is to be supplied when the processing is performed, and based on the extracted function information and the circuit information, A control signal for controlling the clock supply unit is generated and input to the clock supply unit,
The method for controlling power consumption of a semiconductor device, wherein the control unit generates and inputs a control signal corresponding to each of the clock gating circuits .

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