JP5849401B2 - Liquid crystal driving method, liquid crystal driving device, liquid crystal device, and electronic apparatus - Google Patents

Description

  The present invention relates to a liquid crystal driving method, a liquid crystal driving device, a liquid crystal device, an electronic device, and the like, and more particularly to a liquid crystal driving method for driving a liquid crystal panel by a simultaneous selection driving method for simultaneously selecting a plurality of lines.

  Conventionally, this type of liquid crystal panel has a plurality of common electrodes and a plurality of segment electrodes provided so as to intersect the plurality of common electrodes, and corresponds to the intersection position of each common electrode and each segment electrode. Thus, a pixel is formed. A liquid crystal driving device that drives a liquid crystal panel displays an image on the liquid crystal panel by driving a plurality of common electrodes and a plurality of segment electrodes of the liquid crystal panel according to a predetermined liquid crystal driving method. When driving a liquid crystal panel, if a voltage of the same polarity is continuously applied to the pixel, burning will occur, so in general, the liquid crystal drive device periodically reverses the polarity of the voltage applied to the pixel and turns it into an alternating current. The polarity inversion drive is performed.

  As this polarity inversion driving, frame inversion driving in which the polarity is inverted every frame is known. However, the output frequency differs depending on the segment electrode of the liquid crystal panel, which may cause crosstalk, etc. n-line inversion that performs polarity inversion every n lines for the purpose of polarity inversion at shorter time intervals Driving may be performed.

  A technique related to such polarity inversion driving is disclosed in Patent Document 1, for example. In this Patent Document 1, in the 4-line simultaneous selection driving method, a dummy period is added to one horizontal scanning period for each of a plurality of field periods obtained by dividing one frame period, and the number of subgroups is set to an odd number. A technique for obtaining the effect of polarity inversion driving is disclosed.

JP-A-8-160919

  In so-called line-sequential driving, the relationship between the duty dt and the number of lines whose polarity is inverted is such that when the number of display lines is L and the duty dt = 1 / L, L is an odd number and there is no common divisor with L. The number of inversion lines is preferably a prime number. As for the simultaneous selection driving method, for example, Patent Document 1 discloses that the number of subgroups is desirably an odd number.

  However, in the 4-line simultaneous selection driving method, one frame period is divided into four field periods, and scanning is performed for each field period, so that four scans are performed in one frame period. Accordingly, when n-line inversion driving is performed by the 4-line simultaneous selection driving method as disclosed in Patent Document 1, the number of subgroups in one frame period is an even number. Therefore, when there is a bias potential shift, there is a problem that an effective voltage difference is generated, a light and dark stripe pattern is seen, and image quality may be deteriorated.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, when a liquid crystal panel is driven by n-line inversion driving in a simultaneous selection driving method that simultaneously selects a plurality of lines, a liquid crystal driving method that suppresses image quality degradation even when there is a bias potential shift. A liquid crystal driving device, a liquid crystal device, an electronic device, and the like can be provided.

  (1) According to a first aspect of the present invention, a liquid crystal driving method for driving a liquid crystal panel by the S (S is a natural number of 2 or more) line simultaneous selection driving method includes a first field period to a first field period divided by one frame period. N line inversion driving for performing polarity inversion control for each n (n is a natural number) line in a field period from the first field period to the Lth (1 ≦ L ≦ S−1, L is a natural number) among S field periods. A first driving step for driving the liquid crystal panel, and at least one horizontal scanning period in the (L + 1) -th field period to the S-th field period among the first field period to the S-th field period. And a second driving step of driving the liquid crystal panel by n-line inversion driving by adding a dummy period.

  In this aspect, n-line inversion that performs polarity inversion control for each n-line in the first field period to the L-th field period among the first field period to the S-th field period obtained by dividing one frame period Drive. Then, in the (L + 1) -th field period to the S-th field period, n-line inversion driving is performed by adding at least one dummy period corresponding to the horizontal scanning period. As a result, the number of positive pulses and the number of negative positive pulses can be made equal between polarity inversion periods, and even if there is a deviation in bias potential, there is no difference in effective voltage depending on the common electrode. In the liquid crystal panel, the occurrence of light and shade stripes can be suppressed.

  (2) In the liquid crystal driving method according to the second aspect of the present invention, in the first aspect, in the second driving step, a non-selection voltage is supplied to the common electrode of the liquid crystal panel in the dummy period, A given dummy voltage is supplied to the segment electrode of the liquid crystal panel.

  According to this aspect, in addition to the above-described effect, the above-described effect can be obtained without affecting the display by adding a dummy period.

  (3) In the liquid crystal driving method according to the third aspect of the present invention, in the first aspect or the second aspect, L is (S-1), and one horizontal scan is performed in the second driving step. The dummy period for the period is added.

  According to this aspect, in addition to the above-described effect, it is possible to minimize the decrease in contrast due to the addition of the dummy period.

  (4) According to a fourth aspect of the present invention, there is provided a liquid crystal driving method for driving a liquid crystal panel by an S (S is a natural number of 2 or more) line simultaneous selection driving method, wherein an applied voltage of a pixel constituting the liquid crystal panel is positive. A positive polarity driving step of driving the liquid crystal panel by n line inversion driving for performing polarity inversion control for each n (n is a natural number) line, and the application voltage of the pixel is negative. negative polarity driving step of driving the liquid crystal panel by n-line inversion driving, and (reciprocal number of the duty of the liquid crystal panel × A) / (n / S) (A is a minimum natural number that makes the expression divisible) Is an even number, the number of positive pulses applied to each common electrode of the liquid crystal panel during the polarity inversion period is equal to the number of negative positive pulses.

  According to this aspect, among the combinations of the number S of lines simultaneously selected by the simultaneous selection driving method, the duty of the liquid crystal panel, and the number n of lines to be polarity-inverted in the n-line inversion drive, The following effects are obtained. That is, even if there is a deviation in the bias potential, it is possible to suppress the occurrence of light and shade stripe patterns in the liquid crystal panel without causing a difference in effective voltage depending on the common electrode.

  (5) In the liquid crystal driving method according to the fifth aspect of the present invention, in any one of the first to fourth aspects, the number of lines n for polarity inversion is variably configured.

  According to this aspect, since the number of lines to be polarity-inverted can be changed according to the generation condition of the striped pattern caused by the number of display lines of the liquid crystal panel, the display quality regardless of the number of display lines of the liquid crystal panel. Can be improved.

  (6) According to a sixth aspect of the present invention, there is provided a driving unit that drives the liquid crystal panel by an S (S is a natural number of 2 or more) line simultaneous selection driving method, and the driving unit that drives the liquid crystal panel A polarity inversion control unit that performs polarity inversion control of a driving signal supplied to the liquid crystal panel, and the driving unit includes a first field period to an S-th field period obtained by dividing one frame period. In the field period from 1 to L (1 ≦ L ≦ S−1, L is a natural number), n line inversion driving is performed to perform polarity inversion control for each n (n is a natural number) line. The n-line inversion driving is performed by adding a dummy period for at least one horizontal scanning period in the field period to the S-th field period.

  In this aspect, n-line inversion that performs polarity inversion control for each n-line in the first field period to the L-th field period among the first field period to the S-th field period obtained by dividing one frame period Drive. Then, in the (L + 1) -th field period to the S-th field period, n-line inversion driving is performed by adding at least one dummy period corresponding to the horizontal scanning period. As a result, the number of positive pulses and the number of negative positive pulses can be made equal during the polarity inversion period. Therefore, even if there is a deviation in the bias potential, it is possible to provide a liquid crystal driving device that suppresses the occurrence of shading in the liquid crystal panel without causing a difference in effective voltage depending on the common electrode.

  (7) In the liquid crystal drive device according to a seventh aspect of the present invention, in the sixth aspect, the drive section supplies a non-selection voltage to the common electrode of the liquid crystal panel in the dummy period, A given dummy voltage is supplied to the segment electrode.

  According to this aspect, in addition to the above-described effect, it is possible to provide a liquid crystal driving device that can obtain the above-described effect without affecting the display by adding a dummy period.

  (8) In the liquid crystal driving device according to the eighth aspect of the present invention, in the fifth aspect or the sixth aspect, L is (S-1), and the driving unit is for one horizontal scanning period. The n-line inversion driving is performed by adding the dummy period.

  According to this aspect, in addition to the above effect, it is possible to provide a liquid crystal driving device that minimizes a decrease in contrast due to the addition of a dummy period.

  (9) A liquid crystal driving device according to a ninth aspect of the present invention is the n-line inversion number register in which setting information corresponding to the number of lines whose polarity is inverted is set in any of the fifth to eighth aspects. The driving unit performs the n-line inversion driving for each number of lines corresponding to the setting information set in the n-line inversion number register.

  According to this aspect, since the number of lines to be polarity-inverted can be changed according to the generation condition of the striped pattern caused by the number of display lines of the liquid crystal panel, the display quality regardless of the number of display lines of the liquid crystal panel. It is possible to provide a liquid crystal driving device that improves the above.

  (10) In a tenth aspect of the present invention, a liquid crystal device includes the liquid crystal driving device according to any one of the sixth to ninth embodiments, and a liquid crystal panel driven by the liquid crystal driving device.

  According to this aspect, it is possible to provide a liquid crystal device that suppresses deterioration in image quality even when there is a bias potential shift when a liquid crystal panel is driven by n-line inversion driving by a simultaneous selection driving method that selects a plurality of lines simultaneously. It becomes like this.

  (11) In an eleventh aspect of the present invention, an electronic device includes the liquid crystal driving device according to any one of the sixth to ninth aspects.

  According to this aspect, when a liquid crystal panel is driven by n-line inversion driving in a simultaneous selection driving method in which a plurality of lines are simultaneously selected, an electronic device to which a liquid crystal driving device that suppresses deterioration in image quality even if there is a bias potential shift is applied Equipment can be provided.

1 is a block diagram of a configuration example of a liquid crystal device according to an embodiment of the present invention. 2A to 2D are explanatory diagrams of the principle of the MLS driving method. The figure which shows the relationship of the voltage of 7 levels at the time of driving a liquid crystal panel by the MLS drive method of 4 line simultaneous selection. Explanatory drawing of the selection voltage of the common electrode of the liquid crystal panel in the MLS drive method of 4 line simultaneous selection. The figure which shows the selection voltage of the common electrodes COM0-COM3 selected simultaneously when n line inversion drive is set to disable. The figure which shows the selection voltage of the common electrodes COM0-COM3 selected simultaneously when n line inversion drive is set to enable. The flowchart of the liquid crystal drive method by the liquid crystal drive device in this embodiment. Explanatory drawing of the liquid-crystal drive method in this embodiment. Explanatory drawing of the liquid-crystal drive method in this embodiment. Explanatory drawing of the effect of the liquid-crystal drive method in this embodiment. FIG. 3 is a block diagram of a configuration example of a liquid crystal driving device in the present embodiment. Explanatory drawing of the common address and line address in this embodiment. FIG. 12 is a block diagram of a configuration example of a polarity inversion control circuit in FIG. 11. The flowchart of the operation example of a field number counter. The flowchart of the operation example of a common address counter. The flowchart of the operation example of a line address counter. The flowchart of the operation example of an n line inversion number counter. The flowchart of the operation example of a polarity register. The timing diagram of the operation example of a polarity inversion control circuit. The figure which shows an example of the drive timing of the liquid crystal drive device in this embodiment. FIGS. 21A and 21B are perspective views illustrating the configuration of an electronic apparatus to which the present embodiment is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[Liquid Crystal Display]
FIG. 1 shows a block diagram of a configuration example of a liquid crystal device according to an embodiment of the present invention. Although FIG. 1 illustrates a configuration example in which the liquid crystal device includes a liquid crystal driving device, the liquid crystal driving device may be provided outside the liquid crystal device.

  The liquid crystal device 10 as an electro-optical device includes a liquid crystal panel (display panel or electro-optical panel in a broad sense) 20, a host processor 30, and a power supply circuit 40.

  The liquid crystal panel 20 is a passive-type liquid crystal display panel, and is formed between a pair of transparent glass substrates with a plurality of common electrodes, a plurality of segment electrodes, an alignment film, Formed by enclosing liquid crystal or the like. The liquid crystal panel 20 includes a pixel formation region 22, and the pixel formation region 22 includes a common electrode disposed in a first direction and a segment disposed in a second direction intersecting the first direction. A pixel is formed corresponding to the position of intersection with the electrode. In FIG. 1, a common electrode COMj (0 ≦ j ≦ Q, j is an integer) of a plurality of common electrodes COM0 to COMQ (Q is a natural number) and a segment electrode SEGk (0 of a plurality of segment electrodes SEG0 to SEGR (R is a natural number)). ≦ k ≦ R, k is an integer). A pixel Pjk is formed corresponding to the intersection position of the common electrode COMj and the segment electrode SEGk. A liquid crystal driving device 100 is mounted on a glass substrate constituting the liquid crystal panel 20 by COG (Chip On Glass).

  The liquid crystal driving device 100 includes a plurality of common electrode output terminals for supplying a given selection voltage to the common electrode, and a plurality of segment electrode output terminals for supplying a liquid crystal driving voltage corresponding to image data to the segment electrode. Have Each of the plurality of common electrode output terminals is electrically connected to the corresponding common electrode, and each of the plurality of segment electrode output terminals is electrically connected to the corresponding segment electrode. The liquid crystal driving device 100 drives the common electrodes COM0 to COMQ and the segment electrodes SEG0 to SEGR formed in the pixel formation region 22 of the liquid crystal panel 20 by an MLS (Multi Line Selection) driving method (simultaneous selection driving method). That is, the liquid crystal driving device 100 drives a plurality of times in a plurality of field periods obtained by dividing one frame period as a period necessary to display one screen by simultaneously selecting a plurality of common electrodes. The liquid crystal driving device 100 drives a plurality of simultaneously selected common electrodes based on a selected pattern (scanning pattern) for each field period, and drives corresponding to a given MLS calculation result based on the selected pattern and image data. A voltage is applied to the plurality of segment electrodes.

  The host processor 30 performs drive control of the liquid crystal drive device 100 by reading a program stored in a built-in memory or a memory (not shown) and executing processing corresponding to the program. Therefore, the host processor 30 can control the operation of the liquid crystal driving device 100 by setting a setting value in a setting register built in the liquid crystal driving device 100. Further, the host processor 30 supplies image data corresponding to an image to be displayed on the liquid crystal panel 20 to the liquid crystal driving device 100. In FIG. 1, the host processor 30 may be mounted on a glass substrate constituting the liquid crystal panel 20.

  The power supply circuit 40 supplies an operating power supply voltage and a drive power supply voltage for the liquid crystal panel 20 or a reference voltage for generating these voltages to each of the host processor 30 and the liquid crystal drive device 100. In FIG. 1, the power supply circuit 40 may be mounted on a glass substrate constituting the liquid crystal panel 20 or may be built in the liquid crystal driving device 100.

[MLS drive method]
Compared with the simple driving method, the MLS driving method by the liquid crystal driving device 100 can narrow the interval of the period during which the common electrode is selected, suppresses the decrease in the transmittance of the pixel, and improves the average transmittance. Can be made. Moreover, the drive voltage (selection voltage) applied to a common electrode can be made low by selecting a some common electrode simultaneously.

  2A to 2D are explanatory diagrams of the principle of the MLS driving method. Each of FIGS. 2A to 2D represents an example in which a pixel (dot) at a position where the common electrodes COM0, COM1 and the segment electrode SEG0 intersect is turned on or off. 2A to 2D show examples of the MLS driving method in which two lines of common electrodes COM0 and COM1 are simultaneously selected and two lines are simultaneously selected.

  In FIG. 2A to FIG. 2D, a pixel that is turned on (on pixel) is represented by “−1”, and a pixel that is turned off (off pixel) is represented by “+1”. Specified by. A selection pattern for selecting each of the common electrodes COM0 and COM1 is represented by binary values “+1” and “−1”. Further, the drive voltage of the segment electrode SEG0 has three values “MV2”, “V2”, and “V1”.

  In the MLS driving method, the driving voltage of the segment electrode SEG0 is determined by the selection pattern of the common electrodes COM0 and COM1 that are selected simultaneously with the image data. Here, if the image data is the image data vector d and the selection pattern is the matrix β, it is determined whether the drive voltage of the segment electrode SEG0 is “MV2”, “V2”, or “V1”. And the matrix β. The image data vector d represents data representing on or off of a pixel at a position where the segment electrode SEG0 intersects each common electrode. In the case of FIG. 2A, d · β = −2, in the case of FIG. 2B, d · β = + 2, and in the case of FIG. 2C, d · β = + 2. In the case of 2 (D), d · β = 0. When the product of the image data vector d and the matrix β is “−2”, “MV2” is selected as the drive voltage of the segment electrode SEG0, “V2” is selected when it is “+2”, and “0”. “V1” is selected.

  For example, when the calculation of the product of the image data vector d and the matrix β is performed by hardware, the number of mismatches between each element data of the image data vector d and each element data of the matrix β may be determined. . For example, when the number of mismatches is “2”, “MV2” is selected as the drive voltage for the segment electrode SEG0. If the number of mismatches is “0”, “V2” is selected as the drive voltage. If the number of mismatches is “1”, “V1” is selected as the drive voltage.

  In the two-line simultaneous MLS driving method, the driving voltage of the segment electrode SEG0 is determined as described above, and two field periods are provided within one frame period to control the on / off of the pixels. Since the field period is provided a plurality of times, the decrease in the transmittance in the non-field period is reduced, the average transmittance in the liquid crystal panel 20 can be improved, and the contrast of the liquid crystal panel can be improved.

  In the present embodiment described below, an MLS driving method in which four lines of common electrodes are simultaneously selected is adopted. In this case, four field periods can be provided within one frame period, and the contrast of the liquid crystal panel 20 can be further improved. In the 4-line simultaneous selection MLS driving method, a voltage of 7 levels is used.

  FIG. 3 shows the relationship between the seven levels of voltage when the liquid crystal panel 20 is driven by the MLS driving method of simultaneous selection of four lines.

  The voltages V3 and MV3 are common electrode selection voltages. The voltage VC is a non-selection voltage for the common electrode, and is a driving voltage for the segment electrode. The voltages V2, V1, MV1, and MV2 are segment electrode drive voltages. And the transmittance | permeability of a pixel changes according to the voltage difference of the common electrode and segment electrode which cross | intersect.

Here, a voltage difference between the voltage V3 and the center voltage VC _{v 3,} the voltage difference between the voltage V2 and the center voltage VC _{v 2,} the voltage difference between the voltage V1 and the center voltage VC and _{v 1.} At this time, the voltage difference between the center voltage VC and the voltage MV3 is v ₃ , the voltage difference between the center voltage VC and the voltage MV2 is v ₂ , and the voltage difference between the center voltage VC and the voltage MV1 is v ₁ . Here, the voltage difference between the voltage V2 and the voltage V1 (= the voltage difference between the voltage MV1 and the voltage MV2) is the voltage difference between the voltage V1 and the center voltage VC (= the voltage difference between the center voltage VC and the voltage MV1). equal.

  Among these seven level voltages, the voltage MV3 has the lowest potential, and in the present embodiment, the ground voltage VSS is adopted as the voltage MV3.

  The liquid crystal driving device 100 drives the common electrode and the segment electrode by the MLS driving method using the voltage shown in FIG. At this time, the liquid crystal driving device 100 performs the n-line polarity inversion control to invert the polarity every time n (n is an integer of 1 or more) common electrodes are scanned, thereby preventing the deterioration of the liquid crystal and the image quality. Improve.

  FIG. 4 is an explanatory diagram of the selection voltages of the common electrodes COMp (0 ≦ p ≦ Q, p is an integer) to COMp + 3 of the liquid crystal panel 20 in the MLS driving method of simultaneous selection of four lines. FIG. 4 shows a selection voltage applied to the common electrodes COMp to COMp + 3 according to the polarity and the field period defined by the polarity inversion signal FR that is an internal signal of the liquid crystal driving device 100.

  When the polarity inversion signal FR is at the L level, the liquid crystal driving device 100 supplies the selection voltage to the corresponding common electrode and drives the corresponding segment electrode so that the applied voltage of the pixel to be driven becomes positive. Supply voltage. When the polarity inversion signal FR is at the H level, the liquid crystal driving device 100 supplies the selection voltage to the corresponding common electrode so that the applied voltage of the pixel to be driven has a negative polarity, and the corresponding segment electrode. The drive voltage is supplied to At this time, in the MLS driving method, a scanning pattern in each field period of the common electrodes selected simultaneously is determined. Therefore, in the 4-line simultaneous selection MLS driving method, the selection voltages V3 and MV3 are applied to the common electrodes COMp to COMp + 3 as shown in FIG.

  When n-line inversion driving is performed in the MLS driving method as described above, there are the following problems. Hereinafter, for convenience of explanation, an example in which the liquid crystal panel 20 having 76 lines is driven will be mainly described.

  FIG. 5 shows the selection voltages of the common electrodes COM0 to COM3 that are simultaneously selected when the n-line inversion drive is disabled. FIG. 5 shows selection voltages supplied to the common electrodes COM0 to COM3 in accordance with the polarity for each field period of one frame period when driving a 76-line liquid crystal panel. Although the common electrodes COM0 to COM3 are illustrated in FIG. 5, the other common electrodes that are simultaneously selected are also the same.

  When n-line inversion driving is set to disable, the polarity inversion period is 2 frames. Each common electrode is supplied with selection pulses of voltages V3 and MV3 during this polarity inversion period. The selection pulse of voltage V3 corresponds to a positive polarity pulse, and the selection pulse of voltage MV3 corresponds to a negative polarity positive pulse. Here, paying attention to the type of selection pulse, for each of the common electrodes COM0 to COM3, the selection pulse number of the voltage V3 is “4” and the selection pulse number of the voltage MV3 is “4”.

  FIG. 6 shows the selection voltages of the common electrodes COM0 to COM3 that are simultaneously selected when n-line inversion driving is enabled. FIG. 6 shows selection voltages supplied to the common electrodes COM0 to COM3 in accordance with the polarity for each field period of one frame period when driving a 76-line liquid crystal panel. Here, n is “5”, and 20 (= 5 × 4) line inversion driving is performed. In FIG. 6, the common electrodes COM <b> 0 to COM <b> 3 are illustrated, but the same applies to other common electrodes that are simultaneously selected.

  Accordingly, when the n-line inversion driving is set to enable, the polarity inversion period is 5 frames. Here, focusing on the type of selection pulse, for each of the common electrodes COM0 and COM2, the number of selection pulses of the voltage V3 is “9” and the number of selection pulses of the voltage MV3 is “11”. Further, for each of the common electrodes COM1 and COM3, the number of selection pulses of the voltage V3 is “11”, and the number of selection pulses of the voltage MV3 is “9”. That is, when the n-line inversion driving is enabled, the number of selection pulses of the voltage V3 and the number of selection pulses of the voltage MV3 are different depending on the common electrode. For this reason, when there is a bias potential shift, there is a problem that an effective voltage difference is generated according to the common electrode, and a dark and light stripe pattern is generated in the liquid crystal panel 20.

[Liquid crystal drive]
When n-line inversion driving is performed by the MLS driving method in which S (S is a natural number of 2 or more) lines are simultaneously selected, if the condition of the following equation (1) is satisfied, The number of negative positive pulses is equal. In equation (1), the duty of the liquid crystal panel is dt, and the natural number is d. That is, when the condition of the formula (1) is not satisfied, if there is a bias potential shift, a difference in effective voltage is generated according to the common electrode, and a light and dark stripe pattern is generated on the liquid crystal panel.
(1 / dt × d) / (n / S) = odd number (1)

  On the other hand, in the present embodiment, when the condition of Expression (1) is not satisfied, even if there is a bias potential shift, deterioration of image quality is suppressed without causing a light and dark stripe pattern on the liquid crystal panel 20. Specifically, when (reciprocal of duty dt of liquid crystal panel 20 × A) / (n / S) is an even number, the number of positive pulses applied to each common electrode of liquid crystal panel 20 and the negative electrode during the polarity inversion period Make the number of positive pulses equal. Here, A is the smallest natural number that makes the left side of the expression divisible. That is, the liquid crystal driving method in the present embodiment includes a positive polarity driving step and a negative polarity positive driving step. In the positive polarity driving step, the liquid crystal panel 20 is driven by n-line inversion driving so that the applied voltage of the pixels constituting the liquid crystal panel 20 is positive. In the negative polarity positive drive step, the liquid crystal panel 20 is driven by n-line inversion drive so that the applied voltage of the pixel becomes negative. When (the reciprocal of the duty of the liquid crystal panel 20 × A) / (n / S) is an even number, the number of positive pulses and the number of negative positive pulses applied to each common electrode of the liquid crystal panel during the polarity inversion period Make equal.

  More specifically, in the S (S is a natural number of 2 or more) line simultaneous selection driving method, the first field period to the Lth (first field period to Sth field periods divided into one frame period). The n-line inversion drive is performed in the field period of 1 ≦ L ≦ S−1, where L is a natural number. In addition, a dummy period corresponding to at least one horizontal scanning period is added in the (L + 1) -th field period to the S-th field period among the first field period to the S-th field period, and n-line inversion driving is performed. That is, n-line inversion driving is performed by adding at least one horizontal scanning period dummy period to at least one field period without adding a dummy period of one horizontal scanning period to all field periods. Thereby, even if it is the MLS driving method of 4 lines simultaneous selection, the polarity of the positive polarity pulse and the number of negative polarity pulses supplied to each common electrode can be made equal during the polarity inversion period. Become.

  FIG. 7 shows a flow chart of a liquid crystal driving method by the liquid crystal driving device 100 in the present embodiment.

  First, the liquid crystal drive device 100 waits for the start of one frame period (step ST10: N). When one frame period is started (step ST10: Y), when it is not a field period for adding a dummy period (step ST12: N), the liquid crystal drive device 100 drives the liquid crystal panel 20 by n-line inversion drive ( Step ST14, first driving step). When it is a field period to add a dummy period (step ST12: Y), the liquid crystal driving device 100 drives the liquid crystal panel 20 by n-line inversion driving including the dummy period (step ST16, second driving step). It is desirable that the field period for adding the dummy period is determined in advance.

  In step ST16, in the dummy period, the liquid crystal driving device 100 supplies a non-selection voltage (center voltage VC) to the common electrode of the liquid crystal panel 20, and supplies a given dummy voltage to the segment electrode of the liquid crystal panel 20. desirable. The dummy voltage is preferably an on-level or off-level voltage (voltages V1 and MV1 depending on the polarity).

  When there is a next field period following step ST14 or step ST16 (step ST18: Y), the liquid crystal driving device 100 returns to step ST12 and continues n-line inversion driving. That is, the liquid crystal driving device 100 performs n-line inversion in the first field period to the L-th field period among the first field period to the S-th field period obtained by dividing one frame period as the first driving step. The liquid crystal panel 20 can be driven by driving. Further, the liquid crystal driving device 100 performs a dummy for at least one horizontal scanning period in the (L + 1) -th field period to the S-th field period among the first field period to the S-th field period as the second driving step. The liquid crystal panel can be driven by n-line inversion driving for an additional period.

  Here, L is (S-1), and it is desirable to add a dummy period for one horizontal scanning period in step ST16. By doing so, it is possible to minimize the influence of contrast reduction due to the addition of the dummy period.

  When there is no next field period (step ST18: N) and there is a next frame period (step ST20: Y), the liquid crystal driving device 100 returns to step ST10 and continues driving the liquid crystal panel 20. In step ST20, when there is no next frame period (step ST20: N), the liquid crystal drive device 100 ends a series of processes (end).

  8 and 9 are explanatory views of the liquid crystal driving method in the present embodiment. FIGS. 8 and 9 show the polarity corresponding to the common electrode in each field period when driving the 76-line liquid crystal panel 20 when n is set to “20” in the 4-line simultaneous selection MLS driving method. Represent. 8 and 9, it is assumed that a dummy period is provided in the last field period of each frame. 8 and 9, “L” and “H” represent the logic level of the polarity inversion signal FR, “L” represents positive polarity, and “H” represents negative polarity. 8 shows the polarities from 1 to 5 frames, and FIG. 9 shows from 6 frames to 10 frames following FIG.

  The liquid crystal driving device 100 starts from the positive polarity in the field period “1” of the first frame, and performs n-line inversion driving for every 20 lines (corresponding to 5 blocks in the MLS driving method for simultaneous selection of 4 lines). Until the field period “4” of the first frame, the n-line inversion driving in each immediately preceding field period is continued. Therefore, for example, when 16 lines (4 blocks) of the common electrodes COM60 to COM75 are negative and the n-line inversion driving in the field period “1” is completed, the 4 lines (1 block) of the common electrodes COM0 to COM3 in the field period “2” are completed. ) Is driven as it is with negative polarity. Thereafter, the common electrodes COM4 to COM7 in the field period “2” are driven to be inverted to the positive polarity.

  Thus, when the field period “4”, which is the last field period of the first frame, is completed, a dummy period for one horizontal scanning period is added. Therefore, in one block of the common electrodes COM72 to COM75 in the field period “4”, the dummy period, and three blocks of the common electrodes COM0 to COM11 in the field period “1” of the second frame, the n-line inversion driving is performed with a negative polarity. Is called. In the five blocks of the common electrodes COM12 to COM31 in the field period “1”, the n-line inversion driving is performed with a positive polarity.

  When the field period “4”, which is the final field period of the second frame, is completed, a dummy period for one horizontal scanning period is added again. At this time, the n-line inversion drive is positive in three blocks of the common electrodes COM64 to COM75 in the field period “4”, the dummy period, and one block of the common electrodes COM0 to COM3 in the field period “1” of the third frame. Done.

  Similarly, from the sixth frame, n-line inversion driving is performed with the opposite polarity to that of the first frame. Therefore, from the 10th frame, n-line inversion drive is performed with the same polarity as the first frame, and the polarity inversion period is 10 frames.

  FIG. 10 is an explanatory diagram of the effect of the liquid crystal driving method in the present embodiment. FIG. 10 shows a selection voltage supplied to the common electrodes COM0 to COM3 in accordance with the polarity for each field period of one frame period when driving a 76-line liquid crystal panel when n is set to “20”. Represents. That is, the selection pulses output to the common electrodes COM0 to COM3 in the liquid crystal driving method described with reference to FIGS.

  As described above, the polarity inversion period is 10 frames. Here, paying attention to the type of selection pulse, for each of the common electrodes COM0 to COM3, the number of selection pulses (positive pulse) of the voltage V3 is “20” and the number of selection pulses of the voltage MV3 is “20”. In FIG. 10, the selection pulses of the common electrodes COM0 to COM3 are illustrated, but the same applies to the other common electrodes (for example, the common electrodes COM4 to COM7). Therefore, according to the present embodiment, there is no bias of the selection pulse corresponding to the common electrode, and even if there is a deviation of the bias potential, there is no difference in effective voltage depending on the common electrode, and the liquid crystal panel 20 is shaded. The striped pattern does not occur.

  The liquid crystal driving device 100 that realizes the liquid crystal driving method as described above can have the following configuration.

FIG. 11 shows a block diagram of a configuration example of the liquid crystal driving device 100 in the present embodiment. In FIG. 11, the pixel formation region 22 is also illustrated.
FIG. 12 is an explanatory diagram of common addresses and line addresses in the present embodiment.

  The liquid crystal driving device 100 includes a host processor interface 110, an oscillation circuit 112, a control circuit 114, a common address decoder 116, a common output arithmetic circuit 118, a common driver 120, and a page address control circuit 122. Yes. In addition, the liquid crystal driving device 100 includes a column address control circuit 124, a line address control circuit 126, an image data RAM 128, an image data latch circuit 130, an MLS decoder 132, and a segment driver 134. The image data RAM 128 functions as a frame memory (image data memory). The control circuit 114 includes a polarity inversion control circuit (polarity inversion control unit) 200. The driving unit in the present embodiment includes a common driver 120 and a segment driver 134, and may further include at least one of a common address decoder 116, a common output arithmetic circuit 118, and an MLS decoder 132.

  The host processor interface 110 performs input interface processing of input signals input from the host processor 30 via input terminals or input / output terminals of the liquid crystal driving device 100. The host processor interface 110 performs output interface processing of an output signal output to the host processor 30 via an output terminal or an input / output terminal included in the liquid crystal driving device 100.

  The oscillation circuit 112 generates an oscillation clock OSC serving as a reference for a display timing signal generated by the liquid crystal driving device 100 by an oscillation operation. For example, the control circuit 114 generates a plurality of types of display timing signals based on the oscillation clock OSC. The control circuit 114 generates a control signal for controlling each part of the liquid crystal driving device 100 such as the common address decoder 116. The polarity inversion control circuit 200 performs polarity inversion control of a drive signal supplied to the liquid crystal panel 20 (specifically, the pixel formation region 22) by the common driver 120, the segment driver 134, and the like. The driving signal includes a selection pulse output from the common driver 120 to the common electrode, and a liquid crystal driving voltage output from the segment driver 134 to the segment electrode.

  The common address decoder 116 decodes common addresses corresponding to a plurality of common electrodes generated in the control circuit 114 and simultaneously selected in the MLS drive. The decoding result is output to the common driver 120. A common address is assigned to each of a plurality of common electrodes that are simultaneously selected, and a corresponding common electrode is selected by designating the common address when performing MLS driving.

  The common output arithmetic circuit 118 controls the output level of the common output based on the polarity inversion signal FR generated in the control circuit 114 and the field identification signals F1 and F2 for identifying the MLS drive pattern.

  The common driver 120 controls selection / non-selection of the common output based on the decoding result of the common address decoder 116, and outputs the output level generated by the common output arithmetic circuit 118 as the selected common output.

  The page address control circuit 122 controls a page address for accessing image data RAM 128 for image data input from the host processor 30 via the host processor interface 110. The page address is defined with the bus width of image data input from the host processor 30 as an access unit.

  The column address control circuit 124 controls a column address for accessing image data RAM 128 for image data input from the host processor 30 via the host processor interface 110. The column address is defined corresponding to the segment electrode in the pixel formation region 22.

  The line address control circuit 126 controls a line address that specifies a read line in the image data stored in the image data RAM 128. The line address is defined corresponding to the common electrode in the pixel formation region 22. The common address and line address in this embodiment are defined as shown in FIG. For example, when the control circuit 114 outputs the common address “0”, the common electrodes COM0 to COM3 are simultaneously selected. At this time, among the image data stored in the image data RAM 128, the image data corresponding to the line addresses 0 to 3 is read. Similarly, when the control circuit 114 outputs the common address “1”, the common electrodes COM4 to COM7 are simultaneously selected. At this time, image data corresponding to the line addresses 4 to 7 is read out from the image data stored in the image data RAM 128. As described above, the common address can be specified in units of blocks in which four lines of common electrodes selected simultaneously are defined as one block, and the line address is also uniquely determined.

  In FIG. 11, the image data RAM 128 has a storage area in which image data of each pixel is stored corresponding to the arrangement of the pixels in the pixel formation area 22. Each storage area is specified by a page address and a column address. As a result, the image data is written in the image data RAM 128 in an area specified by the page address and the column address. On the other hand, image data is read from the image data RAM 128 in units of one line.

  The image data latch circuit 130 latches the image data read out from the image data RAM 128 line by line for four lines.

  The MLS decoder 132 decodes the image data and a display timing signal generated by the control circuit 114 and used for MLS driving. More specifically, the MLS decoder 132 performs segment output based on the image data latched by the image data latch circuit 130 and the polarity inversion signal FR and the field identification signals F1 and F2 generated by the control circuit 114. Control the output level. The decoding result of the MLS decoder 132 is output to the segment driver 134.

  The segment driver 134 outputs the output level decoded by the MLS decoder 132 to the segment electrode based on the decoding result of the MLS decoder 132. The segment driver 134 is controlled to turn off the display by outputting a given output level to the segment electrode regardless of the decoding result of the MLS decoder 132 by the display off signal XDOF generated by the control circuit 114. be able to. In this embodiment, the display is turned off by outputting to the segment electrode an output level that is the same potential as the common electrode by the display off signal XDOF.

  Each field period provided within one frame period in the MLS driving method is specified by the field identification signals F1 and F2 in the liquid crystal driving device 100. The liquid crystal driving device 100 outputs the voltage V3 or the voltage MV3 to each common electrode for each field period corresponding to the four states represented by the 2-bit field identification signals F1 and F2. An output pattern to each common electrode in each field period is defined by an orthogonal function system as a selection pattern. The liquid crystal driving device 100 appropriately selects one of the three types of driving voltages V3, VC, and MV3 in accordance with a selection pattern defined by a predetermined orthogonal function system, and applies each to the simultaneously selected common electrodes. It has become.

  Each field period is divided into a plurality of sub-selection periods assigned to a plurality of common electrodes selected simultaneously. Among the plurality of sub-selection periods obtained by dividing the field period “1”, the following operation is performed in the sub-selection period in which the common electrodes COM0 to COM3 selected at the same time are selected. The liquid crystal driving device 100 selects one of the voltages (V2, V1, VC, MV1, MV2) and applies the selected voltage to the segment electrode SEG0. At this time, the liquid crystal driving device 100 applies a voltage according to the number of polarity mismatches between the display pattern of each dot corresponding to the intersection position with each of the common electrodes COM0 to COM3 selected simultaneously with the segment electrode SEG0. select. Similarly, the selected voltage is applied to the other segment electrodes.

  Next, among the plurality of sub-selection periods obtained by dividing the field period “1”, the number of inconsistencies in the column of each segment electrode is determined in the sub-selection period in which the next simultaneously selected common electrode is selected. Apply the voltage data. Thus, when the above procedure is repeated for all the common electrodes, the operation in the field period “1” is completed. Similarly, in the field period “2” and thereafter, when the above procedure is repeated for all the common electrodes, one frame period is completed, thereby displaying one screen.

  In the liquid crystal drive device 100 having such a configuration, the common driver 120 scans the common electrode with a selection pattern corresponding to each field over a plurality of fields in a block unit in which a plurality of common electrodes to be simultaneously selected are one block. . The segment driver 134 drives the segment electrodes with image data corresponding to a plurality of common electrodes that are simultaneously selected and a driving voltage corresponding to the selection pattern. This drive voltage is obtained as a result of decoding based on the image data and the display timing signal.

  FIG. 13 shows a block diagram of a configuration example of the polarity inversion control circuit 200 of FIG.

  The polarity inversion control circuit 200 includes a field number counter 210, a common address counter 220, and a line address counter 230. The polarity inversion control circuit 200 includes an n-line inversion number register 240, an n-line inversion number counter 250, and a polarity register 260.

  The field number counter 210 counts the number of field periods obtained by dividing one frame period. The common address counter 220 counts a common address count value corresponding to a common address that specifies four lines of common electrodes that are simultaneously selected, and outputs a common address corresponding to the common address count value. The line address counter 230 counts the line address count value corresponding to the line address corresponding to each common electrode selected at the same time, and outputs the line address corresponding to the line address count value.

  In the n-line inversion number register 240, setting information corresponding to the number n of lines whose polarity is inverted is set by the host processor 30. That is, the number n of lines whose polarity is inverted in the n-line inversion drive is variably configured. The n-line inversion number counter 250 counts the number of lines whose polarity is inverted by n-line inversion driving. The polarity register 260 holds a register value generated by each part constituting the polarity inversion control circuit 200 and outputs a polarity inversion signal FR corresponding to the register value.

  Hereinafter, an operation example of each part constituting the polarity inversion control circuit 200 will be described. Hereinafter, an example will be described in which the polarity inversion control circuit 200 performs the polarity inversion control in the n-line inversion driving by the MLS driving method of the 4-line simultaneous selection.

FIG. 14 shows a flowchart of an operation example of the field number counter 210.
The field number counter 210 receives a vertical synchronization signal VSYNC and a field signal FIELD. At the start timing of the field period, the field signal FIELD is set to “1”. In FIG. 14, the count value of the field number counter 210 is expressed as a field number count value.

  When the vertical synchronization signal VSYNC becomes “1” (step ST30: Y), the field number counter 210 initializes the count value to “0” (step ST32), and returns to step ST30 (return). When the vertical synchronizing signal VSYNC is “0” (step ST30: N) and the field signal FIELD is “1” (step ST34: Y), the field number counter 210 increments the count value (step ST36). Thereafter, the process returns to step ST30 (return).

  When the field signal FIELD is "0" in step ST34 (step ST34: N), the field number counter 210 returns to step ST30 (return) without updating the count value (step ST38).

  As described above, the field number counter 210 can increment the count value initialized for each vertical scanning period in synchronization with the field signal FIELD. The count value “0” of the field number counter 210 corresponds to the field period “1”, the count value “1” corresponds to the field period “2”, the count value “2” corresponds to the field period “3”, The count value “3” corresponds to the field period “4”.

FIG. 15 shows a flowchart of an operation example of the common address counter 220.
The common address counter 220 receives the count value of the field number counter 210, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the field signal FIELD. In FIG. 15 as well, as in FIG. 14, the count value of the field number counter 210 is expressed as a field number count value.

  When the vertical synchronization signal VSYNC is “1” or the field signal FIELD is “1” (step ST50: Y), the common address counter 220 sets the common address to the start address “0” (step ST52), and proceeds to step ST50. Return (return). When the vertical synchronization signal VSYNC is not “1” or the field signal FIELD is not “1” (step ST50: N), the common address counter 220 determines update of the count value corresponding to the common address based on the horizontal synchronization signal HSYNC. (Step ST54).

  When the horizontal synchronization signal HSYNC is “1” (step ST54: Y), the common address counter 220 has a count value of the field number counter 210 of “3” and the common address is a common address corresponding to the number of display lines. It is determined whether or not the address is an end address (step ST56). When the count value of the field number counter 210 is “3” and it is determined that the common address is an end address (step ST56: Y), the common address counter 220 sets a dummy common address as the common address ( Step ST58). Thereafter, the process returns to step ST50 (return). Here, the dummy common address is an address that cannot be decoded by the common address decoder 116, and a common address that does not exist is adopted. The common address decoder 116 inserts a dummy period by decoding so that all the common electrodes output a voltage VC that is a non-selection voltage when a dummy common address is given.

  When the count value of the field number counter 210 is “3” and it is not determined that the common address is a given end address (step ST56: N), the common address counter 220 increments the common address (step ST60). ). Thereafter, the process returns to step ST50 (return). Specifically, the common address counter 220 increments a count value corresponding to the common address.

  When the horizontal synchronization signal HSYNC is not “1” in Step ST54 (Step ST54: N), the common address counter 220 returns to Step ST50 without updating the count value corresponding to the common address (Step ST62) (Return). ).

  As described above, the common address counter 220 can generate a common address having a dummy common address corresponding to the dummy period while updating the count value corresponding to the common address. The common driver (common electrode driving unit) 120 receiving such a common address can scan the common electrode while inserting a dummy period in the scanning period of the common electrode in the pixel formation region 22.

FIG. 16 shows a flowchart of an operation example of the line address counter 230.
The line address counter 230 receives the count value of the field number counter 210, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the field signal FIELD. Also in FIG. 16, the count value of the field number counter 210 is expressed as a field number count value, as in FIG. 14.

  When the vertical synchronization signal VSYNC is “1” or the field signal FIELD is “1” (step ST70: Y), the line address counter 230 sets the line address to the start address “0” (step ST72), and the process proceeds to step ST70. Return (return). When the vertical synchronization signal VSYNC is not "1" or the field signal FIELD is not "1" (step ST70: N), the line address counter 230 determines update of the count value corresponding to the line address based on the horizontal synchronization signal HSYNC. (Step ST74).

  When the horizontal synchronization signal HSYNC is “1” (step ST74: Y), the line address counter 230 has a count value of the field number counter 210 of “3” and the line address of the line address corresponding to the liquid crystal panel 20. It is determined whether or not the address is an end address (step ST76). When it is determined that the count value of the field number counter 210 is “3” and the line address is an end address (step ST76: Y), the line address counter 230 sets a dummy line address as the line address ( Step ST78). Thereafter, the process returns to step ST70 (return). Here, a non-existent line address is adopted as the dummy line address, and image data corresponding to the dummy line address is used in the dummy period. Thereby, a dummy voltage corresponding to the image data can be supplied to the segment electrode. The dummy line address may be an arbitrary address, and a given on voltage or off voltage may be supplied to the segment electrode as a dummy voltage regardless of the dummy line address in the dummy period.

  When the count value of the field number counter 210 is “3” and it is not determined that the line address is a given end address (step ST76: N), the line address counter 230 increments the line address (step ST80). ). Thereafter, the process returns to step ST70 (return). Specifically, the line address counter 230 increments the count value corresponding to the line address.

  When the horizontal synchronization signal HSYNC is not “1” in step ST74 (step ST74: N), the line address counter 230 determines whether or not the line address is a dummy line address (step ST82). When the line address is not a dummy line address (step ST82: N), the line address counter 230 increments the line address (step ST80) and returns to step ST70 (return). When the line address is a dummy line address (step ST82: Y), the line address counter 230 returns to step ST70 (return) without updating the count value corresponding to the line address (step ST84).

  As described above, the line address counter 230 can generate a line address including a dummy line address corresponding to the dummy period while updating the count value corresponding to the line address. Based on the image data read using such a line address, the segment driver (segment electrode drive unit) 134 drives the segment electrode in the pixel formation region 22.

FIG. 17 shows a flowchart of an operation example of the n-line inversion number counter 250.
The n-line inversion number counter 250 receives the horizontal synchronization signal HSYNC and the register value of the n-line inversion number register 240. In FIG. 17, the count value of the n-line inversion number counter 250 is expressed as an n-line inversion number count value.

  When the horizontal synchronization signal HSYNC is “1” (step ST90: Y), the n-line inversion number counter 250 determines whether or not the count value is (polarity inversion line number / 4-1) (step ST92). . The number of polarity inversion lines in step ST92 is set by the register value of the n line inversion number register 240. When it is determined that the count value is (polarity inversion line number / 4-1) (step ST92: Y), the n-line inversion number counter 250 initializes the count value to “0” (step ST94). Return to ST90 (return). When it is determined that the count value is not (polarity inversion line number / 4-1) (step ST92: N), the n-line inversion number counter 250 increments the count value (step ST96), and returns to step ST90 ( return).

  In step ST90, when the horizontal synchronization signal HSYNC is not “1” (step ST90: N), the n-line inversion counter 250 does not update the count value (step ST98) and returns to step ST90 (return).

  As described above, the n-line inversion number counter 250 can count the number of lines for n-line inversion driving for each number of polarity inversion lines set in the n-line inversion number register 240.

FIG. 18 shows a flowchart of an operation example of the polarity register 260.
The polarity register 260 receives the horizontal synchronization signal HSYNC and the count value of the n-line inversion number counter 250. In FIG. 18, the count value of the n-line inversion number counter 250 is expressed as an n-line inversion number count value, and the register value of the polarity register 260 is expressed as a polarity register value.

  When the horizontal synchronization signal HSYNC is “1” (step ST100: Y), the polarity register 260 determines whether or not the count value of the n-line inversion number counter 250 is (polarity inversion line number / 4-1). (Step ST102). When it is determined that this count value is (number of polarity inversion lines / 4-1) (step ST102: Y), the polarity register 260 reverses the register value of the polarity register 260 to the polarity inversion signal FR of the logic level after inversion. Is output (step ST104). In step ST104, the value obtained by inverting the register value of the polarity register 260 is set in the polarity register 26 again. Thereafter, the process returns to step ST100 (return).

  When it is determined that the count value is not (polarity inversion line number / 4-1) (step ST102: N), or when the horizontal synchronization signal HSYNC is not “1” in step ST100 (step ST100: N), the polarity The register 260 outputs a polarity inversion signal FR having a logic level corresponding to the register value of the polarity register 260 (step ST106). Thereafter, the process returns to step ST100 (return).

  As described above, the polarity register 260 can output the polarity inversion signal FR in accordance with the number of lines n whose polarity is to be inverted.

  FIG. 19 shows a timing chart of an operation example of the polarity inversion control circuit 200. FIG. 19 shows an example of timing when the number of display lines is “16” and n is “12” (= 3 blocks).

  When the vertical synchronization signal VSYNC becomes “1”, each field period obtained by dividing one vertical scanning period is started. In each field period, one horizontal scanning period is started each time the horizontal synchronization signal HSYNC becomes “1”. The count value of the common address counter 220 is updated every horizontal scanning period. Here, when the field period “4” which is the final field period of one frame is reached, the common address becomes the end address with the count value “3” of the common address counter 220, and a dummy period for one horizontal scanning period is inserted. . In the dummy period, the line address is set to the dummy line address.

  When the dummy period ends, the field period “1” of the next frame is started. At this time, the count value of the common address counter 220 and the count value of the line address counter 230 are initialized.

  As described above, the polarity inversion control circuit 200 can output the polarity inversion signal FR in which the inversion of the logic level is repeated according to the number of lines n, while inserting a dummy period. Thereby, the polarity inversion control circuit 200 performs control to invert the polarity of the voltage between the common electrode and the segment electrode.

  FIG. 20 shows an example of the drive timing of the liquid crystal drive device 100 in the present embodiment. FIG. 20 shows the waveform of the common electrode and the waveform of the segment electrode under the same conditions as in FIG. The waveform of the segment electrode is a waveform when all the lights are on. Further, in the dummy period, it is assumed that the drive voltage for turning on all is supplied to the segment electrode SEGk.

  As shown in FIG. 20, four lines of common electrodes are simultaneously selected, and a selection voltage corresponding to the selection pattern is supplied. In the field period “4” of the first frame, a dummy period is inserted. In the dummy period, as described above, the common address counter 220 sets the dummy common address to the common address and supplies the center voltage VC, which is a non-selection voltage, to all the common electrodes. In addition, the line address counter 230 drives each segment electrode with, for example, an ON voltage (dummy voltage in a broad sense) in the dummy period. That is, the driving unit of the liquid crystal driving device 100 supplies a non-selection voltage to the common electrode of the liquid crystal panel and supplies a given dummy voltage to the segment electrode of the liquid crystal panel in the dummy period.

  When the dummy period ends, the field period “1” of the next frame is started. At this time, the common electrode and the segment electrode are continuously subjected to n-line inversion driving by the MLS driving method in which four lines are simultaneously selected.

  As described above, in the present embodiment, the polarity of every n lines in the first field period to the Lth field period among the first field period to the Sth field period obtained by dividing one frame period. An n-line inversion drive for inversion control is performed. Then, in the (L + 1) -th field period to the S-th field period, n-line inversion driving is performed by adding at least one dummy period corresponding to the horizontal scanning period. As a result, the number of positive pulses and the number of negative positive pulses can be made equal between polarity inversion periods, and even if there is a deviation in bias potential, there is no difference in effective voltage depending on the common electrode. In the liquid crystal panel 20, it is possible to suppress the occurrence of light and shade stripe patterns.

  At this time, as shown in FIG. 20, L is (S-1), and it is desirable to perform n-line inversion driving by adding a dummy period for one horizontal scanning period. By doing so, it is possible to minimize a decrease in contrast.

〔Electronics〕
The liquid crystal driving device or the liquid crystal panel 20 or the liquid crystal device 10 to which the liquid crystal driving device is applied in the above embodiment can be applied to the following electronic devices.

  21A and 21B are perspective views of the configuration of an electronic device to which the present embodiment is applied. FIG. 21A is a perspective view of a configuration of a mobile personal computer. FIG. 21B illustrates a perspective view of a structure of a mobile phone.

  A personal computer 800 illustrated in FIG. 21A includes a main body portion 810 and a display portion 820. As the display unit 820, the liquid crystal panel 20 or the liquid crystal device 10 in the above embodiment is applied. The main body 810 includes a host processor, and the main body 810 is provided with a keyboard 830. That is, the personal computer 800 includes at least the liquid crystal driving device 100 in the above-described embodiment. The operation information via the keyboard 830 is analyzed by the host processor, and an image is displayed on the display unit 820 according to the operation information.

  A cellular phone 900 illustrated in FIG. 21B includes a main body portion 910 and a display portion 920. As the display unit 920, the liquid crystal panel 20 or the liquid crystal device 10 in the above embodiment is applied. The main body 910 includes a host processor, and the main body 910 is provided with a keyboard 930. That is, the mobile phone 900 includes the liquid crystal driving device 100 in the above embodiment. Operation information via the keyboard 930 is analyzed by the host processor, and an image is displayed on the display unit 920 in accordance with the operation information.

  Note that the electronic device to which the above embodiment or embodiment is applied is not limited to the electronic devices shown in FIGS. 21A and 21B. For example, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, POS (Point of sale systems ) Devices such as terminals, printers, scanners, copiers, video players and touch panels.

  The liquid crystal driving method, the liquid crystal driving device, the liquid crystal device, the electronic apparatus, and the like according to the present invention have been described based on the above embodiments, but the present invention is not limited to the above embodiments. For example, the present invention can be implemented in various modes without departing from the gist thereof, and the following modifications are possible.

  (1) In the above embodiment, an example in which the liquid crystal driving device is driven by the MLS driving method has been described, but the present invention is not limited to this.

  (2) In the above embodiment, the MLS driving method for simultaneously selecting four lines has been described as an example, but the present invention is not limited to the number of simultaneously selected lines. Further, the present invention is not limited to the number of display lines of the liquid crystal panel described in the above embodiment and the number of lines n to be polarity-inverted in n-line inversion driving. Furthermore, the present invention is not limited to the common electrode selection pattern described in the above embodiment.

  (3) Although the polarity inversion control circuit 200 has been described as having the configuration of FIG. 13 in the above embodiment, the present invention is not limited to the configuration of the polarity inversion control circuit 200.

  (4) In the above embodiment, the line address counter 230 has been described as generating a dummy line address, but the present invention is not limited to this. The line address counter 230 may generate an arbitrary line address, and for example, the latch function of the image data latch circuit 130 may be disabled in the dummy period.

  (5) In the above embodiment, the liquid crystal driving method, the liquid crystal driving device, the liquid crystal device, and the electronic apparatus have been described. However, the present invention is not limited to this, for example, by the liquid crystal driving method according to the present invention. The image display method of the liquid crystal panel implement | achieved etc. may be sufficient.

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal device, 20 ... Liquid crystal panel, 22 ... Pixel formation area,
30 ... Host processor, 40 ... Power supply circuit, 100 ... Liquid crystal drive,
110: Host processor interface 112: Oscillator circuit,
114: Control circuit, 116: Common address decoder,
118 ... Common output arithmetic circuit, 120 ... Common driver,
122: Page address control circuit, 124 ... Column address control circuit,
126: Line address control circuit, 128: Image data RAM,
130: Image data latch circuit, 132: MLS decoder,
134 ... segment driver 200 ... polarity inversion control circuit,
210 ... Field number counter, 220 ... Common address counter,
230 ... line address counter, 240 ... n line inversion number register,
250 ... n-line inversion counter, 260 ... Polarity register,
800 ... Personal computer, 810, 910 ... Main unit,
820, 920 ... display unit, 830, 930 ... keyboard, 900 ... mobile phone,
COM0 to COMQ: common electrode, FIELD: field signal,
FR: polarity inversion signal, HSYNC: horizontal synchronization signal,
SEG0 to SEGR: Segment electrode, VSYNC: Vertical synchronization signal

Claims (10)

A liquid crystal driving method for driving a liquid crystal panel by S (S is a natural number of 2 or more) line simultaneous selection driving method,
N lines for which polarity inversion control is performed for each n (n is a natural number) line in the first field period to the S-1 field period among the first field period to the Sth field period obtained by dividing one frame period. A first driving step of driving the liquid crystal panel by inversion driving;
A second driving step of adding a dummy period for at least one horizontal scanning period in the S-th field period and driving the liquid crystal panel by n-line inversion driving,
(Reciprocal number of duty of the liquid crystal panel × A) / (n / S) (A is the smallest natural number that can be divided by the equation) is an even number , and is applied to each common electrode of the liquid crystal panel during the polarity inversion period A liquid crystal driving method characterized in that the number of positive and negative pulses made equal is equal. In claim 1,
In the second driving step,
A liquid crystal driving method, wherein a non-selection voltage is supplied to a common electrode of the liquid crystal panel and a given dummy voltage is supplied to a segment electrode of the liquid crystal panel in the dummy period. In claim 1 or 2,
In the second driving step, the dummy period for one horizontal scanning period is added. In any one of Claims 1 thru | or 3,
A liquid crystal driving method characterized in that the number of lines n for polarity inversion is variably configured. A liquid crystal driving device for driving a liquid crystal panel,
A driving unit for driving the liquid crystal panel by S (S is a natural number of 2 or more) line simultaneous selection driving method;
A polarity inversion control unit that performs polarity inversion control of a drive signal supplied to the liquid crystal panel by the drive unit,
The drive unit is
Among the first field period to the Sth field period obtained by dividing one frame period, the polarity inversion control is performed for each n (n is a natural number) line in the first field period to the S-1 field period. Performing line inversion driving, adding a dummy period for at least one horizontal scanning period in the S-th field period, and performing the n line inversion driving,
(Reciprocal number of duty of the liquid crystal panel × A) / (n / S) (A is the smallest natural number that can be divided by the equation) is an even number , and is applied to each common electrode of the liquid crystal panel during the polarity inversion period A liquid crystal driving device characterized in that the number of positive and negative pulses made equal is equal. In claim 5,
The drive unit is
A liquid crystal driving device, wherein a non-selection voltage is supplied to a common electrode of the liquid crystal panel and a given dummy voltage is supplied to a segment electrode of the liquid crystal panel in the dummy period. In claim 5 or 6,
The liquid crystal driving device according to claim 1, wherein the driving unit performs the n-line inversion driving by adding the dummy period for one horizontal scanning period. In any of claims 5 to 7,
Including an n-line inversion number register in which setting information corresponding to the number of lines to be polarity-inverted is set;
The drive unit is
The liquid crystal driving device according to claim 1, wherein the n line inversion driving is performed for each number of lines corresponding to setting information set in the n line inversion number register. A liquid crystal driving device according to any one of claims 5 to 8,
And a liquid crystal panel driven by the liquid crystal driving device.   An electronic apparatus comprising the liquid crystal driving device according to claim 5.

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