JP2012053117A - Liquid crystal driver, liquid crystal display device, electronic equipment and liquid crystal driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driver, a liquid crystal display device or the like improving cross-talk caused by polarity inversion driving according to display contents.SOLUTION: A liquid crystal driver includes: a scan controller for inserting a dummy period within a common electrode scanning period of a liquid crystal display device; a common electrode driver for rendering common electrodes non-selective during the dummy period while scanning the common electrodes within the scanning period; a segment electrode driver for driving segment electrodes based on predetermined dummy data during the dummy period while driving the segment electrodes of the liquid crystal display device based on image data corresponding to the common electrodes scanned by the common electrode driver; and a polarity inversion controller for performing control so as to invert a voltage polarity between the common electrodes driven by the common electrode driver and the segment electrodes driven by the segment electrode driver for each predetermined number of polarity inversion line.

Description

  The present invention relates to a liquid crystal driving device, a liquid crystal display device, an electronic apparatus, a liquid crystal driving method, and the like.

  Conventionally, this type of liquid crystal display device includes a plurality of common electrodes and a plurality of segment electrodes provided so as to cross the plurality of common electrodes, and at the intersections of the common electrodes and the segment electrodes. Correspondingly, pixels are formed. The liquid crystal drive device displays an image on the liquid crystal display device by scanning a plurality of common electrodes of the liquid crystal display device line-sequentially in a predetermined direction and driving the segment electrodes with a drive voltage corresponding to the image data.

  However, when scanning is simply line-sequentially, crosstalk occurs in the common electrode and segment electrode driven by the liquid crystal driving device, and a desired voltage cannot be supplied to the common electrode or segment electrode at a desired timing. Cause deterioration. Therefore, the liquid crystal display device is driven by various driving methods without simply scanning the liquid crystal display device in line-sequential manner, thereby preventing image quality degradation caused by various factors such as crosstalk. Yes.

  For example, Patent Document 1 discloses a technique in which a common electrode of a liquid crystal display device is scanned in either an interlace scanning mode or a progressive scanning mode. In the interlaced scanning mode, odd-numbered common electrodes are continuously scanned, and then even-numbered common electrodes are continuously scanned. For example, Patent Document 2 discloses a technique for realizing pseudo interlace scanning even when a wiring of a liquid crystal display device has a one-side extraction structure by adding a pulse signal with a short interval to a scanning shift clock signal. Is disclosed. Further, for example, Patent Document 3 discloses a technique that can be selected from line sequential scanning and interlace scanning in which a common electrode is scanned over one or more lines.

JP 2010-39464 A JP 2000-20032 A JP 2001-282203 A

  By the way, the manner of occurrence of crosstalk changes depending on the display contents. Therefore, the image quality cannot be improved even if the interlace scanning is simply performed regardless of the image. In addition, since crosstalk occurs not only between adjacent electrodes but also between the common electrode and the segment electrode, it is considered that image quality may be deteriorated due to crosstalk caused by polarity inversion driving performed in liquid crystal driving. It is done.

  The techniques disclosed in Patent Document 1 and Patent Document 3 only perform interlaced scanning that skips one or more lines regardless of the image, and prevents deterioration in image quality due to crosstalk caused by polarity inversion driving performed in liquid crystal driving. Can not do it. Further, since the technique disclosed in Patent Document 2 is pseudo interlaced scanning, there is a problem in that if the number of interlaced lines is increased, waveform distortion occurs and the image quality is affected.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, it is possible to provide a liquid crystal driving device, a liquid crystal display device, an electronic apparatus, a liquid crystal driving method, and the like that improve crosstalk due to polarity inversion driving according to display contents.

  (1) According to one embodiment of the present invention, a liquid crystal driving device that drives a passive liquid crystal display device includes: a scanning control unit that inserts a dummy period within a scanning period of a common electrode of the liquid crystal display device; And scanning the common electrode and deselecting the common electrode in the dummy period, and the liquid crystal display device based on image data corresponding to the common electrode scanned by the common electrode driving unit A segment electrode driving unit that drives the segment electrode based on given dummy data, a common electrode driven by the common electrode driving unit, and a segment electrode driving unit. Polarity that controls the reversal of the polarity of the voltage between the driven segment electrodes for a given number of polarity reversal lines Rolling and a control unit.

  In this aspect, when the passive liquid crystal display device is driven while inverting the polarity, a dummy period is inserted in the scanning period of the common electrode. In the dummy period, the common electrode is in a non-selected state, and the segment electrode is given a driving voltage based on given dummy data. For this reason, when the waveform of the segment electrode drive voltage becomes dull or the potential fluctuation of the common electrode due to the potential fluctuation of the segment electrode occurs, the effective voltage can be adjusted by the drive voltage in the dummy period, and image quality degradation is easy. Can be suppressed.

  (2) In the liquid crystal driving device according to the second aspect of the present invention, in the first aspect, the scanning control unit is a dummy in which a set value corresponding to the insertion position of the dummy period in the scanning period is set. Including an insertion register, the common electrode driving unit deselects the common electrode in the dummy period corresponding to the setting value of the dummy insertion register, and the segment electrode driving unit corresponds to the setting value of the dummy insertion register In the dummy period, the segment electrode is driven based on the dummy data.

  According to this aspect, since the insertion position of the dummy period can be changed according to the setting value of the dummy insertion register, it is possible to easily suppress the deterioration of the image quality due to the crosstalk according to the display content. become.

  (3) A liquid crystal driving device according to a third aspect of the present invention includes the image data memory in which the image data and the dummy data are buffered in the first aspect or the second aspect, and the segment electrode driving The unit drives the segment electrode based on the dummy data read from the image data memory during the dummy period.

  In this embodiment, dummy data is buffered in the image data memory, and the segment electrode driving unit drives the segment electrode based on the dummy data in the dummy period. This makes it possible to vary the potential for each segment electrode in accordance with the display contents without uniformly setting the entire line as an on pixel or an off pixel, and to finely adjust the change in effective voltage caused by crosstalk. become.

  (4) In the liquid crystal drive device according to a fourth aspect of the present invention, in any one of the first to third aspects, the dummy data is a reverse data of image data corresponding to a scanning period immediately before insertion. Including.

  According to this aspect, the effective voltage due to crosstalk can be reliably adjusted.

  (5) In the liquid crystal driving device according to the fifth aspect of the present invention, in any one of the first to fourth aspects, the dummy data is such that one line is all on or all off in the dummy period. It is data.

  According to this aspect, the effective voltage due to the crosstalk can be adjusted by the dummy data with simple control.

  (6) In the liquid crystal driving device according to a sixth aspect of the present invention, in the first aspect, the scanning control unit inserts any part of the scanning period of the common electrode as the dummy period, The common electrode driving unit scans the common electrode corresponding to the scanning period inserted by the scanning control unit, and the segment electrode driving unit is based on image data corresponding to the scanning period inserted by the scanning control unit. The segment electrode is driven.

  According to this aspect, a scanning period different from the scanning order is inserted in the scanning period of the common electrode. As a result, when there is almost no continuity between the image in the scanning period of the original common electrode and the image in the inserted scanning period, the output potential of the segment electrode of the mark portion is changed while preventing a decrease in contrast. Will be able to. This makes it possible to adjust the change in effective voltage due to crosstalk due to polarity inversion driving.

  (7) In the liquid crystal driving device according to a seventh aspect of the present invention, in the sixth aspect, the scanning control unit is configured to insert the set value corresponding to the insertion position of the dummy period within the scanning period. Including an original register and an insertion destination register in which a setting value corresponding to any part of the scanning period of the common electrode inserted as the dummy period is set, and the common electrode driving unit includes: The common electrode corresponding to the setting value of the insertion destination register is scanned during the dummy period corresponding to the setting value, and the segment electrode driving unit is configured to insert the insertion into the dummy period corresponding to the setting value of the insertion source register. The segment electrode is driven based on the image data corresponding to the set value of the previous register.

  According to this aspect, since the insertion source register and the insertion destination register are provided, an arbitrary scanning period can be inserted within an arbitrary scanning period of the common electrode, and crosstalk can be reduced according to display contents. This can be realized while preventing a decrease in contrast.

  (8) A liquid crystal driving device according to an eighth aspect of the present invention includes, in the first to seventh aspects, a polarity inversion line number setting register in which a setting value corresponding to the number of polarity inversion lines is set. The common electrode driver scans the common electrode using a selection voltage obtained by reversing the polarity for each number of polarity inversion lines corresponding to a setting value of the polarity inversion line number setting register, and the segment electrode driving unit Then, the segment electrode is driven using a drive voltage in which the polarity is inverted for each number of polarity inversion lines corresponding to the set value of the polarity inversion line number setting register.

  According to this aspect, since the number of polarity inversion lines can be set, even when the waveform of the drive voltage of the segment electrode becomes dull or the potential fluctuation of the common electrode due to the potential fluctuation of the segment electrode occurs, Can be adjusted easily.

  (9) In the liquid crystal driving device according to a ninth aspect of the present invention, in any one of the first to eighth aspects, the common electrode driving unit includes a plurality of common electrodes selected simultaneously as one block. Scanning the common electrode of the liquid crystal display device with a selection pattern corresponding to each field over a plurality of fields in a block unit, and the segment electrode driving unit includes image data corresponding to the plurality of common electrodes selected simultaneously, and The segment electrode of the liquid crystal display device is driven with a driving voltage corresponding to the selection pattern, and the number of polarity inversion lines is a multiple of the number of the plurality of common electrodes selected at the same time.

  According to this aspect, even when the liquid crystal display device is driven by the MLS (Multi Line Selection) driving method, the waveform fluctuation of the drive voltage of the segment electrode and the potential fluctuation of the common electrode caused by the potential fluctuation of the segment electrode Even if this occurs, it can be easily adjusted according to the image.

  (10) In a tenth aspect of the present invention, the liquid crystal display device scans the plurality of common electrodes, the plurality of segment electrodes provided to intersect the plurality of common electrodes, and the plurality of common electrodes, A liquid crystal driving device according to any one of the first to ninth aspects, which drives the plurality of segment electrodes.

  According to this aspect, it is possible to provide a liquid crystal display device that improves crosstalk due to polarity inversion driving according to display contents.

  (11) In an eleventh aspect of the present invention, the electronic device includes the liquid crystal display device according to the tenth aspect.

  According to this aspect, it is possible to provide an electronic apparatus to which a liquid crystal display device that improves crosstalk due to polarity inversion driving is applied according to display contents.

  (12) According to a twelfth aspect of the present invention, in a liquid crystal driving method for driving a passive liquid crystal display device, a scanning control step of inserting a dummy period within a scanning period of a common electrode of the liquid crystal display device, and the scanning Scanning the common electrode within a period and deselecting the common electrode in the dummy period, and the liquid crystal based on image data corresponding to the common electrode scanned in the common electrode driving step A segment electrode driving step of driving a segment electrode of the display device and driving the segment electrode based on given dummy data in the dummy period, a common electrode driven in the common electrode driving step, and the segment electrode driving Inverted voltage polarity between segment electrodes driven in step That controls and a polarity inversion control step performed for each given polarity inversion line number.

  (13) In the liquid crystal driving method according to the thirteenth aspect of the present invention, the scanning control step inserts any part of the scanning period of the common electrode as the dummy period, and the common electrode driving step includes: The common electrode corresponding to the scanning period inserted in the scanning control step is scanned, and the segment electrode driving step drives the segment electrode based on image data corresponding to the scanning period inserted in the scanning control step. To do.

1 is a block diagram of a configuration example of a liquid crystal display device according to an embodiment of the present invention. 2A to 2D are explanatory diagrams of the principle of the MLS driving method. The figure which shows the relationship of the voltage of 7 levels in the MLS drive method of 4 line simultaneous selection. FIG. 4A and FIG. 4B are explanatory diagrams of the state of image quality deterioration in the first embodiment. The figure which shows the waveform of the drive voltage of an ideal segment electrode. The figure which shows the waveform blunting of the drive voltage of a segment electrode. The figure which shows typically distortion of the center voltage which is a non-selection voltage of a common electrode. The figure which shows the effective voltage at the time of considering the waveform blunting of a segment electrode and distortion of the center voltage level of a common electrode. 1 is a block diagram of a configuration example of a liquid crystal driving device according to a first embodiment. Explanatory drawing of a common address and a line address. The figure which shows an example of the selection pattern in the case of performing MLS drive method. FIG. 10 is a block diagram of a configuration example of a dummy insertion control circuit in FIG. 9. Explanatory drawing of a dummy insertion setting register. FIG. 14A to FIG. 14D schematically show an explanatory diagram of dummy insertion control. Explanatory drawing of a dummy insertion address register. Explanatory drawing of a dummy data setting register. The flowchart of the operation example of a common address counter. The flowchart of the operation example of a line address counter. The flowchart of the operation example of a polarity inversion line number counter. The flowchart of the operation example of a polarity inversion signal generation circuit. The timing diagram of the operation example of a dummy insertion control circuit. FIG. 5 is a diagram illustrating an example of drive timing of the liquid crystal drive device according to the first embodiment. The block diagram of the structural example of the liquid-crystal drive device in 2nd Embodiment. The block diagram of the structural example of the block insertion control circuit of FIG. Explanatory drawing of a block insertion setting register. FIG. 26A to FIG. 26D are diagrams schematically illustrating the block insertion control. Explanatory drawing of a block insertion address register. The flowchart of the operation example of the common address counter of FIG. The flowchart of the operation example of the line address counter of FIG. The timing diagram of the example of operation of a block insertion control circuit. The figure which shows an example of the drive timing of the liquid crystal drive device in 2nd Embodiment. 32A and 32B are perspective views illustrating the configuration of an electronic device to which any of the embodiments or the modifications thereof is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[First Embodiment]
[Liquid Crystal Display]
FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device according to an embodiment of the present invention. FIG. 1 illustrates a configuration example in which the liquid crystal display device includes a liquid crystal drive device. However, the liquid crystal drive device may be provided outside the liquid crystal display device.

  The liquid crystal display system 10 includes a liquid crystal display panel (liquid crystal display device in a broad sense) 20, a host processor 30, and a power supply circuit 40.

  The liquid crystal display panel 20 is a passive liquid crystal display panel, and is formed of a transparent electrode between a pair of transparent glass substrates, and a plurality of common electrodes, a plurality of segment electrodes, and an alignment film. And liquid crystal or the like is enclosed. The liquid crystal display panel 20 has a pixel formation region 22, and the pixel formation region 22 is disposed in a second direction intersecting the first direction with a common electrode disposed in the first direction. Pixels are formed corresponding to the intersection positions with the segment electrodes. In FIG. 1, a common electrode COMj (0 ≦ j ≦ Q, j is an integer) of a plurality of common electrodes COM0 to COMQ (Q is an integer of 2 or more) and a plurality of segment electrodes SEG0 to SEGR (R is an integer of 2 or more). Segment electrodes SEGk (0 ≦ k ≦ R, k is an integer). A pixel Pjk is formed corresponding to the intersection position of the common electrode COMj and the segment electrode SEGk. A liquid crystal driving device 100 is mounted on a glass substrate constituting the liquid crystal display panel 20 by COG (Chip On Glass).

  The liquid crystal driving device 100 includes a plurality of common electrode output terminals for supplying a given selection voltage to the common electrode, and a plurality of segment electrode output terminals for supplying a liquid crystal driving voltage corresponding to image data to the segment electrode. Have The plurality of common electrode output terminals are electrically connected to the corresponding common electrodes, and the plurality of segment electrode output terminals are electrically connected to the corresponding segment electrodes. The liquid crystal driving device 100 drives the common electrodes COM0 to COMQ and the segment electrodes SEG0 to SEGR formed in the pixel formation region of the liquid crystal display panel 20 by an MLS (Multi Line Selection) driving method. That is, the liquid crystal driving device 100 drives a plurality of times in a plurality of field periods obtained by dividing one frame period as a period necessary to display one screen by simultaneously selecting a plurality of common electrodes. The liquid crystal driving device 100 drives a plurality of simultaneously selected common electrodes based on a selected pattern (scanning pattern) for each field period, and drives corresponding to a given MLS calculation result based on the selected pattern and image data. A voltage is applied to the plurality of segment electrodes.

  The host processor 30 performs drive control of the liquid crystal drive device 100 by reading a program stored in a built-in memory or a memory (not shown) and executing processing corresponding to the program. Therefore, the host processor 30 controls the operation of the liquid crystal driving device 100 by setting a setting value in a setting register built in the liquid crystal driving device 100. In addition, the host processor 30 supplies image data corresponding to an image to be displayed on the liquid crystal display panel 20 to the liquid crystal driving device 100. In FIG. 1, the host processor 30 may be mounted on a glass substrate constituting the liquid crystal display panel 20.

  The power supply circuit 40 supplies an operating power supply voltage and a drive power supply voltage for the liquid crystal display panel 20, or a reference voltage for generating these voltages, to the host processor 30 and the liquid crystal drive device 100, respectively. In FIG. 1, the power supply circuit 40 may be mounted on a glass substrate constituting the liquid crystal display panel 20 or may be built in the liquid crystal driving device 100.

[MLS drive method]
Compared with the simple driving method, the MLS driving method by the liquid crystal driving device 100 can narrow the interval of the period during which the common electrode is selected, suppresses the decrease in the transmittance of the pixel, and improves the average transmittance. Can be made. Moreover, the drive voltage (selection voltage) applied to a common electrode can be made low by selecting a some common electrode simultaneously.

  2A to 2D are explanatory diagrams of the principle of the MLS driving method. Each of FIGS. 2A to 2D represents an example in which a pixel (dot) at a position where the common electrodes COM0, COM1 and the segment electrode SEG0 intersect is turned on or off. 2A to 2D show examples of the MLS driving method in which two lines of common electrodes COM0 and COM1 are simultaneously selected and two lines are simultaneously selected.

  In FIG. 2A to FIG. 2D, a pixel that is turned on (on pixel) is represented by “−1”, and a pixel that is turned off (off pixel) is represented by “+1”. Specified by. A selection pattern for selecting each of the common electrodes COM0 and COM1 is represented by binary values “+1” and “−1”. Further, the drive voltage of the segment electrode SEG0 has three values “MV2”, “V2”, and “V1”.

  In the MLS driving method, the driving voltage of the segment electrode SEG0 is determined by the selection pattern of the common electrodes COM0 and COM1 that are selected simultaneously with the image data. Here, if the image data is the image data vector d and the selection pattern is the matrix β, it is determined whether the drive voltage of the segment electrode SEG0 is “MV2”, “V2”, or “V1”. And the matrix β. The image data vector d represents data representing on or off of a pixel at a position where the segment electrode SEG0 intersects each common electrode. In the case of FIG. 2A, d · β = −2, in the case of FIG. 2B, d · β = + 2, and in the case of FIG. 2C, d · β = + 2. In the case of 2 (D), d · β = 0. When the product of the image data vector d and the matrix β is “−2”, “MV2” is selected as the drive voltage of the segment electrode SEG0, “V2” is selected when it is “+2”, and “0”. “V1” is selected.

  For example, when the calculation of the product of the image data vector d and the matrix β is performed by hardware, the number of mismatches between each element data of the image data vector d and each element data of the matrix β may be determined. . For example, when the number of mismatches is “2”, “MV2” is selected as the drive voltage for the segment electrode SEG0. If the number of mismatches is “0”, “V2” is selected as the drive voltage. If the number of mismatches is “1”, “V1” is selected as the drive voltage.

  In the two-line simultaneous MLS driving method, the driving voltage of the segment electrode SEG0 is determined as described above, and two field periods are provided within one frame period to control the on / off of the pixels. Since the field period is provided a plurality of times, the decrease in the transmittance in the non-field period is reduced, the average transmittance in the liquid crystal display panel 20 can be improved, and the contrast of the liquid crystal panel can be improved. In the following, it is assumed that the MLS driving method of simultaneously selecting four lines of common electrodes is performed. In this case, four field periods can be provided within one frame period, and the contrast of the liquid crystal display panel 20 can be further improved. In the 4-line simultaneous selection MLS driving method, a voltage of 7 levels is used.

  FIG. 3 shows the relationship between the seven levels of voltage when the liquid crystal display panel 20 is driven by the MLS driving method of simultaneous selection of four lines.

  The voltages V3 and MV3 are common electrode selection voltages. The voltage VC is a non-selection voltage for the common electrode, and is a driving voltage for the segment electrode. The voltages V2, V1, MV1, and MV2 are segment electrode drive voltages. And the transmittance | permeability of a pixel changes according to the voltage difference of the common electrode and segment electrode which cross | intersect.

Here, a voltage difference between the voltage V3 and the center voltage VC _{v 3,} the voltage difference between the voltage V2 and the center voltage VC _{v 2,} the voltage difference between the voltage V1 and the center voltage VC and _{v 1.} At this time, the voltage difference between the center voltage VC and the voltage MV3 is v ₃ , the voltage difference between the center voltage VC and the voltage MV2 is v ₂ , and the voltage difference between the center voltage VC and the voltage MV1 is v ₁ . Here, the voltage difference between the voltage V2 and the voltage V1 (= the voltage difference between the voltage MV1 and the voltage MV2) is the voltage difference between the voltage V1 and the center voltage VC (= the voltage difference between the center voltage VC and the voltage MV1). equal.

[Liquid crystal drive]
In the liquid crystal driving device 100, the common electrode and the segment electrode are driven by the MLS driving method using the voltage shown in FIG. At this time, the liquid crystal driving device 100 performs the N-line polarity inversion control that inverts the polarity every time N (N is an integer of 1 or more) common electrodes are scanned, thereby preventing the deterioration of the liquid crystal and improving the image quality. Improve. However, when the background is an on-pixel (off-pixel) and an off-pixel (on-pixel) is present in a part of the screen, degradation of image quality due to crosstalk is assumed.

  FIG. 4A and FIG. 4B are explanatory diagrams showing how the image quality deteriorates in the first embodiment. FIG. 4A schematically shows an ideal display image, where a black area is an off pixel and a white area is an on pixel. FIG. 4B schematically shows an actual display image and shows deterioration of image quality due to crosstalk.

  That is, in FIG. 4A, it is assumed that the background is an on-pixel area ARon and an off-pixel area ARoff exists in part of the screen. When the liquid crystal driving device 100 drives the common electrode and the segment electrode line-sequentially by the MLS driving method based on the image data corresponding to the image shown in FIG. 4A, an image as shown in FIG. Is displayed. In FIG. 4B, the area AR1 is an on area, but is displayed in a direction in which the pixel is turned on from the original on display. The area AR2 is also an on area, but is displayed in a direction of turning off from the original on display. The area AR3 is also an on area, but is displayed in a direction that is turned off from the original on display and in a direction that is turned on rather than the area AR2. The area AR4 is an off area, but is displayed in a direction in which the pixel is turned on from the original off display. The area AR5 is also an off area, but is displayed in a direction in which the pixels are turned off from the original off display.

  The phenomenon shown in FIG. 4B is considered to occur due to the dull waveform of the drive voltage of the segment electrode and the decrease in effective voltage due to the change in the potential of the segment electrode causing the non-selection voltage of the common electrode to fluctuate. . Here, in order to explain the influence of the waveform dullness and the potential change at the time of polarity reversal, in FIG. 4B, it is assumed that polarity reversal is performed at timings A and D, and scanning is performed at timings B, C, and E. The timings A and D will be described assuming that they coincide with the scanning timing. In the first embodiment, since the potential change of the segment electrode occurs when the image data changes and when the polarity is inverted, the phenomenon shown in FIG. 4B can be explained as follows at each timing.

  In the polarity inversion timing A, most of the segment electrodes are off (driving voltage corresponding to image data indicating off, the same applies hereinafter), and a small number is on (driving voltage corresponding to image data indicating on, the same applies hereinafter). This is the timing when polarity inversion occurs. The scanning timing B is a timing at which many of the segment electrodes change from off to on and a small number remain on. The scanning timing C is a timing at which the majority of the segment electrodes remain on and the minority changes from on to off. The polarity reversal timing D is a timing at which polarity reversal occurs when a large number of segment electrodes are on and a small number are off. The scanning timing E is a timing at which the majority of the segment electrodes remain on and the minority changes from off to on.

Here, an ideal drive voltage waveform at each timing is as follows.
FIG. 5 shows an ideal segment electrode drive voltage waveform. In FIG. 5, the segment electrode SEG0 in the area AR1 in FIG. 4B, the segment electrode SEG50 in the areas AR2 and AR5 in FIG. 4B, and the drive voltage of the segment electrode SEG100 in the areas AR3 and AR4 in FIG. Represents a waveform.

  In this case, the center voltage VC, which is a non-selection voltage of the common electrode, is stable, and no dullness or distortion occurs even if the potential changes in each of the segment electrodes SEG0, SEG50, and SEG100. The same applies to the voltage level of the common electrode and the voltage level of the segment electrode at the polarity inversion timings A and D. Therefore, the effective voltage between each segment electrode and the common electrode corresponds to the shaded portions VV1 to VV3.

  However, in reality, it is considered that the waveform is blunted in the segment electrodes. Due to this waveform dullness, the effective voltage differs from that shown in FIG.

  FIG. 6 shows the waveform dullness of the drive voltage of the segment electrode. In FIG. 6, the center voltage VC of the common electrode is stable, and the waveforms of the segment electrodes SEG0, SEG50, and SEG100 are shown with the center voltage VC as a reference. In FIG. 6, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In the segment electrodes SEG0, SEG50, and SEG100, the drive voltage changes each time the polarity inversion timings A and D change or from the on pixel to the off pixel and from the off pixel to the on pixel. Waveform dullness occurs due to the potential change of the segment electrode, and the effective voltage between the common electrodes becomes as indicated by the shaded portions VV11 to VV13, and the effective voltage is lowered. Therefore, the effective voltage decreases as the number of potential changes of the segment electrode increases. Therefore, the ON areas of the areas AR2 and AR3 are displayed in a direction in which they are turned off, rather than the ON area of the area AR1 in FIG.

  However, the difference in density between the areas AR2 and AR3 and the difference between the densities in the areas AR4 and AR5 cannot be explained only by the dull waveform of the drive voltage of the segment electrode. Therefore, attention is paid to the potential fluctuation of the non-selection voltage of the common electrode caused by the potential change of the segment electrode.

  FIG. 7 schematically shows distortion of the center voltage VC, which is a non-selection voltage of the common electrode. FIG. 7 shows a state in which the potential level of the center voltage VC varies in accordance with the polarity inversion timings A and D and the scanning timings B, C, and E in FIG.

  The degree of influence of the segment electrode potential fluctuation on the potential level of the non-selection voltage of the common electrode is considered to depend on the image data. This is because the degree of potential fluctuation of the common electrode is considered to be different between the case where the potential of the segment electrode varies at the same time depending on the image data and the case where the potential of the segment electrode varies only by one. For this reason, it is considered that the potential level of the non-selection voltage of the common electrode is distorted in the direction in which the potential of the segment electrode varies depending on the image data. From the above, the polarity reversal timings A and D are greatly distorted in the positive direction, and the scanning timing B is largely distorted in the negative direction. On the other hand, at the scanning timings C and E, the distortion is small in the positive direction.

  As described above, the effective voltage is a voltage between the common electrode and the segment electrode. Therefore, considering the waveform dullness of the segment electrode and the distortion of the center voltage level of the common electrode, the following is obtained.

  FIG. 8 shows the effective voltage when the waveform dullness of the segment electrode and the distortion of the center voltage level of the common electrode are taken into consideration. FIG. 8 is obtained by superimposing FIG. 6 and FIG. 7. The same reference numerals are given to the same parts as those in FIG. 6 or FIG.

  When attention is paid to the shaded portions VV21 to VV23 shown in FIG. 8 corresponding to the effective voltage, at the polarity inversion timing A, the effective voltage of the segment electrode SEG0 increases more than the effective voltage of the segment electrodes SEG50 and SEG100. At the scanning timing B, the influence levels of the effective voltages of the segment electrodes SEG0, SEG50, and SEG100 are substantially the same. At the scanning timing C, the effective voltage of the segment electrode SEG100 is slightly lower than that of the segment electrodes SEG0 and SEG50. At the polarity inversion timing D, the effective voltage of the segment electrode SEG100 increases more than that of the segment electrodes SEG0 and SEG50. At the scanning timing E, the influence levels of the effective voltages of the segment electrodes SEG0, SEG50, and SEG100 are substantially the same.

  Accordingly, the area AR1 of the segment electrode SEG0 is displayed in the direction in which the pixels are turned on. In addition, although the area AR2 of the segment electrode SEG50 and the area AR3 of the segment electrode SEG100 are on areas, the pixels are turned off, but the area AR3 is displayed in the on direction compared to the area AR2. Furthermore, it can be seen that the area AR4 of the segment electrode SEG100 is an off area compared to the area AR5 of the segment electrode SEG50, but is displayed in a direction in which the pixels are turned on.

  As described above, when N-line polarity reversal control is performed during simple line sequential scanning, the segment electrode potential change due to the polarity reversal in the on-region is caused by crosstalk to the common electrode, and the segment electrode effective in the on-region is effective. The voltage increases. In that case, a phenomenon as shown in FIG. In order to avoid such a phenomenon, by adjusting the number of polarity inversion lines, the portion where the effective voltage is increased and the portion where the effective voltage is decreased due to crosstalk can be offset. However, when the number of polarity inversion lines is reduced, the effective voltage in the on region increases, and crosstalk occurs in which the off regions above and below the on region are displayed in the on direction. On the other hand, when the number of polarity inversion lines is increased, it becomes difficult to obtain the effect of preventing the original liquid crystal deterioration. As described above, there is a problem that the adjustment of the number of polarity inversion lines is liable to cause the deterioration of the image quality and the adjustment becomes difficult.

  Therefore, in the first embodiment, a dummy period is provided during the scanning period of the common electrode, and the segment electrode is driven based on given dummy data in the dummy period, so that the effective voltage due to the crosstalk is reduced. Reduce change. As a result, even if the number of polarity inversion lines is the same, it is possible to prevent the deterioration of the image quality due to the crosstalk, and the adjustment for improving the crosstalk becomes easy. This dummy period is provided so that the output potential of the segment electrode in the mark portion of the on pixel with the off pixel as a background and the mark portion of the off pixel with the on pixel as a background changes.

Such a liquid crystal driving device 100 can have the following configuration.
FIG. 9 is a block diagram illustrating a configuration example of the liquid crystal driving device 100 according to the first embodiment. In FIG. 9, the pixel formation region 22 is also illustrated.

  The liquid crystal driving device 100 includes a host processor interface 110, an oscillation circuit 112, a control circuit 114, a common address decoder 116, a common output arithmetic circuit 118, and a common driver 120. Further, the liquid crystal driving device 100 includes a page address control circuit 122, a column address control circuit 124, a line address control circuit 126, an image data RAM 128, an image data latch circuit 130, an MLS decoder 132, and a segment driver 134. The image data RAM 128 functions as a frame memory (image data memory). The control circuit 114 includes a dummy insertion control circuit (scanning control unit) 200. The driving unit in the first embodiment includes a common driver 120 and a segment driver 134, and may further include at least one of a common address decoder 116, a common output arithmetic circuit 118, and an MLS decoder 132.

  The host processor interface 110 performs input interface processing of input signals input from the host processor 30 via input terminals or input / output terminals of the liquid crystal driving device 100. The host processor interface 110 performs output interface processing of an output signal output to the host processor 30 via an output terminal or an input / output terminal included in the liquid crystal driving device 100.

  The oscillation circuit 112 generates an oscillation clock OSC serving as a reference for a display timing signal generated by the liquid crystal driving device 100 by an oscillation operation. For example, the control circuit 114 generates a plurality of types of display timing signals based on the oscillation clock OSC. The control circuit 114 generates a control signal for controlling each part of the liquid crystal driving device 100 such as the common address decoder 116. The dummy insertion control circuit 200 performs control to insert a dummy period within the scanning period of the common electrode.

  The common address decoder 116 decodes common addresses corresponding to a plurality of common electrodes generated in the control circuit 114 and simultaneously selected in the MLS drive. The decoding result is output to the common driver 120. A common address is assigned to each of a plurality of common electrodes that are simultaneously selected, and a corresponding common electrode is selected by designating the common address when performing MLS driving.

  The common output arithmetic circuit 118 controls the output level of the common output based on the field inversion signals FR and F2 that identify the polarity inversion signals FR and MLS drive patterns generated in the control circuit 114.

  The common driver 120 controls selection / non-selection of the common output based on the decoding result of the common address decoder 116, and outputs the output level generated by the common output arithmetic circuit 118 as the selected common output.

  The page address control circuit 122 controls a page address for accessing image data RAM 128 for image data input from the host processor 30 via the host processor interface 110. The page address is defined with the bus width of image data input from the host processor 30 as an access unit.

  The column address control circuit 124 controls a column address for accessing image data RAM 128 for image data input from the host processor 30 via the host processor interface 110. The column address is defined corresponding to the segment electrode in the pixel formation region 22.

  The line address control circuit 126 controls a line address that specifies a read line in the image data stored in the image data RAM 128. The line address is defined corresponding to the common electrode in the pixel formation region 22. The common address and line address in the first embodiment are defined as shown in FIG. For example, when the control circuit 114 outputs the common address “0”, the common electrodes COM0 to COM3 are simultaneously selected. At this time, among the image data stored in the image data RAM 128, the image data corresponding to the line addresses 0 to 3 is read. Similarly, when the control circuit 114 outputs the common address “1”, the common electrodes COM4 to COM7 are simultaneously selected. At this time, image data corresponding to the line addresses 4 to 7 is read out from the image data stored in the image data RAM 128. As described above, the common address can be specified in units of blocks in which four lines of common electrodes selected simultaneously are defined as one block, and the line address is also uniquely determined.

  In FIG. 9, the image data RAM 128 has a storage area in which image data of each pixel is stored corresponding to the arrangement of the pixels in the pixel formation area 22. Each storage area is specified by a page address and a column address. As a result, the image data is written in the image data RAM 128 in an area specified by the page address and the column address. On the other hand, image data is read from the image data RAM 128 in units of one line.

  The image data latch circuit 130 latches the image data read out from the image data RAM 128 line by line for four lines. The image data latch circuit 130 receives the display on signal DON from the control circuit 114 and controls the image data in the dummy period based on the display on signal DON.

  The MLS decoder 132 decodes the image data and a display timing signal generated by the control circuit 114 and used for MLS driving. More specifically, the MLS decoder 132 outputs a segment output based on the image data latched by the image data latch circuit 130 and the polarity inversion signal FR and the field signals F1 and F2 generated by the control circuit 114. Control the level. The decoding result of the MLS decoder 132 is output to the segment driver 134.

  The segment driver 134 outputs the output level decoded by the MLS decoder 132 to the segment electrode based on the decoding result of the MLS decoder 132. The segment driver 134 is controlled to turn off the display by outputting a given output level to the segment electrode regardless of the decoding result of the MLS decoder 132 by the display off signal XDOF generated by the control circuit 114. be able to. In the first embodiment, the display is turned off by outputting to the segment electrode an output level that is the same potential as the common electrode by the display off signal XDOF.

  FIG. 11 shows an example of a selection pattern when performing the MLS driving method. FIG. 11 shows an example of a selection pattern when the polarity inversion signal FR is at the L level. Even when the polarity inversion signal FR is at the H level, it corresponds to the voltage applied to each common electrode for each field period. The selected pattern is provided.

  Each field period provided within one frame period in the MLS driving method is specified by the field signals F1 and F2 in the liquid crystal driving device 100. The liquid crystal driving device 100 outputs the voltage V3 or the voltage MV3 to each common electrode for each field period corresponding to the four states represented by the 2-bit field signals F1 and F2 shown in FIG. An output pattern to each common electrode in each field period shown in FIG. 11 is defined by an orthogonal function system as a selection pattern. The liquid crystal driving device 100 appropriately selects one of the three types of driving voltages V3, VC, and MV3 in accordance with a selection pattern defined by a predetermined orthogonal function system, and applies them to the simultaneously selected common electrodes. It has become.

  Each field period is divided into a plurality of sub-selection periods assigned to a plurality of common electrodes selected simultaneously. Of the plurality of sub-selection periods obtained by dividing the first field period (1f), the following operation is performed in the sub-selection period in which the simultaneously selected common electrodes COM0 to COM3 are selected. The liquid crystal driving device 100 selects one of the voltages (V2, V1, VC, MV1, MV2) and applies the selected voltage to the segment electrode SEG0. At this time, the liquid crystal driving device 100 applies a voltage according to the number of polarity mismatches between the display pattern of each dot corresponding to the intersection position with each of the common electrodes COM0 to COM3 selected simultaneously with the segment electrode SEG0. select. Similarly, the selected voltage is applied to the other segment electrodes.

  Next, among the plurality of sub-selection periods obtained by dividing the first field period, in the sub-selection period in which the next common electrode to be simultaneously selected is selected, the number of inconsistencies in the column of each segment electrode is determined and obtained. Apply the voltage data. Thus, when the above procedure is repeated for all the common electrodes, the operation in the first field period is completed. Similarly, in the second and subsequent field periods, when the above procedure is repeated for all the common electrodes, one frame period ends, and one screen is displayed.

  In the liquid crystal drive device 100 having such a configuration, the common driver 120 scans the common electrode with a selection pattern corresponding to each field over a plurality of fields in a block unit in which a plurality of common electrodes to be simultaneously selected are one block. . The segment driver 134 drives the segment electrodes with image data corresponding to a plurality of common electrodes that are simultaneously selected and a driving voltage corresponding to the selection pattern. This drive voltage is obtained as a result of decoding based on the image data and the display timing signal.

FIG. 12 shows a block diagram of a configuration example of the dummy insertion control circuit 200 of FIG.
The dummy insertion control circuit 200 includes a dummy insertion setting register 202, a dummy insertion address register (dummy insertion register) 204, a common address counter 206, a line address counter 208, and a dummy data setting register 210. The dummy insertion control circuit 200 includes a polarity inversion line number setting register 212, a polarity inversion line number counter 214, and a polarity inversion signal generation circuit (polarity inversion control unit) 216. The dummy insertion control circuit 200 controls the common address, the line address, and the polarity inversion signal FR using the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the field signals F1 and F2.

  The dummy insertion setting register 202 is configured to be accessible by the host processor 30 via the host processor interface 110, and a setting value corresponding to ON or OFF of dummy insertion control is set. When a set value corresponding to ON of dummy insertion control is set in this register, the dummy insertion control circuit 200 performs control to insert a dummy period during the scanning period of the common electrode.

FIG. 13 is an explanatory diagram of the dummy insertion setting register 202. In FIG. 13, it is assumed that the dummy insertion setting register 202 is a 2-bit register.
According to the setting values (P1, P0) set in the dummy insertion setting register 202 by the host processor 30, it is possible to designate the dummy insertion control to be turned off and the dummy insertion control to be turned on. For example, if a plurality of common electrodes (four lines in this case) simultaneously selected by the MLS are defined as one block, it is possible to specify how many blocks are inserted when the dummy insertion control is turned on. In FIG. 12, one block (= 4 lines) is inserted when the set value (P1, P0) = (0, 1), and two blocks (= 8) when the set value (P1, P0) = (1, 0). Line) is inserted, and when the set value (P1, P0) = (1, 1), 3 blocks (= 12 lines) are inserted.

  FIGS. 14A to 14D schematically illustrate the dummy insertion control. 14A to 14D, the length in the vertical direction corresponds to the vertical scanning period, and the length in the horizontal direction corresponds to the horizontal scanning period. FIG. 14A shows an image of a display image before a dummy period is inserted. FIGS. 14B to 14D show images when dummy periods of one block to three blocks are inserted, respectively.

  Consider a case in which an image including a mark portion MK is displayed as shown in FIG. In contrast to FIG. 14A in which the dummy electrode is not inserted and the common electrode is scanned in one vertical scanning period, when the set values (P1, P0) = (0, 1), FIG. As described above, the dummy period DT1 is inserted in one vertical scanning period (= common electrode scanning period). Similarly, when the set value (P1, P0) = (1, 0), dummy periods DT2 and DT3 are inserted as shown in FIG. 14C. When the set values (P1, P0) = (1, 1), dummy periods DT4, DT5, and DT6 are inserted as shown in FIG. In the dummy periods DT1 to DT6, the segment electrodes are driven based on given dummy data, respectively, and in FIG. 9, the segment electrodes are driven based on image data corresponding to the display ON signal DON.

  In FIG. 12, the dummy insertion address register 204 is configured to be accessible by the host processor 30 via the host processor interface 110. In the dummy insertion address register 204, a set value corresponding to the insertion position of the dummy period within the scanning period of the common electrode is set. Here, a common address is set as a setting value corresponding to the insertion position of the dummy period. The dummy insertion control circuit 200 performs control so that the common electrode is not selected during the dummy period corresponding to the set value of the dummy insertion address register 204.

FIG. 15 shows an explanatory diagram of the dummy insertion address register 204.
The dummy insertion address register 204 includes a first address register 220, a second address register 222, and a third address register 224. These address registers are configured to be accessible by the host processor 30 via the host processor interface 110, and a common address (setting value in a broad sense) corresponding to the insertion position of the dummy period is set. When one block insertion is designated by the dummy insertion setting register 202, the common address set in the first address register 220 is output to the common address counter 206 and the line address counter 208. When 2-block insertion is designated by the dummy insertion setting register 202, the common addresses set in the first address register 220 and the second address register 222 are output to both counters. When 3-block insertion is specified by the dummy insertion setting register 202, the common addresses set in the first address register 220 to the third address register 224 are output to both counters.

  In FIG. 12, a common address counter 206 counts a common address count value corresponding to a common address that specifies four lines of common electrodes that are simultaneously selected. The common address counter 206 outputs a common address corresponding to the common address count value. The line address counter 208 counts a line address count value corresponding to the line address corresponding to each common electrode selected at the same time. The line address counter 208 outputs a line address corresponding to the line address count value.

  The dummy data setting register 210 is configured to be accessible by the host processor 30 via the host processor interface 110, and a setting value corresponding to the output potential of the segment electrode in the dummy period is set. The display on signal DON is output as a signal having a logic level corresponding to the set value of the dummy data setting register 210.

FIG. 16 is an explanatory diagram of the dummy data setting register 210.
When the display on signal DON is designated to be “0” (L level) by the setting value of the dummy data setting register 210, the image data latch circuit 130 forcibly outputs off data for turning off the pixel. . At this time, off-data is forcibly output regardless of the image data output from the image data RAM 128. Similarly, when the display ON signal DON is designated to be “1” (H level) by the setting value of the dummy data setting register 210, the image data latch circuit 130 forcibly sets the ON data for turning on the pixel. Output to. Thereby, in the dummy period, the image data can be forcibly controlled according to the display contents, and the output potential of the segment electrode can be designated.

  The dummy data preferably includes inverted data of image data corresponding to the scanning period immediately before insertion. For example, when scanning a mark portion having an on pixel in the scanning period immediately before insertion, the dummy data is image data such that the on pixel region of the mark portion is an off pixel. Alternatively, for example, when the mark portion of the off pixel is scanned during the scanning period immediately before the insertion, the dummy data is image data so that the off pixel region of the mark portion becomes the on pixel. In the first embodiment, image data in which one line is all on or all off by the display on signal DON is adopted as dummy data.

  In FIG. 12, the polarity inversion line number setting register 212 is configured to be accessible by the host processor 30 via the host processor interface 110, and a setting value corresponding to the number of polarity inversion lines is set. The dummy insertion control circuit 200 performs control to invert the polarity of the voltage applied to the liquid crystal for each number of lines corresponding to the set value set in the polarity inversion line number setting register 212. In the first embodiment, since the MLS driving method for simultaneously selecting four lines is employed, a setting value corresponding to a multiple of the number of common electrodes selected simultaneously is set in the polarity inversion line number setting register 212. The polarity inversion line number counter 214 counts the polarity inversion line number count value based on the number of polarity inversion lines corresponding to the set value set in the polarity inversion line number setting register 212. The polarity inversion signal generation circuit 216 inverts the logic level for each polarity inversion line number based on the polarity inversion line number count value and outputs the polarity inversion signal FR. As a result, the polarity inversion signal generation circuit 216 can perform control for inverting the polarity of the voltage between the common electrode and the segment electrode for each given number of polarity inversion lines.

  Hereinafter, an operation example of each part constituting the dummy insertion control circuit 200 will be described. In the following, for simplification of explanation, one block insertion will be described as an example, but it goes without saying that the same can be realized when two or three blocks are inserted.

FIG. 17 shows a flowchart of an operation example of the common address counter 206.
The common address counter 206 receives a vertical synchronization signal VSYNC, field signals F1 and F2, and a horizontal synchronization signal HSYNC. Internally, the field head signal FIELD is set to “1” at the start timing of the field period specified based on the field signals F1 and F2. At this time, when the vertical synchronization signal VSYNC is “1” or the field head signal FIELD is “1” (step S10: Y), the common address counter 206 sets the start address “0” as the common address (step S12). ). More specifically, the common address counter 206 sets “0” to the common address count value.

  On the other hand, when the vertical synchronization signal VSYNC is not “1” or the field head signal FIELD is not “1” (step S10: N), the common address counter 206 determines whether to update the common address count value based on the horizontal synchronization signal HSYNC. Perform (step S14). In step S14, when the horizontal synchronization signal HSYNC is “1” (step S14: Y), the common address counter 206 determines whether the common address is a dummy common address based on the common address count value (step S14). S16). Here, the dummy common address is an address that cannot be decoded by the common address decoder 116, and a common address that does not exist is adopted. The common address decoder 116 decodes all the common electrodes so as to output a voltage VC which is a non-selection voltage when a dummy common address is given. When it is determined in step S16 that the common address is a dummy common address (step S16: Y), the common address counter 206 sets the common address to (address immediately before dummy insertion + 1) (step S18). Specifically, the common address counter 206 sets the common address count value so that (address immediately before dummy insertion + 1) becomes the common address. Here, the address immediately before dummy insertion is the common address immediately before the common address corresponding to the insertion position in the dummy period. Thereby, the scanning of the common electrode can be continued after the dummy period is inserted.

  When it is determined in step S16 that the common address is not a dummy common address (step S16: N), the common address counter 206 performs a common address determination process corresponding to the dummy period (step S20). That is, in step S20, the common address counter 206 determines whether or not the common address is (dummy insertion address-1) based on the common address count value. Here, the dummy insertion address is an address set in the first address register 220 of FIG. When it is determined in step S20 that the common address is (dummy insertion address-1) (step S20: Y), the common address counter 206 sets the common address to the dummy common address (step S22). Specifically, the common address counter 206 sets the common address count value so that the dummy common address becomes the common address. Thereby, a dummy period is inserted. On the other hand, when it is determined in step S20 that the common address is not (dummy insertion address-1) (step S20: N), the common address counter 206 increments the common address (step S24). Specifically, the common address counter 206 increments the common address count value.

  In step S14, when the horizontal synchronization signal HSYNC is not "1" (step S14: N), the common address counter 206 returns to step S10 (return) without updating the common address count value (step S26). Similarly, after the process of step S12, step S18, step S22, and step S24, the process returns to step S10 (return).

  The common driver (common electrode driving unit) 120 that has received the common address corresponding to the common address count value counted as described above inserts a dummy period into the scanning period of the common electrode in the pixel formation region 22, Can be scanned.

FIG. 18 shows a flowchart of an operation example of the line address counter 208.
The line address counter 208 receives a vertical synchronization signal VSYNC, field signals F1 and F2, and a horizontal synchronization signal HSYNC. When the vertical synchronization signal VSYNC is “1” or the field head signal FIELD is “1” (step S30: Y), the line address counter 208 sets the line address to “0” as the start address (step S32). More specifically, the line address counter 208 sets “0” to the line address count value.

  On the other hand, when the vertical synchronization signal VSYNC is not “1” or the field head signal FIELD is not “1” (step S30: N), the line address counter 208 determines whether to update the line address count value based on the horizontal synchronization signal HSYNC. This is performed (step S34). In step S34, when the horizontal synchronizing signal HSYNC is “1” (step S34: Y), the line address counter 208 determines whether or not the line address is a dummy line address based on the line address count value ( Step S36). Here, the dummy line address is an address that cannot be decoded by the line address control circuit 126, and a line address that does not exist is adopted. When the output data of the image data latch circuit 130 can be forcibly controlled by the display on signal DON, a line address that does not exist as a dummy line address may not be used. When it is determined in step S36 that the line address is a dummy line address (step S36: Y), the line address counter 208 sets the line address ((address immediately before dummy insertion + 1) × 4) (step S38). . Specifically, the line address counter 208 sets the line address count value such that ((address immediately before dummy insertion + 1) × 4) is the line address. Accordingly, the segment electrode can be continuously driven after the dummy period is inserted.

  When it is determined in step S36 that the line address is not a dummy line address (step S36: N), the line address counter 208 performs a line address determination process corresponding to the dummy period (step S40). That is, in step S40, the line address counter 208 determines whether or not the line address is (dummy insertion address × 4-1) based on the line address count value. When it is determined in step S40 that the line address is (dummy insertion address × 4-1) (step S40: Y), the line address counter 208 sets the line address to the dummy line address (step S42). Specifically, the line address counter 208 sets the line address count value so that the dummy line address becomes the line address. On the other hand, when it is determined in step S40 that the line address is not (dummy insertion address × 4-1) (step S40: N), the line address counter 208 increments the line address (step S44). Specifically, the line address counter 208 increments the line address count value.

  In step S34, when the horizontal synchronization signal HSYNC is not "1" (step S34: N), the line address counter 208 determines whether or not the line address is a dummy line address based on the line address count value ( Step S46). When it is determined in step S46 that the line address is a dummy line address (step S46: Y), the line address counter 208 holds the line address as it is (step S48) and returns to step S30 (return). On the other hand, when it is determined in step S46 that the line address is not a dummy line address (step S46: N), the line address counter 208 increments the line address (step S44) and returns to step S30 (return). Similarly, after step S32, step S38, and step S42, the process returns to step S30 (return).

  Based on the image data read using the line address corresponding to the line address count value counted as described above, the segment driver (segment electrode driver) 134 drives the segment electrode in the pixel formation region 22.

FIG. 19 shows a flowchart of an operation example of the polarity inversion line number counter 214.
The horizontal inversion signal HSYNC is input to the polarity inversion line number counter 214. When the horizontal synchronization signal HSYNC is “1” (step S60: Y), the polarity inversion line number counter 214 has a polarity inversion line number count value (polarity inversion line number / 4-1) corresponding to the polarity inversion line number. It is determined whether or not there is (step S62). When it is determined in step S62 that the polarity inversion line number count value is (polarity inversion line number / 4-1) (step S62: Y), the polarity inversion line number counter 214 initially sets the polarity inversion line number count value. (Step S64). Thereafter, the process returns to step S60 (return). On the other hand, when it is determined in step S62 that the polarity inversion line number count value is not (polarity inversion line number / 4-1) (step S62: N), the polarity inversion line number counter 214 counts the polarity inversion line number. The value is incremented (step S66). Thereafter, the process returns to step S60 (return).

  When the horizontal synchronization signal HSYNC is not “1” in step S60 (step S60: N), the polarity inversion line number counter 214 returns to step S60 without updating the polarity inversion line number count value (step S68) (step S68). return).

FIG. 20 shows a flowchart of an operation example of the polarity inversion signal generation circuit 216.
The polarity inversion signal generation circuit 216 receives the horizontal synchronization signal HSYNC. When the horizontal synchronization signal HSYNC is “1” (step S70: Y), the polarity inversion signal generation circuit 216 determines whether or not the polarity inversion line number count value is (polarity inversion line number / 4-1). (Step S72). When it is determined in step S72 that the polarity inversion line number count value is (polarity inversion line number / 4-1) (step S72: Y), the polarity inversion signal generation circuit 216 sets the logic level of the polarity inversion signal FR. The output is inverted (step S74). Thereafter, the process returns to step S70 (return). On the other hand, when it is determined in step S72 that the polarity inversion line number count value is not (polarity inversion line number / 4-1) (step S72: N), the polarity inversion signal generation circuit 216 determines the polarity inversion signal FR. The logic level is not changed (step S76). Thereafter, the process returns to step S70 (return).

  When the horizontal synchronization signal HSYNC is not “1” in step S70 (step S70: N), the polarity inversion signal generation circuit 216 returns to step S70 without changing the logic level of the polarity inversion signal FR (step S78). (return).

Each part of the dummy insertion control circuit 200 having the configuration shown in FIG. 12 operates as shown in FIGS. 17 to 20, and various internal signals and count values change as follows.
FIG. 21 shows a timing chart of an operation example of the dummy insertion control circuit 200. FIG. 21 shows the timing for one field period. In FIG. 21, the number of display lines is “64”, the dummy insertion is one block insertion, the dummy insertion address is “7”, the dummy period display is off (fixed off data), and the polarity inversion line number is “12” ( = 3 blocks).

  As shown in FIG. 21, when the vertical synchronization signal VSYNC becomes “1”, each field period obtained by dividing one vertical scanning period is started. In each field period, one horizontal scanning period is started every time the horizontal synchronization signal HSYNC becomes “1”. The common address count value is updated every horizontal scanning period. When the common address count value becomes “6”, the common address becomes (dummy insertion address−1), and the dummy common address is set as the common address. Similarly, for the line address count value, when the line address count value becomes “27 (= 7 × 4-1)”, the line address becomes (dummy insertion address × 4-1), and the dummy line address is set as the line address. . As a result, the common driver 120 deselects all the common electrodes, and the segment driver 134 drives the segment electrodes based on the image data fixed by the display-on signal DON, and the dummy period is inserted. Thereafter, when the next horizontal scanning period is started, since the address immediately before dummy insertion is “6”, the scanning of the common electrode corresponding to the common address “7” and the driving of the segment electrode corresponding to the line address “28” are performed. Will continue.

  The count value of the polarity inversion lines is counted up every horizontal scanning period, and is set to “0” when the condition of step S62 in FIG. 19 is satisfied. The polarity inversion signal generation circuit 216 inverts the logic level of the polarity inversion signal FR when the polarity inversion line number count value is ((polarity inversion line number / 4) -1). Therefore, in FIG. 21, when the polarity inversion line number count value becomes “2”, the polarity inversion signal generation circuit 216 inverts the logic level of the polarity inversion signal FR. Thus, in the common address count values “0” to “2”, “6” to “7”,..., The polarity inversion signal FR is at the H level, the common address count values “3” to “5”, “8”. ”To“ 10 ”,..., The polarity inversion signal FR is at the L level.

  FIG. 22 shows an example of the drive timing of the liquid crystal drive device 100 according to the first embodiment. In FIG. 22, it is assumed that the number of display lines is “64” and the number of polarity inversion lines is “12”. Note that FIG. 22 is shown in accordance with the field period of FIG.

  As shown in FIG. 22, four lines of common electrodes are simultaneously selected, a selection voltage corresponding to the selection pattern is supplied, and a dummy period is inserted before the scanning period of the common electrode corresponding to the common address “7”. . In the dummy period, all the common electrodes are not selected. When the dummy period ends, scanning of the common electrode corresponding to the common address “7” is started, and scanning of the common electrode is continued.

  As described above, in the first embodiment, a dummy period is inserted in the scanning period of the common electrode. As a result, the output potential of the segment electrode of the mark portion can be changed, and the change in effective voltage caused by crosstalk due to polarity inversion driving can be adjusted. For example, the effective voltage can be lowered by slowing the change in the voltage of the segment electrode against crosstalk in which the off pixels above and below the mark portion are turned on by increasing the effective voltage by polarity inversion driving. In addition, by appropriately setting the insertion position of the dummy period, it becomes possible to improve ghosts caused by the slow voltage change of the segment electrodes.

[Modification of First Embodiment]
In the first embodiment, the example in which the potential corresponding to the image data that is the on pixel or the off pixel is uniformly applied to the segment electrode in the dummy period has been described, but the present invention is not limited to this. For example, dummy data is stored in an empty area of the image data RAM 128, and the image data RAM 128 buffers the image data and the dummy data. Then, dummy data may be read during the dummy period, and the potential of the segment electrode may be changed based on the dummy data. In this dummy period, all the common electrodes are not selected. In the case of MLS, the dummy data is preferably composed of data for one block (= 4 lines). This makes it possible to vary the potential for each segment electrode according to the display contents without uniformly changing the entire line to ON pixels or OFF pixels, and finely adjust the change in effective voltage caused by crosstalk. become able to.

[Second Embodiment]
In the first embodiment, since a dummy period in which the common electrode is not selected is inserted in the scanning period, a decrease in contrast due to the insertion of the dummy period may affect the image quality. Therefore, the second embodiment according to the present invention is realized by adopting any one of the scanning periods of the common electrode as the dummy period in the first embodiment and switching the scanning period. That is, as a dummy period, a part of the scanning period of the common electrode is inserted, the common electrode driver scans the common electrode corresponding to the inserted scanning period, and the segment electrode driver scans the inserted electrode. The segment electrode is driven based on the image data corresponding to the period. In this way, even if a dummy period is inserted, the image quality can be prevented from deteriorating without lowering the contrast.

[Liquid crystal drive]
FIG. 23 is a block diagram illustrating a configuration example of the liquid crystal driving device 100a according to the second embodiment. 23, the same reference numerals are given to the same components as those in FIG. 9, and description thereof will be omitted as appropriate. However, the liquid crystal driving device 100a is applied to the liquid crystal display system 10 in FIG. 1 instead of the liquid crystal driving device 100 in FIG. can do.

  The liquid crystal drive device 100a differs from the liquid crystal drive device 100 in that a control circuit 114a is provided in place of the control circuit 114, and control of output data of the image data latch circuit 130 by a display on signal DON is omitted. . The control circuit 114 a includes a block insertion control circuit 300 instead of the dummy insertion control circuit 200. The block insertion control circuit 300 performs control to switch the scanning period in units of blocks of the common electrodes that are simultaneously selected within the scanning period of the common electrodes that are sequentially scanned. As a result, all the common electrodes can be scanned without bringing the common electrode into a non-selected state, so that the output potential of the segment electrode in the mark portion can be changed while preventing the contrast from being lowered.

FIG. 24 is a block diagram showing a configuration example of the block insertion control circuit 300 shown in FIG. In FIG. 24, the same parts as those in FIG.
The block insertion control circuit 300 includes a block insertion setting register 302, a block insertion address register 304, a common address counter 306, and a line address counter 308. The block insertion control circuit 300 includes a polarity inversion line number setting register 212, a polarity inversion line number counter 214, and a polarity inversion signal generation circuit 216. The block insertion control circuit 300 controls the common address, the line address, and the polarity inversion signal FR using the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the field signals F1 and F2.

  The block insertion setting register 302 is configured to be accessible by the host processor 30 via the host processor interface 110, and a setting value corresponding to ON or OFF of the block insertion control is set. When a setting value corresponding to ON of the block insertion control is set in this register, the block insertion control circuit 300 sets another common electrode scanning period different from the scanning order in block units during the scanning period of the common electrode. Control to insert.

FIG. 25 is an explanatory diagram of the block insertion setting register 302. In FIG. 25, it is assumed that the block insertion setting register 302 is a 2-bit register.
According to the setting values (P1, P0) set in the block insertion setting register 302 by the host processor 30, it is possible to designate the block insertion control off and the block insertion control on. For example, if a plurality of common electrodes (four lines in this case) that are simultaneously selected by the MLS are defined as one block, the number of blocks to be inserted is designated when the block insertion control is turned on. In FIG. 25, one block (= 4 lines) is inserted when the set value (P1, P0) = (0, 1), and two blocks (= 8) when the set value (P1, P0) = (1, 0). Line) is inserted, and when the set value (P1, P0) = (1, 1), 3 blocks (= 12 lines) are inserted.

  FIG. 26A to FIG. 26D schematically illustrate the block insertion control. In FIGS. 26A to 26D, the length in the vertical direction corresponds to the vertical scanning period, and the length in the horizontal direction corresponds to the horizontal scanning period. FIG. 26A shows an image of a display image before inserting a block. FIG. 26B to FIG. 26D show images when block insertion for one block to three blocks is performed, respectively.

  As shown in FIG. 26A, consider a case where an image including a mark portion MK is displayed. In this case, display areas other than the mark portion MK are set as replacement blocks BLA, BLB, and BLC in units of blocks. When the set values (P1, P0) = (0, 1), as shown in FIG. 26B, the scanning period of the replacement block BLA is inserted within the scanning period of the mark portion MK. Similarly, when the set values (P1, P0) = (1, 0), as shown in FIG. 26C, the scanning periods of the replacement blocks BLA and BLB are inserted within the scanning period of the mark portion MK. When the set values (P1, P0) = (1, 1), as shown in FIG. 26D, the scanning periods of the replacement blocks BLA, BLB, and BLC are inserted within the scanning period of the mark portion MK. . In the scanning period of the replacement block BLA, BLB, BLC, the common electrode of each block is scanned and driven based on the corresponding image data.

  In FIG. 24, the block insertion address register 304 is configured to be accessible by the host processor 30 via the host processor interface 110. In the block insertion address register 304, a setting value corresponding to the insertion position in the scanning period of the common electrode and a setting value corresponding to the common electrode inserted in the specified insertion position are set. Here, a common address is set as these setting values.

FIG. 27 shows an explanatory diagram of the block insertion address register 304.
The block insertion address register 304 includes a block insertion address register (insertion source register) and an insertion destination address register (insertion destination register) for each replacement block. Here, three sets of a block insertion address register and an insertion destination address register are provided, and the first set includes a first block insertion address register 320 and a first insertion destination address register 322. The second set includes a second block insertion address register 324 and a second insertion destination address register 326. The third set includes a third block insertion address register 328 and a third insertion destination address register 330. In each block insertion address register, a common address (a set value in a broad sense) corresponding to the insertion position of the scanning period is set. In each insertion destination address register, a common address (a set value in a broad sense) corresponding to a common electrode inserted at a specified insertion position is set. Each register constituting the block insertion address register 304 is configured to be accessible by the host processor 30 via the host processor interface 110. When one block insertion is designated by the block insertion setting register 302, the common addresses set in the first block insertion address register 320 and the first insertion destination address register 322 are output to both counters. When two block insertion is designated by the block insertion setting register 302, the common addresses set in the second block insertion address register 324 and the second insertion destination address register 326 are output in addition to the one block insertion. When 3 block insertion is designated by the block insertion setting register 302, the common addresses set in the third block insertion address register 328 and the third insertion destination address register 330 are output in addition to the insertion of 2 blocks.

  In FIG. 24, a common address counter 306 counts a common address count value corresponding to a common address that specifies four lines of common electrodes that are simultaneously selected. The common address counter 306 outputs a common address corresponding to the common address count value. The line address counter 308 counts the line address count value corresponding to the line address corresponding to each common electrode selected at the same time. The line address counter 308 outputs a line address corresponding to the line address count value.

  Hereinafter, an example of the operation of each unit constituting the block insertion control circuit 300 will be described. In the following, for simplification of explanation, one block insertion will be described as an example, but it goes without saying that the same can be realized when two or three blocks are inserted.

FIG. 28 shows a flowchart of an operation example of the common address counter 306.
The common address counter 306 receives a vertical synchronization signal VSYNC, field signals F1 and F2, and a horizontal synchronization signal HSYNC. Internally, the field head signal FIELD is set to “1” at the start timing of the field period specified based on the field signals F1 and F2. At this time, when the vertical synchronization signal VSYNC is “1” or the field head signal FIELD is “1” (step S80: Y), the common address counter 306 sets the start address “0” as the common address (step S82). ). More specifically, the common address counter 306 sets “0” to the common address count value.

  On the other hand, when the vertical synchronization signal VSYNC is not “1” or the field head signal FIELD is not “1” (step S80: N), the common address counter 306 determines whether to update the common address count value based on the horizontal synchronization signal HSYNC. This is performed (step S84). In step S84, when the horizontal synchronization signal HSYNC is “1” (step S84: Y), the common address counter 306 determines whether or not the common address is an insertion destination address based on the common address count value (step S84). S86). Here, the insertion destination address is a common address set in the first insertion destination address register 322. When it is determined in step S86 that the common address is the insertion destination address (step S86: Y), the common address counter 306 sets the common address to (address immediately before block insertion + 1) (step S88). Specifically, the common address counter 306 sets the common address count value so that (address just before block insertion + 1) becomes the common address. Here, the address immediately before the block insertion is a common address immediately before the common address corresponding to the scanning period inserted in block units. Thereby, the scanning of the common electrode can be continued after the block is inserted.

  When it is determined in step S86 that the common address is not the insertion destination address (step S86: N), the common address counter 306 performs a common address determination process corresponding to the insertion position (step S90). That is, in step S90, the common address counter 306 determines whether or not the common address is (block insertion address-1) based on the common address count value. Here, the block insertion address is an address set in the first block insertion address register 320. When it is determined in step S90 that the common address is (block insertion address-1) (step S90: Y), the common address counter 306 sets the common address as the insertion destination address (step S92). Specifically, the common address counter 306 sets the common address count value so that the insertion destination address becomes the common address. As a result, the block insertion destination scanning period is inserted in units of blocks. On the other hand, when it is determined in step S90 that the common address is not (block insertion address-1) (step S90: N), the common address counter 306 increments the common address (step S94). Specifically, the common address counter 306 increments the common address count value.

  In step S84, when the horizontal synchronization signal HSYNC is not “1” (step S84: N), the common address counter 306 returns to step S80 without returning the common address count value (step S96) (return). Similarly, after step S82, step S88, step S92, and step S94, the process returns to step S80 (return).

  The common driver 120 that has received the common address corresponding to the common address count value counted as described above inserts the scanning period of the common electrode of the block insertion destination into the scanning period of the common electrode of the pixel formation region 22, All common electrodes can be scanned.

FIG. 29 shows a flowchart of an operation example of the line address counter 308.
The line address counter 308 receives a vertical synchronization signal VSYNC, field signals F1 and F2, and a horizontal synchronization signal HSYNC. When the vertical synchronization signal VSYNC is “1” or the field head signal FIELD is “1” (step S100: Y), the line address counter 308 sets the line address to “0” as the start address (step S102). More specifically, the line address counter 308 sets “0” to the line address count value.

  When the vertical synchronization signal VSYNC is not “1” or the field head signal FIELD is not “1” (step S100: N), the line address counter 308 makes an update determination of the line address count value based on the horizontal synchronization signal HSYNC (step S100). S104). In step S104, when the horizontal synchronization signal HSYNC is “1” (step S104: Y), the line address counter 308 determines whether or not the line address is (insertion destination address × 4 + 3) based on the line address count value. (Step S106). When it is determined in step S106 that the line address is (insertion destination address × 4 + 3) (step S106: Y), the line address counter 308 sets the line address to ((address immediately before block insertion + 1) × 4). (Step S108). Specifically, the line address counter 308 sets the line address count value so that ((address immediately before block insertion + 1) × 4) is the line address. Thereby, the drive of a segment electrode can be continued after block insertion.

  When it is determined in step S106 that the line address is not (insertion destination address × 4 + 3) (step S106: N), the line address counter 308 performs a process for determining the line address corresponding to the insertion position in the scanning period ( Step S110). That is, in step S110, the line address counter 308 determines whether or not the line address is (block insertion address × 4-1) based on the line address count value. When it is determined in step S110 that the line address is (block insertion address × 4-1) (step S110: Y), the line address counter 308 sets the line address to (insertion destination address × 4) ( Step S112). Specifically, the line address counter 308 sets the line address count value so that (insertion destination address × 4) becomes the line address. On the other hand, when it is determined in step S110 that the line address is not (block insertion address × 4-1) (step S110: N), the line address counter 308 increments the line address (step S114). Specifically, the line address counter 308 increments the line address count value.

  In step S104, when the horizontal synchronization signal HSYNC is not “1” (step S104: N), the line address counter 308 increments the line address (step S116), and returns to step S100 (return). Specifically, the line address counter 308 increments the line address count value in step S116. Similarly, after the processes of step S102, step S108, step S112, and step S114, the process returns to step S100 (return).

  The segment driver 134 drives the segment electrode in the pixel formation region 22 based on the image data read using the line address corresponding to the line address count value counted as described above.

Each part of the block insertion control circuit 300 having the configuration shown in FIG. 24 operates as shown in FIGS. 19 to 20 and FIGS. 28 to 29, so that various internal signals and count values change as follows.
FIG. 30 shows a timing chart of an operation example of the block insertion control circuit 300. FIG. 30 shows the timing for one field period. In FIG. 30, the number of display lines is “64”, the block insertion is one block insertion, the block insertion address is “7”, the insertion destination address is “15”, and the polarity inversion line number is “12” (= 3 blocks). ).

  As shown in FIG. 30, when the vertical synchronization signal VSYNC becomes “1”, each field period obtained by dividing one vertical scanning period is started. In each field period, one horizontal scanning period is started every time the horizontal synchronization signal HSYNC becomes “1”. The common address count value is updated every horizontal scanning period. When the common address count value becomes “6”, the common address becomes (block insertion address−1), and the insertion destination address is set as the common address. Similarly, for the line address count value, when the line address count value is “27 (= 7 × 4-1)”, the line address is (block insertion address × 4-1), and the line address is (insertion destination address × 4). “60 (= 15 × 4)” is set. Thereby, the common driver 120 scans the common electrode corresponding to the insertion destination address “15”, and the segment driver 134 drives the segment electrode based on the image data of the line addresses “60” to “63”. Thereafter, when the next horizontal scanning period is started, since the address immediately before dummy insertion is “6”, the scanning of the common electrode corresponding to the common address “7” and the driving of the segment electrode corresponding to the line address “28” are performed. Will continue.

  For the polarity inversion signal FR, the common address count values “0” to “2”, “6” to “7”,..., The polarity inversion signal FR is at the H level, and the common address count values “3” to “3”. In the case of “5”, “8” to “10”,..., The polarity inversion signal FR becomes L level.

  FIG. 31 shows an example of the drive timing of the liquid crystal drive device 100a in the second embodiment. In FIG. 31, it is assumed that the number of display lines is “64” and the number of polarity inversion lines is “12”. Note that FIG. 31 is shown in accordance with the field period of FIG.

  As shown in FIG. 31, four lines of common electrodes are simultaneously selected, a selection voltage corresponding to the selection pattern is supplied, and before the scanning period of the common electrode corresponding to the common address “7”, the common address “15” The scanning period of the common electrode corresponding to is inserted. When the inserted scanning period ends, scanning of the common electrode corresponding to the common address “7” is started, and scanning of the common electrode is continued. As described above, the liquid crystal driving device 100 a scans the common electrode corresponding to the setting value of the first insertion destination address register 322 during the period corresponding to the setting value of the first block insertion address register 320. At this time, the liquid crystal driving device 100a drives the segment electrode based on the image data corresponding to the setting value of the first insertion destination address register 322 during the period corresponding to the setting value of the first block insertion address register 320. be able to.

  As described above, in the second embodiment, a scanning period different from the scanning order is inserted in the scanning period of the common electrode. Thereby, when there is almost no continuity between the image in the original scanning period of the common electrode and the image in the inserted scanning period, the same effect as that in the case of inserting the dummy period can be obtained. As a result, the output potential of the segment electrode in the mark portion can be changed, and the change in effective voltage caused by crosstalk due to polarity inversion driving can be adjusted.

[Other variations]
When the image data RAM included in the liquid crystal driving device has a storage area for two screens, display data for the next screen is buffered when one screen is displayed. Thereby, the display content can be changed only by changing the display start line address. In such a case, image quality degradation due to crosstalk depends on the display content, so it is desirable that the dummy period insertion position and block insertion position can be changed for each display screen. For example, the dummy insertion setting register 202, the dummy insertion address register 204, the dummy data setting register 210, and the polarity inversion line number setting register 212 of FIG. 12 may be provided for each screen. Alternatively, for example, the block insertion setting register 302, the block insertion address register 304, and the polarity inversion line number setting register 212 of FIG. 24 may be provided for each screen.

〔Electronics〕
The liquid crystal driving device or the liquid crystal display panel or the liquid crystal display system to which the liquid crystal driving device or the liquid crystal driving device according to any one of the above-described embodiments or modifications thereof is applied can be applied to the following electronic devices.
FIGS. 32A and 32B are perspective views illustrating configurations of electronic devices to which any of the above-described embodiments or modifications thereof are applied. FIG. 32A is a perspective view of a configuration of a mobile personal computer. FIG. 32B illustrates a perspective view of a structure of a mobile phone.

  A personal computer 800 illustrated in FIG. 32A includes a main body portion 810 and a display portion 820. As the display unit 820, the liquid crystal display panel or the liquid crystal display system in any of the above-described embodiments or modifications thereof is applied. The main body 810 includes a host processor, and the main body 810 is provided with a keyboard 830. That is, the personal computer 800 includes at least the liquid crystal driving device according to any of the above-described embodiments or modifications thereof. The operation information via the keyboard 830 is analyzed by the host processor, and an image is displayed on the display unit 820 according to the operation information.

  A cellular phone 900 illustrated in FIG. 32B includes a main body portion 910 and a display portion 920. As the display unit 920, the liquid crystal display panel or the liquid crystal display system in any one of the above-described embodiments or modifications thereof is applied. The main body 910 includes a host processor, and the main body 910 is provided with a keyboard 930. That is, the mobile phone 900 is configured to include the liquid crystal driving device in any of the above-described embodiments or modifications thereof. Operation information via the keyboard 930 is analyzed by the host processor, and an image is displayed on the display unit 920 in accordance with the operation information.

  Note that electronic devices to which any of the above-described embodiments or modifications thereof are applied are not limited to those shown in FIGS. 32A and 32B. For example, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, POS (Point of sale systems ) Devices such as terminals, printers, scanners, copiers, video players and touch panels.

  As described above, the liquid crystal driving device, the liquid crystal display device, the electronic apparatus, the liquid crystal driving method, and the like according to the present invention have been described based on any one of the above-described embodiments or modifications thereof. Or it is not limited to the modification. For example, the present invention can be implemented in various modes without departing from the gist thereof, and the following modifications are possible.

  (1) In the above embodiment, an example in which the liquid crystal driving device is driven by the MLS driving method has been described, but the present invention is not limited to this.

  (2) In the above embodiment, the present invention has been described as a liquid crystal driving device, a liquid crystal display device, an electronic apparatus, a liquid crystal driving method, and the like, but the present invention is not limited to this.

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display system, 20 ... Liquid crystal display panel, 22 ... Pixel formation area,
30 ... Host processor, 40 ... Power supply circuit, 100, 100a ... Liquid crystal drive device,
110: Host processor interface 112: Oscillator circuit,
114: Control circuit, 116: Common address decoder,
118 ... Common output arithmetic circuit, 120 ... Common driver,
122: Page address control circuit, 124 ... Column address control circuit,
126: Line address control circuit, 128: Image data RAM,
130: Image data latch circuit, 132: MLS decoder,
134: Segment driver 200: Dummy insertion control circuit,
202 ... dummy insertion setting register, 204 ... dummy insertion address register,
206, 306 ... Common address counter,
208, 308 ... line address counter, 210 ... dummy data setting register,
212 ... polarity inversion line number setting register, 214 ... polarity inversion line number counter,
216: Polarity inversion signal generation circuit, 220: First address register,
222 ... second address register, 224 ... third address register,
300 ... Block insertion control circuit, 302 ... Block insertion setting register,
304: Block insertion address register, COM0 to COMQ: Common electrode,
FR: Polarity inversion signal, SEG0 to SEGR: Segment electrode

Claims (13)

A liquid crystal driving device for driving a passive liquid crystal display device,
A scanning control unit for inserting a dummy period within the scanning period of the common electrode of the liquid crystal display device;
Scanning the common electrode within the scanning period, and a common electrode driving unit for deselecting the common electrode in the dummy period;
A segment for driving the segment electrode of the liquid crystal display device based on image data corresponding to the common electrode scanned by the common electrode driving unit, and for driving the segment electrode based on given dummy data in the dummy period An electrode driver;
A polarity inversion control unit that performs control for inverting the polarity of the voltage between the common electrode driven by the common electrode driving unit and the segment electrode driven by the segment electrode driving unit for each given number of polarity inversion lines; A liquid crystal driving device comprising: In claim 1,
The scanning control unit
A dummy insertion register in which a setting value corresponding to the insertion position of the dummy period in the scanning period is set;
The common electrode driver is
Deselecting the common electrode during the dummy period corresponding to the setting value of the dummy insertion register,
The segment electrode driver is
The liquid crystal driving device according to claim 1, wherein the segment electrode is driven based on the dummy data during the dummy period corresponding to a set value of the dummy insertion register. In claim 1 or 2,
An image data memory in which the image data and the dummy data are buffered;
The segment electrode driver is
In the dummy period, the segment electrode is driven based on the dummy data read from the image data memory. In any one of Claims 1 thru | or 3,
The dummy data is
A liquid crystal driving device comprising inverted data of image data corresponding to a scanning period immediately before insertion. In any one of Claims 1 thru | or 4,
The dummy data is
2. A liquid crystal driving device according to claim 1, wherein the data is data in which one line is all on or all off in the dummy period. In claim 1,
The scanning control unit
As the dummy period, insert any part of the scanning period of the common electrode,
The common electrode driver is
Scan the common electrode corresponding to the scanning period inserted by the scanning control unit,
The segment electrode driver is
A liquid crystal driving device, wherein the segment electrode is driven based on image data corresponding to a scanning period inserted by the scanning control unit. In claim 6,
The scanning control unit
An insertion source register in which a setting value corresponding to the insertion position of the dummy period in the scanning period is set;
An insertion destination register in which a setting value corresponding to any part of the scanning period of the common electrode inserted as the dummy period is set,
The common electrode driver is
During the dummy period corresponding to the setting value of the insertion source register, the common electrode corresponding to the setting value of the insertion destination register is scanned,
The segment electrode driver is
The liquid crystal driving device, wherein the segment electrode is driven based on image data corresponding to a setting value of the insertion destination register during the dummy period corresponding to a setting value of the insertion source register. In any one of Claims 1 thru | or 7,
A polarity inversion line number setting register in which a setting value corresponding to the number of polarity inversion lines is set;
The common electrode driver is
The common electrode is scanned using a selection voltage obtained by inverting the polarity for each number of polarity inversion lines corresponding to the setting value of the polarity inversion line number setting register,
The segment electrode driver is
A liquid crystal driving device, wherein a segment electrode is driven by using a driving voltage whose polarity is inverted every number of polarity inversion lines corresponding to a setting value of the polarity inversion line number setting register. In any one of Claims 1 thru | or 8.
The common electrode driver is
Scanning the common electrode of the liquid crystal display device in a selection pattern corresponding to each field over a plurality of fields in a block unit in which a plurality of simultaneously selected common electrodes are one block;
The segment electrode driver is
Driving the segment electrodes of the liquid crystal display device with image data corresponding to the plurality of common electrodes selected simultaneously and a drive voltage corresponding to the selection pattern;
The liquid crystal driving device according to claim 1, wherein the number of polarity inversion lines is a multiple of the number of the plurality of common electrodes selected simultaneously. A plurality of common electrodes;
A plurality of segment electrodes provided crossing the plurality of common electrodes;
A liquid crystal display device comprising: the liquid crystal drive device according to claim 1, wherein the liquid crystal drive device scans the plurality of common electrodes and drives the plurality of segment electrodes.   An electronic apparatus comprising the liquid crystal display device according to claim 10. A liquid crystal driving method for driving a passive liquid crystal display device,
A scanning control step of inserting a dummy period within the scanning period of the common electrode of the liquid crystal display device;
A common electrode driving step of scanning the common electrode within the scanning period and deselecting the common electrode in the dummy period;
A segment for driving the segment electrode of the liquid crystal display device based on image data corresponding to the common electrode scanned in the common electrode driving step, and for driving the segment electrode based on given dummy data in the dummy period. An electrode driving step;
A polarity inversion control step for performing control for inverting the polarity of the voltage between the common electrode driven in the common electrode driving step and the segment electrode driven in the segment electrode driving step for each given number of polarity inversion lines. A liquid crystal driving method comprising: In claim 12,
The scanning control step includes
As the dummy period, insert any part of the scanning period of the common electrode,
The common electrode driving step includes:
Scanning the common electrode corresponding to the scanning period inserted in the scanning control step;
The segment electrode driving step includes:
A liquid crystal driving method, wherein the segment electrode is driven based on image data corresponding to a scanning period inserted in the scanning control step.