JP5842946B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit that controls connection and non-connection of an internal voltage line of a circuit block and a wiring to which a power supply voltage or a reference voltage is applied by a switch.

An MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor) technique is known as a circuit that controls the interruption and release of power supply by a switch.
Generally, it is necessary to lower the threshold voltage of a transistor such as a logic circuit as a design value so that signal delay does not occur accompanying power supply voltage reduction or element miniaturization. When the threshold voltage of a transistor such as a logic circuit is small, the leakage current is large. In the MTCMOS technology, a leakage current path is blocked by a transistor (power switch) having a larger threshold voltage than a transistor such as a logic circuit in a stopped state, thereby preventing waste of power consumption.

In application of the MTCMOS technology to a circuit block, an internal voltage line provided in the circuit block, which is called a virtual VDD line or a virtual GND line, is provided. The internal voltage line has a power switch for shutting off and releasing the power supply for the global real power line (real VDD line) and real reference voltage line (real VSS line) that connect the blocks outside the circuit block. Connected through.
There are three power switch locations: between the functional circuit that is repeatedly activated and deactivated and the actual VDD line, and between the functional circuit and the actual VSS line. An NMOS transistor is used on the transistor and VSS line side.

  The activation and deactivation of the functional circuit of the MTCMOS application block is performed by a circuit in the MTCMOS non-application block that is always in operation after receiving power supply from the actual VDD line and the actual VSS line after the semiconductor integrated circuit is activated. Be controlled. Alternatively, a configuration may be employed in which a control signal for controlling activation and stop of the functional circuit of the MTCMOS application block can be input from an external terminal of the semiconductor integrated circuit.

  By the way, the power switch may be realized by a cell in an MTCMOS application block. More specifically, in the MTCMOS application block, when a power switch is provided in each logic circuit cell such as an inverter, NAND circuit, NOR circuit, etc., or in a functional circuit cell realized by several logic circuits, A dedicated power switch cell that does not have a circuit or a functional circuit may be provided. Hereinafter, this type of switch arrangement is referred to as an “internal switch (SW) arrangement”, and a semiconductor integrated circuit employing the arrangement is referred to as an “internal SW arrangement type IC”.

A semiconductor integrated circuit is known in which a power switch is arranged around a circuit block to be controlled for power supply with respect to an internal SW arrangement IC (see, for example, Patent Document 1 and Patent Document 2). This type of switch arrangement is referred to as “external SW arrangement”, and a semiconductor integrated circuit employing this arrangement is referred to as “external SW arrangement type IC”.
The external SW arrangement is suitably used in combination with a circuit block that includes a general-purpose circuit (for example, a memory, a CPU, or the like) called a “macro” in part or in whole.

In Patent Document 2, transistor cells (switches) having a longitudinal direction along each side are arranged for three or four sides of a circuit block, and the arrangement direction of transistor gate lines in the switch is the longitudinal direction. The same configuration is disclosed.
In this configuration, the VDD supply ring and the VSS supply ring are arranged as annular lines surrounding the circuit block in an annular shape on the side opposite to the circuit block (outside) of the transistor cell arrangement region. The VDD supply ring and the drain of the switch transistor are connected by a metal wiring layer having a layer different from that of the VDD supply ring. The VSS supply ring and the VSS line in the circuit block are connected by a metal wiring layer having a layer different from that of the VSS supply ring. In addition, the source of the switch transistor and the virtual VSS line in the circuit block are connected by a metal wiring layer having a layer different from that of the VSS supply ring.

JP 2003-289245 A JP 2003-158189 A

In the semiconductor integrated circuit described in Patent Document 1, since the VDD voltage supply line is not annularly arranged around the circuit block (internal circuit), the voltage at the VDD voltage supply line is far from the VDD voltage supply source. Dropping occurs, and as a result, even if a switch transistor of the same size as the other is turned on or off for the same time, a difference occurs in the ability to charge and discharge the internal voltage line of the internal circuit. For this reason, it is necessary to devise such as increasing the size of the switch transistor or increasing the number of transistors as the position is farther from the VDD voltage supply source. As a result, there is a disadvantage that the leakage current through the switch transistor increases when the internal circuit is stopped.
The threshold voltage of the switch transistor is set larger than the threshold voltage of the transistor in the internal circuit, and the leakage current is relatively small. However, if the stop period is long, useless power consumption due to an increase in the size and number of switch transistors cannot be ignored.

  In the semiconductor integrated circuit described in Patent Document 2, the supply lines of the VDD voltage and the VSS voltage are annularly arranged as a supply ring, so that the voltage is higher than that of the semiconductor integrated circuit described in Patent Document 1 without the supply ring. The voltage drop from the supply source to each switch transistor is made uniform. Therefore, the increase in the leakage current is relatively suppressed.

  However, in the semiconductor integrated circuit described in Patent Document 2, since the annular line (supply ring) is arranged separately from the switch transistor, the switch transistor and the supply ring (VDD supply ring and VSS supply ring) are connected. Wiring is complicated.

  Although the VDD supply ring and the VSS supply ring are provided for the purpose of uniforming the voltage drop, the potential may not be completely uniform due to the influence of the peripheral operation circuit. Of course, by reducing the wiring resistance of these supply rings, it becomes more uniform, but in the vicinity of peripheral circuits that frequently operate with a large amplitude, for example, the potential of the VSS supply ring becomes the reference potential (for example, 0 [V]). However, since it is difficult to fully estimate the operation of the peripheral circuit, to avoid the influence of the peripheral circuit and stabilize the operation of the switch transistor, the position of the switch transistor is shifted during the design, or It is necessary to change the size, and the design burden of redoing the connection wiring is large.

That is, the configuration of the switch transistor described in Patent Document 2 (referred to as “macro” in the Patent Document) does not have a structure corresponding to such a design change.
The fact that the position and size of the switch transistor are important is that, in Patent Document 2, various changes such as changing the size of the switch transistor or providing double switch transistors are shown. it is obvious.

According to the present invention, a rectangular circuit block having an internal power supply line having a row-direction wiring and a column-direction wiring, and arranged to surround the internal block outside the circuit block, the internal power supply of the circuit block lines and is electrically connected to a second power source line having a wiring row direction wiring and the column direction, are arranged to surround the inner block further outside of the second power supply line surrounding the inner block , supply voltage or reference voltage is applied, electrical connection and control the disconnection of the first power source line having a wiring row direction wiring and the column direction, and the second power supply line and the first power supply line And a switch to
The internal power supply line in the column direction is formed one layer above the layer in which the internal power supply line in the row direction is formed, and is connected at the intersection of these ends,
Form the column-direction wiring of the second power supply line one layer above the layer in which the row-direction wiring of the second power supply line is formed, and connect at the intersection of these ends,
The first power supply line in the column direction is formed one layer above the layer in which the first power supply line in the row direction is formed, and is connected at the intersection of these ends,
The row of the internal power supply line in the row direction is formed one layer above the layer in which the column direction wiring of the second power supply line is formed,
The wiring in the column direction of the first power supply line is formed in the same layer as the layer in which the wiring in the column direction of the second power supply line is formed,
The switch is arranged in a lower layer of the first power supply line and the second power supply line every four sides of the internal block so as to surround the internal block .
A semiconductor integrated circuit is provided.

Preferably, a plurality of the switches are disposed below the first power supply line and the second power supply line.

Preferably, each of the plurality of switches is connected to one of a plurality of control lines capable of switch control independently of each other.

According to the configuration of the other form described above, two annular rail lines are formed, which are referred to as first and second annular rail lines.
Therefore, each of the plurality of switch blocks includes a first voltage line segment that is a part of the first annular rail line, and a second voltage line segment that is a part of the second annular rail line, A switch is connected between the second voltage line segments. In this case, preferably, in the plurality of switch blocks, the positional relationship between the first and second annular rail lines and the switches is constant.
Therefore, the switch blocks are adjacent to each other and the first voltage line segments are connected to each other, or the second voltage line segments are connected to each other, or when the distance is long, the corresponding voltage line segments are connected by wiring. Two annular rail lines are formed which are closed around the circuit block.

When the position of the switch block is moved, components other than the voltage line segment of the switch block to be moved are moved to a desired position, and are connected to the annular rail line at the moved position.
At this time, in the above-described one form, the connection with the circuit block may need to be changed. In particular, when the first and second annular rail lines are provided for each switch block as in the other form, the circuit block There is no need to change the connection. For this reason, the switch block can be freely moved on the power line rail only by moving the components other than the first and second voltage line segments of the switch block with respect to the first and second annular rail lines, respectively.

  The above is an explanation of the operation of the switch movement. However, when a switch is inserted or deleted, similarly, components other than the voltage line segment (or the first and second voltage line segments) of the switch block are required. You can insert and delete as many as you need.

  According to the present invention, when moving or changing the number of switches, it is mainly necessary to change the components other than the voltage line segments of the switch block. Therefore, the design can be easily changed and the position and number of the switches can be optimized. The benefit is that it is easy. More specifically, when the power supply voltage or reference voltage supply line is separated from the switch and the mutual positional relationship is not uniform, the metal wiring layer at a different level is used for design changes such as switch movement, switch insertion, and deletion. However, in the present invention, there is no need to rework wiring other than the annular rail line one by one.

1 is a block diagram showing an overall configuration of a semiconductor integrated circuit according to an embodiment of the present invention. It is an internal block diagram of the circuit block of the power-off target related to the embodiment. It is a figure which shows the rail arrangement example 1 of embodiment. It is a figure which shows the rail arrangement example 2 of embodiment. In an embodiment, it is a figure showing wiring of a control line to a circuit block and its surrounding switch block. It is a block diagram which shows the structure which does not have an annular rail line. In an embodiment, it is a figure showing typically arrangement of a switch transistor. In relation to the embodiment, (A) is a configuration diagram of an upper switch block, and (B) is a configuration diagram of a lower switch block. (A) is a block diagram of a left switch block, and (B) is a block diagram of a right switch block. It is a figure which shows the use condition of the wiring layer of each hierarchy in a multilayer wiring structure with the code | symbol of 1M-7M. FIG. 3 is a schematic layout diagram of a switch cell according to the embodiment. FIG. 5 is a schematic layout diagram of another switch cell according to the embodiment. FIG. 12A is a configuration diagram of an upper switch block formed using the switch cell of FIG. 11, and FIG. 12B is a configuration diagram of a lower switch block according to the embodiment. (A) is a block diagram of a left switch block formed using the switch cell of FIG. 11, and (B) is a block diagram of a right switch block. In an embodiment, it is a figure showing proper arrangement of the number of switch blocks.

  Embodiments of the present invention will be described below with reference to the drawings.

<Overall configuration>
FIG. 1 shows the overall configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
In FIG. 1, a plurality of input / output cells 40 are arranged in rows along four sides of a rectangular semiconductor chip on which a semiconductor integrated circuit is formed.

Several circuit blocks are arranged in a chip area for circuit arrangement surrounded by the input / output cell 40 shown in FIG. In the example shown in FIG. 1, a basic configuration of a semiconductor integrated circuit called “energization region”, for example, an energization circuit block 32 including a CPU, a register, a memory, a power supply circuit, and the like is arranged in the chip area. The energizing circuit block 32 corresponds to a non-applied circuit block of the MTCMOS technology, and always operates after receiving the supply of the power supply voltage VDD and the reference voltage VSS after the semiconductor integrated circuit is activated.
In the chip area for circuit arrangement, a number of circuit blocks including part or all of general-purpose circuits that are individually designed to be diverted in other semiconductor integrated circuits are arranged. Yes. The “macro” can be designed by outsourcing and can be purchased from other companies as an IP (Intellectual Property).

A circuit block as a “macro”, like the energization circuit block 32, is an MTCMOS called an “energization macro” that operates with the supply of the power supply voltage VDD and the reference voltage VSS at all times after the semiconductor integrated circuit is activated. Non-applied circuit block 33 to which the technology is not applied and circuit block 1 that is called “power-off macro” and to which power-off is appropriately performed when the MTCMOS technology is applied and power is cut off as necessary. it can.
Note that the energizing circuit block 32, the non-applicable circuit block 33, and the circuit block 1 to be powered off arranged in the chip area surrounded by the input / output cell 40 are omitted in FIG. And the real VSS line are arranged in a pair, thereby receiving power supply. More specifically, some of the input / output cells 40 are allocated for power supply, and the row (row) direction and the column (column) direction in the chip area from the input / output cells 40 for power supply. The actual power supply line pair is wired to each of the power supply circuit blocks 32, thereby providing power supply wiring for the energizing circuit block 32, the non-applicable circuit block 33, and the circuit block 1 to be shut off.

The circuit block 1 subject to power interruption is a so-called “external SW arrangement type” in which a switch for controlling power interruption and connection is arranged around the circuit block 1 subject to power interruption. As shown in FIG. 1, a predetermined number of switch blocks 2 including switches are arranged around a circuit block 1 to be powered off.
Although not shown in FIG. 1, the annular rail line to which the power supply voltage VDD or the reference voltage VSS is applied is arranged so as to overlap the plurality of switch blocks 2 arranged around the circuit block 1 to be shut off. Has been. At least one annular rail line is provided, preferably two. Hereinafter, the positional relationship between the annular rail line and the switch block 2 will be described with reference to the drawings.

As described above, in the MTCMOS technology, there are three places where the switch transistor is provided, that is, between the functional circuit that is repeatedly activated and deactivated and the actual VDD line, and between the functional circuit and the actual VSS line. In general, a PMOS transistor is used on the VDD side, and an NMOS transistor is used on the VSS line side.
The place where the switch transistor is provided in this embodiment may be any of the above three types. However, if switch transistors are provided on both the VDD side and the VSS side, the disadvantage of increasing the occupied area is great for the effect. Therefore, the switch transistors are preferably provided on one side of the VDD side and the VSS side. Further, since the NMOS transistor has a higher driving capability per unit gate width than the PMOS transistor, it is more desirable to provide a switch transistor on the VSS side.
Therefore, in the following description, it is assumed that a switch (transistor) is provided on the VSS side.

FIG. 2 shows an example of the internal configuration of the circuit block 1 to be powered off.
In the illustrated configuration example, the circuit block 1 is divided into a standard cell arrangement region 1A in which a functional circuit is realized by standard cells and a macro cell region 1B such as a RAM. With regard to the application of the present invention, the “circuit block” subject to power shutdown control does not need to have a “macro”, and may be configured with only the standard cell arrangement region 1A.
On the standard cell arrangement region 1A and the macro cell region 1B, internal voltage lines 11 referred to as so-called “virtual VSS lines” to which the reference voltage VSS is applied are arranged in parallel in the row (row) direction and the column (column) direction. ing. The internal voltage line 11 in the row direction and the internal voltage line 11 in the column direction are formed by a wiring layer higher than the cell and are interconnected at the intersection.
On the other hand, although illustration is omitted to avoid complication, a power line to which a power supply voltage VDD is applied, which is called a “real VDD line”, and further a power supply line to which a reference voltage VSS is applied are the same. Are arranged in a grid pattern.

In the standard cell arrangement region 1A, a plurality of branch lines 11A extend in the row direction at predetermined intervals from the column direction trunk wiring of the internal voltage line 11 as the “virtual VSS line”. In the standard cell arrangement region 1A, a plurality of branch lines 12A extend in the row direction at a predetermined interval from a column-direction trunk line of a voltage supply line (not shown) as a “real VDD line”.
In FIG. 2, one inverter cell 13 is shown enlarged as a representative of the standard cell. The inverter cell 13 has a VSS line segment which is a part of the branch line 11A and a VDD line segment which is a part of the branch line 12A, and a PMOS transistor and an NMOS transistor are connected in series between the two segments. ing. Both the gates of the PMOS transistor and the NMOS transistor are connected to the input signal line. A node between the PMOS transistor and the NMOS transistor is connected to the output signal line. The input signal line and the output signal line are formed by the signal line segment in the inverter cell 13 and the adjacent cell. However, the input / output lines of the entire standard cell arrangement region 1A are formed by an upper wiring layer (not shown).

<Rail arrangement example 1>
FIG. 3 shows an example 1 of rail arrangement.
As illustrated in FIG. 3, a plurality of switch blocks 2 are arranged so as to surround the circuit block 1 in the vicinity of the four sides of the circuit block 1 to be powered off. Here, for convenience, the switch block 2 is classified into an upper switch block 2U, a lower switch block 2D, a right switch block 2R, and a left switch block 2L for each side of the circuit block 1 to be powered off. The upper switch blocks 2U, the lower switch blocks 2D, the right switch blocks 2R, and the left switch blocks 2L have the same configuration.

Each of the four types of switch blocks 2U, 2D, 2R, 2L includes a voltage line segment 21 and a switch (not shown).
The voltage line segment 21 is a wiring portion which is shown by a broken line in FIG. 3 and becomes a part of the annular rail line 3 forming a closed annular line around the circuit block 1 to be shut off.
In the layout and wiring design stage, the annular rail line 3 is arranged and connected to the switch or the like in the wiring stage after the switch is arranged. Once arranged and connected, the components other than the voltage line segment 21 (including the switch) are moved in units of the switch blocks 2U, 2D, 2R, and 2L, and the annular rail line 3 is moved to the position after the movement. Connect a switch, etc. In FIG. 3, the internal voltage line 11 (see FIG. 2) in the circuit block 1 to be turned off and the switch connection wiring must be changed each time the switch block is moved. However, with respect to the annular rail line 3, there is no need to change the connection wiring with the switch, and the switch can be easily moved accordingly.

In the case of inserting a switch block, in the same manner, a component other than the voltage line segment 21 in the switch block is used as a unit, and the required number is inserted in a necessary place, and a switch or the like is inserted into the annular rail line 3 at that place. Connect.
The same applies to the case of deleting the switch, and the components other than the voltage line segment 21 in the switch block are deleted as a unit.
Even when the switch is inserted or deleted, there is no need to change the connection wiring with the switch with respect to the annular rail line 3, and the switch can be easily moved accordingly.

<Rail arrangement example 2>
FIG. 4 shows a second rail arrangement example.
4 is provided with a virtual annular rail line 3V as a “second annular rail line” in addition to the annular rail line 3 as a “first annular rail line”. It has been.
The virtual annular rail line 3 </ b> V is disposed in parallel with the annular rail line 3 between the annular rail line 3 and the circuit block 1 to be shut off. The virtual annular rail line 3V is connected to the internal voltage line 11 (see FIG. 2) in the circuit block 1 to be powered off, in a predetermined location, for example, in the case of FIG. 4 points in the column direction).
In each of the switch blocks 2U, 2D, 2R, 2L, a switch (not shown) is connected between the annular rail line 3 (voltage line segment 21) and the virtual annular rail line 3V (virtual voltage line segment 21V).

The second difference is that each of the switch blocks 2U, 2D, 2R, 2L has a virtual voltage line segment as a “second voltage line segment” in parallel with the voltage line segment 21 as a “first voltage line segment”. 21V is provided.
Other arrangements of the switch blocks 2U, 2D, 2R, and 2L with respect to the circuit block 1 that is the target of power cutoff are the same as those in FIG.

In the rail arrangement example 2 as well, as in the rail arrangement example 1, only the components other than the voltage line segment 21 and the virtual voltage line segment 21V of the switch block are moved, inserted, and deleted. Therefore, it is easy to move the switch.
Further, in the rail arrangement example 2, the virtual annular rail line 3V is connected to, for example, each end of the internal voltage line 11 (three locations in the row direction and four locations in the column direction). Even with regard to the virtual annular rail line 3V, there is no need to change the connection wiring with the switch, and the switch can be easily moved accordingly.

In the rail arrangement example 1 (FIG. 3) and the rail arrangement example 2 (FIG. 4) described above, the components other than the voltage line segment 21 (and virtual voltage line segment 21V) of the switch block described above are the annular rail lines 3 (and virtual lines). It has already been described that the position and number of switch blocks can be freely changed by simply moving, inserting and deleting along the annular rail line 3V).
In order to enable this free design change, the sizes of the switch blocks 2U, 2D, 2R, and 2L are the same, and each block frame is opposed to each other across the annular rail line 3 (and the virtual annular rail line 3V). On the two sides, it is necessary that the edge positions of the voltage line segment 21 (and the virtual voltage line segment 21V) are standardized (constant).

  If the edge positions are not standardized, the components other than the voltage line segment 21 (and virtual voltage line segment 21V) of the switch block are moved along the annular rail line 3 (and virtual annular rail line 3V). After the insertion and deletion, it is necessary to correct the pattern of the voltage line segment 21 (and the virtual annular rail line 3V) so as to connect the ends between adjacent switch blocks. However, since this operation is a simple operation for connecting the end sides, it can be automated. Therefore, it is easier to change the switch arrangement at each stage after the switch arrangement as compared with the case where the connection line is redone using the annular line arranged outside the switch and the wiring layer of another layer manually.

<Switch control line>
Although not shown in FIGS. 3 and 4, a plurality of switch control lines may be wired depending on the number of switch groups to be controlled simultaneously.

FIG. 5 is a diagram illustrating an example of wiring of control lines when there are two control lines. Here, the rail arrangement example 2 (FIG. 4) is adopted for the annular rail line.
The control circuit 34 shown in FIG. 5 is provided in an MTCMOS non-application circuit block such as the energization circuit block 32 and the non-application circuit block 33 in FIG. It is a circuit that can operate upon receiving. The control line 35 from the control circuit 34 is wired in the order of the upper switch block 2U, the left switch block 2L, the lower switch block 2D, and the right switch block 2R, and the control signals are applied in this order. The control signal controls the conduction and non-conduction of the switches in each switch block.

Note that the configuration shown in FIG. 5 is provided with a branch of the actual VSS wiring at a predetermined position of the annular rail line 3 so that it can be used in place of the configuration without the annular rail line shown in FIG.
In the external SW arrangement configuration to which the present invention is not applied as shown in FIG. 6, each global real VSS wiring 5 provided in a grid is connected to the circuit block 1 to be powered off via the switch block SB. .
The annular rail line 3 shown in FIG. 5 is connected to the actual VSS wiring 5 arranged in a grid pattern at two places in the row direction and four places in the column direction.
On the other hand, the virtual annular rail line 3V is connected to the circuit block 1 to be shut off at six locations in the row direction and eight locations in the column direction.
These connection points need not be changed at all when the switch blocks 2U, 2D, 2R, and 2L are moved, inserted, and deleted.

  Next, a more detailed switch configuration will be described with reference to the drawings, taking as an example the case of switch control by two control lines 35.

<Switch configuration example>
FIG. 7 schematically shows the arrangement of switch transistors between a voltage line segment 21 to which a reference voltage VSS (for example, 0 [V]) is applied and a virtual voltage line segment 21V held at the virtual reference voltage VSSV. It is a block diagram of a block.
In FIG. 7, the voltage line segment 21 is provided with three branch lines 21B, and the virtual voltage line segment 21V is provided with three branch lines 21VB. The branch lines 21B and the branch lines 21VB are alternately arranged. Four switch transistors SWT are connected in parallel between one branch line 21B and one adjacent branch line 21VB. This switch transistor array is provided in five stages, and a total of 4 × 5 = 20 switch transistors SWT are arranged in a matrix.

  Of the 20 switch transistors SWT, conduction and non-conduction are controlled by a single control line (not shown) for a total of five switch transistors SWT, one for each stage. The circuit symbol portions of the five switch transistors SWT are shown with a dark mesh in FIG. The other 15 switch transistors SWT that are not meshed are simultaneously controlled by other control lines.

  In this way, some switches and other switches are controlled separately by starting the power supply from the stop state in which the power supply of the circuit block 1 (see FIGS. 1 to 5) to be powered off is cut off. This is to suppress potential fluctuation of the voltage line segment 21 (annular rail line 3) due to abrupt switching when returning to the operating state. Therefore, the potential of the virtual voltage line segment 21V (internal voltage line 11 in the circuit block 1 to be shut off) is reduced to a certain extent with a relatively high on-resistance by turning on a small number, here five switch transistors SWT first. When the value is stabilized after the value is lowered, control is performed to turn on the remaining 15 switch transistors SWT. As a result, the peak value of the potential increase (power supply noise) of the reference voltage VSS transmitted from the annular rail line 3 to the actual VSS wiring 5 is suppressed to the extent that it does not affect other circuits that are always operating.

FIG. 8A to FIG. 9B show actual arrangement examples in the switch block. 3 and FIG. 4, FIG. 8A shows the upper switch block 2U, FIG. 8B shows the lower switch block 2D, FIG. 9A shows the left switch block 2L, and FIG. (B) shows the right switch block 2R.
The four types of switch blocks 2U, 2D, 2R, 2L have the same size. Here, the sides of the block frame (hereinafter referred to as connection sides) to which the reference voltage VSS, the virtual reference voltage VSSV, and the control signal are input / output, that is, the sides LU1 and LU2 in FIG. 8A and the sides in FIG. LD1 and LD2, sides LL1 and LL2 in FIG. 9A, and sides LR1 and LR2 in FIG. 9B are set to the same length. In addition, the end sides of the voltage line segment 21, the virtual voltage line segment 21V, the first switch control line 35_1, and the second switch control line 35_2 at these connection sides are standardized at the same position on any connection side. .

  Here, the first switch control line 35_1 controls several switch transistors SWT previously controlled as in FIG. 7, and the second switch control line 35_2 controls the remaining several switch transistors SWT. It is.

The switch blocks 2U, 2D, 2R, and 2L shown in FIGS. 8 and 9 are different from FIG. 7 in that the voltage line segment 21 and the virtual voltage line segment 21V are arranged in parallel so as to overlap above the switch arrangement region surrounded by a broken line. . This has the advantage that the occupied area of the block can be reduced. However, as shown in FIG. 7, an arrangement in which the voltage line segment 21 and the virtual voltage line segment 21V are not overlapped in the switch arrangement area can be employed.
When the voltage line segment 21 and the virtual voltage line segment 21V are arranged in parallel over the switch arrangement region, the first and second switch control lines 35_1 and 35_2 are arranged in the switch arrangement in a limited number of layers of the multilayer wiring structure. Cannot be placed in the area. Therefore, in this example, the first and second switch control lines 35_1 and 35_2 are arranged outside the switch arrangement region located outside the circuit block 1 to be powered off.

In the left switch block 2L and the right switch block 2R shown in FIG. 9, six switch cells shown in FIG. 7 are provided in the X direction (left and right directions in the figure) and six in the Y direction (up and down directions in the figure). A total of 36 are arranged.
On the other hand, in the upper switch block 2U and the lower switch block 2D shown in FIG. 8, the total number of switch cells is 36, which is the same as in FIG. 9, but the number of arrangement in the X direction is 12, The number of arrangement is three.
The reason is that the switch cell has the same size corresponding to the fact that the size of the switch cell is larger than that of the X direction and the longitudinal direction of the gate electrode needs to be aligned in the Y direction in FIGS. This is because the aspect ratio of the switch arrangement area accommodated in the block is adapted to the vertical and horizontal sizes of the switch blocks interchanged in FIGS.

In the case of FIG. 9, each of the voltage line segment 21 and the virtual voltage line segment 21V intersects all of the branch lines 21B and 21VB. For this reason, the voltage line segment 21 can be connected to all the lower branch lines 21B and 21VB via contacts, and the virtual voltage line segment 21V can contact all the lower branch lines 21B and 21VB. Can be connected through.
On the other hand, in the case of FIG. 8, the voltage line segment 21 and the virtual voltage line segment 21V do not cross all lower layer wirings (branch lines 21B and 21VB) to be contacted. Therefore, as shown in FIG. 8, in the upper switch block 2U and the lower switch block 2D, the access branch line 21Ba orthogonal to the voltage line segment 21 and the branch line 21B is provided in the access path from the voltage line segment 21 to the branch line 21B. It is necessary to provide. The access branch line 21Ba is formed of a wiring layer below the voltage line segment 21 and above the branch line 21B. Therefore, the branch line of the voltage line segment 21 is the access branch line 21Ba, and a two-stage branch structure in which the branch line 21B branches from the access branch line 21Ba is adopted.
Similarly, an access branch line 21VBa that is orthogonal to the virtual voltage line segment 21V branches, and further, a branch line 21VB that is orthogonal to the access branch line 21VBa branches to adopt a two-stage branch structure. Yes.

  The total gate width (total length in the longitudinal direction) of several switch transistors SWT controlled by the first switch control line 35_1 is set to be the same in FIGS. Similarly, the total gate widths of the remaining several switch transistors SWT controlled by the second switch control line 35_2 are set to be the same in FIGS.

Each of the switch blocks 2U, 2D, 2R, 2L includes a buffer circuit BUF1 provided in the middle of the first switch control line 35_1 on the side (outside) opposite to the circuit block 1 in the switch arrangement region, and a second switch And a buffer circuit BUF2 provided in the middle of the control line 35_2.
The buffer circuits BUF1 and BUF2 are connected to a real VDD line and a voltage line segment 21 (not shown), thereby having a function of shaping a control signal attenuated during transmission into a pulse signal having a power supply voltage VDD amplitude. For this reason, the arrangement area of the buffer circuit indicated by the broken line is provided outside the switch arrangement area.

From each output of the buffer circuits BUF1 and BUF2, wiring for switch control extends to the switch arrangement region and is connected to the gate of the corresponding switch transistor group.
In addition, although this wiring and the 1st switch control line 35_1 and the 2nd switch control line 35_2 are shown by the line in FIG.8 and FIG.9, actually, it has the width | variety similar to the voltage line segment 21 grade | etc.,. It is formed of a wiring layer.
The first switch control line 35_1 and the second switch control line 35_2 are provided on the input side of the corresponding buffer circuits BUF1 and BUF2 in the switch block, respectively, and are “first control line segments” to which control signals are input. The “second control line segment” is provided on the output side and outputs a waveform-shaped control signal.

<Wiring structure>
FIG. 10 shows an example of use of wiring layers at each level in a multilayer wiring structure. Here, in the multilayer wiring structure, using the first layer wiring layer (first wiring layer (1M)) to the seventh layer wiring layer (seventh wiring layer (7M)) stacked in order from the lower layer, Each wiring is formed.

  Specifically, the standard cells 15 such as the inverter cells 13 (FIG. 2) in the circuit block 1 to be powered off are formed from the first wiring layer (1M) to the fourth wiring layer (4M). Further, signal lines drawn out from a certain standard cell 15 are also formed by the first wiring layer (1M) to the fourth wiring layer (4M).

The wiring 3C in the column direction of the annular rail line 3 is formed from the fifth wiring layer (5M). The row direction wiring 3R of the annular rail line 3 is formed by a sixth wiring layer (6M) on one layer connected to both ends of the column direction wiring 3C.
Similarly, the wiring 3VC in the column direction of the virtual annular rail line 3V is formed from the fifth wiring layer (5M). The row 3VR in the row direction of the virtual annular rail line 3V is formed by a sixth wiring layer (6M) on one layer connected to both ends of the column-direction wire 3VC.

On the other hand, the wiring 11R in the row direction of the internal voltage line 11 is connected to the wiring 3VC in the column direction of the virtual annular rail line 3V formed by the fifth wiring layer (5M). It is formed of a wiring layer (6M). Furthermore, the wiring 11R in the row direction of the internal voltage line 11 formed by 6M is connected to the wiring 11C in the column direction of the internal voltage line 11 formed by the seventh wiring layer (7M) that is one layer higher than that. Connected at intersections.
The actual VSS wiring 5 is also formed of the seventh wiring layer (7M).

  In this way, the wiring in the column direction is formed from the wiring one layer below in the row direction, and the interwiring connection is successfully achieved while applying the rule.

In the above description, the switch cell pattern is arbitrary and not mentioned. Next, a switch cell having a biaxial symmetry pattern will be described as a desirable specific example.
FIG. 11 shows a schematic layout diagram of one switch cell. In addition, FIG. 11 does not necessarily mean that the dimension of the pattern is the same as the actual one, but merely schematically shows the rough arrangement of the pattern and the connection relationship.

  A switch cell 20N shown in FIG. 11 is obtained by converting one NMOS transistor into a standard cell, and has an axially symmetric arrangement with respect to the X axis and the Y axis passing through the cell center. Hereinafter, this symmetry is referred to as “biaxial symmetry”.

The entire region of the switch cell 20N illustrated in FIG. 11 is a part of the P well.
A gate electrode connecting portion 21C passing through the center of the cell along the X axis is formed. The length of the connecting portion 21C from the cell center is the same (symmetric) with respect to the Y axis. That is, the connecting portion 21C has a biaxially symmetric pattern.
From the connecting portion 21C, four gate electrodes 21A having the same length extend on one side in the width direction, and four gate electrodes 21B having the same length extend on the other side. The four gate electrodes 21A are arranged at equal intervals in the X-axis direction, and the four gate electrodes 21B are similarly arranged at equal intervals in the X-axis direction, and all have the same length and thickness, so that they are Y-axis symmetric. It has become. The gate electrodes 21A and 21B are symmetrical about the X axis because the branching points from the connecting portion 21C are the same. The connecting portion 21C and the gate electrodes 21A and 21B are integrally formed by processing the same conductive material.

Two N-type active regions 22A and 22B of the same size are formed in the P-well at the same distance from the X axis. The N-type active region 22A is formed at a position that intersects the four four gate electrodes 21A, and the N-type active region 22B is formed at a position that intersects the four gate electrodes 21B. N-type active regions 22A and 22B are formed by selectively introducing N-type impurities into a P-well after forming gate electrodes 21A and 21B using these gate electrodes as a mask.
Each of the N-type active regions 22A and 22B is divided into five regions which are divided at the gate electrode portion and function alternately as a source (S) and a drain (D).
Thus, the biaxial symmetry of the first unit transistor (TR1) having the isolation portion of the N-type active region 22A as a channel and the second unit transistor (TR2) having the isolation portion of the N-type active region 22B as a channel can be obtained. A basic structure is formed.

In the arrangement region of the first unit transistor (TR1), the voltage cell line 23A formed from the second wiring layer (2M) is arranged orthogonal to the four gate electrodes 21A. Similarly, in the arrangement region of the second unit transistor (TR2), the voltage cell line 23B formed from the second wiring layer (2M) is arranged orthogonal to the four gate electrodes 21B.
The two voltage cell lines 23A and 23B are electrically connected to the internal voltage line 11 (see FIG. 2) in the circuit block 1 by the upper virtual voltage line segment 21V (see FIG. 7), respectively. Cell internal line. That is, in terms of the correspondence with FIG. 7, the two voltage cell lines 23A and 23B in FIG. 11 correspond to the single branch line 21VB in FIG.

In each of the N-type active regions 22A and 22B, two drain lines 28 connected to each of the two drains (D) via the 1st contact (1C) are provided. A total of four drain lines 28, two each in the N-type active regions 22A and 22B, are formed by the first wiring layer (1M).
The voltage cell line 23A is connected to the two drain lines 28 on the N-type active region 22A through a 2nd contact (2C). Similarly, the voltage cell line 23B is connected to the two drain lines 28 on the N-type active region 22B through a 2nd contact (2C).
The two voltage cell lines 23A and 23B are arranged parallel to each other and equidistant from the X axis.

A power cell line 24A parallel to the voltage cell line 23A is disposed on the tip side of the four gate electrodes 21A. Similarly, a power cell line 24B parallel to the voltage cell line 23B is disposed on the tip side of the four gate electrodes 21B.
The two power cell lines 24A and 24B are cell internal lines that are electrically connected to the upper real VDD line (voltage line segment 21 in FIG. 7). In other words, for this reason, the two power cell lines 24A and 24B are in correspondence with FIG. 7, and the two power cell lines 24A and 24B in FIG. 11 are replaced with one branch line 21B in FIG. Correspond.

The two power cell lines 24A and 24B are respectively a wiring region 24d formed simultaneously with a P-type active region (not shown) and the like, a first backing wiring 24m1 formed from the first wiring layer (1M), A second wiring line 24m2 formed from the second wiring layer (2M) is included.
In each of the two power cell lines 24A and 24B, the wiring region 24d and the first backing wiring 24m1 are short-circuited at equal intervals by the 1st contact (1C), and the first backing wiring 24m1 and the second backing wiring 24m2 are 2nd contacts ( 2C) are short-circuited at equal intervals.
The first backing wiring 24m1 constituting the power cell line 24A is formed integrally with two source lines 24S extending to the two source (S) sides of the N-type active region 22A. Similarly, the first backing wiring 24m1 constituting the power cell line 24B is formed integrally with two source lines 24S extending to the two source (S) sides of the N-type active region 22B.
Each source (S) is connected to the source line 24S via a 1st contact (1C).

Here, the gate electrode connecting portion 21C described first can be omitted, and can be replaced by four contact pad portions.
In any case, as a whole, the four gate electrodes composed of the gate electrodes 21A and 21B parallel to the Y-axis are short-circuited by the upper wiring layer. The cell internal wiring that short-circuits the gate electrode is referred to as a “control cell line”.
The control cell line 25 of this example is formed by overlapping a first control cell line 26 made of the first wiring layer (1M) and a second control cell line 27 made of the second wiring layer (2M). The connecting portion 21C (or four contact pad portions) and the first control cell line 26 are connected by the 1st contact (1C), and the first control cell line 26 and the second control cell line 27 are connected by the 2nd contact (2C). ing.
The control cell line 25 is arranged along the X axis with the center in the width direction and the length direction coincided with the cell center.
Therefore, the control cell line 25 is arranged in parallel to each of the two voltage cell lines 23A and 23B and the two power cell lines 24A and 24B.

FIG. 12 shows a switch cell 20P of a PMOS transistor.
The switch cell 20P illustrated in FIG. 12 is different from the switch cell 20N of FIG. 11 in that the whole is formed in an N well, and the first unit transistor (TR1) and the second unit transistor (TR2) formed in the N well. ) Are P-type N-type active regions 22AP and 22BP. Other configurations are the same as those in FIG.

FIGS. 13A and 13B are configuration diagrams of the upper switch block 2U and the lower switch block 2D that use the switch cell 20N having the NMOS transistor configuration of FIG. FIGS. 14A and 14B are configuration diagrams of the left switch block 2L and the right switch block 2R that similarly use the switch cell 20N.
Comparing FIG. 13 and FIG. 14 with FIG. 8 and FIG. 9, the power cell line 24AB corresponding to the branch line 21B of FIG. 8 and FIG. 9 is formed at twice the density of the branch line 21B. It can be seen that the voltage cell lines 23A and 23B corresponding to the nine branch lines 21B are formed at twice the density of the branch line 21VB. Here, the power cell line 24AB is shared with the power cell line 24A in FIG. 11 and the power cell line 24B of another cell adjacent in the Y direction.
Since other configurations are common, description thereof is omitted here.

  Although not shown in FIGS. 13 and 14, in order to connect the switch cells 20 </ b> N at a predetermined position in a predetermined number to each of the first and second switch control lines 35 </ b> _ <b> 1 and 35 </ b> _ <b> 2, multiple layers are provided. A wiring structure is used. If the wiring layers are multi-layered, the switch control lines can be symmetrically arranged with respect to the block center. However, it is not desirable to increase the manufacturing cost by making the wiring structure complicated only for this purpose. In this example, since it is necessary to arrange the buffer circuits BUF1 and BUF2, the first and second switch control lines 35_1 and 35_2 must be asymmetrically arranged with respect to the center of the switch block.

  Next, advantages of the switch cell wiring symmetrical structure when the switch control lines cannot be symmetrically arranged at the block center will be described.

The first advantage will be described that the design of the switch block is easy.
A preferred switch placement and routing method (switch block design method) in the present embodiment uses the layout symmetry of the switch cell 20N and takes the following procedure.
First step: Two voltage cell lines 23A and 23B, each of which is provided with a transistor and electrically connected to the internal voltage line 11, and a power supply voltage VDD (in the case of the switch cell 20P) or a reference voltage VSS (switch cell) Two power cell lines 24A and 24B (or two shared power cell lines 24AB) that are electrically connected to the second power source line to which the second power source line is applied, and the switch control line Each of the control cell lines 25 electrically connected to 29A to 29C is arranged symmetrically with respect to each of the X axis and Y axis passing through the cell center and connected to the transistor, whereby the switch Cells 20N and / or 20P (or both) are formed.
Second step: The formed switch cells 20N and / or 20P (or both) are arranged in a matrix, and predetermined switch cells 20N and / or 20P (or both) are arranged for each of the plurality of switch control lines 29A to 29C. Connected to form the switch block 20.
Third step: Reversing switch by mirror-inverting the created data of switch block 2 with a line parallel to the X axis or Y axis as an axis, or rotating 180 degrees (inverting 180 degrees) about the cell center Form a block.
Fourth step: A plurality of switch control lines 29A to 29C and a second power supply line are connected between the arranged switch block and inverting switch block, and the voltage cell lines 23A and 23B are connected to the internal voltage line 11 of the circuit block 1. .

More specifically, the control cell line 25, the voltage cell lines 23A and 23B, and the power cell lines 24A and 24B (or two power cell lines 24AB) are respectively connected to the X axis and the Y axis. Is symmetric. Therefore, even if the switch cell 20N is mirror-reversed with the line along the X-axis or Y-axis as the reversal axis, or rotated 180 degrees with the cell center as the axis, the positional relationship of the five cell lines remains unchanged. It remains.
In particular, in the case of FIG. 5 in which two transistors are symmetrically arranged up to the transistor, even if a certain switch block 2 is designed up to the switch control line as shown in FIG. In the switch cell group in the shape, there is no change in the basic pattern of each switch cell 20N shown in FIG. There is a change in the switch control lines 29A to 29C and their connection lines formed by the wiring layers of the third wiring layer (3M) or higher that are not symmetrically arranged in the block.

When the distances from the circuit block 1 to the first and second switch control lines 35_1 and 35_2 are the same, inter-block wiring is easy. In addition, the direction of the gate (longitudinal direction) of the transistor is often restricted to be the same in the integrated circuit in order to make the characteristics uniform. In such a case, the switch blocks arranged on the four sides of the circuit block 1 have different patterns for each side.
However, if the five cell lines, that is, the voltage cell lines 23A and 23B, the power cell lines 24A and 24B, and the control cell line 25 have a biaxial symmetry as shown in FIG. The switch block can be easily designed by the method having the first to fifth steps.

If the relationship between the five cell lines does not change before and after mirror inversion or 180 ° rotation, and the fact that the wiring in the upper layer changes, the circuit block 1 is opposed to each other in the first and second steps. After designing one switch block 2 to be arranged on one side of the two sides, the data of the designed switch block 2 is mirror-inverted with a line parallel to the two sides as an axis, or 180 degrees By rotating, the data of the other switch block 2 to be arranged on the other side can be easily created (third step).
Similarly, on the other two sides, after designing the switch block 2 to be arranged on the one side in the first and second steps, the designed data is mirror-inverted or rotated 180 degrees (first step). 3 steps), data of the switch block 2 to be arranged on the other side can be easily created.
The four types of switch blocks (2U, 2D, 2L, 2R) created in this way have the same distance from the switch control lines 29A to 29C to the circuit block 1 in the four types of switch blocks. Therefore, it is easy to connect the switch control lines between the blocks in the fourth step. This also applies to other wirings to be connected between switch blocks.

Next, as a second advantage, the fact that the switch cell design itself is easy will be described.
In addition to the symmetry of the five cell lines, as shown in FIG. 11 and FIG. 12, if the transistor pattern is biaxially symmetric, the pattern in the first to fourth quadrants divided by the X axis and the Y axis (hereinafter referred to as the pattern) 4 pattern) is designed, and after that, the pattern data after the design is copied and pasted by mirror inversion or by combining mirror inversion and 180 degree rotation. Thus, the design of the switch cell is completed.
Therefore, the design of the switch cell is very easy. In addition, if the high-density design is performed so that the maximum gate width can be ensured at the stage of designing the quadrant pattern first, a switch cell can be designed without waste.

According to this embodiment, the following benefits can be obtained.
A plurality of switch blocks arranged around the circuit block 1 to be turned off includes a voltage line segment and a switch that are part of an annular rail line to which a power supply voltage or a reference voltage is applied. For this reason, the switch segment can be moved freely along the annular line rail and newly inserted just by moving, inserting and deleting the switch block with the positional relationship between the voltage line segment and the switch fixed. Or can be easily deleted.

In particular, as shown in FIG. 15, a wiring for supplying a power supply voltage or a reference voltage to the circuit block 1 viewed from each of the four sides of the circuit block 1 to be shut off (in the description of this embodiment, a specific example Specifically, a plurality of switch blocks are arranged so that the number of switch blocks is increased as the impedance of the wiring of the actual VSS wiring 5 and the annular rail line 3) is smaller.
In FIG. 15, the impedance indicated by the thick arrow is lower than that indicated by the thin arrow. That is, since the input / output cell 40 shown in FIG. 1 is arranged on the side of the thick arrow, the reference voltage from the outside takes a value almost close to 0 [V]. On the other hand, since another circuit block (for example, energization circuit block 32) that always operates is arranged on the side indicated by the thin arrow, the potential of the actual VDD line is higher than 0 [V] when taking a time average. It becomes a state.

  In such a case, if many switch blocks are arranged on the side where the reference voltage is fixed to 0 [V], the discharge of the internal voltage line 11 proceeds more efficiently within the same switch-on time. On the contrary, if a large number of switches are arranged on the side where the reference voltage is higher than 0 [V], the number of switch blocks must be increased to obtain the same discharge effect, which is wasteful.

In the present embodiment, there is an effect that such an effective switch block arrangement can be easily performed.
Specifically, it is possible to cope with the determination of power consumption in the second half of the design, and the number of switch blocks to be used can be reduced as compared with the conventional case. If the number of switch blocks is reduced to reduce the total gate width of the switch transistors, the leakage current is reduced by that amount, and the power is reduced. Further, since no circuit block is operating on the input / output cell 40 side, the influence of power supply noise due to discharge is small, and adverse effects on the operation speed to other circuit blocks can be suppressed.
In addition, since the annular line to which the power supply voltage and the reference voltage are applied can be placed overlapping the switch, the area reduction effect is also great.

  Further, when a switch cell having a biaxial symmetry pattern is used, the above-described first advantage (easy to design the switch block) and second advantage (easy to design the switch cell itself) can be obtained.

  DESCRIPTION OF SYMBOLS 1 ... Circuit block of power-off object, 2 ... Switch block, 2U ... Upper switch block, 2D ... Lower switch block, 2L ... Left switch block, 2R ... Right switch block, 3 ... Ring rail line, 3V ... Virtual ring rail line 5 ... Real VSS wiring, 11 ... Internal voltage line, 21 ... Voltage line segment, 21A, 21B ... Gate electrode, 21C ... Connection part, 21V ... Virtual voltage line segment, 22A, 22B ... N-type active region, 22AP, 22BP ..., P-type active region, 23A, 23B ... Voltage cell line, 24A, 24B ... Power supply cell line, 24S ... Source line, 25 ... Control cell line, 28 ... Drain line, 34 ... Control circuit, 35 ... Control line, 35_1 ... 1st switch control line, 35_2 ... 2nd switch control line, BUF1, BUF2 ... Buffer circuit, SWT ... Switch transistor

Claims (3)

A rectangular circuit block comprising internal power lines having row-direction wiring and column-direction wiring;
A second power supply line having a row-direction wiring and a column-direction wiring, which is disposed outside the circuit block so as to surround the internal block and is electrically connected to the internal power supply line of the circuit block;
A first power supply line having a row-direction wiring and a column-direction wiring, which is arranged so as to surround the internal block further outside the second power supply line surrounding the internal block and to which a power supply voltage or a reference voltage is applied. When,
A switch for controlling electrical connection and disconnection between the second power supply line and the first power supply line,
Have
The internal power supply line in the column direction is formed one layer above the layer in which the internal power supply line in the row direction is formed, and is connected at the intersection of these ends,
Form the column-direction wiring of the second power supply line one layer above the layer in which the row-direction wiring of the second power supply line is formed, and connect at the intersection of these ends,
The first power supply line in the column direction is formed one layer above the layer in which the first power supply line in the row direction is formed, and is connected at the intersection of these ends,
The row of the internal power supply line in the row direction is formed one layer above the layer in which the column direction wiring of the second power supply line is formed,
The wiring in the column direction of the first power supply line is formed in the same layer as the layer in which the wiring in the column direction of the second power supply line is formed,
The switch is arranged in a lower layer of the first power supply line and the second power supply line every four sides of the internal block so as to surround the internal block .
Semiconductor integrated circuit. A plurality of the switches are disposed below the first power supply line and the second power supply line;
The semiconductor integrated circuit according to claim 1. Each of the plurality of switches is connected to any of a plurality of control lines capable of switch control independently of each other.
The semiconductor integrated circuit according to claim 2.

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