JP2004172627A - Semiconductor integrated circuit device, memory medium memorizing cell library, and design method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device where an increase of a power consumption caused from a leak current of MOSFETs and an operation speed are harmonized suitably in the semiconductor integrated circuit device composed of MOSFETs. <P>SOLUTION: For a plurality of signal routes of the semiconductor integrated circuit device, a delay when signals are transmitted along the signal routes is considered. A route having room for delay consists of MOSFETs of a high threshold voltage, contrarily, a route having no room for delay consists of MOSFETs of a low threshold voltage whose leak current is large, however, its operation speed is quick. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device suitable for high-speed and low-voltage operation and a storage medium storing a cell library.

  In semiconductor integrated circuit devices currently manufactured, MOSFETs having characteristics of high integration and low power consumption are widely used. A MOSFET has a threshold voltage, which determines the on-off characteristics of the FET. To increase the drive capability and the operation speed of the circuit, the threshold voltage must be set low.

  However, 1993 Symposium on VLSI Circuits Digest of Technical Papers (May 1993), pp. 45-46 (May 1993), pp. 45-46. As described in, if the threshold voltage is set too low, the FET cannot be completely turned off due to the MOSFET sub-threshold characteristic (tailing characteristic), and the sub-threshold leakage current (hereinafter referred to as leakage current) And the power consumption of the semiconductor integrated circuit becomes very large.

  Generally, in order to increase the threshold voltage of a MOSFET, a method of increasing the thickness of a gate oxide film or increasing the impurity concentration under the gate oxide film has been adopted. That is, when designing a semiconductor integrated circuit device composed of MOSFETs, the threshold voltage of the MOSFET is determined in consideration of a desired operating frequency and power consumption, and semiconductor manufacturing process conditions are determined.

  It is common practice to set the threshold voltage of the MOSFET in a semiconductor integrated circuit device to a uniform and constant value. According to recent inventions, however, it has also been reported that 1996 IEE International Solid State Circuit Conference Digest of Technical Papers (1996), pages 166 to 167 (IEEE International Solid State Circuits Conference Digest of Technical Papers, pp.166-167, 1996) There has been proposed a semiconductor integrated circuit capable of controlling a threshold voltage of a MOSFET by changing a substrate bias voltage value according to an operation state.

  In Japanese Patent Application Laid-Open No. 8-274620, when a semiconductor integrated circuit is composed of a plurality of functional blocks, a block in which the substrate bias voltage value is independently changed for each functional block and high-speed performance is important is a low threshold voltage MOSFET. It has also been proposed to operate the other blocks as high threshold voltage MOSFETs.

  According to IEE Journal of Solid State Circuit, VOL30, NO8 (August 1995), pages 847 to 854 (IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL30, NO8, AUGUST 1995). A power supply line and a pseudo power supply line are provided, and a switching MOSFET is arranged between them.The main circuit has a configuration in which power is supplied from the pseudo power supply line. Proposals have been made to reduce power consumption by not supplying power to the main circuit. Here, it has been proposed that the switching MOSFET has a higher threshold voltage than the MOSFET constituting the main circuit in order to maintain the ON state without performing a switching operation during operation.

1993 Symposium on VSI Circuit Digest of Technical Papers (May 1993) pp. 45-46

1996 IEE International Solid State Circuit Conference Digest of Technical Papers (1996) 166-167 IEE Journal of Solid State Circuit, VOL30, NO8 (August 1995) pp. 847-854 JP-A-8-274620

  As described above, in the above-described conventional technology, the threshold voltage of the MOSFET is controlled by changing the substrate bias voltage value in accordance with the operation state such as a standby state or an active operation, or the substrate is independently controlled for each functional block. It has been proposed that a block in which high-speed performance is emphasized by changing a bias voltage value is operated as a low threshold voltage MOSFET, and a block which is not so operated as a high threshold voltage MOSFET. Further, it has been proposed to increase the threshold voltage of a special MOSFET which does not require a switching speed during operation. However, in a method of uniformly increasing the threshold voltage during standby and uniformly decreasing the threshold voltage during active operation, an increase in power consumption due to leakage current cannot be avoided in order to operate at high speed during active operation. . In addition, the present inventors have found that, even in the same functional block, the required operation speed may be different depending on the individual logic gates constituting the functional block.

  FIG. 11 shows a frequency distribution of delay values of a path between flip-flops in a semiconductor integrated circuit operating at 100 MHz. The horizontal axis indicates the delay value of the path, and the vertical axis indicates the frequency of the path having the delay value. In order to operate at 100 MHz, it is necessary that all the paths are distributed to a value smaller than the delay value of 10 nsec as in the distribution (1) in the figure. If the operating speed of this semiconductor integrated circuit is to be 125 MHz, it is necessary that all the paths are distributed to a value smaller than the delay value of 8 nsec. Therefore, according to the prior art, the threshold voltage of the MOSFET constituting the circuit is reduced uniformly by changing the process conditions or the substrate bias power supply.

  As a result, for example, the distribution changes as shown in (2) in FIG. However, at this time, the power consumption due to the leak current increases, and the required power consumption condition may not be satisfied. Conversely, if it is desired to lower the power consumption, according to the prior art, the threshold voltage of the MOSFETs constituting the circuit is uniformly increased by changing the process conditions or the substrate bias power supply. Was. As a result, for example, the distribution changes as indicated by (3) in the figure. That is, the operation speed of the circuit is reduced, and 100 MHz cannot be realized.

  Therefore, it is necessary to decide whether to emphasize the operation speed or the power consumption, and to compromise between the two.

  An object of the present invention is to solve the above-described problems of the related art. In other words, in a semiconductor integrated circuit device composed of MOSFETs, the increase in power consumption due to leakage current and the operation speed can be appropriately coordinated, and the increase in power consumption due to MOSFET leakage current during active operation can be suppressed and high-speed operation is possible. It is to provide a simple semiconductor integrated circuit device.

It is still another object of the present invention to provide a storage medium storing a cell library necessary for appropriately designing an increase in power consumption due to a leak current and a harmony of an operation speed.
It is still another object of the present invention to provide a method of designing a semiconductor integrated circuit for suitably designing an increase in power consumption due to a leak current and a harmony of an operation speed.

  The gist of the present invention for solving the above-mentioned problem is that, in a certain operating state, for example, in an active operating state where high-speed operation is required, even in the same functional block, a semiconductor using MOSFETs having different threshold voltages is used. This is to constitute an integrated circuit device.

  More specifically, a first characteristic of the semiconductor integrated circuit device of the present invention is that, for a plurality of signal paths in the semiconductor integrated circuit device, an operation required in consideration of a time, that is, a delay in which a signal is transmitted along each signal path, that is, a required operation. In order to satisfy the frequency, a path with a delay allowance is constituted by a MOSFET with a high threshold voltage such that the operation speed is slow but a leakage current is small, and conversely, in a path with a delay allowance, It is to be configured by a MOSFET having a low threshold voltage which has a large leakage current but a high operation speed.

A second feature of the semiconductor device of the present invention is that, when a certain signal path in a semiconductor integrated circuit device is composed of only MOSFETs with a high threshold voltage, the delay of the path becomes large and the required operating frequency is satisfied. However, if only low-threshold MOSFETs are used, there is a margin for delay, and when power consumption due to leakage current is increased unnecessarily, low-threshold MOSFETs are placed along the signal path. And a MOSFET having a high threshold voltage, as appropriate, to minimize the leakage current while securing a delay that satisfies the required operating frequency.
Further, a third feature of the semiconductor device of the present invention is that, as described above, a signal path from one start node in a semiconductor integrated circuit device is branched at a certain node and reaches a plurality of nodes. When appropriately mixing low-threshold and high-threshold-voltage MOSFETs, use a low-threshold MOSFET in the path from the start node to the branch node to minimize the use of the low-threshold MOSFET. The use of many MOSFETs. In addition, as described above, a low-threshold MOSFET and a high-threshold voltage MOSFET are appropriately connected to a signal path from a plurality of start nodes at a certain node to a single end node. When mixed, the use of many low-threshold MOSFETs in the path from the junction node to the end node is to minimize the use of low-threshold MOSFETs.

  Further, in the present invention, a first means for forming a semiconductor integrated circuit by MOSFETs having different threshold voltages is to change an impurity concentration of a semiconductor substrate under a gate oxide film of the MOSFET, and The third means is to change the gate oxide film thickness of the MOSFET, and the fourth means is to change the gate length of the MOSFET. is there.

  Further, the invention is characterized in that MOSFETs having different threshold voltages are formed by combining the above four means.

  Further, in the above-mentioned second means for forming MOSFETs having different threshold voltages, a plurality of island-shaped well regions insulated from each other are formed in order to change a bias voltage value supplied to the substrate. MOSFETs having different threshold voltages are arranged on different well regions.

  Further, as described above, in order to configure MOSFETs having different threshold voltages on different well regions, logic gates are arranged in a one-dimensional column, and a plurality of columns are arranged in a direction orthogonal to the columns. Logic gates are two-dimensionally arranged, and logic gates composed of MOSFETs with the same threshold voltage are arranged on the same column, and the same threshold voltage is placed on the same well region along the column. A feature is that a MOSFET is configured and a bias power is supplied by wiring in the same direction as a column.

  Furthermore, as described above, when logic gates constituted by MOSFETs having the same threshold voltage are arranged on the same column, and are arranged on the same well region along the column, a plurality of adjacent logic gates are arranged. In the case where the logic gates of a column are formed by MOSFETs having the same threshold voltage, a well region is shared over the plurality of columns.

  Further, the storage medium storing the cell library used for designing the semiconductor integrated circuit device as described above has the same function and the same outer shape, and is constituted by MOSFETs having different threshold voltages. At least two or more types of cells having different delays and different power consumptions are registered.

  Further, a design method for designing a semiconductor integrated circuit device as described above includes a step of calculating a delay of a signal path using a storage medium storing the above-described cell library, and a step of calculating a delay of the signal path. Using the calculation result by, selecting one cell from at least two or more types of cells having the same function and the same shape and configured by switching elements having different threshold voltages, and assigning the selected cell to a logic circuit. It is characterized by including.

  Further, another design method for designing a semiconductor integrated circuit device as described above uses a storage medium storing the above-described cell library, and uses only a cell constituted by a high-threshold switching element. A circuit designing step, a signal path delay calculating step, and a part of the cells of the logic circuit designed using only the cells constituted by the high threshold switching elements, having the same function. The method is characterized in that the method includes a step of replacing the cell with a switching element having a low threshold voltage having a shape.

  According to another aspect of the present invention, a signal path includes a plurality of circuits for holding a state of a signal such as a latch circuit, a flip-flop circuit, a signal output terminal, or a signal input terminal, and a signal path between these circuits is provided. Some of the transistors have different threshold values. Alternatively, a plurality of first circuits controlled by a clock signal are provided in a signal path, and a second circuit including a plurality of transistors having different thresholds is provided in a signal path between the first circuits.

  As a design concept, a semiconductor having a plurality of first circuits controlled by a clock signal in a signal path and a second circuit including a plurality of transistors having different thresholds in a signal path between the first circuits is provided. A method of designing an integrated circuit device, wherein a threshold value of a transistor forming a second circuit is set such that a signal delay time between first circuits forming a circuit does not exceed a predetermined target value.

  That is, assuming that transistors having the same threshold value are used, it is inevitable that a path having a large delay time, which determines the operation speed of the entire circuit, among paths among a plurality of first circuits. However, by appropriately using a high-speed transistor having a small threshold value in such a path having a large delay time, the delay time of the path can be reduced, and the operating frequency of the entire circuit can be improved.

  As described above, according to the present invention, even in the same functional block in a certain operating state, the MOSFETs having different threshold voltages are appropriately selected and the semiconductor integrated circuit device is configured to be active. A semiconductor integrated circuit device capable of operating at high speed while suppressing an increase in power consumption due to leakage current of the MOSFET during operation can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a typical embodiment of the present invention. The circuit of FIG. 1 includes flip-flops f11 to f14 and NAND elements g11 to g19. In the figure, for the sake of simplicity, all the logic gates g11 to g19 are shown as NAND, but the semiconductor integrated circuit device of the present invention is not limited to being constituted only by NAND elements. In the drawing, signals not related to the description are omitted. The circuit in the example of FIG. 1 is operated at 200 MHz. To this end, a delay in the path from the input of the clock signal CK to the flip-flop f11 to the input of the signal to the flip-flop f12, and the input of the clock signal CK to the flip-flop f13, It is required that the delay of the path until input to f14 is within 5 nsec. Here, it is assumed that the delay when the NAND element and the flip-flop are constituted by the high threshold voltage MOSFET is 1 nsec, and the delay when the NAND element and the flip-flop are constituted by the low threshold voltage MOSFET is 0.8 nsec.

  In FIG. 1, the shaded logic gates, i.e., f13 and g15 to g19, are constituted by low threshold voltage MOSFETs, and the elements outlined are constituted by high threshold voltage MOSFETs. I have. Thus, the delay of the path from f11 and g11 to f12 via g14 is 5 nsec, the delay of the path from f13 and g15 to f14 via g19 is 4.8 nsec, and both paths are within 5 nsec and the target It can operate at 200MHz.

  Here, if all the logic gates are composed of high-threshold MOSFETs as in the prior art, the delay of the path from f13 and g15 to f14 via g19 is 6 nsec, and this circuit can be operated only at 167 MHz. Can not.

  Next, attention is paid to the leak current. Here, it is assumed that the leakage current of one logic gate in the case of a MOSFET with a high threshold voltage is 1 pA, and the leakage current of one logic gate in the case of a MOSFET with a low threshold voltage is 5 pA. At this time, when the threshold voltage of the MOSFET constituting the logic gate is changed for each signal path as shown in FIG. 1, the total leakage current is 37 pA. As in the prior art, the total leakage current is 13 pA when all the logic gates are configured with a uniformly high threshold voltage MOSFET, and the total leakage current is 65 pA when configured with a uniformly low threshold voltage MOSFET. Become.

  That is, in the example of FIG. 1, only the operating frequency of 167 MHz with the leak current of 13 pA or the operating frequency of 200 MHz with the leak current of 65 pA could be selected. Can be realized. In other words, the essence of the embodiment shown in FIG. 1 is that the low threshold voltage MOSFET and the high threshold voltage are realized by the delay of the signal path constituting the semiconductor integrated circuit in order to suppress the leakage current while achieving the target operating frequency. The purpose is to use MOSFETs with different voltage values.

Another embodiment of the present invention will be described with reference to FIG. The circuit of FIG. 2 is exactly the same as that of FIG. 1, but the only difference is that in FIG. 2, the logic gate g17 is constituted by a MOSFET having a high threshold voltage. In FIG. 1, all the logic gates on the path from f13 and g15 to f14 via g19 are formed of low threshold voltage MOSFETs, and the delay is 4.8 nsec. That is, in order for the operating frequency to be 200 MHz, there is a margin of 0.2 nsec. In the case of Fig. 2, a delay of 5nsec is achieved by mixing one element composed of a MOSFET with a high threshold voltage on the path from f13 and g15 to f14 via g19, further reducing leakage current. And the total leakage current is 33 pA. In other words, the gist of the embodiment shown in FIG. 2 is to appropriately mix MOSFETs having different threshold voltages even in one signal path in order to minimize the leakage current while achieving the target operating frequency. is there.

  Another embodiment of the present invention will be described with reference to FIG. In FIG. 3, the circuit includes flip-flops f31, f32, and f33 and logic gates g301 to g317. The target delay of the path from f31 to f32 and the path from f31 to f33 is 10 nsec. The values of the delay and the leak current of each element are the same as those in FIGS. Both the path from f31 to f32 and the path from f31 to f33 are composed of 11 logic gates, and in order to realize a delay of 10 nsec, at least 5 elements are reduced in 11 logic gates. It must be composed of a MOSFET with a threshold voltage.

  At this time, as shown in FIG. 3, by configuring g301 to g305, which is a common part of both paths, with low threshold voltage MOSFETs, the number of logic gates composed of low threshold voltage MOSFETs as a whole is reduced. Can be minimized. In this case, the total leakage current is 37 pA, and if logic gates other than the common part of both paths, such as g307 to g311 and g313 to g317, are formed by low threshold voltage MOSFETs, the total leakage current is 57 pA, which is the same as in the prior art. In the case where all the logic gates are composed of low threshold voltage MOSFETs, it becomes 85 pA. In other words, the gist of the embodiment shown in FIG. 3 is that the signal path from one start node is divided into a signal path from a certain node to a plurality of nodes. In order to minimize the use of low-threshold MOSFETs, low-threshold MOSFETs are often used in the path from the starting node to the branch node.

  Another embodiment of the present invention will be described with reference to FIG. FIG. 4 includes flip-flops f41, f42, and f43 and logic gates g401 to g417. The target delay of the path from f41 to f43 and the path from f42 to f43 is 10 nsec as in FIG. The values of the delay and the leak current of each element are the same as in FIGS. Both the path from f41 to f43 and the path from f42 to f43 are composed of 11 logic gates, and in order to realize a delay of 10 nsec, at least 5 elements are reduced in 11 logic gates. It must be composed of a MOSFET with a threshold voltage.

At this time, as shown in FIG. 4, by configuring g407 to g411, which are common parts of both paths, with low threshold voltage MOSFETs, the number of logic gates composed of low threshold voltage MOSFETs as a whole is reduced. Can be minimized. In this case, the total leakage current is 37 pA, and when logic gates other than the common part of both paths, such as g401 to g405 and g412 to g416, are configured by low threshold voltage MOSFETs, the total leakage current is 57 pA, which is the same as in the prior art. In the case where all the logic gates are composed of low threshold voltage MOSFETs, it becomes 85 pA. In other words, the gist of the embodiment shown in FIG. 4 is that the signal paths from a plurality of start-point nodes are merged at a certain node and reach a single node. In order to minimize the use of the low-threshold MOSFETs, the use of many low-threshold MOSFETs in the path from the junction node to the end point node.

  Another embodiment of the present invention will be described with reference to FIG. FIG. 19 shows a first signal path from a flip-flop f191 to a flip-flop f192 through a circuit c191 including one or more logic gates, a logic gate g191, a logic gate g192, a logic gate group gg191, and a flip-flop. This is an example in which there is a second signal path from the flip-flop f191 to the flip-flop f193 through the circuit c191 including one or more logic gates, the logic gate g191, the logic gate g193, and the logic gate group gg192. It is assumed that if only MOSFETs having a uniform high threshold voltage are used, both paths exceed the target delay.

  In this case, as described above, the MOSFET of g191, which is a shared logic gate of both paths, is configured by a low threshold voltage MOSFET. Further focusing on the logic gate groups gg191 and gg192, gg192 is composed of N stages of logic gates, and gg191 is composed of N + M stages, which are M stages more than gg192. At this time, the first signal path including gg191 has a larger delay than the second signal path including gg192. In such a case, the logic gate g192 of the first path fanned out by the g191 formed of a low threshold voltage MOSFET is formed of a low threshold voltage MOSFET. Although not shown, some of the logic gates of gg191 are formed of low threshold voltage MOSFETs as necessary.

  Another embodiment of the present invention will be described with reference to FIG. FIG. 20 shows a first signal path from a flip-flop f201 to a flip-flop f203 through a logic gate group gg201, a logic gate g201, a logic gate g202, a circuit c201 including one or more logic gates, and a flip-flop. In this example, there is a second signal path from the flip-flop f202 to the flip-flop f203 through the logic gate group gg202, the logic gate g203, the logic gate g202, and the circuit c201 including one or more logic gates. It is assumed that if only MOSFETs having a uniform high threshold voltage are used, both paths exceed the target delay.

  In this case, as described above, the MOSFET of g202, which is a shared logic gate of both paths, is configured by a low threshold voltage MOSFET. Furthermore, focusing on the logic gate groups gg201 and gg202, gg202 is configured by K stages of logic gates, and gg201 is configured by K + L stages L stages more than gg202. At this time, the first signal path including gg201 has a larger delay than the second signal path including gg202. In such a case, the logic gate g201 in the first path is configured by a low threshold voltage MOSFET. Although not shown in the figure, some of the logic gates of gg201 are formed of low threshold voltage MOSFETs as necessary.

  An embodiment of the present invention using a complementary MOSFET constituted by a p-channel MOSFET and an n-channel MOSFET will be described with reference to FIG. The output pin of the flip-flop f121 is connected to the gate of the first p-channel MOSFET pm1 and the gate electrode of the first n-channel MOSFET nm1 through one or more MOSFETs. The p-channel MOSFET pm1 is connected to have a source / drain path between the first operating potential supply line Vdd121 and the first node nd1, and the n-channel MOSFET nm1 is connected to the first node nd1 and the second operating potential supply It is connected so as to have a source / drain path between it and the line Vss121.

  Further, the first node nd1 is connected to the gate of the second p-channel MOSFET pm2 and the gate electrode of the second n-channel MOSFET nm2. The p-channel MOSFET pm2 is connected to have a source / drain path between the first operating potential supply line Vdd121 and the second node nd2, and the n-channel MOSFET nm2 is connected to the second node nd2 and the second operating potential supply It is connected so as to have a source / drain path between it and the line Vss121. Further, the second node nd2 is connected to the input pin of the second flip-flop f122 through one or more MOSFETs.

  In the figure, the insides of the flip-flops f121 and f122 indicate inverters, tri-state gates, transfer gates, and the like with logic gate symbols. The clock signal CK is input to the flip-flops f121 and f122. In the figure, the high threshold voltage MOSFETs are shown by thin solid lines, and the low threshold voltage MOSFETs are shown by thick solid lines. Hereinafter, this notation is used.

  In FIG. 12, the p-channel MOSFET pm2 and the n-channel MOSFET nm2 are low threshold voltage MOSFETs, and the p-channel MOSFET pm1 and the n-channel MOSFET nm1 are high threshold voltage MOSFETs. As indicated by the frame, the inverter logic gate inv1 is formed by the p-channel MOSFET pm1 and the n-channel MOSFET nm1, and the inverter logic gate inv2 is formed by the p-channel MOSFET pm2 and the n-channel MOSFET nm2. In this circuit, the time from when the clock signal CK is input to the flip-flop f121 to when the signal is output from the output pin of the flip-flop f121 and passes through the inverters inv1 and inv2 and reaches the input of the flip-flop f122 That is, the delay of this path needs to be within the cycle of the clock signal CK.

  Actually, it is necessary to consider the time required for the setup of the flip-flop, the time lag of the clock signal reaching the flip-flop, and the like, but they are ignored here because they are irrelevant to the description. That is, the delay of this path is the sum of the delay for the flip-flop f121 to output a signal after the clock signal is input to the flip-flop f121, the delay of the inverter inv1, and the delay of the inverter inv2. Here, when the p-channel MOSFET pm1 and the n-channel MOSFET nm1 and the p-channel MOSFET pm2 and the n-channel MOSFET nm2 are all composed of high threshold voltage MOSFETs, the delay of this path becomes longer than the clock cycle, and It is assumed that a delay occurs when a MOSFET is used (that is, power is wasted).

  As described above, in the conventional technology, the delay and the power consumption cannot be optimized to the utmost, but as in the present embodiment, only the p-channel MOSFET pm2 and the n-channel MOSFET nm2 are set to the low threshold voltage. Thus, the power consumption can be suppressed after the delay is set in time.

  Another embodiment of the present invention using a complementary MOSFET composed of a p-channel MOSFET and an n-channel MOSFET will be described with reference to FIG. The output pin of the flip-flop f131 is connected to the gate of the first p-channel MOSFET pm131 and the gate electrode of the first n-channel MOSFET nm131.

  The p-channel MOSFET pm131 is connected so as to have a source / drain path between the first operating potential supply line Vdd131 and the first node nd131, and the n-channel MOSFET nm131 is connected to the first operating potential supply line Vdd131 and the second operating potential supply line. It is connected to the line Vss131 so as to have a source / drain path. Further, the first node nd131 is connected to the gate of the second p-channel MOSFET pm132, the gates of the second n-channel MOSFET nm132 and the third p-channel MOSFET pm134, and the gate of the third n-channel MOSFET nm134.

  The p-channel MOSFET pm132 is connected so as to have a source-drain path between the first operating potential supply line Vdd131 and the second node nd132, and the fourth p-channel MOSFET pm133 is similarly connected to the first operating potential supply line. The source and drain paths are connected between the line Vdd131 and the second node nd132. The n-channel MOSFET nm132 and the fourth n-channel MOSFET nm133 are connected in series so as to have a source / drain path between the second node nd132 and the second operating potential supply line Vss131.

   The p-channel MOSFET pm134 and the fifth p-channel MOSFET pm135 are connected in series with a source-drain path between the first operating potential supply line Vdd131 and the third node nd133, and the n-channel MOSFET nm132 is connected to the third The source and drain paths are connected between the node nd133 and the second operating potential supply line Vss131. Similarly, the fifth n-channel MOSFET nm135 is also connected so as to have a source / drain path between the third node nd133 and the second operating potential supply line Vss131.

  Further, the second node nd132 is connected to an input pin of a second flip-flop f132 via a circuit c131 (shown as an abbreviation in this drawing) composed of one or more logic gates. I have. Further, the third node nd133 is connected to an input pin of the third flip-flop f133 via a circuit c132 (shown by an ellipse like c131) composed of one or a plurality of logic gates.

  In this figure, the internal gate of the flip-flop is omitted. The clock signal CK is input to the flip-flop. Also, as indicated by the frame, an inverter logic gate inv131 is constituted by the p-channel MOSFET pm131 and the n-channel MOSFET nm131, and a NAND logic gate NAND131 is constituted by the p-channel MOSFETs pm132 and pm133 and the n-channel MOSFETs nm132 and nm133. MOSFETs pm134 and pm135 and n-channel MOSFETs nm134 and nm135 form a NOR logic gate NOR131. Note that the NAND 131 receives an in2 signal in addition to the output of the inv 131, and the NOR 131 receives an in3 signal in addition to the output of the omv 131.

  In this circuit, after the clock signal CK is input to the flip-flop f131, a signal is output from the output pin of the flip-flop f131, passes through the inverter inv131 and the NAND131, passes through c131, and reaches the input of the flip-flop f132. Until the signal is output from the output pin of the flip-flop f131, passes through the inverter inv131 and the NOR131, passes through c132, and reaches the input of the flip-flop f133 within the cycle of the clock signal CK. There is a need. Also in this embodiment, when all the MOSFETs constituting the NAND 131, NOR 131 and inv 131 are configured with the high threshold voltage, the delay of the above two paths becomes longer than the clock cycle, and all are configured with the low threshold MOSFET. In this case, it is assumed that a margin occurs in the delay between the two paths (that is, power is wasted unnecessarily).

  In the embodiment of FIG. 12, there is no difference in power consumption regardless of which of inv1 and inv2 is configured with the low threshold voltage, but as in this embodiment, when the path is branched at nd131. Makes the MOSFETs pm131 and nm131 of the logic gates upstream of the branch node nd131, that is, the logic gates shared by both paths, have a low threshold voltage. As a result, the number of low threshold voltage MOSFETs required to keep the delay within the target time can be minimized, and the power consumption can be further reduced. In the present embodiment, an example of branching into two routes has been described. However, the same applies to a case of three branches, that is, a fan-out of 3 or more, which is included in the present invention.

  Another embodiment of the present invention using a complementary MOSFET constituted by a p-channel MOSFET and an n-channel MOSFET will be described with reference to FIG. The output pin of the flip-flop f141 is connected to the gate electrodes of the first p-channel MOSFET pm141 and the first n-channel MOSFET nm141 via the logic gate circuit c141. The p-channel MOSFET pm141 is connected to have a source / drain path between the first operating potential supply line Vdd141 and the first node nd141. Similarly, the second p-channel MOSFET pm142 is connected to have a source / drain path between the first operating potential supply line Vdd141 and the first node nd141. The n-channel MOSFET nm141 and the second n-channel MOSFET nm142 are connected in series so as to have a source / drain path between the first node nd141 and the second operating potential supply line Vss141.

  The output pin of the flip-flop f142 is connected to the gate electrodes of the third p-channel MOSFET pm143 and the third n-channel MOSFET nm143 via the logic gate circuit c142. The p-channel MOSFET pm143 is connected so as to have a source / drain path between the first operating potential supply line Vdd141 and the second node nd142. Similarly, the fourth p-channel MOSFET pm144 is connected to have a source / drain path between the first operating potential supply line Vdd141 and the second node nd142. The n-channel MOSFET nm143 and the fourth n-channel MOSFET nm144 are connected in series so as to have a source / drain path between the second node nd142 and the second operating potential supply line Vss141.

  Further, the first node nd141 is connected to the gate electrodes of the fifth p-channel MOSFET pm145 and the fifth n-channel MOSFET nm145. Further, the second node nd142 is connected to the gate electrodes of the sixth p-channel MOSFET pm146 and the sixth n-channel MOSFET nm146. The p-channel MOSFETs pm145 and pm146 are connected so as to have a source / drain path between the first operating potential supply line Vdd141 and the third node nd143, and the n-channel MOSFET nm145 and the n-channel MOSFET nm146 are connected to the third node nd143. The source and drain paths are connected in series with the second operating potential supply line Vss141. Further, the third node nd143 is connected to the input pin of the third flip-flop f143. Note that the internal gate of the flip-flop is also omitted in this drawing. The clock signal CK is input to the flip-flop. Also, as indicated by the frame, the p-channel MOSFETs pm141 and pm142 and the n-channel MOSFETs nm141 and pm142 form a NAND logic gate NAND141. The p-channel MOSFETs pm145 and pm146 and the n-channel MOSFETs nm145 and nm146 form a NAND logic gate NAND143.

  In this circuit, after the clock signal CK is input to the flip-flop f141, a signal is output from the output pin of the flip-flop f141, passes through c141, passes through NAND141 and NAND143, and reaches the input of the flip-flop f143. And a signal is output from the output pin of the flip-flop f142, and after the clock signal CK is input to the flip-flop f142, a signal is output from the output pin of the flip-flop f142 and passes through c142. And the time required for the signal to pass through the NAND 143 and reach the input of the flip-flop f143 must be within the cycle of the clock signal CK.

  Also in this embodiment, when all the MOSFETs constituting the NAND 141, NAND 142, and NAND 143 are configured with the high threshold voltage, the delay of the above two paths becomes longer than the clock cycle, and all of the MOSFETs are configured with the low threshold MOSFET. In this case, it is assumed that a margin occurs in the delay between the two paths (that is, power is wasted unnecessarily). In the embodiment of FIG. 12, there is no difference in power consumption regardless of which of inv1 and inv2 is configured with the low threshold voltage. However, as in the present embodiment, the paths from the two inputs merge. In such a case, the logic gate MOSFET shared by both paths is preferentially set to a low threshold voltage, as described with reference to FIG. That is, in this drawing, pm145, pm146 and nm145, nm146 are MOSFETs with a low threshold voltage. For this reason, it is possible to minimize the number of low threshold voltage MOSFETs required to keep the delay within the target time and to suppress power consumption. In the present embodiment, an example in which two routes merge is described. However, the case where three or more routes merge is the same and is included in the present invention.

  An embodiment of the present invention using a complementary MOSFET constituted by a p-channel MOSFET and an n-channel MOSFET and a pass transistor gate constituted by an n-channel MOSFET will be described with reference to FIG.

  The input signal in211 enters the drain electrode of the first n-channel MOSFET nm212, the input signal in212 enters the drain electrode of the second n-channel MOSFET nm213, and the input signal in213 enters the gate electrode of the second n-channel MOSFET nm213, The negation of the input signal in213 is input to the gate electrode of the first n-channel MOSFET nm212, and the source electrodes of the first n-channel MOSFET nm212 and the second n-channel MOSFET nm213 are connected to the first node nd211. The n-channel MOSFET nm212 and the second n-channel MOSFET nm213 configure a 2-input / 1-output selector logic gate sel211 by a pass transistor.

  Further, the first node nd211 is connected to the gate electrodes of the first p-channel MOSFET pm211 and the third n-channel MOSFET nm211. The first p-channel MOSFET pm211 is connected to have a source-drain path between the first operating potential supply line Vdd211 and the second node nd212, and the third n-channel MOSFET nm211 is connected to the second operating potential The source and drain paths are connected between the supply line Vss211 and the second node nd212. As a result, the first p-channel MOSFET pm211 and the third n-channel MOSFET nm211 form an inverter logic gate inv211. The circuit shown in FIG. 21 is a circuit in which pass transistor logic gates and complementary MOSFET logic gates coexist.

  At this time, the first and second n-channel MOSFETs nm212 and nm213, which are pass transistors, are set to a low threshold voltage. In recent years, logic gates using pass transistors have attracted attention due to the advantage of being able to construct logic gates in a compact manner.However, there is a problem that the switching speed at the time of low-voltage operation is significantly reduced in pass transistors compared to complementary MOSFETs. The inventors have found. Therefore, in a semiconductor integrated circuit in which a complementary MOSFET and a pass transistor are used together as in this embodiment, the above problem can be solved by configuring the pass transistor with a low threshold voltage. In a semiconductor device in which pass transistors are mixed, low-voltage and high-speed operations can be performed without lowering the operation speed of the pass transistors.

  Next, an embodiment of means for realizing MOSFETs having different threshold voltages in the present invention will be described. A first means of forming a semiconductor integrated circuit with MOSFETs having different threshold voltages is to change an impurity concentration of a semiconductor substrate under a gate oxide film of the MOSFET.

  FIG. 15 shows an embodiment in which the circuit of FIG. 12 is laid out using the above method. In FIG. 15, the flip-flops f121 and f122 are omitted. The output pin of the flip-flop f121 is connected to term121. term121 is connected to the first gate electrode gate121. The gate electrode gate121 forms a first p-channel MOSFET pm1 by passing over the p + source / drain region darea121, and forms a first n-channel MOSFET nm1 by passing over the n + source / drain region darea122. The p + source / drain region darea121 is formed on the n-well region nw121, and the n + source / drain region darea122 is formed on the p-well region pw121.

  The source of the p-channel MOSFET pm1 is connected to the first operating potential supply line Vdd121, and the drain is connected to the drain of the n-channel MOSFET nm1 and the terminal term122. The source of the n-channel MOSFET nm1 is connected to the second operating potential supply line Vss121. In the figure, black squares indicate through holes for connection to different metal wiring layers and semiconductor substrates. Power is supplied to the n-well region nw121 from Vdd121 through the through-hole TH121, and power is supplied to the p-well region pw121 from Vss121 through the through-hole TH122.

  Thereby, the inverter logic gate inv1 of FIG. 2 is configured. The first p-channel MOSFET pm1 and the first n-channel MOSFET nm1 form a first inverter logic gate inv1. Similarly, the second gate electrode gate122 and the p + source / drain region darea123 and the n + source / drain region darea124 form a second p-channel MOSFET pm2 and a second n-channel MOSFET nm2, which form the second inverter logic gate. inv2 is configured. A term122 which is an output terminal of inv1 and a term123 which is an input terminal of inv2 are connected to form a two-stage inverter circuit shown in FIG.

  The output terminal term124 of inv2 is connected to the input pin of the second flip-flop f122. Here, hatched areas area121 and area122 are shown below the first gate electrode gate121. In the manufacturing process of the semiconductor integrated circuit, after the impurities are thinly distributed in each of the well regions pw121 and nw121, a step of selectively adding and distributing the impurities again only in the area 121 and the area 122 is performed, whereby these regions are formed. The impurity concentration increases, and only the MOSFETs pm1 and nm1 have a high threshold voltage.

  As shown in FIG. 5, according to this method, the threshold voltage of the MOSFET constituting the logic gate at an arbitrary position of the semiconductor integrated circuit can be freely changed. In FIG. 5, all the logic gates of the semiconductor integrated circuit LSI50 are schematically represented by rectangles. A shaded rectangle, for example, g51 indicates a logic gate formed of a low threshold voltage MOSFET, and a white rectangle, for example, g52 indicates a logic gate formed of a high threshold voltage MOSFET. In the figure, the path from f11 to f12 in FIG. 2 is shown as path51, and the path from f13 to f14 in FIG. 2 is shown as path52.

  However, in this method, in the manufacturing process of the semiconductor integrated circuit, a step of distributing impurities to the substrate, for example, an ion implantation step requires the number of types of MOSFETs to be used.

FIG. 25 shows an example of a vertical structure of a device in the case of using this method, which is an example of two inverters each having a MOSFET having two kinds of thresholds, high and low, shown in FIG. Since the example of FIG. 12 uses a complementary MOSFET, it has a double well structure in which an n well is formed in a part of the p-type substrate surface layer. On the surface layer of the p substrate, n + type source / drain regions diff2501, diff2504, gate oxide films ox2501, ox2504 and gate electrodes gate2501, gate2504 are formed to form n-channel MOSFETs nm2501, nm2504. On the surface layer of the n-well region, p-channel source / drain regions diff2502, diff2503, gate oxide films ox2502, ox2503, and p-channel MOSFETs pm2502, pm2503 including gate electrodes gate2502, gate2503 are formed. Further, Vdd is connected to the source of the p-channel MOSFET and n-well, and Vss is connected to the source of the n-channel MOSFET and the p-substrate.

  Here, it is assumed that the inverter inv1 in FIG. 12 is configured by nm2501 and pm2502, and the inverter inv2 in FIG. 12 is configured by nm2504 and pm2503. Since inv1 is composed of a high threshold MOSFET, the impurity concentration (impurity concentration 1 in the figure) of the semiconductor substrate under the gate oxide film of nm2501 and pm2502 is high, and inv2 is composed of a low threshold MOSFET. Therefore, the impurity concentration (impurity concentration 2 in the figure) of the semiconductor substrate under the gate oxide film of nm2504 and pm2503 is reduced.

  A third means of forming a semiconductor integrated circuit using MOSFETs having different threshold voltages is to change the gate oxide film thickness of the MOSFET. Even with this means, it is possible to freely change the threshold voltage of the MOSFET constituting the logic gate at an arbitrary position in the semiconductor integrated circuit as shown in FIG. However, even in this method, in the manufacturing process of the semiconductor integrated circuit, a step of forming a gate oxide film, for example, a thermal oxidation step requires the number of types of MOSFETs to be used.

  FIG. 26 is a view showing a vertical structure of another device, and shows an example of two inverters using MOSFETs having two kinds of high and low threshold values shown in FIG. 12 when the above method is used.

  As in FIG. 25, a double well structure in which an n-well is formed in a part of the p-type substrate surface layer is employed. On the surface layer of the p substrate, n + type source / drain regions diff2601, diff2604, gate oxide films ox2601, ox2604 and gate electrodes gate2601, gate2604 are formed to form n-channel MOSFETs nm2601, nm2604. On the surface layer of the n-well region, p-type source / drain regions diff2602, diff2603, gate oxide films ox2602, ox2603, and p-channel MOSFETs pm2602, pm2603 each including a gate electrode gate2602, gate2603 are formed.

  Further, Vdd is connected to the source of the p-channel MOSFET and the n-well, and Vss is connected to the source of the n-channel MOSFET and the p-substrate. Here, it is assumed that the inverter inv1 in FIG. 12 is configured by the nm2601 and pm2602, and the inverter inv2 in FIG. 12 is configured by the nm2604 and pm2603. Inv1 is composed of a high-threshold MOSFET, so the thickness of the gate oxide film of nm2601 and pm2602 (thickness t1 in the figure) is increased, and inv2 is composed of a low-threshold MOSFET. The thickness (thickness t2 in the figure) of the gate oxide film of nm2604 and pm2603 is reduced.

  A fourth means for configuring a semiconductor integrated circuit with MOSFETs having different threshold voltages is to change the gate length of the MOSFET. Even with this means, it is possible to freely change the threshold voltage of the MOSFET constituting the logic gate at an arbitrary position in the semiconductor integrated circuit as shown in FIG.

FIG. 6 shows an example of the relationship between the gate length and the threshold voltage. For example, as shown in the graph of FIG.
By choosing two points and changing the gate length slightly, two types of MOSFETs with different threshold voltages can be formed.

  FIG. 27 shows the vertical structure of the device in the case of using this method, for an example of two inverters each having a MOSFET having two kinds of high and low threshold values shown in FIG. As in FIG. 25, a double well structure in which an n-well is formed in a part of the p-type substrate surface layer is employed. On the surface layer of the p substrate, n + type source / drain regions diff2701, diff2704, gate oxide films ox2701, ox2704, and gate electrodes gate2701, gate2704 are formed to form n-channel MOSFETs nm2701, nm2704. In the surface layer of the n-well region, p-channel source / drain regions diff2702 and diff2703, gate oxide films ox2702 and ox2703, and p-channel MOSFETs pm2702 and pm2703 each composed of gate electrodes gate2702 and gate2703 are formed. Further, Vdd is connected to the source of the p-channel MOSFET and the n-well, and Vss is connected to the source of the n-channel MOSFET and the p-substrate.

  Here, it is assumed that the inverter inv1 of FIG. 12 is configured by the nm2701 and pm2702, and the inverter inv2 of FIG. 12 is configured by the nm2704 and pm2703. Inv1 has a large gate length of nm2701 and pm2702 (the gate length Lg1 in the figure) in order to be composed of a high threshold MOSFET, and inv2 has a large threshold of nm2704 and pm2703 in order to be composed of a low threshold MOSFET. Reduce the gate length (gate length Lg2 in the figure).

  Referring to FIG. 7, an embodiment of the second means for realizing MOSFETs having different threshold voltages in the present invention will be described. A second means of forming a semiconductor integrated circuit with MOSFETs having different threshold voltages is to change a bias voltage value supplied to a substrate of the MOSFET. Therefore, unlike the above three means, it is necessary to separate well regions in order to supply different substrate bias voltages to MOSFETs having different threshold voltages.

  Further, a substrate bias operation potential supply line to be supplied to each well region is required. For this reason, it is not practical to freely change the threshold voltage of the MOSFET of the logic gate at an arbitrary position as shown in FIG. 5, since the area increases greatly.

  Therefore, as shown in FIG. 7, a layout is performed in which MOSFETs having the same threshold voltage are collectively arranged on the same well region as much as possible. However, when this means is used, there is an advantage that an additional manufacturing step for forming MOSFETs having a plurality of threshold voltages is not required.

FIG. 7 shows an example in which well regions from well 71 to well 75 are formed on a semiconductor integrated circuit LSI70. Here, wells 71 to 74 are well regions for a low threshold voltage MOSFET, and well 75 is a well region for a high threshold voltage MOSFET. In this case, the location where the logic gate can be arranged is restricted by the threshold voltage of the MOSFET. Therefore, when laying out the logic gate, it is necessary to arrange the logic gate in accordance with the constraint.

  FIG. 7 shows an example in which the area ratio between a logic gate formed by a low threshold voltage MOSFET and a logic gate formed by a high threshold voltage MOSFET is 1: 3. This ratio is determined by a target operating frequency, a target leak current value, and a logic circuit to be mounted. In addition, when the present invention is used for a gate array, an approximate value of the usage ratio of a logic gate formed by a low-threshold voltage MOSFET and a logic gate formed by a high threshold-voltage MOSFET is estimated in advance. A base will be formed in advance. Further, as shown in FIG. 7, when using two types of MOSFETs with thresholds, two types of operating potential supply lines for supplying a substrate bias are required.

  Although FIG. 7 shows an example in which either an n-channel MOSFET or a p-channel MOSFET is used alone, an embodiment in which a semiconductor integrated circuit is formed by a complementary MOSFET using both an n-channel MOSFET and a p-channel MOSFET will be described. In the case of a complementary MOSFET, a p-well region for forming an n-channel MOSFET and an n-well region for forming a p-channel MOSFET are required. A well structure is used.

  FIG. 8 shows a vertical structure of a device adopting a triple well structure for an example of two inverters each including a MOSFET having two kinds of thresholds, high and low, shown in FIG. Two insulated p-wells p-well1 and p-well2 are formed in part of the surface layer of the n-type substrate, and n-wells n-well1 and p-well1 are formed in part of the surface layer of p-well1. It has a triple well structure in which an n-well n-well2 is formed in part of the surface layer of well2. The n + type source / drain regions diff801 and diff804, gate oxide films ox801 and ox804, and gate electrodes gate801 and gate804 are formed on the surface layer of the p-well to form n-channel MOSFETs nm801 and nm804. On the surface layer of the n-well region, p-channel MOSFETs pm802 and pm803 including p + type source / drain regions diff802 and diff803, gate oxide films ox802 and ox803, and gate electrodes gate802 and gate803 are formed.

  Vdd is connected to the source of the p-channel MOSFET and Vss is connected to the source of the n-channel MOSFET. Vbp1 is connected to the n-well of the p-channel MOSFET pm802, and Vbn1 is connected to the p-well of the n-channel MOSFET nm801. Further, Vbp2 is connected to the n-well of the p-channel MOSFET pm803, and Vbn2 is connected to the p-well of the n-channel MOSFET nm804. Here, it is assumed that the inverter inv1 in FIG. 12 is configured by nm801 and pm802, and the inverter inv2 in FIG. 12 is configured by nm804 and pm803. Since inv1 is composed of a high threshold MOSFET and inv2 is composed of a low threshold MOSFET, Vbp1 is set to a voltage higher than Vbp2 and Vbn1 is set to a voltage lower than Vbn2. The respective voltage values are set to, for example, Vdd = 1.5V, Vss = 0V, Vbp1 = 2.0V, Vbn1 = -0.5V, Vbp2 = 1.5V, Vbn2 = 0V, and the like.

FIG. 16 shows a plan view of a layout of the circuit of FIG. 12 using the device having the structure of FIG.
FIG. 16 differs from FIG. 15 in that a first p-channel MOSFET pm1 composed of a first gate electrode gate121 and a p + source / drain region darea121, and a second gate electrode gate122 and a p + source / drain region darea123 The second p-channel MOSFET pm2 to be formed is formed on different n-well regions nw151 and nw152, respectively. Similarly, a first n-channel MOSFET nm1 constituted by a first gate electrode gate121 and an n + source / drain region darea 122, and a second n-channel MOSFET constituted by a second gate electrode gate122 and an n + source / drain region darea124 MOSFET nm2 is formed on different p-well regions pw151 and pw152, respectively.

This is because the well region needs to be separated in order to change the potential supplied to the well region between the low threshold MOSFET and the high threshold MOSFET. nw151 is supplied with a bias voltage via a third operating potential supply line Vbp151 through a through hole TH151, nw152 is supplied with a bias voltage via a fourth operating potential supply line Vbp152 through a through hole TH153, and pw151 is supplied with a through voltage. A bias voltage is supplied through a hole TH152 by a fifth operating potential supply line Vbn151, and a bias voltage is supplied to the nw152 through a through hole TH154 by a sixth operating potential supply line Vbn152.
According to the method of changing the bias voltage value supplied to the MOSFET substrate, as shown in FIG. 16, a layout area is required because a new operating potential supply line is required and a well region needs to be separated. However, as shown in FIG. 15, there is an advantage that the threshold voltage of the MOSFET can be changed without performing a new process in the manufacturing process of the semiconductor integrated circuit.

  FIG. 9 shows an embodiment of the semiconductor integrated circuit device of the present invention constituted by the complementary MOSFETs shown in FIG. FIG. 9A shows an example in which logic gates are two-dimensionally arranged on a semiconductor integrated circuit LSI 90 by arranging logic gates in one row and arranging a plurality of columns row 91 to row 98 in a vertical direction. In this embodiment, the logic gate is shown by a rectangle and the internal pattern is omitted, but the p-channel MOSFET and the n-channel MOSFET are arranged vertically. Here, the logic gates on row 91 and row 96 are constituted by low threshold voltage MOSFETs, and the logic gates in the other columns are all constituted by high threshold voltage MOSFETs.

  In this case, four insulated p-well regions pw91 to pw94 are required. The adjacent columns row92, row93, row94, and row95 are configured by MOSFETs having the same threshold voltage, and thus can share the p-well region pw92. Similarly, row97 and row98 share a p-well region pw94. Also, five n-well regions from nw91 to nw95 are required. Also for the n-well, adjacent rows row92 and row93 can share one n-well area nw92, row93 and row94 can share an n-well area nw93, and row97 and row98 can share an n-well area nw95.

  FIG. 9B shows an operating potential supply line for supplying the substrate bias power when the arrangement shown in FIG. 9A is performed. In (b) of FIG. 9, the well region is omitted to avoid complication. Wires 91 to 94 are wired in parallel to the columns. In addition, an example is shown in which wiring is also provided on the left and right sides of the column in a direction perpendicular to the reinforcement for reinforcement. wire91 is bias power supply for high threshold MOSFET p-well, wire92 is high threshold MOSFET n-well, wire93 low threshold MOSFET p-well, wire94 is low threshold MOSFET n-well. Has been supplied. By laying out in this way, the separation of wells is reduced, and the increase in the area when a semiconductor integrated circuit is formed with MOSFETs having different threshold voltages by means of changing the bias voltage value supplied to the substrate is minimized. It becomes possible to limit.

  Next, in the present invention, an example in which a second means for realizing MOSFETs having different threshold voltages is implemented using an SOI (silicon-on-insulator) device structure will be described. In the SOI structure, there is no need to separate well regions of individual MOSFETs. Therefore, it is not necessary to form MOSFETs having the same threshold voltage in the same well region as described above. In this case, as shown in FIG. 5, a MOSFET having an arbitrary threshold voltage can be arranged at an arbitrary location on the semiconductor integrated circuit. However, the second means for realizing MOSFETs having different threshold voltages requires changing the voltage value of the substrate bias power supply, and therefore requires an operating potential supply line.

  FIG. 22 shows the embodiment. The semiconductor integrated circuit LSI220 is an example in which logic gates composed of complementary MOSFETs having an SOI structure are arranged in columns. In the figure, logic gates, for example, g221 and g222 are represented by rectangles. Shaded rectangles, such as g221, indicate logic gates composed of low threshold voltage MOSFETs, and white rectangles, such as g222, indicate logic gates composed of high threshold voltage MOSFETs. is there.

  Also, a substrate bias potential supply line Vbp221 for a low threshold voltage p-channel MOSFET, a substrate bias potential supply line Vbp222 for a high threshold voltage p-channel MOSFET, and a substrate bias potential supply line for a low threshold voltage n-channel MOSFET. The line Vbn221 and the substrate bias potential supply line Vbn221 of the low threshold voltage n-channel MOSFET are wired in parallel with the columns.

In this figure, the potential supply line of the source electrode of the MOSFET is omitted. The potential supply line and the substrate are connected to the through holes TH221, TH222, and the like, and the bias power of the substrate of the MOSFET constituting each gate is supplied. Here, as shown in the figure, connect the bias potential supply lines parallel to the columns with the number of threshold types (however, in the case of complementary MOSFETs, the potential supply lines for p-channel MOSFET and n-channel MOSFET are required respectively. By laying out the wires and punching through holes depending on the threshold voltage of the MOSFET, MOSFETs having different threshold voltages can be arranged at arbitrary locations.

  That is, in the present invention, when the means for changing the threshold voltage of the MOSFET by changing the substrate bias power supply is used, the increase in the area is small, so that it is more preferable to use the SOI device structure.

  Next, an embodiment of a storage medium storing a cell library necessary for designing the above-described semiconductor integrated circuit of the present invention will be described. Before describing the embodiments, a brief description of the cell and the cell library will first be given below. Usually, when designing a semiconductor integrated circuit, a component having a small logic function called a predesigned cell is used. For the cell, internal circuit elements and their connections, layout patterns, etc. are designed in advance, and information such as shapes, terminal positions for connection to the outside, logical functions, delay characteristics, and power consumption characteristics are registered as a cell library. . By distributing the storage medium in which the cell library is stored, it is possible to use components that have already been designed and whose operations are guaranteed, in designing many semiconductor integrated circuits.

  FIG. 10 shows an example of a storage medium storing the cell library of the present invention. The example of FIG. 10 is an example in which a library in which three types of inverter cells are registered is stored. In this embodiment, as the information on the cell, the name, size, gate length, pin, delay characteristic, leak current, threshold voltage, function, and the like of the cell are written. c101 is a standard inverter cell, and c102 is a cell in which the gate width W of the MOSFET is doubled.

  In the related art, when a plurality of cells having the same function are prepared as described above, cells having different gate characteristics W and different delay characteristics are prepared. c103 is a cell having the same gate width W and the same dimensions as c102, but differing only in delay characteristics and power consumption characteristics. In other words, c103 is a cell constituted by a MOSFET having a low MOSFET threshold voltage, that is, a cell having a large leak current and a small delay. In order to design and manufacture the semiconductor integrated circuit device of the present invention as described above, the library shown in FIG. 10 is required. For example, in the manufacturing process of the semiconductor integrated circuit device of the present invention, when MOSFETs having different threshold voltages are used, in the process of selectively adding impurities or the process of changing the thickness of the gate oxide film depending on the location, As described above, a special mask pattern is required.

  When creating this mask pattern, it is necessary to have layout information of cells and wiring of the designed integrated circuit, connection information of the cells, and information capable of recognizing which cells are constituted by MOSFETs of which threshold value. . Since information on the threshold voltage of the MOSFET of each cell is stored in a storage medium storing the cell library of the present invention, the above-described mask pattern can be created by using this information. In this sense, not only the storage medium that stores the cell library but also the storage medium that stores the connection relationship between the cells and the wiring, that is, the so-called netlist, has information that can recognize MOSFETs having different threshold voltages. By analogy, it is included in the present invention.

  In this embodiment, the inverter cell is shown. However, the present invention can be similarly applied to cells such as AND, OR, NAND, NOR, a selector, and a flip-flop. There is no particular limitation.

  Next, an example of a design method using a storage medium storing the library will be described.

  FIG. 23 shows a process of performing a logic design using a storage medium storing the cell library of FIG. In the figure, rectangular boxes step 230 to step 232 indicate processing, black arrows indicate processing flow, and white arrows indicate data flow. The logical description LOG 230 is written in a higher-level logical description language such as VHDL. The logic description LOG230 is read, and logic optimization processing step230 is performed.

  The logic optimization process step 230 is an optimization process that does not depend on technology, and is, for example, a process of expressing logic by a Boolean expression and minimizing the number of terms in the Boolean expression. At this time, optimization processing is performed based on the delay estimated in the delay estimation processing step 231. After that, a cell allocation process step 232 is performed. This is a process of reading the cell library LIB230 and assigning technology-independent logic to actual cells.

  Here, the delay calculation processing step 233 and the power consumption calculation processing step 234 are repeatedly executed to perform optimal cell allocation and output the netlist net230. Since the cell allocation process is a characteristic process of the design method of the present invention, a detailed example is shown in the drawing. In this example, the cell allocation of a part of the path from A to D is being executed. It is assumed that the cell allocation for the routes A to B and C to D has already been completed, and the delays are 3.22 nsec and 1.70 sec, respectively. Assuming that the logic from B to C is expressed as C = not (B), this Boolean expression should be assigned to the inverter. Assuming that the target delay of the path from A to D is 5 nsec, the delay of the inverter needs to be 0.08 or less.

  At this time, as a result of reading the cell library LIB230, it is known that there are cells c102 and c103 having the same function, that is, the inverter cells and different threshold values because of different threshold voltages. Here, the delay and the power saving when each cell is used are calculated, and as a result, the cell c103 having a low threshold voltage is selected.

  An example of another design method using a storage medium storing the library will be described with reference to FIG. FIG. 24 shows a process of performing a logic design using the storage medium storing the cell library of FIG. As in FIG. 23, rectangular boxes step 240 to step 244 indicate processing, black arrows indicate processing flows, and white arrows indicate data flows. The logic description LOG240 is read, and logic optimization processing step240 is performed. This is the same as step 230 in FIG. Thereafter, a cell allocation process step 241 using only the high threshold cell is performed.

As in the embodiment of FIG. 23, the delay and power consumption calculation processing step 242 is repeatedly executed, and the optimal cell allocation is performed under the limitation that only the high threshold value cells are used. After that, a placement and routing process step 243 is performed. Furthermore, the delay and power consumption calculation processing step 242 are performed in consideration of the actual wiring length after the placement and routing, and as a result, a more accurate calculation result is obtained. As a result, if there is a delay violation path, a process step 244 of replacing cells on the violation path with cells of a low threshold MOSFET by the same function is performed, and a netlist net240 to which layout information is added is output.
Thus, there is an advantage that the violation can be eliminated without changing the surrounding layout.

  Also, contrary to the embodiment of FIG. 24, cell assignment and placement and routing are performed using only low-threshold MOSFET cells, and delay calculation is performed thereafter. A method is also conceivable in which cells on a path with a margin are replaced with cells of a high threshold MOSFET.

  Next, an example in which the present invention is applied to a semiconductor integrated circuit having about 8000 cells will be described. In this embodiment, a complementary MOSFET having a gate length of 0.25 μm is operated at Vdd = 1.6V and Vss = 0V.

  FIG. 18 is a graph in which the horizontal axis indicates the cycle time (maximum path delay), and the vertical axis indicates the number of cells included in the path of the delay value. When a cell is included in a plurality of paths, it is assumed that the cell is included in a path having the largest delay value. The solid line (1) indicates the case where a high threshold voltage (0.15 V) MOSFET is used uniformly, and the thick solid line (2) indicates the result of the present invention. When the threshold voltage is set to (−0.05 V), a thin solid line (3) indicates a case where a MOSFET having a uniform low threshold voltage (−0.05 V) is used. The solid line (1) has a maximum path of 5 nsec, but in (2) and (3), it has a maximum of 3.95 nsec, which indicates that both are speeded up.

  However, when the uniform threshold value is lowered as in (3), the speed of the region where the delay value is small is also increased, and the distribution of (1) is translated to the left. This indicates that even if a MOSFET with a high threshold voltage is used, the speed of the cell in the path within the target cycle is increased, and power is wasted.

  On the other hand, in (2), which is the result of the implementation of the present invention, in the region where the delay is small, only the range of 3.95 nsec to 5 nsec is compressed to the left without substantially changing the distribution of (1). In other words, this indicates that the speed has been increased without consuming unnecessary power.

  FIG. 17 is a graph in which the horizontal axis represents cycle time (maximum path delay) and the vertical axis represents power consumption due to leakage current. This circuit is a circuit that operates with a cycle time of 5 nsec (200 MHz) when a MOSFET having a high threshold voltage (0.15 V) is used uniformly. The value of the power consumption is normalized by assuming that the power consumption when a MOSFET having a high threshold voltage (0.15 V) is uniformly set to 1.

  In the figure, the triangles indicate the results when the threshold voltage was reduced uniformly, and the circles indicate the results of using two types of threshold voltage MOSFETs according to the present invention. It is. The threshold voltage is shown next to each plot point. For example, in the present invention, the low threshold voltage is -0.05 V, the high threshold voltage is 0.15 V, and when two types of threshold voltage MOSFETs are used, the cycle time is 3.95 nsec (253 MHz). The speed can be increased to about 20 and the power consumption will be about 20.

  On the other hand, when the threshold voltage is uniformly set to −0.05 V, the cycle time is similarly 3.95 nsec, but the power consumption is 60 or more. Further, for example, under the condition that the power consumption due to the leakage current is kept within 10 or less, the cycle time is 4.33 nsec (231 MHz) when the threshold voltage is changed uniformly, but according to the present invention, the cycle time is 4.07 nsec (246 MHz). It can be seen that the operation can be performed at high speed up to).

  In FIG. 17, when the present invention is implemented, the ratio of the low threshold voltage MOSFET is 6% when the low threshold voltage is 0.1 V, 15% when the low threshold voltage is 0.05 V, When the low threshold voltage is 0.0V, it is 23%, and when the low threshold voltage is -0.05V, it is 30%. Since the leakage current of the MOSFET when the threshold voltage is lowered increases exponentially, the ratio of the MOSFET that lowers the threshold voltage is preferably within about 30%. In order to suppress the power consumption appropriately, it is more preferable to suppress the power consumption within 10%. According to the present invention, it is possible to minimize the number of MOSFETs for setting the low threshold voltage, and the ratio of the low threshold MOSFET to the total MOSFET is within 30%. is there.

  From the above embodiment, by implementing the present invention, a semiconductor integrated circuit device having a high operation speed can be realized while minimizing an increase in power consumption due to MOSFET leakage current even during an active operation for operating at a high speed. It is clear that it can be obtained.

  FIG. 28 shows an example in which the semiconductor integrated circuit of the present invention is applied to a microprocessor. FIG. 28 shows main constituent blocks of a microprocessor, and the arrangement of cells inside the microprocessor is schematically represented by a rectangle.

In the example of FIG. 28, the constituent blocks are a CPU (central processing unit), an FPU (floating point arithmetic unit), a cache (built-in memory), a BSC (bus control), a DMA (direct memory access), a CPG (clock control), INT (interrupt control). The cells shaded in the block to be written are cells with a low threshold, and those outlined are cells with a high threshold. For example, it can be seen that the CPU, FPU, cache, etc., where many timing-critical paths exist, have a large number of cells with low thresholds. In addition, in a block INT or the like having extra timing, the ratio of cells having a low threshold value is small. As described above, according to the present invention, instead of simply changing the threshold voltage for each block, even in the same block, a low-threshold MOSFET and a high-threshold MOSFET are appropriately used as needed, and The use of low-threshold MOSFETs can be minimized, and high-speed operation and low power consumption can be achieved simultaneously.
Although the present invention realizes high-speed operation and low leakage current during active mode, it can be combined with a well-known technique for increasing the threshold value by controlling the substrate bias power supply during standby.

  In the embodiment described above, a case where two types of MOSFETs having different threshold voltages are mainly used has been described. However, it is possible to easily mix three or more types of threshold voltage MOSFETs. , Included in the present invention.

FIG. 1 is a logic gate circuit diagram of a typical embodiment of a semiconductor integrated circuit device of the present invention. FIG. 10 is a logic gate circuit diagram of another embodiment of the semiconductor integrated circuit device of the present invention. 7 shows a logic gate circuit according to another embodiment of the semiconductor integrated circuit device of the present invention. FIG. 10 is a logic gate circuit diagram of another embodiment of the semiconductor integrated circuit device of the present invention. FIG. 3 is a layout diagram of logic gates in a practical example of the semiconductor integrated circuit device of the present invention. FIG. 4 is a diagram illustrating a relationship between a gate length and a threshold voltage. FIG. 3 is a configuration diagram of a well region in a practical example of the semiconductor integrated circuit device of the present invention. 1 is a sectional view of a device structure in an embodiment of a semiconductor integrated circuit device of the present invention. FIG. 11 is a configuration diagram of a well region in another actual example of the semiconductor integrated circuit device of the present invention. 1 is an embodiment of a storage medium storing a cell library according to the present invention. FIG. 6 is a diagram illustrating an example of a distribution of delay values of a general signal path. 1 is a MOSFET circuit diagram of an embodiment of a semiconductor integrated circuit device of the present invention. 7 is a MOSFET circuit according to another embodiment of the semiconductor integrated circuit device of the present invention. FIG. 6 is a MOSFET circuit diagram of another embodiment of the semiconductor integrated circuit device of the present invention. 1 is a layout diagram of an embodiment of a semiconductor integrated circuit device of the present invention. FIG. 10 is a layout diagram of another embodiment of the semiconductor integrated circuit device of the present invention. FIG. 4 is a diagram showing a relationship between delay and power consumption in the embodiment of the present invention. FIG. 4 is a diagram illustrating a distribution of delay values according to the embodiment of the present invention. FIG. 1 is a logic gate circuit diagram of an embodiment of a semiconductor integrated circuit device of the present invention. FIG. 1 is a logic gate circuit diagram of an embodiment of a semiconductor integrated circuit device of the present invention. FIG. 1 is a MOSFET circuit diagram of an embodiment in which a pass transistor and a complementary MOSFET are mixed in a semiconductor integrated circuit device of the present invention. FIG. 1 is a layout diagram of a semiconductor integrated circuit device when the present invention is implemented using an SOI device structure. FIG. 1 is a diagram showing an embodiment of a method for designing a semiconductor integrated circuit according to the present invention. FIG. 4 is a diagram showing another embodiment of a method for designing a semiconductor integrated circuit according to the present invention. 1 is a sectional view of a device structure in an embodiment of a semiconductor integrated circuit device of the present invention. FIG. 9 is a sectional view of a device structure in another embodiment of the semiconductor integrated circuit device of the present invention. FIG. 9 is a sectional view of a device structure in another embodiment of the semiconductor integrated circuit device of the present invention. 1 is a diagram of an embodiment in which a semiconductor integrated circuit device of the present invention is applied to a microprocessor.

Explanation of reference numerals

g11-g222… logic gate
gg191, gg192, gg201, gg202… logic gate group
f11-f14, f121-f143, f191-f203… flip-flop
LSI50, LSI70, LSI90… Semiconductor integrated circuit
well71 to well74… well area
darea121-darea124, diff801-diff2704 ... source / drain area
ox801 ～ ox2704… gate oxide film
gate121 to gate2704… gate electrode
row91-row98… logic gate row
pw91 to pw94, pw121, pw151, pw152, 802 ... p-well region
nw91 to nw95, nw121, nw151, nw152, 803 ... n-well region
wire91 to wire94, Vdd, Vss, Vdd121, Vdd131, Vdd141, Vss121, vss131, Vss141
, Vbp1 to Vbp222, Vbn1 to Vbn222… Operating potential supply line
c101 ~ c103… cell
nd1, nd2, nd131 to nd141 to nd143, nd211 to nd212… node
pm1 to pm2703… p-channel MOSFET
nm1-nm2704… n-channel MOSFET
inv1, inv2, inv131, inv211… Inverter logic gate
NAND131, NAND141 to NAND143… NAND logic gate
term121 to term124… terminal
TH121, TH122, TH151-TH154, TH221, TH222… Through hole
c131, c132, c141, c142, c191, c201 ... Logic gate circuit
step230-step232, step240-step244… processing step
LOG230, LOG240… Logical description
LIB230, LIB230… cell library
net230, net240 ... Netlist.

Claims (26)

A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device, wherein the switching elements include at least two or more types of switching elements: a low threshold voltage switching element and a high threshold voltage switching element;
There are a plurality of paths through which the signal propagates, and a threshold voltage of a switching element forming a logic gate of the first path is different from a threshold voltage of a switching element forming a logic gate of the second signal path. A semiconductor integrated circuit device characterized in that: A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device, wherein the switching elements include at least two or more types of switching elements: a low threshold voltage switching element and a high threshold voltage switching element;
A semiconductor integrated circuit, wherein a logic gate composed of a switching element with a low threshold voltage and a logic gate composed of a switching element with a high threshold voltage are mixed on one path through which the signal propagates. Circuit device. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device, wherein the switching elements include at least two or more types of switching elements: a low threshold voltage switching element and a high threshold voltage switching element;
There is a signal path from the first node to the second node, a signal path branching from the second node to the third node, and a signal path branching from the second node to the fourth node. , The ratio of the number of logic gates constituted by the low threshold switching elements to the total number of logic gates on the path from the first node to the second node is different from the path from the second node to the third node. And a ratio higher than the ratio of the number of logic gates constituted by the low threshold switching elements to the total number of logic gates on the path from the second node to the fourth node. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device, wherein the switching elements include at least two or more types of switching elements: a low threshold voltage switching element and a high threshold voltage switching element;
There is a signal path from the first node to the second node, a path from the third node to the second node, and a path from the second node to the fourth node. The ratio of the number of logic gates constituted by the low threshold switching elements to the total number of logic gates on the path to the node is the path from the first node to the second node and the ratio from the third node to the second node. A ratio higher than the ratio of the number of logic gates constituted by the low threshold switching elements to the total number of logic gates on the path to the node.   The path through which the signal propagates is, as a first path, a path from the input pin of the semiconductor integrated circuit to the input pin of the state holding circuit where the signal first arrives, and as a second path, an output of the state holding circuit, A third path from a pin to an input pin of a state holding circuit to which a signal arrives next is an output of a semiconductor integrated circuit to which a signal reaches from an output pin of the state holding circuit without passing through another state holding circuit. 5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is one of three types of routes to a pin or a partial route of the three types of routes. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device,
At least a first and second state holding circuit and first, second, third and fourth switching elements;
A first operating potential supply line to which a first operating potential point is supplied, a second operating potential supply line to which a second operating point potential is supplied, and first and second nodes;
An output pin of the first state holding circuit or an input pin of the semiconductor integrated circuit is connected to the gate electrodes of the first and second switching elements directly or via one or more logic gates. ,
The first switching element is connected to have a source / drain path between the first operating potential point and the first node,
The second switching element is connected to have a source / drain path between the second operating potential point and the first node,
The first node is connected to gate electrodes of the third and fourth switching elements;
The third switching element is connected to have a source / drain path between the first operating potential point and the second node,
The fourth switching element is connected to have a source / drain path between the second operating potential point and the second node,
Further, the second node is connected to an input pin of the second state holding circuit or an output pin of the semiconductor integrated circuit directly or via one or more logic gates,
A semiconductor integrated circuit, wherein threshold voltages of the first switching element and the third switching element are different, or threshold voltages of the second switching element and the fourth switching element are different. Circuit device. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device,
At least a first, second, and third state holding circuit and first, second, third, fourth, fifth, and sixth switching elements;
A first operating potential supply line to which a first operating potential point is supplied, a second operating potential supply line to which a second operating point potential is supplied, and first, second, and third nodes;
An output pin of the first state holding circuit or an input pin of the semiconductor integrated circuit is connected to the gate electrodes of the first and second switching elements directly or via one or more logic gates. ,
The first switching element is connected to have a source / drain path between the first operating potential point and the first node,
The second switching element is connected to have a source / drain path between the second operating potential point and the first node,
The first node is connected to gate electrodes of the third, fourth, fifth, and sixth switching elements;
The third switching element is connected to have a source / drain path between the first operating potential point and the second node,
The fourth switching element is connected to have a source / drain path between the second operating potential point and the second node,
The fifth switching element is connected to have a source / drain path between the first operating potential point and the third node,
The sixth switching element is connected to have a source / drain path between the second operating potential point and the third node,
Further, the second node is connected to an input pin of the second state holding circuit or an output pin of the semiconductor integrated circuit directly or via one or more logic gates,
Further, the third node is connected to an input pin of the third state holding circuit or an output pin of a semiconductor integrated circuit directly or through one or more logic gates,
The threshold voltage of the third switching element is higher than the threshold voltage of the first switching element, or the threshold voltage of the fourth switching element is the threshold voltage of the second switching element. A semiconductor integrated circuit device which is higher than a voltage. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device,
At least a first, second, and third state holding circuit and first, second, third, fourth, fifth, sixth, seventh, and eighth switching elements;
A first operating point potential supply line to which the first operating potential point is supplied, a second operating potential supply line to which the second operating point potential is supplied, and first, second, and third nodes ,
An output pin of the first state holding circuit or an input pin of the semiconductor integrated circuit is connected to the gate electrodes of the first and second switching elements directly or via one or more logic gates. ,
The first switching element is connected to have a source / drain path between the first operating potential point and the first node,
The second switching element is connected to have a source / drain path between the second operating potential point and the first node,
An output pin of the second state holding circuit or an input pin of the semiconductor integrated circuit is connected to a gate electrode of the third and fourth switching elements directly or via one or more logic gates. ,
The third switching element is connected to have a source / drain path between the first operating potential point and the second node,
The fourth switching element is connected to have a source / drain path between the second operating potential point and the second node,
The first node is connected to gate electrodes of the fifth and sixth switching elements;
The second node is connected to gate electrodes of the seventh and eighth switching elements;
The fifth and seventh switching elements are connected to have a source / drain path between the first operating potential point and the third node,
The sixth and eighth switching elements are connected to have a source / drain path between the second operating potential point and the third node,
Further, the third node is connected to an input pin of the third state holding circuit or an output pin of a semiconductor integrated circuit directly or through one or more logic gates,
The threshold voltage of the first switching element is higher than the threshold voltage of the fifth or seventh switching element, or the threshold voltage of the second switching element is the sixth or the 8. A semiconductor integrated circuit device which is higher than the threshold voltage of the switching element of No. 8. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device having at least first, second, and third state holding circuits and first, second, third, fourth, fifth, and sixth switching elements;
A first operating potential supply line to which a first operating potential point is supplied, a second operating potential supply line to which a second operating point potential is supplied, and first, second, and third nodes;
A first logic gate group in which a plurality of logic gates are connected in series;
The output pin of the first state holding circuit or the input pin of the semiconductor integrated circuit is directly or via one or more logic gates, and the gate electrode of the first switching element and the second switching element Connected to the gate electrode of
The first switching element is connected to have a source / drain path between the first operating potential point and a first node;
The second switching element is connected to have a source / drain path between the first node and the second operating potential point;
The first node is connected to gate electrodes of the third, fourth, fifth, and sixth switching elements;
The third switching element is connected to have a source / drain path between the first operating potential point and the second node,
The fourth switching element is connected to have a source / drain path between the second node and the second operating potential point,
The fifth switching element is connected to have a source / drain path between the first operating potential point and the third node,
The sixth switching element is connected to have a source / drain path between the third node and the second operating potential point,
Further, the second node is connected to an input pin of the second state holding circuit via the first logic gate group,
Further, the third node is connected to an input pin of the third state holding circuit via the second logic gate group,
The first logic gate group has more logic gate stages than the second logic gate group,
The threshold voltage of the fifth switching element is higher than the threshold voltages of the first and third switching elements, or the threshold voltage of the sixth switching element is higher than the threshold voltage of the second and fourth switching elements. A semiconductor integrated circuit device characterized by being higher than a threshold voltage of a switching element. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device,
At least a first, second, and third state holding circuit and first, second, third, fourth, fifth, sixth, seventh, and eighth switching elements;
A first operating point potential supply line to which the first operating potential point is supplied, a second operating potential supply line to which the second operating point potential is supplied, and first, second, and third nodes ,
A first logic gate group in which a plurality of logic gates are connected in series;
An output pin of the first state holding circuit is connected to gate electrodes of the first and second switching elements via the first logic gate group,
The first switching element is connected to have a source / drain path between the first operating potential point and the first node,
The second switching element is connected to have a source / drain path between the second operating potential point and the first node,
An output pin of the second state holding circuit is connected to a gate electrode of the third and fourth switching elements via the first logic gate group,
The third switching element is connected to have a source / drain path between the first operating potential point and the second node,
The fourth switching element is connected to have a source / drain path between the second operating potential point and the second node,
The first node is connected to gate electrodes of the fifth and sixth switching elements;
The second node is connected to gate electrodes of the seventh and eighth switching elements;
The fifth and seventh switching elements are connected to have a source / drain path between the first operating potential point and the third node,
The sixth and eighth switching elements are connected to have a source / drain path between the second operating potential point and the third node,
Further, the third node is connected to an input pin of the third state holding circuit or an output pin of a semiconductor integrated circuit directly or via one or more logic gates, The gate group has a greater number of logic gate stages than the second logic gate group,
The threshold voltage of the third switching element is higher than the threshold voltage of the first and fifth or seventh switching elements, or the threshold voltage of the fourth switching element is A semiconductor integrated circuit device which is higher than a threshold voltage of the sixth or eighth switching element. A semiconductor having a logic gate constituted by a switching element formed on a semiconductor substrate, performing a predetermined process on at least one or a plurality of input signals by the logic gate, and outputting at least one or a plurality of signals An integrated circuit device,
Having at least a first, a second, and a third switching element;
A first operating point potential supply line to which the first operating potential point is supplied, a second operating potential supply line to which the second operating point potential is supplied, and first, second, and third nodes ,
The first node is connected to a gate electrode of the first switching element;
The second node is connected to a drain electrode of the first switching element;
A source electrode of the first switching element is connected to gate electrodes of the second and third switching elements,
The second switching element is connected to have a source / drain path between the first operating potential point and the third node,
The third switching element is connected to have a source / drain path between the second operating potential point and the third node,
A signal is input to the first and second nodes and a signal is output from the third node;
A semiconductor integrated circuit device, wherein a threshold voltage of the first switching element is lower than threshold voltages of the second and third switching elements.   12. The semiconductor according to claim 1, wherein the means for forming the switching elements having different threshold voltages includes changing an impurity concentration of a semiconductor substrate under a gate oxide film of the switching elements. Integrated circuit device.   12. The semiconductor integrated circuit device according to claim 1, wherein a bias voltage value supplied to a substrate of the switching element is changed as a means for configuring the switching element having the different threshold voltage. .   12. The semiconductor integrated circuit device according to claim 1, wherein a gate oxide film thickness of the switching element is changed as a means for configuring the switching element having the different threshold voltage.   12. The semiconductor integrated circuit device according to claim 1, wherein a gate length of the switching element is changed as means for forming the switching element having the different threshold voltage.   The first means for changing the impurity concentration of the semiconductor substrate under the gate oxide film of the switching element and the second means for changing the bias voltage value supplied to the substrate of the switching element include means for forming the switching elements having different threshold voltages. 2. A method according to claim 1, wherein a plurality of means are combined among the second means, the third means for changing the gate oxide film thickness of the switching element, and the fourth means for changing the gate length of the switching element. 12. The semiconductor integrated circuit device according to any one of 11. A semiconductor integrated circuit device in which the logic gates are two-dimensionally arranged by arranging the logic gates in a one-dimensional column and arranging a plurality of columns in a direction orthogonal to the columns.
14. The semiconductor integrated circuit device according to claim 13, further comprising a substrate bias operating potential supply line parallel to the same number of columns as the types of threshold voltages of the switching elements to be used.   14. The semiconductor integrated circuit device according to claim 13, comprising a plurality of well regions insulated from each other, wherein the switching elements having different threshold voltages are formed on different well regions. A semiconductor integrated circuit device in which the logic gates are two-dimensionally arranged by arranging the logic gates in a one-dimensional column and arranging a plurality of columns in a direction orthogonal to the columns.
Logic gates composed of switching elements having the same threshold voltage are arranged on the same column, are arranged on the same well region along the column, and operate in parallel with the column to supply substrate bias power. 19. The semiconductor integrated circuit device according to claim 18, further comprising a potential supply line.   20. The semiconductor integrated circuit according to claim 19, wherein, when the logic gates of a plurality of adjacent columns are configured by switching elements having the same threshold voltage, a well region is shared over the plurality of columns. apparatus.   A storage medium storing a cell library that describes the function, shape, delay, power consumption, etc. of each of the above-described logic circuit components, that is, cells, having a specific logic function designed in advance. A cell library characterized by storing at least two or more types of cells having different shapes and having different threshold voltages so that delay and power consumption are registered. A storage medium that stores. A design method for designing a semiconductor integrated circuit device according to any one of claims 1 to 20, using a storage medium storing a cell library according to claim 21. Using a calculation result of the step of calculating the delay and the step of calculating the power consumption and the delay of the signal path, at least two types of switching elements having the same function and the same shape and having different threshold voltages. A method for designing a semiconductor integrated circuit, comprising the step of selecting one cell from the above cells and assigning it to a logic circuit.   21. A design method for designing a semiconductor integrated circuit device according to claim 1 using a storage medium storing the cell library according to claim 21, wherein the cell comprises at least a switching element having a high threshold value. Designing the logic circuit using only the logic circuit, calculating the power consumption and the delay of the signal path, and a part of the logic circuit designed using only the cell constituted by the high-threshold switching element. Replacing the cells with cells formed of low threshold switching elements having the same function and the same shape. A plurality of circuits including at least one of a latch circuit, a flip-flop circuit, a signal output terminal, or a signal input terminal in a signal path;
A semiconductor integrated circuit having a plurality of transistors having different thresholds in a signal path between the circuits. A plurality of first circuits controlled by a clock signal in a signal path;
A semiconductor integrated circuit having a second circuit including a plurality of transistors having different thresholds in a signal path between the first circuits. A plurality of first circuits controlled by a clock signal in a signal path;
A method of designing a semiconductor integrated circuit device having a second circuit including a plurality of transistors having different thresholds in a signal path between the first circuits,
A method of designing a semiconductor integrated circuit, comprising: setting a threshold value of a transistor included in the second circuit so that a signal delay time between the first circuits does not exceed a predetermined target value.

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