JP2006032519A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can reduce power consumption due to leak current of a transistor in standby mode without providing a power switch for each of circuit block. <P>SOLUTION: A low power cell has such a circuit configuration that, when the level of the input/output signal of the cell is kept at a specified level during standby mode, the current of a power supply becomes smaller than when the input/output signal has another level. Therefore, in this case, the current of the power supply flowing to an earth line from a power line can be made the smallest in the standby mode, and the power consumption during standby mode can be suppressed without providing a power switch for interrupting leak current outside the circuit cell. Since no power switch is required, a burden required for layout design of the power switch is eliminated, and no simulation difference due to voltage drop of the power switch occurs. As a result, the entire characteristic of the semiconductor integrated circuit can be accurately verified. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that reduces power consumption caused by a leakage current of a transistor.

  In order to cope with low power consumption and miniaturization of processing dimensions, the power supply voltage of a semiconductor integrated circuit is decreasing year by year. When the signal amplitude is reduced due to a decrease in the power supply voltage, the threshold voltage of the transistor is relatively increased with respect to the signal amplitude, so that the on-current of the transistor is reduced and the delay is increased. Therefore, it is necessary to reduce the threshold voltage of the transistor according to the power supply voltage. However, when the threshold voltage of the transistor is lowered, the leakage current in the off state increases, which causes a disadvantage that the reduction in power consumption is hindered.

  As a technique for preventing such an increase in leakage current, a circuit technique called MTCMOS (multi-threshold complementary metal oxide semiconductor) is known. In MTCMOS, for example, a high threshold voltage transistor switch is inserted into the power supply line of each circuit block that performs a specific function. When the circuit block becomes unused, the transistor switch is set to OFF, and the leakage current flowing through each transistor in the circuit block is cut off. As a result, useless leakage current flowing in unused circuit blocks can be greatly reduced.

  However, conventionally, when designing a semiconductor integrated circuit incorporating such MTCMOS technology, layout design of a transistor switch inserted into a power supply line has been manually performed. For example, for each circuit block that performs a specific function, the layout and wiring of circuit cells inside the circuit block are automatically designed by a CAD device, and then a transistor switch is manually placed on the power supply line outside the circuit block. ing. As a result, there is a problem that the burden of layout design increases.

  In addition, as the power supply voltage decreases, a slight voltage drop that occurs in the resistance component of the power supply line greatly affects the signal delay. That is, when the power supply voltage is lowered, the signal amplitude margin with respect to the threshold voltage of the transistor is reduced, so that a large signal delay occurs even if the power supply voltage is slightly lowered.

  When the transistor switch is inserted into the power supply line, a voltage drop due to this is further added, and the above problem becomes more serious. In particular, since the signal delay at the center of a circuit block that increases the distance from the external power supply line increases, even if the circuit block is designed normally, it will not operate properly afterwards. There is a problem that it does not work when inserted. In addition, when a circuit block is connected to a block in a higher layer, there arises a problem that the required timing cannot be satisfied.

  As described above, the method of providing the power switch for each circuit block has disadvantages such as increasing the layout design burden and making it difficult to verify the signal delay.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor integrated circuit capable of reducing power consumption due to a leakage current without providing a power switch for each circuit block.

  The semiconductor integrated circuit of the present invention has a circuit cell for stopping the operation in the standby mode, and the circuit cell has the input / output signal when the level of the input / output signal has a predetermined level in the standby mode. Compared with the case where has other levels, the power supply current flowing from the power supply line to the ground line is reduced.

  According to the present invention, the power supply current flowing from the power supply line to the ground line in the circuit cell is the smallest in the standby mode. For this reason, it is possible to suppress power consumption in the standby mode without providing a power switch for cutting off leakage current outside the circuit cell.

  Preferably, the semiconductor integrated circuit of the present invention includes at least two types of transistors having the same conductivity type and different leakage current characteristics. Preferably, at least a part of the plurality of circuit cells is a transistor having a small leakage current among the two types of transistors, and is inserted in a current path between the power supply line and the ground line. And a transistor that is inserted on a signal path for propagating a signal from the input to the output and is turned off in the standby mode.

  According to the above configuration, in the standby mode, the current that flows in the current path between the power supply line and the ground line of the circuit cell is an off-state leakage current characteristic of a transistor having a small leakage current. Limited by. In addition, since this transistor with a small leakage current is a transistor inserted on the signal path for propagating a signal from the input to the output of the cell, compared with the case where a power switch transistor that does not contribute to the propagation of the output is provided separately. The increase in circuit area is suppressed.

  Note that the type of transistor having a small leakage current may be a gate insulating field effect transistor having a channel length longer than that of other types of transistors.

  In addition, the type of transistor having a small leakage current may have a higher threshold voltage than other types of transistors.

  Alternatively, the type of transistor having a small leakage current may be a gate insulating field effect transistor having a substrate bias voltage input node for inputting a substrate bias voltage capable of increasing a threshold voltage as compared with other types of transistors. good.

  According to the present invention, power consumption due to leakage current can be effectively reduced without providing a power switch for each circuit block.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram illustrating a configuration example of a semiconductor integrated circuit 1 according to an embodiment of the present invention.
In the example of FIG. 1, the semiconductor integrated circuit 1 includes a circuit block 2 that does not have a standby mode (that is, is always in an operating state), and circuit blocks 3 and 4 that have a standby mode.

The circuit block 2 is composed of circuit cells (hereinafter referred to as normal cells) in which static power consumption is normal when the circuit operation is stopped.
On the other hand, the circuit blocks 3 and 4 are configured by circuit cells (hereinafter referred to as low power cells) that consume less static power than normal cells.

A low power cell is identical to a normal cell in terms of the function that the circuit performs. For example, it is a circuit element having basic functions necessary for configuring an integrated circuit, such as a NAND circuit, a NOR circuit, and a NOT circuit.
The low power cell differs from the normal cell in that the internal circuit is configured so that the current flowing from the power supply line to the ground line (hereinafter referred to as power supply current) is minimized in the standby mode.

That is, the circuit of the low power cell is configured such that when the input / output signal level has a predetermined level in the standby mode, the power supply current becomes smaller than when the input / output signal has another level. The
For example, in the case of an inverter circuit cell in which the input signal is at a low level in the standby mode, the circuit is configured such that the power supply current is smaller when the input signal is at a low level than when the input signal is at a high level.
In addition, for example, in the case of an inverter circuit cell in which the input signal is at a high level in the standby mode, the circuit is configured such that the power supply current becomes smaller when the input signal is at a high level than when the input signal is at a low level.

  Such a circuit configuration of the low power cell can be realized by using, for example, a plurality of types of transistors having different leakage current characteristics.

Here, the semiconductor integrated circuit 1 is a CMOS type integrated circuit.
In this case, the semiconductor integrated circuit 1 has, for example, two types of MOS transistors having different leakage current characteristics for each of an n-type MOS transistor and a p-type MOS transistor.

  A normal cell includes only a MOS transistor having a large leakage current (hereinafter referred to as a normal transistor) of these two types of MOS transistors, and a MOS transistor having a small leakage current (hereinafter referred to as a low leakage current transistor). ) Is not included.

On the other hand, the low power cell includes two types of MOS transistors, that is, both a normal transistor and a low leakage current transistor.
In a low power cell, a transistor inserted in a current path between a power supply line and a ground line, and inserted in a signal path that propagates a signal from the cell input to the output, is in a standby mode. A low leakage current transistor is used for some or all of the transistors that are turned off in FIG.
Thereby, the power supply current in the standby mode is limited by the minute leakage current of the low leakage current transistor.
Further, by inserting a low leakage current transistor on the cell signal path, the low leakage current transistor can contribute to signal propagation. Therefore, for example, compared with a configuration in which a low leakage current transistor for a power switch is provided in a cell, it is not necessary to add a useless transistor that does not contribute to signal propagation, and an increase in circuit area can be suppressed. In addition, since a circuit for controlling on / off of the power switch transistor is not necessary, an increase in circuit area can be suppressed in this respect.

  Next, specific configurations of the normal cell and the low power cell will be described by taking a circuit cell that performs NAND operation as an example.

FIG. 2 is a diagram illustrating a configuration example of a normal cell that performs a NAND operation.
The normal cell shown in FIG. 2 has n-type MOS transistors Qn1 and Qn2 and p-type MOS transistors Qp1 and Qp2. These transistors are all normal transistors.

N-type MOS transistors Qn1 and Qn2 are connected in series between output node O and ground line G.
P-type MOS transistors Qp1 and Qp2 are connected in parallel between output node O and power supply line VDD.
The gates of n-type MOS transistor Qn1 and p-type MOS transistor Qp1 are connected to input node I1.
The gates of n-type MOS transistor Qn2 and p-type MOS transistor Qp2 are connected to input node I2.

  According to the normal cell shown in FIG. 2, when a low level signal is input to one or both of the input nodes I1 and I2, one or both of the p-type MOS transistors Qp1 and Qp2 are turned on, and the n-type MOS is turned on. Since one or both of the transistors Qn1 and Qn2 are turned off, a high level signal is output from the output node O. When high level signals are input to both input nodes I1 and I2, both p-type MOS transistors Qp1 and Qp2 are turned off, and both n-type MOS transistors Qn1 and Qn2 are turned on. Is output. Therefore, according to the normal cell shown in FIG. 2, the NAND operation result of the two signals inputted to the input nodes I1 and I2 is outputted from the output node O.

  FIG. 3 is a first diagram illustrating a configuration example of a low power cell that performs NAND operation, and illustrates an example in which a transistor having a long channel length is used as a low leakage current transistor.

In the example of FIG. 3, there are three types of low-power cells according to the state of input / output signals in the standby mode.
That is, in each standby mode, the low power cell shown in FIG. 3A inputs a high level signal to the input node I1 and a low level signal to the input node I2, and the low power cell shown in FIG. A low level signal is input to the input node I1 and a high level signal is input to the input node I2. The low power cell illustrated in FIG. 3C inputs a high level signal to the input nodes I1 and I2.

The low power cell shown in FIG. 3A is obtained by replacing the n-type MOS transistor Qn2 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn2A having a longer channel length.
In the low power cell, in the standby mode, a high level signal is input to the input node I1 and a low level signal is input to the input node I2, and the n-type MOS transistor Qn2A is turned off. Therefore, the power supply current flowing from the power supply line VDD to the ground line G can be suppressed to a slight leak current flowing to the n-type MOS transistor Qn2A in the off state.

The low power cell shown in FIG. 3B is obtained by replacing the n-type MOS transistor Qn1 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn1A having a longer channel length.
In the standby mode, the low power cell inputs a low level signal to the input node I1 and a high level signal to the input node I2, and the n-type MOS transistor Qn1A is turned off. Therefore, the power supply current flowing from the power supply line VDD to the ground line G is suppressed to a slight leak current flowing to the n-type MOS transistor Qn1A in the off state.

The low power cell shown in FIG. 3C is obtained by replacing the p-type MOS transistors Qp1 and Qp2 in the normal cell shown in FIG. 2 with p-type MOS transistors Qp1A and Qp2A having longer channel lengths, respectively.
In the low power cell, a high level signal is input to input nodes I1 and I2 in the standby mode, and both p-type MOS transistors Qp1A and Qp2A are turned off. Therefore, the power supply current flowing from power supply line VDD to ground line G can be suppressed to a slight leak current flowing to p-type MOS transistors Qp1A and Qp2A in the off state.

  As described above, in the low power cell shown in FIG. 3, among the transistors of the normal cell shown in FIG. 2, the low leakage current transistor having a long channel length is used as the transistor that is turned off in the standby mode. The power supply current is reduced.

The method for reducing the leakage current of the MOS transistor is not limited to the method for increasing the channel length as described above. For example, the threshold voltage of the transistor can be increased and leakage current can be reduced by adjusting the doping amount of impurities in the channel formation region.
The low power cell illustrated in FIG. 4 uses a transistor having a high threshold voltage as a low leakage current transistor.

The low power cell shown in FIG. 4A is obtained by replacing the n-type MOS transistor Qn2 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn2B having a higher threshold voltage.
In the low power cell, in the standby mode, a high level signal is input to the input node I1 and a low level signal is input to the input node I2, and the n-type MOS transistor Qn2B is turned off. Therefore, the power supply current flowing from the power supply line VDD to the ground line G can be suppressed to a slight leak current flowing to the n-type MOS transistor Qn2B in the off state.

The low power cell shown in FIG. 4B is obtained by replacing the n-type MOS transistor Qn1 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn1B having a higher threshold voltage.
In the low power cell, in the standby mode, a low level signal is input to the input node I1 and a high level signal is input to the input node I2, and the n-type MOS transistor Qn1B is turned off. Therefore, the power supply current flowing from the power supply line VDD to the ground line G can be suppressed to a slight leak current flowing to the n-type MOS transistor Qn1B in the off state.

The low power cell shown in FIG. 4C is obtained by replacing the p-type MOS transistors Qp1 and Qp2 in the normal cell shown in FIG. 2 with p-type MOS transistors Qp1B and Qp2B having higher threshold voltages, respectively.
In the low power cell, a high level signal is input to input nodes I1 and I2 in standby mode, and both p-type MOS transistors Qp1B and Qp2B are turned off. Therefore, the power supply current flowing from power supply line VDD to ground line G can be suppressed to a slight leak current flowing to p-type MOS transistors Qp1B and Qp2B in the off state.

By the way, the method of increasing the threshold voltage of the MOS transistor is not limited to the method of adjusting the impurity doping amount as described above, and there is, for example, a method of adjusting the substrate bias voltage.
The low power cell illustrated in FIG. 5 has a low leakage current transistor provided with an input node for a substrate bias voltage in order to adjust the threshold voltage.

The low power cell shown in FIG. 5A is obtained by replacing the n-type MOS transistor Qn2 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn2C.
N-type MOS transistor Qn2C receives a substrate bias voltage from input node BSn. This substrate bias voltage is adjusted in the negative direction (the direction in which the potential is lower than that of the ground line G) compared to the n-type MOS transistor Qn2, so that the n-type MOS transistor Qn2C is higher than the n-type MOS transistor Qn2. Has a threshold voltage.
In the low power cell, in the standby mode, a high level signal is input to the input node I1 and a low level signal is input to the input node I2, and the n-type MOS transistor Qn2C is turned off. Therefore, the power supply current in the standby mode is suppressed to a slight leak current flowing through the n-type MOS transistor Qn2C in the off state.

The low power cell shown in FIG. 5B is obtained by replacing the n-type MOS transistor Qn1 in the normal cell shown in FIG. 2 with an n-type MOS transistor Qn1C.
N-type MOS transistor Qn1C receives a substrate bias voltage from input node BSn. The substrate bias voltage is adjusted in the negative direction (the direction in which the potential is lower than that of the ground line G) compared to the n-type MOS transistor Qn1, and therefore the n-type MOS transistor Qn1C is higher than the n-type MOS transistor Qn1. Has a threshold voltage.
In the standby mode, the low power cell inputs a low level signal to the input node I1 and a high level signal to the input node I2, and the n-type MOS transistor Qn1C is turned off. Therefore, the power supply current in the standby mode can be suppressed to a slight leak current flowing through the n-type MOS transistor Qn1C in the off state.

The low power cell shown in FIG. 5C is obtained by replacing the p-type MOS transistors Qp1 and Qp2 in the normal cell shown in FIG. 2 with p-type MOS transistors Qp1C and Qp2C, respectively.
P-type MOS transistors Qp1C and Qp2C receive a substrate bias voltage from input node BSp. The substrate bias voltage is adjusted in the positive direction (the direction in which the potential is made higher than the power supply line VDD) as compared with p-type MOS transistors Qp1 and Qp2. Therefore, p-type MOS transistors Qp1C and Qp2C are p-type MOS transistors. Has a threshold voltage higher than Qp1 and Qp2.
In the low power cell, a high-level signal is input to input nodes I1 and I2 in the standby mode, and both p-type MOS transistors Qp1C and Qp2C are turned off. Therefore, the power supply current in the standby mode is suppressed to a slight leak current flowing through the p-type MOS transistors Qp1C and Qp2C in the off state.

As described above, according to the present embodiment, when the level of the input / output signal has a predetermined level in the standby mode, the power supply current is made smaller than when the input / output signal has another level. A low power cell circuit is configured.
As a result, the power supply current of the low-power cell can be minimized in the standby mode. As a result, the power consumption in the standby mode can be suppressed without providing a power switch that cuts off the leakage current outside the circuit cell. Is possible.
Since there is no need to provide a power switch for interrupting leakage current outside the circuit cell, the layout design of the power switch becomes unnecessary, and the burden of design work can be reduced.
In addition, since the simulation error due to the voltage drop of the power switch is eliminated, the entire characteristics of the semiconductor integrated circuit can be accurately verified by simulation.

Further, in the low power cell of this embodiment, among the transistors inserted on the current path between the power supply line and the ground line and inserted on the signal path that propagates the signal from the input to the output of the cell, Some or all of the transistors that are turned off in the standby mode may be replaced with low-leakage current transistors.
Thereby, the power supply current in the standby mode can be suppressed to a minute leak current of the low leak current transistor.
In addition, as compared with a configuration in which a low-leakage current transistor for a power switch is provided inside the cell, it is not necessary to add a useless transistor that does not contribute to signal propagation, so that the circuit area can be suppressed.
Further, since a circuit for controlling on / off of the power switch transistor is not necessary, the circuit area can be reduced in this respect.

  In addition, this invention is not limited only to the above-mentioned embodiment, Various variations are included.

  For example, in the above-described embodiment, the semiconductor integrated circuit including the normal cell and the low power cell is shown. However, the present invention is not limited to this, and all circuit blocks may be configured only by the low power cell.

In the above-described embodiment, an example in which two different types of transistors (normal transistor, low leakage current transistor) are provided in the same conductivity type transistor is shown. However, the present invention is not limited to this, and it is possible to have three or more types of transistors. is there.
For example, by using a transistor with a leakage current characteristic between a normal transistor and a low leakage current transistor in a circuit cell that requires high speed, power consumption in standby mode is reduced while satisfying the required operating speed. It becomes possible to do.

  In the above-described embodiment, a CMOS type semiconductor integrated circuit has been described as an example. However, the present invention is not limited to this, and can be applied to other various types of semiconductor integrated circuits.

  Further, the design information of the normal cell and the low leakage current cell can be made into a library so that it can be used in a CAD device that automatically executes gate-level logic synthesis and layout design. That is, a library of normal cells and a library of low leakage current cells may be provided independently and read by the CAD device. Thereby, logic synthesis and layout design can be easily automated while using a conventional design environment.

It is a figure which shows the structural example of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a figure which shows the structural example of the normal cell which performs NAND operation. It is a 1st figure which shows the structural example of the low power cell which performs NAND operation. It is a 2nd figure which shows the structural example of the low power cell which performs NAND operation. It is a 3rd figure which shows the structural example of the low power cell which performs NAND operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2-4 ... Circuit block, Qn1, Qn1A, Qn1B, Qn1C, Qn2, Qn2A, Qn2B, Qn2C ... N-type MOS transistor, Qp1, Qp1A, Qp1B, Qp1C, Qp2, Qp2A, Qp2B, Qp2C ... p-type MOS transistor

Claims (5)

A semiconductor integrated circuit having a circuit cell that stops operation in a standby mode,
In the circuit cell, when the level of the input / output signal has a predetermined level in the standby mode, the power supply current flowing from the power supply line to the ground line becomes smaller than when the input / output signal has another level. Configured as
Semiconductor integrated circuit. Having at least two types of transistors having the same conductivity type and different leakage current characteristics;
The circuit cell is a transistor of a type having a small leakage current among the two types, and is a signal that is inserted on a current path between the power supply line and the ground line and that propagates a signal from the input to the output Including a transistor that is inserted on the path and is turned off in the standby mode,
The semiconductor integrated circuit according to claim 1. The type of transistor having a small leakage current is a gate-insulated field effect transistor having a longer channel length than other types of transistors.
The semiconductor integrated circuit according to claim 2. The type of transistor with a small leakage current has a higher threshold voltage than other types of transistors.
The semiconductor integrated circuit according to claim 2. The type of transistor having a small leakage current is a gate-insulated field effect transistor having a substrate bias voltage input node for inputting a substrate bias voltage that can increase the threshold voltage as compared with other types of transistors. ,
The semiconductor integrated circuit according to claim 2.

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