JP5842912B2 - Resistance memory device and writing method thereof - Google Patents

Resistance memory device and writing method thereof Download PDF

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JP5842912B2
JP5842912B2 JP2013505870A JP2013505870A JP5842912B2 JP 5842912 B2 JP5842912 B2 JP 5842912B2 JP 2013505870 A JP2013505870 A JP 2013505870A JP 2013505870 A JP2013505870 A JP 2013505870A JP 5842912 B2 JP5842912 B2 JP 5842912B2
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resistance
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resistance memory
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JPWO2012128017A1 (en
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加藤　有光
有光 加藤
信 宮村
信 宮村
直樹 伴野
直樹 伴野
宗弘 多田
宗弘 多田
岡本　浩一郎
浩一郎 岡本
阪本　利司
利司 阪本
仁彦 伊藤
仁彦 伊藤
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NEC Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

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  • Mram Or Spin Memory Techniques (AREA)

Description

本発明は抵抗記憶装置の書き込み方法に関し、特に書き込みに電流をともない、この電流経路の抵抗が低抵抗から高抵抗に変化する書き込み過程を有する抵抗記憶素子を用いる抵抗記憶装置およびその書き込み方法に関する。   The present invention relates to a writing method for a resistance memory device, and more particularly to a resistance memory device using a resistance memory device having a writing process in which the resistance of a current path changes from a low resistance to a high resistance with a current during writing and a writing method thereof.

この種の抵抗記憶装置としては、例えば、ナノブリッジ素子を抵抗記憶素子として用いてクロスバースイッチを構成するものがあった。
まず、抵抗記憶素子の例として、ナノブリッジ素子と呼ばれる構造について説明する。図６に非特許文献１（２０１０ ＩＥＥＥ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ ＭＥＥＴＩＮＧ ＴＥＣＨＮＩＣＡＬ ＤＩＧＥＳＴ（ｐｐ．３０３−３０６））で報告されたナノブリッジ素子の例を示す。同図では、ナノブリッジ素子の断面形状と動作を示し、ルテニウム（Ｒｕ）電極１０１と固体電解質層１０２と銅（Ｃｕ）電極１０３とを積層した構造のナノブリッジ素子である。素子抵抗を低抵抗に変化させるには、まず図６Ａに示すように、Ｃｕ電極１０３にプラスの電圧（＋Ｖ）を印加することでＣｕイオン（Ｃｕ＋）をＲｕ電極１０１へ向かう方向に移動させる。これにより、固体電解質層１０２内にＣｕ導電領域１３２を形成して（図６Ｂ参照）、Ｃｕ電極１０３とＲｕ電極１０１の間を低抵抗（ＯＮ）にする。逆に、図６Ｃに示すように、Ｒｕ電極１０１にプラスの電圧（＋Ｖ）を印加するとＣｕイオンがＣｕ電極１０３へ向かう方向に移動してＣｕ電極１０３に回収されるため、Ｃｕ電極１０３とＲｕ電極１０１の間は高抵抗（ＯＦＦ）に変化する（図６Ｄ参照）。このように、図６に示すナノブリッジ素子では、電圧の印加方向により抵抗を変化させることができる。
次に、このナノブリッジ素子を用いて構成したクロスバースイッチについて図７を用いて説明する。本例では交差する２系統の配線群、例えば、ビット線Ｂ１乃至Ｂ３とワード線Ｗ１乃至Ｗ３の交差部分に両配線を接続するようにナノブリッジ素子Ａ１１乃至Ａ３３が配置されている。初期状態ではすべてのナノブリッジ素子が高抵抗の状態とする。ナノブリッジ素子Ａ１１を低抵抗にして配線Ｂ１と配線Ｗ１間を電気的接続状態にするには、Ｂ１とＷ１にそれぞれ電圧Ｖｄｄと０Ｖを、その他の配線にＶｄｄ／２を印加する。Ｖｄｄをナノブリッジ素子が低抵抗に変化する閾値電圧Ｖｔｈより大きく、かつＶｄｄ／２がＶｔｈより小さくなるように設定することで、所望のナノブリッジ素子Ａ１１だけ低抵抗に変化させることができる。これにより所望の１対の配線Ｂ１とＷ１が低抵抗で接続されることになる。
配線間を電気的に切断するには逆向きの電圧−Ｖｄｄを印加して、ナノブリッジ素子を高抵抗に変化させる。これらの動作により、２系統の配線群同士の接続を自由に切り替えるクロスバースイッチを構成することができる。
ほかの抵抗記憶素子の例として、特許文献１（国際公開番号ＷＯ２００５／００８７８３）で示された抵抗記憶素子の例を図８に示す。図８では、絶縁膜としてシリコン酸化膜がシリコン基板に被覆された基板１５５上に形成されたゲート電極１５３と、ゲート電極１５３上に形成されたイオン伝導体１５４と、イオン伝導体１５４上に形成されたソース電極１５１およびドレイン電極１５２とを有する。イオン伝導体１５４は電気化学反応のための金属イオンを含んでいる。また、ソース電極１５１とドレイン電極１５２は互いに所定の距離を隔てて形成さている。
ゲート電極１５３は、印加される電圧の大きさにより、ソース電極１５１とドレイン電極１５２の間に延在するイオン伝導体１５４の伝導度を制御するためのものである。ソース電極５１、ドレイン電極１５２およびゲート電極１５３は相互に電気的に絶縁された状態で配置されている。ゲート電極１５３は電気化学反応によってイオン伝導体１５４に金属イオンを供給するための材料を含んでいる。ソース電極１５１およびドレイン電極１５２のイオン伝導体１５４と接する部位には電気化学反応によってイオン伝導体と反応しない材料（例えば、白金等）が用いられているため、ソース電極１５１およびドレイン電極１５２は金属イオンを供給しない。
上記構成の抵抗記憶素子の動作について説明する。ソース電極１５１およびドレイン電極１５２に対してゲート電極１５３に正の電圧を印加すると、近接するソース電極１５１およびドレイン電極１５２上に金属イオンの還元反応によって金属が析出する。そして、ソース電極１５１およびドレイン電極１５２間のギャップに析出した金属のためにソース電極１５１およびドレイン電極１５２が電気的に接続されて、スイッチはオン状態に遷移する。
一方、ソース電極１５１およびドレイン電極１５２に対してゲート電極１５３に負の電圧を印加すると、電極間のギャップにおいて析出した金属が取り除かれてオフ状態に遷移する。これらのオン状態およびオフ状態は、ゲート電極１５３への電圧印加を中止しても、それぞれの状態が保持される。この抵抗記憶素子はソース電極とドレイン電極の間の抵抗値を、これらとは別のゲート電極に印加する電圧で制御する。イオン伝導体の導電性が変化しているためゲート電極とソース・ドレイン電極との間の抵抗も変化している。
このような抵抗記憶素子は、前述のような電気的接続経路を切り替えるスイッチ用途や、データを記憶するメモリ用途などに用いられる。As this type of resistance memory device, for example, there is a device that forms a crossbar switch using a nanobridge element as a resistance memory element.
First, a structure called a nanobridge element will be described as an example of a resistance memory element. FIG. 6 shows an example of a nanobridge element reported in Non-Patent Document 1 (2010 IEEE ELECTRON DEVICES MEETING TECHNICAL DIGEST (pp. 303-306)). The figure shows the cross-sectional shape and operation of the nanobridge element, which is a nanobridge element having a structure in which a ruthenium (Ru) electrode 101, a solid electrolyte layer 102, and a copper (Cu) electrode 103 are laminated. In order to change the element resistance to low resistance, first, as shown in FIG. 6A, a positive voltage (+ V) is applied to the Cu electrode 103 to move Cu ions (Cu + ) in the direction toward the Ru electrode 101. . Thus, a Cu conductive region 132 is formed in the solid electrolyte layer 102 (see FIG. 6B), and the resistance between the Cu electrode 103 and the Ru electrode 101 is reduced (ON). Conversely, as shown in FIG. 6C, when a positive voltage (+ V) is applied to the Ru electrode 101, the Cu ions move in the direction toward the Cu electrode 103 and are collected by the Cu electrode 103. Between the electrodes 101, the resistance changes to high resistance (OFF) (see FIG. 6D). Thus, in the nanobridge element shown in FIG. 6, the resistance can be changed depending on the voltage application direction.
Next, a crossbar switch configured using this nanobridge element will be described with reference to FIG. In this example, the nanobridge elements A11 to A33 are arranged so as to connect both wirings to two intersecting wiring groups, for example, at the intersections of the bit lines B1 to B3 and the word lines W1 to W3. In the initial state, all nanobridge elements are in a high resistance state. In order to make the nanobridge element A11 have a low resistance so that the wiring B1 and the wiring W1 are in an electrically connected state, voltages Vdd and 0V are applied to B1 and W1, respectively, and Vdd / 2 is applied to the other wirings. By setting Vdd to be larger than the threshold voltage Vth at which the nanobridge element changes to low resistance and Vdd / 2 to be lower than Vth, only the desired nanobridge element A11 can be changed to low resistance. As a result, a desired pair of wirings B1 and W1 are connected with low resistance.
In order to electrically disconnect between the wirings, a reverse voltage -Vdd is applied to change the nanobridge element to a high resistance. With these operations, it is possible to configure a crossbar switch that freely switches the connection between two wiring groups.
As another example of the resistance memory element, an example of the resistance memory element disclosed in Patent Document 1 (International Publication No. WO2005 / 008783) is shown in FIG. In FIG. 8, a gate electrode 153 formed on a substrate 155 in which a silicon oxide film is covered with a silicon substrate as an insulating film, an ion conductor 154 formed on the gate electrode 153, and formed on the ion conductor 154. The source electrode 151 and the drain electrode 152 are provided. The ionic conductor 154 contains metal ions for electrochemical reaction. The source electrode 151 and the drain electrode 152 are formed at a predetermined distance from each other.
The gate electrode 153 is for controlling the conductivity of the ion conductor 154 extending between the source electrode 151 and the drain electrode 152 according to the magnitude of the applied voltage. The source electrode 51, the drain electrode 152, and the gate electrode 153 are disposed in a state where they are electrically insulated from each other. The gate electrode 153 includes a material for supplying metal ions to the ion conductor 154 by an electrochemical reaction. Since a material (for example, platinum) that does not react with the ion conductor by an electrochemical reaction is used at a portion of the source electrode 151 and the drain electrode 152 that is in contact with the ion conductor 154, the source electrode 151 and the drain electrode 152 are made of metal. Do not supply ions.
The operation of the resistance memory element having the above configuration will be described. When a positive voltage is applied to the gate electrode 153 with respect to the source electrode 151 and the drain electrode 152, metal is deposited on the adjacent source electrode 151 and drain electrode 152 by a reduction reaction of metal ions. Then, the source electrode 151 and the drain electrode 152 are electrically connected due to the metal deposited in the gap between the source electrode 151 and the drain electrode 152, and the switch is turned on.
On the other hand, when a negative voltage is applied to the gate electrode 153 with respect to the source electrode 151 and the drain electrode 152, the deposited metal is removed in the gap between the electrodes, and the state transitions to the off state. These on-state and off-state are maintained even when voltage application to the gate electrode 153 is stopped. This resistance memory element controls the resistance value between the source electrode and the drain electrode by a voltage applied to another gate electrode. Since the conductivity of the ionic conductor is changed, the resistance between the gate electrode and the source / drain electrodes is also changed.
Such a resistance memory element is used for a switch for switching the electrical connection path as described above, a memory for storing data, and the like.

国際公開番号ＷＯ２００５／００８７８３（図５）International publication number WO2005 / 008783 (FIG. 5)

２０１０ ＩＥＥＥ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ ＭＥＥＴＩＮＧ ＴＥＣＨＮＩＣＡＬ ＤＩＧＥＳＴ（ｐｐ．３０３−３０６）2010 IEEE ELECTRON DEVICES MEETING TECHNICAL DIgest (pp. 303-306)

図６に示す抵抗記憶素子を低抵抗から高抵抗に変化させた時の書き込み後抵抗値のばらつきを繰り返し測定した結果を、２つの書き込みパルス幅（ｔ１、ｔ２）について図９に示す。図９の横軸は抵抗値を示し、縦軸は抵抗値分布の標準偏差を示す。図中の点線ｔ１で示すように、パルス幅が短い場合でも抵抗記憶素子は高抵抗に変化するが、図中の実線ｔ２で示すように、パルス幅が長いほどより高抵抗に分布することがわかる。これは、時間とともに固体電解質層内のイオンの移動が進むことによるためと考えられる。
スイッチ用途でもメモリ用途でも、高抵抗状態では電流が流れないことが理想であり、流れる分は損失となるため、できるだけ高い抵抗を実現できることが望ましい。このことから、書き込み端子間の抵抗を低抵抗から高抵抗に変化させる場合、書き込みパルスは長い方が望ましい。
書き込み方法として、たとえば１抵抗記憶素子ずつ長い時間をかけて書き込みを行うと、すべての書き込み抵抗記憶素子を処理するのに長時間かかってしまう。一方、複数の抵抗記憶素子を一度に書き込む方法が考えられるが、書き込み時点では各抵抗記憶素子は低抵抗であるため、選択抵抗記憶素子数が多いほど瞬間的に大きな電流が流れてしまう。
このため複数の抵抗記憶素子を同時に書き込むには、大電流に対応できるよう電源回路や配線の電流耐性を設計する必要があるが、この対応は装置面積を大きくしてしまう。このように、抵抗値が非常に高い高抵抗状態を得ようとした場合、書き込み時間の短縮と装置面積の抑制とを両立することが困難という問題があった。
本発明の目的は、上述した課題を解決した抵抗記憶装置およびその書き込み方法を提供することにある。FIG. 9 shows results of repeatedly measuring resistance variation after writing when the resistance memory element shown in FIG. 6 is changed from low resistance to high resistance with respect to two writing pulse widths (t1, t2). The horizontal axis in FIG. 9 indicates the resistance value, and the vertical axis indicates the standard deviation of the resistance value distribution. As shown by the dotted line t1 in the figure, the resistance memory element changes to a high resistance even when the pulse width is short, but as the pulse width is long, the resistance memory element is distributed to a higher resistance as shown by the solid line t2. Recognize. This is presumably because the movement of ions in the solid electrolyte layer proceeds with time.
Whether it is a switch application or a memory application, it is ideal that a current does not flow in a high resistance state, and the flow amount is a loss. For this reason, when the resistance between the write terminals is changed from a low resistance to a high resistance, it is desirable that the write pulse be long.
As a writing method, for example, if writing is performed over a long time for each resistance memory element, it takes a long time to process all the writing resistance memory elements. On the other hand, a method of writing a plurality of resistance memory elements at a time is conceivable. However, since each resistance memory element has a low resistance at the time of writing, a larger current flows instantaneously as the number of selected resistance memory elements increases.
For this reason, in order to simultaneously write a plurality of resistance memory elements, it is necessary to design the current resistance of the power supply circuit and the wiring so as to cope with a large current, but this correspondence increases the device area. As described above, when trying to obtain a high resistance state having a very high resistance value, there is a problem that it is difficult to achieve both shortening of the writing time and suppression of the device area.
An object of the present invention is to provide a resistance memory device and a writing method thereof in which the above-described problems are solved.

本発明の抵抗記憶装置は、第１の書き込み端子と、第２の書き込み端子と、第１の読み出し端子と、第２の読み出し端子と、前記第１の書き込み端子と前記第２の書き込み端子とを電気的に接続する第１の可変抵抗体と、前記第１の読み出し端子と前記第２の読み出し端子とを電気的に接続する第２の可変抵抗体とを有し、前記第１の書き込み端子と前記第２の書き込み端子との間に電圧を印加することで前記第１の可変抵抗体と前記第２の可変抵抗体の抵抗値がそれぞれ変化する抵抗記憶素子を複数有し、前記第１の可変抵抗体を低抵抗から高抵抗に変化させる書き込み手段を有し、前記書き込み手段は、単数もしくは複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の書き込み手段と、前記第１の書き込み手段による書き込みの後、複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の書き込み手段であり、さらに第２の書き込み手段での選択素子数が第１の書き込み手段での選択素子数より多く、かつ前記第２の書き込み時間が前記第１の書き込み時間より長時間であることを特徴としている。
また、本発明の抵抗記憶装置の書き込み方法は、抵抗記憶素子を複数有する抵抗記憶装置に対し、第１の可変抵抗体が低抵抗から高抵抗に変化する書き込み処理において、単数もしくは複数の抵抗記憶素子を選択し第１の書き込み端子と第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の処理と、複数の抵抗記憶素子を選択し第１の書き込み端子と第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の処理を順に行う書き込み方法であって、さらに第２の処理での選択素子数が第１の処理での選択素子数より多く、かつ第２の書き込み時間が第１の書き込み時間より長時間であることを特徴としている。The resistance memory device of the present invention includes a first write terminal, a second write terminal, a first read terminal, a second read terminal, the first write terminal, and the second write terminal. A first variable resistor that electrically connects the first read terminal and the second variable resistor that electrically connects the second read terminal and the first write A plurality of resistance memory elements, each of which changes a resistance value of the first variable resistor and the second variable resistor by applying a voltage between the terminal and the second write terminal; Writing means for changing one variable resistor from a low resistance to a high resistance, wherein the writing means selects one or a plurality of resistance memory elements and connects the first write terminal and the second write terminal. In between the first write voltage A first write means for applying a write time; and after writing by the first write means, a plurality of resistance memory elements are selected and a second write terminal is connected between the first write terminal and the second write terminal. Second writing means for applying a writing voltage for a second writing time, and the number of selected elements in the second writing means is larger than the number of selected elements in the first writing means, and the second writing time. Is longer than the first writing time.
Further, the writing method of the resistance memory device according to the present invention provides a resistance memory device having a plurality of resistance memory elements in a writing process in which the first variable resistor changes from low resistance to high resistance. A first process of selecting an element and applying a first write voltage between a first write terminal and a second write terminal for a first write time; and selecting a plurality of resistance memory elements to perform a first write A writing method for sequentially performing a second process of applying a second write voltage between a terminal and a second write terminal for a second write time, wherein the number of selected elements in the second process is the first. This is characterized in that the number of selected elements in the process is larger and the second writing time is longer than the first writing time.

この発明によれば、抵抗記憶素子の書き込み時に流れる電流の増加を抑制しながら、書き込み時間を短縮することができる。   According to the present invention, the write time can be shortened while suppressing an increase in current flowing during writing of the resistance memory element.

上述した目的、およびその他の目的、特徴および利点は、以下に述べる好適な実施の形態、およびそれに付随する以下の図面によってさらに明らかになる。
［図１Ａ］
本発明の第一の実施の形態を適用する抵抗記憶素子の等価回路図である。
［図１Ｂ］
図１Ａの抵抗記憶素子の要部構成を示す概略断面図である。
［図２］
本発明の第一の実施の形態を示す書き込み処理を示すフロー図である。
［図３Ａ］
本発明の第一の実施の形態を適用する抵抗記憶素子の別の等価回路図である。
［図３Ｂ］
図３Ａの抵抗記憶素子の要部構成を示す概略断面図である。
［図４Ａ］
発明の第二の実施の形態を適用する抵抗記憶素子の別の等価回路図である。
［図４Ｂ］
図４Ａの抵抗記憶素子の要部構成を示す概略断面図である。
［図５Ａ］
発明の第三の実施の形態を適用する抵抗記憶素子の別の等価回路図である。
［図５Ｂ］
図５Ａの抵抗記憶素子の要部構成を示す概略断面図である。
［図６Ａ−図６Ｄ］
非特許文献１に開示の抵抗記憶素子とその動作を示す概略断面図である。
［図７］
図６に示す抵抗記憶素子を用いたクロスバースイッチ回路を示す要部概要図である。
［図８］
特許文献１に開示の抵抗記憶素子を示す要部概略断面図である。
［図９］
図６の抵抗記憶素子の特性図である。
［図１０Ａ］
本発明の第一の実施例の動作方法を説明するクロスバースイッチ回路を示す要部概要図である。
［図１０Ｂ］
図１０Ａのクロスバースイッチ回路の要部構成を示す概略斜視図である。
［図１１］
各印加電圧パルスと各抵抗記憶素子での印加電圧値との関係を示すタイミングチャートを示す。
［図１２］
各印加電圧パルスと各抵抗記憶素子での抵抗値との関係を示すタイミングチャートを示す。The above-described object and other objects, features, and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.
[FIG. 1A]
It is an equivalent circuit diagram of the resistance memory element to which the first embodiment of the present invention is applied.
[Fig. 1B]
It is a schematic sectional drawing which shows the principal part structure of the resistance memory element of FIG. 1A.
[Figure 2]
It is a flowchart which shows the write-in process which shows 1st embodiment of this invention.
[FIG. 3A]
It is another equivalent circuit schematic of the resistance memory element to which the first embodiment of the present invention is applied.
[FIG. 3B]
It is a schematic sectional drawing which shows the principal part structure of the resistance memory element of FIG. 3A.
[FIG. 4A]
It is another equivalent circuit schematic of the resistance memory element to which the second embodiment of the invention is applied.
[FIG. 4B]
It is a schematic sectional drawing which shows the principal part structure of the resistance memory element of FIG. 4A.
[FIG. 5A]
It is another equivalent circuit schematic of the resistance memory element to which the third embodiment of the invention is applied.
[FIG. 5B]
It is a schematic sectional drawing which shows the principal part structure of the resistance memory element of FIG. 5A.
[FIGS. 6A-6D]
It is a schematic sectional drawing which shows the resistance memory element of the nonpatent literature 1, and its operation | movement.
[Fig. 7]
It is a principal part schematic diagram which shows the crossbar switch circuit using the resistance memory element shown in FIG.
[Fig. 8]
It is a principal part schematic sectional drawing which shows the resistive memory element disclosed by patent document 1. FIG.
[Fig. 9]
FIG. 7 is a characteristic diagram of the resistance memory element in FIG. 6.
[FIG. 10A]
It is a principal part schematic diagram which shows the crossbar switch circuit explaining the operation | movement method of the 1st Example of this invention.
[FIG. 10B]
It is a schematic perspective view which shows the principal part structure of the crossbar switch circuit of FIG. 10A.
[Fig. 11]
4 is a timing chart showing the relationship between each applied voltage pulse and the applied voltage value at each resistance memory element.
[Fig. 12]
3 is a timing chart showing the relationship between each applied voltage pulse and the resistance value at each resistance memory element.

本発明の実施の形態につき図面を参照して説明する。
図１、図２を参照すると、本発明の第一の実施の形態として複数で抵抗記憶装置を構成する抵抗記憶素子の構成図と書き込み処理が示されている。
第一の実施の形態による抵抗記憶装置は、図１Ａに等価回路図として示すように、第１の書き込み端子１と、第２の書き込み端子２と、第１の読み出し端子３と、第２の読み出し端子４と、第１の可変抵抗体５と、第２の可変抵抗体６とを有する。このような抵抗記憶装置の概略構成図の一例を図１Ｂに示す。ここで、第２の可変抵抗体６は、第１の可変抵抗体５の抵抗値の変化に従い、抵抗値が変化するものとする。第１の可変抵抗体５は第１の書き込み端子１と第２の書き込み端子２と電気的に接続されており、第２の可変抵抗体６は第１の読み出し端子３と第２の読み出し端子４と電気的に接続されている。図１Ｂの構成において、第１の可変抵抗体５と第２の可変抵抗体６とは同じ材質でもよいが、磁気力等により互いに影響を及ぼすものであれば、互いに異なるものであっても構わない。一例として挙げれば、第１の可変抵抗体５として第１の強磁性体を、第２の可変抵抗体６として第２の強磁性体を用い、第１の強磁性体の磁気異方性が第２の強磁性体より大きくなるように材料や形状を選択する。第１の強磁性体の磁化方向を設定したい向きに磁場を与えた状態で第１の強磁性体に電流を流し発熱させると、適切な磁場強度と温度の条件において第１の強磁性体の磁化方向は印加磁場方向に変化する。磁場を停止した後も磁気異方性により磁化方向は維持され、第１の強磁性体から発生する磁場が第２の強磁性体に影響する。この磁場で磁化方向が変化する程度に第２の強磁性体の磁気異方性を小さく設定することで、第２の強磁性体の磁化方向も変化する。磁性体の抵抗値はその磁化方向により変化するため、第１の強磁性体と第２の強磁性体の抵抗値は変化する。また、書き込み電流を流す第１の強磁性体と読み出しを行う第２の強磁性体とが絶縁されている構造でも、第２の強磁性体の抵抗値を変化させることができる。
次に本抵抗記憶装置の書き込み方法について説明する。書き込みは、第１の書き込み端子１と第２の書き込み端子２との間に電圧を印加し、第１の可変抵抗体５に電流を流すことで行う。この電流の向きや大きさによって、第１の可変抵抗体５の抵抗値が高抵抗から低抵抗、もしくは低抵抗から高抵抗に変化するとともに、第２の可変抵抗体６の抵抗値も連動して変化する。
第１の可変抵抗体５の抵抗値が高抵抗から低抵抗に変化する書き込みにおいては、書き込む抵抗記憶素子を一つ、もしくは複数選択し、少なくとも所望の電圧を所望の時間印加することで行う。この書き込み方法については、図７を参照して背景技術で説明しているので、ここではその説明を割愛する。
第１の可変抵抗体５の抵抗値が低抵抗から高抵抗に変化する書き込みにおいては、図２に示すように、まず一つ、もしくは複数の所望の書き込み抵抗記憶素子（セル）を選択し（Ｓ１）、少なくとも所望の電圧Ｖ１を所望の時間ｔ１印加する第１の処理を行う（Ｓ２）。この第１の処理を他の選択された複数の書き込み抵抗記憶素子（セル）に対しても行ない、全ての所望の書き込み素子（セル）への第１の処理が終わるまで繰り返した後、処理するセルが終了したことを確認したら（Ｓ３）、複数の所望の書き込み抵抗記憶素子（セル）を選択し（Ｓ４）、複数の選択された所望の書き込み抵抗記憶素子（セル）に対して、少なくとも所望の電圧Ｖ２を所望の時間ｔ２印加する第２の処理を行う（Ｓ５）。処理するセルが終了すると（Ｓ６）、書き込みが終了する（Ｓ７）。ここで、第２の処理の選択素子数は第１の処理の選択素子数以上であり、さらにｔ２はｔ１より長時間である。
読み出しは、第２の可変抵抗体６の抵抗値を第１の読み出し端子３と第２の読み出し端子４とを介して評価して行う。
このような書き込みにより、本抵抗記憶装置を、データの記憶装置や、接続を切り替えるスイッチなどとして用いることができる。
このように、本発明では、少数の抵抗記憶素子を選択し、短時間の書き込み処理を行うことで、低電流である程度の高抵抗にする第１の処理と、第１の処理を繰り返して書き込みを行う抵抗記憶素子を処理した後、第１の処理より多くの素子を選択し、第１の処理より長い時間の書き込み処理を一度に行う第２の処理を行うことで、抵抗記憶素子のさらなる高抵抗化を行なっている。
第１の可変抵抗体５と第２の可変抵抗体６とは、図３に示すように電気的に接続されていても良い。すなわち、図３Ａに示す等価回路図および図３Ｂに示す概略断面図に示すように、第１の可変抵抗体５および第２の可変抵抗体６として固体電解質５（６）の上面および下面に、第１の書き込み端子１および第２の書き込み端子２をそれぞれ設けている。一方、固体電解質５（６）の両側面には第１の読み出し端子３および第２の読み出し端子４をそれぞれ設けている。
電圧印加は、一つの電圧を一定期間印加するほか、印加中に電圧を増減させたり、極性を反転させたり、それぞれの印加時間を変えたりしてもよい。特に初期の抵抗値が低いため、初期は電圧を低く、以降に増加させる方法を採用することにより、漏れ電流を抑えることが可能である。
また、抵抗変化の過程はエネルギーバリアを超えて起こる現象が用いられているため、温度を上げることで変化しやすくなる。このため、まず書き込みとは逆の向きに電圧を印加して所望の時間電流を流すことで素子温度を上昇させ、その後正規の方向に電圧を印加して書き込みを行う方法も効果的である。
また、すべての抵抗記憶素子が高抵抗に到達すれば漏れ電流が所望の値以下に減少するため、第２の処理中、もしくは処理後に漏れ電流を評価し、所望の値に到達していれば第２の処理を終了する。所望の値に達成していなければ延長したり、再度行ったりする。これらの方法も時間短縮と高抵抗の達成の面で効果的である。
本実施の形態では、第１の処理において、いくつかの抵抗記憶素子を選択してある程度高抵抗化させる作業を分けて行うことで、すべての書き込みセルを選択すると流れてしまう瞬間的な大電流を軽減している。さらに、その後時間のかかる第２の処理をより多くの抵抗記憶素子に対して同時に行うことで書き込み時間を短縮している。ここで、ある程度高抵抗とは、低抵抗状態の抵抗値と高抵抗状態の抵抗値の間の抵抗値のことと定義し、以下では低抵抗と高抵抗との中間ということで中抵抗と呼ぶ。このように、書き込み電流の増加と書き込み時間の増加を抑制し、より高い抵抗値を利用できる抵抗記憶装置が得られる。
図４を参照すると、本発明の第二の実施の形態として抵抗記憶装置を構成する抵抗記憶素子の構成図が示されている。
第二の実施の形態による抵抗記憶装置は、図４に示すように、第１の書き込み端子１と、第２の書き込み端子２と、第２の読み出し端子４と、第１の可変抵抗体５と、第２の可変抵抗体６とを有する。第２の可変抵抗体６は、第１の可変抵抗体５の抵抗値の変化に従い、抵抗値が変化する。第１の可変抵抗体５は第１の書き込み端子１と第２の書き込み端子２と電気的に接続されており、第２の可変抵抗体６は第１の書き込み端子１と第２の読み出し端子４と電気的に接続されている。すなわち、図４Ａに示す等価回路図および図４Ｂに示す概略断面図に示すように、第１の可変抵抗体５および第２の可変抵抗体６としての固体電解質５および６の上面に、読み出し端子３を兼ねる共通の第１の書き込み端子１を設けている。一方、固体電解質５および６の下面には第２の書き込み端子２および第２の読み出し端子４をそれぞれ設けている。
本実施の形態の書き込み方法は上記実施の形態と同様に、第１の書き込み端子１と第２の書き込み端子２との間に電圧を印加し、第１の可変抵抗体５に電流を流すことで行う。前述したように、第１の処理が終わった後、第２の処理を行う。一方、読み出し方法は、第１の書き込み端子１が第１の実施の形態の第１の読み出し端子３を兼ねているので、第２の可変抵抗体５（６）の抵抗値を第１の読み出し端子としての第１の書き込み端子１と第２の読み出し端子４とを介して評価して行う。
本実施の形態では、抵抗記憶素子の端子数が減少するため、装置面積を小さくすることができる。
図５を参照すると、本発明の第三の実施の形態として抵抗記憶装置を構成する抵抗記憶素子の構成図が示されている。
第三の実施の形態による抵抗記憶装置は、図５に示すように、第１の書き込み端子１と、第２の書き込み端子２と、第１の可変抵抗体５とを有する。第１の可変抵抗体５は第１の書き込み端子１と第２の書き込み端子２と電気的に接続されている。ここでは、第１の書き込み端子１および第２の書き込み端子２が第一の実施の形態の第１の読み出し端子３および第２の読み出し端子４をそれぞれ兼ねており、第１の可変抵抗体５が第一の実施の形態の第２の可変抵抗体６を兼ねている。
したがって、本実施の形態における書き込み方法は上述したと同様に、第１の書き込み端子１と第２の書き込み端子２との間に電圧を印加し、第１の可変抵抗体５に電流を流すことで行う。前述したように、第１の処理が終わった後、第２の処理を行う。
読み出し方法は上述したと同様に、第２の可変抵抗体を兼ねる第１の可変抵抗体５の抵抗値を第１の読み出し端子および第２の読み出し端子をそれぞれ兼ねる第１の書き込み端子１および第２の書き込み端子２を介して評価しておこなう。
本実施の形態では、さらに抵抗記憶素子の端子数が減少するため、装置面積をさらに小さくすることができる。Embodiments of the present invention will be described with reference to the drawings.
Referring to FIG. 1 and FIG. 2, there are shown a configuration diagram and a writing process of a resistance memory element that constitutes a plurality of resistance memory devices as a first embodiment of the present invention.
As shown in FIG. 1A as an equivalent circuit diagram, the resistance memory device according to the first embodiment includes a first write terminal 1, a second write terminal 2, a first read terminal 3, and a second It has a read terminal 4, a first variable resistor 5, and a second variable resistor 6. An example of a schematic configuration diagram of such a resistance memory device is shown in FIG. 1B. Here, it is assumed that the resistance value of the second variable resistor 6 changes according to the change of the resistance value of the first variable resistor 5. The first variable resistor 5 is electrically connected to the first write terminal 1 and the second write terminal 2, and the second variable resistor 6 is the first read terminal 3 and the second read terminal. 4 is electrically connected. In the configuration of FIG. 1B, the first variable resistor 5 and the second variable resistor 6 may be the same material, but may be different from each other as long as they influence each other by magnetic force or the like. Absent. As an example, the first ferromagnet is used as the first variable resistor 5 and the second ferromagnet is used as the second variable resistor 6. The material and shape are selected so as to be larger than the second ferromagnetic material. When a current is applied to the first ferromagnet while the magnetic field is applied in the direction in which the magnetization direction of the first ferromagnet is desired to be set, the first ferromagnet is heated under appropriate magnetic field strength and temperature conditions. The magnetization direction changes to the applied magnetic field direction. Even after the magnetic field is stopped, the magnetization direction is maintained by the magnetic anisotropy, and the magnetic field generated from the first ferromagnet affects the second ferromagnet. By setting the magnetic anisotropy of the second ferromagnet to be small enough to change the magnetization direction with this magnetic field, the magnetization direction of the second ferromagnet also changes. Since the resistance value of the magnetic material changes depending on the magnetization direction, the resistance values of the first ferromagnetic material and the second ferromagnetic material change. Also, the resistance value of the second ferromagnetic material can be changed even in the structure in which the first ferromagnetic material for supplying the write current and the second ferromagnetic material for reading are insulated.
Next, a writing method of the resistance memory device will be described. Writing is performed by applying a voltage between the first write terminal 1 and the second write terminal 2 and passing a current through the first variable resistor 5. Depending on the direction and magnitude of this current, the resistance value of the first variable resistor 5 changes from high resistance to low resistance, or from low resistance to high resistance, and the resistance value of the second variable resistor 6 is also linked. Change.
In writing in which the resistance value of the first variable resistor 5 changes from high resistance to low resistance, one or a plurality of resistance memory elements to be written are selected, and at least a desired voltage is applied for a desired time. Since this writing method has been described in the background art with reference to FIG. 7, the description thereof is omitted here.
In writing in which the resistance value of the first variable resistor 5 changes from a low resistance to a high resistance, as shown in FIG. 2, first, one or a plurality of desired write resistance memory elements (cells) are selected ( S1) A first process of applying at least a desired voltage V1 for a desired time t1 is performed (S2). This first process is performed for a plurality of other selected write resistance memory elements (cells), and is repeated until the first process is completed for all desired write elements (cells). When it is confirmed that the cell is completed (S3), a plurality of desired write resistance memory elements (cells) are selected (S4), and at least desired for the plurality of selected desired write resistance memory elements (cells). The second process of applying the voltage V2 is applied for a desired time t2 (S5). When the cell to be processed is finished (S6), the writing is finished (S7). Here, the number of selected elements in the second process is equal to or greater than the number of selected elements in the first process, and t2 is longer than t1.
Reading is performed by evaluating the resistance value of the second variable resistor 6 via the first reading terminal 3 and the second reading terminal 4.
By such writing, the resistance memory device can be used as a data memory device, a switch for switching connection, and the like.
As described above, in the present invention, by selecting a small number of resistance memory elements and performing a short-time write process, the first process for reducing the current to a certain degree with a low current and the first process are repeated. After the resistance memory element to be processed is processed, a larger number of elements than the first process are selected, and a second process in which a writing process for a longer time than the first process is performed at one time is performed. The resistance is increased.
The first variable resistor 5 and the second variable resistor 6 may be electrically connected as shown in FIG. That is, as shown in the equivalent circuit diagram shown in FIG. 3A and the schematic cross-sectional view shown in FIG. 3B, the first variable resistor 5 and the second variable resistor 6 are formed on the upper and lower surfaces of the solid electrolyte 5 (6). A first write terminal 1 and a second write terminal 2 are provided. On the other hand, the first readout terminal 3 and the second readout terminal 4 are provided on both side surfaces of the solid electrolyte 5 (6).
In addition to applying a single voltage for a certain period of time, the voltage may be increased or decreased during application, the polarity may be reversed, or the respective application times may be changed. In particular, since the initial resistance value is low, the leakage current can be suppressed by adopting a method in which the voltage is initially low and then increased.
In addition, since the phenomenon of resistance change uses a phenomenon that occurs beyond the energy barrier, it is likely to change by raising the temperature. For this reason, it is also effective to first apply a voltage in the opposite direction to the writing and flow the current for a desired time to increase the element temperature, and then apply the voltage in the normal direction to perform the writing.
In addition, if all the resistance memory elements reach high resistance, the leakage current decreases to a desired value or less. Therefore, the leakage current is evaluated during or after the second process, and if the desired value is reached. The second process is terminated. If the desired value is not achieved, it is extended or re-executed. These methods are also effective in reducing time and achieving high resistance.
In the present embodiment, an instantaneous large current that flows when all the write cells are selected by separately performing an operation of selecting some resistance memory elements and increasing the resistance to some extent in the first process. Has been reduced. Further, the second processing, which takes time thereafter, is simultaneously performed on a larger number of resistance memory elements, thereby reducing the writing time. Here, a certain amount of high resistance is defined as a resistance value between a resistance value in a low resistance state and a resistance value in a high resistance state, and hereinafter referred to as an intermediate resistance between the low resistance and the high resistance. . In this manner, a resistance memory device that can suppress an increase in write current and an increase in write time and can use a higher resistance value can be obtained.
Referring to FIG. 4, there is shown a configuration diagram of a resistance memory element constituting a resistance memory device as a second embodiment of the present invention.
As shown in FIG. 4, the resistance memory device according to the second embodiment includes a first write terminal 1, a second write terminal 2, a second read terminal 4, and a first variable resistor 5. And a second variable resistor 6. The resistance value of the second variable resistor 6 changes according to the change of the resistance value of the first variable resistor 5. The first variable resistor 5 is electrically connected to the first write terminal 1 and the second write terminal 2, and the second variable resistor 6 is the first write terminal 1 and the second read terminal. 4 is electrically connected. That is, as shown in the equivalent circuit diagram shown in FIG. 4A and the schematic cross-sectional view shown in FIG. 4B, readout terminals are provided on the upper surfaces of the solid electrolytes 5 and 6 as the first variable resistor 5 and the second variable resistor 6. A common first write terminal 1 also serving as 3 is provided. On the other hand, a second write terminal 2 and a second read terminal 4 are provided on the lower surfaces of the solid electrolytes 5 and 6, respectively.
In the writing method of the present embodiment, a voltage is applied between the first write terminal 1 and the second write terminal 2 and a current is caused to flow through the first variable resistor 5 as in the above embodiment. To do. As described above, after the first process is completed, the second process is performed. On the other hand, in the reading method, since the first writing terminal 1 also serves as the first reading terminal 3 of the first embodiment, the resistance value of the second variable resistor 5 (6) is determined as the first reading. Evaluation is performed through the first writing terminal 1 and the second reading terminal 4 as terminals.
In this embodiment, since the number of terminals of the resistance memory element is reduced, the device area can be reduced.
Referring to FIG. 5, there is shown a configuration diagram of a resistance memory element constituting a resistance memory device as a third embodiment of the present invention.
As shown in FIG. 5, the resistance memory device according to the third embodiment has a first write terminal 1, a second write terminal 2, and a first variable resistor 5. The first variable resistor 5 is electrically connected to the first write terminal 1 and the second write terminal 2. Here, the first write terminal 1 and the second write terminal 2 also function as the first read terminal 3 and the second read terminal 4 of the first embodiment, respectively, and the first variable resistor 5 Serves also as the second variable resistor 6 of the first embodiment.
Therefore, in the writing method in the present embodiment, as described above, a voltage is applied between the first writing terminal 1 and the second writing terminal 2 to cause a current to flow through the first variable resistor 5. To do. As described above, after the first process is completed, the second process is performed.
As described above, in the reading method, the resistance value of the first variable resistor 5 that also serves as the second variable resistor is set to the first write terminal 1 and the second write terminal 1 that also serve as the first read terminal and the second read terminal, respectively. The evaluation is performed through the write terminal 2.
In this embodiment, since the number of terminals of the resistance memory element is further reduced, the device area can be further reduced.

次に、具体的な実施例を用いて本発明の動作を説明する。
図５に示した抵抗記憶素子を、図１０Ａに示したクロスバースイッチの構成に適用した場合について、本発明の第一の実施例の動作方法を説明する。図１０Ｂは図１０Ａの概略構成図を示す。
本発明の第一の実施例は、抵抗記憶素子の抵抗値が低抵抗から高抵抗になる書き込みにおいて適用される。抵抗記憶素子Ａ１１、Ａ２２、Ａ３３が低抵抗であり、これらを高抵抗に書き換える場合について説明する。ほかの抵抗記憶素子は高抵抗とする。
まず、全ワード線Ｗと全ビット線ＢをＶｄｄ／２に設定する。次にワード線Ｗ１に電圧Ｖｄｄ、たとえば１．５Ｖの印加電圧パルスを０．１ｎｓ〜１μｓの時間印加する（第１の処理）。図１１にワード線およびビット線での電位（０、Ｖｄｄ／２、Ｖｄｄ）と各抵抗記憶素子における電位差（０、Ｖ１、Ｖ２）との関係を示すタイミングチャートを示す。第１の処理を行うときは、書き込みを行う素子のワード線にＶｄｄ、ビット線に０を印加する。また、図１２に各印加電圧パルス（０、Ｖｄｄ／２、Ｖｄｄ）と各抵抗記憶素子での抵抗値（低抵抗Ｌ、中抵抗Ｍ、高抵抗Ｈ）との関係を示すタイミングチャートを示す。
上記第１の処理により抵抗記憶素子Ａ１１の抵抗は、図１２に示すように中抵抗（Ｍ）、たとえば１ＭΩに変化する。同様の処理をＡ２２、Ａ３３に対しても行い、１ＭΩ程度に変化させる。
次に、Ｂ１〜Ｂ３を０Ｖとし、Ｗ１〜Ｗ３にたとえば１．２Ｖ〜３Ｖを１０ｎｓ〜１００μｓで先の印加時間より長い時間（約１００倍）印加する（第２の処理）。これにより図１０のすべての抵抗記憶素子に電圧が印加されるが、もとから高抵抗（Ｈ）か、第１の処理で中抵抗（Ｍ）化しているので、流れる電流は少ない。この第２の処理により、Ａ１１、Ａ２２、Ａ３３の抵抗値はさらに高抵抗化が進み、たとえば５００ＭΩにすることができる。このように高抵抗（Ｈ）を実現することで、高抵抗に設定された抵抗記憶素子を回路動作中に流れてしまう無駄な電流を低減できる。
第１の処理における印加電圧は、低いほど無駄な電流を少なくできるが、抵抗値の上昇量も少なくなってしまうため、第２の処理における電圧印加時の漏れ電流が増えてしまうことを考慮して設定する。最初低い電圧で増加するようなランプ波や階段波を用いると印加初期の漏れ電流を抑えることができ効果的である。
第２の処理における印加電圧は、低いほど抵抗記憶素子へのダメージが少なく、高いほど高抵抗化が早く進むため、抵抗記憶素子の特性と所望の動作速度を考慮して設定する。こちらにも最初低い電圧で増加するようなランプ波や階段波を用いると印加初期の漏れ電流を抑えることができ効果的である。
接続配線を切り替えるには、背景技術で述べたように、配線間に逆向きの電圧（−Ｖｄｄを印加して、抵抗記憶素子を高抵抗に変化させる処理で切断した後、接続すべき抵抗記憶素子を低抵抗に変化させる書き込みを行う。この書き込み端子間の抵抗を高抵抗から低抵抗にする書き込みについても、背景技術で述べたのと同様である。
本例では、最初に１抵抗記憶素子ずつ高抵抗化を行ったが、複数の抵抗記憶素子ずつ処理することも可能であり、書き込み時に流れる電流量と必要な回路面積を考慮して決定することもできる。また、最終的な高抵抗化処理は全抵抗記憶素子に対して行ったが、漏れ電流が大きすぎないように、いくつかのブロックに分けて処理しても良い。
また、図８に示す抵抗記憶素子を用いた場合、前述のように図６に示す抵抗記憶素子を採用する場合とは動作のさせ方が異なるが、同様の効果が得られる。電圧印加は、一つの電圧を一定期間印加するほか、印加中に電圧を増減させたり、反転させたり、それぞれの印加時間を変えたりしてもよい。
本実施例に依れば、書き込み時の電流の増加を抑制し、書き込み時間を短縮しながら、高抵抗状態を利用することができる抵抗記憶装置が実現可能となる。
なお、本発明は上記各実施例に限定されず、本発明の技術思想の範囲内において、各実施例は適宜変更され得ることは明らかである。
上記の実施形態の一部又は全部は、以下の付記のようにも記載されうるが、以下には限られない。
（付記１）
第１の書き込み端子と、第２の書き込み端子と、第１の読み出し端子と、第２の読み出し端子と、前記第１の書き込み端子と前記第２の書き込み端子とを電気的に接続する第１の可変抵抗体と、前記第１の読み出し端子と前記第２の読み出し端子とを電気的に接続する第２の可変抵抗体とを有し、前記第１の書き込み端子と前記第２の書き込み端子との間に電圧を印加することで前記第１の可変抵抗体と前記第２の可変抵抗体の抵抗値がそれぞれ変化する抵抗記憶素子を複数有し、前記第１の可変抵抗体を低抵抗から高抵抗に変化させる書き込み手段を有し、前記書き込み手段は、単数もしくは複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の書き込み手段と、前記第１の書き込み手段による書き込みの後、複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の書き込み手段であり、さらに第２の書き込み手段での選択素子数が第１の書き込み手段での選択素子数より多く、かつ前記第２の書き込み時間が前記第１の書き込み時間より長時間であることを特徴とする抵抗記憶装置。
（付記２）
前記第２の書き込み電圧が前記第１の書き込み電圧より大きいことを特徴とする付記１記載に記載の抵抗記憶装置。
（付記３）
前記第１の書き込み手段により電圧が印加された前記抵抗記憶素子の抵抗値は前記第２の書き込み手段による書き込みの後の抵抗値より小さいことを特徴とする付記１に記載の抵抗記憶装置。
（付記４）
前記第２の書き込み時間が１０ｎｓ〜１００μｓであることを特徴とする付記１から３のいずれか１項に記載の抵抗記憶装置。
（付記５）
前記第１の書き込み時間が０．１ｎｓ〜１μｓであることを特徴とする付記１から４のいずれか１項に記載の抵抗記憶装置。
（付記６）
複数の前記抵抗記憶素子でクロスバースイッチを構成していることを特徴とする付記１から５のいずれか１項に記載の抵抗記憶装置。
（付記７）
前記第１の書き込み端子と前記第３の読み出し端子とが共通であることを特徴とする付記１から６のいずれか１項に記載の抵抗記憶装置。
（付記８）
前記第１の書き込み端子と前記第１の読み出し端子とが共通であり、かつ前記第２の書き込み端子と前記第２の読み出し端子とが共通であることを特徴とする付記１から６のいずれか１項に記載の抵抗記憶装置。
（付記９）
前記第１の可変抵抗体と前記第２の可変抵抗体とが電気的に接続されていることを特徴とする付記１から６のいずれか１項に記載の抵抗記憶装置。
（付記１０）
第１の書き込み端子と、第２の書き込み端子と、第１の読み出し端子と、第２の読み出し端子と、前記第１の書き込み端子と前記第２の書き込み端子とを電気的に接続する第１の可変抵抗体と、前記第１の読み出し端子と前記第２の読み出し端子とを電気的に接続する第２の可変抵抗体とを有し、前記第１の書き込み端子と前記第２の書き込み端子との間に電圧を印加することで前記第１の可変抵抗体と前記第２の可変抵抗体の抵抗値がそれぞれ変化する抵抗記憶素子を複数有する抵抗記憶装置に対し、前記第１の可変抵抗体が低抵抗から高抵抗に変化する書き込み処理において、単数もしくは複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の処理と、複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の処理を順に行う書き込み方法であって、さらに第２の処理での選択素子数が第１の処理での選択素子数より多く、かつ前記第２の書き込み時間が前記第１の書き込み時間より長時間であることを特徴とする抵抗記憶装置の書き込み方法。
（付記１１）
前記第２の書き込み手段による電圧印加中、もしくは電圧印加停止後に、書き込みを行った素子に流れる電流を評価し、所望の値に達していれば前記書き込み手段を終了し、達していなければ前記書き込み手段の延長、もしくは再度第２の書き込み手段を実行することを特徴とする付記１から９のいずれか１項に記載の抵抗記憶装置。
（付記１２）
前記第２の書き込み電圧が前記第１の書き込み電圧より小さいことを特徴とする付記１に記載の抵抗記憶装置。
（付記１３）
前記第１の書き込み電圧、および／または前記第２の書き込み電圧が印加中に増減、極性反転することを特徴とする付記１から５のいずれか１項に記載の抵抗記憶装置。
（付記１４）
前記第１の書き込み電圧、および／または前記第２の書き込み電圧が印加中に増加する時間を有することを特徴とする付記１から６のいずれか１項に記載の抵抗記憶装置。
（付記１５）
前記第１の可変抵抗体内部、および／または前記第２の可変抵抗体内部に記憶データにより低抵抗の導電領域が形成・消滅する抵抗記憶素子を用いていることを特徴とする付記１から１４のいずれか１項に記載の抵抗記憶装置。
（付記１６）
素子をグループ分けし、前記第２の書き込み手段をグループごとに行うことを特徴とする付記１から１５のいずれか１項に記載の抵抗記憶装置。
この出願は、２０１１年３月２２日に出願された日本出願特願２０１１−０６２１７０を基礎とする優先権を主張し、その開示の全てをここに取り込む。Next, the operation of the present invention will be described using specific examples.
The operation method of the first embodiment of the present invention will be described in the case where the resistance memory element shown in FIG. 5 is applied to the configuration of the crossbar switch shown in FIG. 10A. FIG. 10B shows a schematic configuration diagram of FIG. 10A.
The first embodiment of the present invention is applied in writing in which the resistance value of the resistance memory element is changed from a low resistance to a high resistance. A case will be described in which the resistance memory elements A11, A22, and A33 have low resistance, and these are rewritten to high resistance. Other resistance memory elements have high resistance.
First, all word lines W and all bit lines B are set to Vdd / 2. Next, a voltage Vdd, for example, an applied voltage pulse of 1.5 V, for example, is applied to the word line W1 for a period of 0.1 ns to 1 μs (first process). FIG. 11 is a timing chart showing the relationship between the potential (0, Vdd / 2, Vdd) on the word line and the bit line and the potential difference (0, V1, V2) in each resistance memory element. When performing the first process, Vdd is applied to the word line of the element to be written, and 0 is applied to the bit line. FIG. 12 is a timing chart showing the relationship between each applied voltage pulse (0, Vdd / 2, Vdd) and the resistance value (low resistance L, medium resistance M, high resistance H) at each resistance memory element.
By the first process, the resistance of the resistance memory element A11 is changed to a medium resistance (M), for example, 1 MΩ, as shown in FIG. The same processing is performed for A22 and A33, and is changed to about 1 MΩ.
Next, B1 to B3 are set to 0 V, and for example, 1.2 V to 3 V is applied to W1 to W3 for 10 ns to 100 μs, which is longer (about 100 times) than the previous application time (second processing). As a result, a voltage is applied to all of the resistance memory elements in FIG. 10, but since the resistance is originally high (H) or has been changed to the middle resistance (M) in the first process, the flowing current is small. By this second processing, the resistance values of A11, A22, and A33 are further increased, and can be set to 500 MΩ, for example. By realizing the high resistance (H) in this way, it is possible to reduce a wasteful current that flows through the resistance memory element set to a high resistance during the circuit operation.
As the applied voltage in the first process is lower, the wasteful current can be reduced. However, since the amount of increase in the resistance value is also reduced, the leakage current at the time of voltage application in the second process is increased. To set. Using a ramp wave or staircase wave that increases at a low voltage at the beginning is effective in suppressing the leakage current at the initial application stage.
The applied voltage in the second process is set in consideration of the characteristics of the resistance memory element and a desired operation speed because the lower the damage to the resistance memory element is, the higher the resistance is increased. If a ramp wave or staircase wave that increases at a low voltage at first is used, the leakage current at the initial application can be suppressed, which is effective.
In order to switch the connection wiring, as described in the background art, a reverse voltage (−Vdd is applied between the wirings and the resistance memory element is changed to a high resistance, and then the resistance memory to be connected is disconnected. Writing in which the element is changed to low resistance is performed, and writing in which the resistance between the writing terminals is changed from high resistance to low resistance is the same as described in the background art.
In this example, the resistance is increased by one resistance memory element at the beginning. However, it is also possible to process a plurality of resistance memory elements, and it is determined in consideration of the amount of current flowing during writing and the required circuit area. You can also. In addition, although the final high resistance processing is performed on all the resistance memory elements, the processing may be divided into several blocks so that the leakage current is not too large.
Further, when the resistance memory element shown in FIG. 8 is used, the operation is different from the case where the resistance memory element shown in FIG. 6 is adopted as described above, but the same effect can be obtained. In addition to applying a single voltage for a certain period of time, the voltage may be increased or decreased or reversed during application, or the respective application times may be changed.
According to this embodiment, it is possible to realize a resistance memory device that can use the high resistance state while suppressing an increase in current during writing and shortening the writing time.
It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.
A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
A first write terminal, a second write terminal, a first read terminal, a second read terminal, a first write terminal that electrically connects the first write terminal and the second write terminal. And a second variable resistor for electrically connecting the first read terminal and the second read terminal, the first write terminal and the second write terminal. A plurality of resistance memory elements that change the resistance values of the first variable resistor and the second variable resistor by applying a voltage between the first variable resistor and the first variable resistor. Writing means for changing the resistance from high to low, wherein the writing means selects one or a plurality of resistance memory elements and applies a first write voltage between the first write terminal and the second write terminal. Applying the first writing time to the first After writing by the write-in means and the first writing means, a plurality of resistance memory elements are selected, and a second write voltage is applied between the first write terminal and the second write terminal. A second writing means for applying a writing time; the number of selected elements in the second writing means is greater than the number of selected elements in the first writing means; and the second writing time is the first writing time. A resistance memory device characterized by being longer than time.
(Appendix 2)
The resistance memory device according to claim 1, wherein the second write voltage is larger than the first write voltage.
(Appendix 3)
The resistance memory device according to appendix 1, wherein a resistance value of the resistance memory element to which a voltage is applied by the first writing unit is smaller than a resistance value after writing by the second writing unit.
(Appendix 4)
4. The resistance memory device according to claim 1, wherein the second write time is 10 ns to 100 μs.
(Appendix 5)
5. The resistance memory device according to claim 1, wherein the first write time is 0.1 ns to 1 μs.
(Appendix 6)
The resistance memory device according to any one of appendices 1 to 5, wherein a plurality of the resistance memory elements constitute a crossbar switch.
(Appendix 7)
The resistance memory device according to any one of appendices 1 to 6, wherein the first write terminal and the third read terminal are common.
(Appendix 8)
Any one of appendix 1 to 6, wherein the first write terminal and the first read terminal are common, and the second write terminal and the second read terminal are common. 2. The resistance memory device according to item 1.
(Appendix 9)
The resistance memory device according to any one of appendices 1 to 6, wherein the first variable resistor and the second variable resistor are electrically connected.
(Appendix 10)
A first write terminal, a second write terminal, a first read terminal, a second read terminal, a first write terminal that electrically connects the first write terminal and the second write terminal. And a second variable resistor for electrically connecting the first read terminal and the second read terminal, the first write terminal and the second write terminal. For the resistance memory device having a plurality of resistance memory elements that change the resistance values of the first variable resistor and the second variable resistor by applying a voltage between the first variable resistor and the first variable resistor, In a writing process in which the body changes from a low resistance to a high resistance, one or a plurality of resistance memory elements are selected, and a first write voltage is applied between the first write terminal and the second write terminal. Apply the first write time And a writing method of sequentially performing a second process of selecting a plurality of resistance memory elements and applying a second writing voltage between the first writing terminal and the second writing terminal for a second writing time. The number of selected elements in the second process is larger than the number of selected elements in the first process, and the second write time is longer than the first write time. To write resistance memory device.
(Appendix 11)
During the voltage application by the second writing means or after the voltage application is stopped, the current flowing through the element to which writing has been performed is evaluated, and if the desired value is reached, the writing means is terminated. The resistive memory device according to any one of appendices 1 to 9, wherein the extension of the means or the second writing means is executed again.
(Appendix 12)
The resistance memory device according to appendix 1, wherein the second write voltage is smaller than the first write voltage.
(Appendix 13)
6. The resistance memory device according to any one of appendices 1 to 5, wherein the first write voltage and / or the second write voltage increase / decrease and polarity is reversed during application.
(Appendix 14)
7. The resistance memory device according to any one of appendices 1 to 6, characterized in that the first write voltage and / or the second write voltage has a time to increase during application.
(Appendix 15)
Additional remarks 1 to 14 using a resistance memory element in which a low resistance conductive region is formed and disappeared by stored data in the first variable resistor and / or in the second variable resistor. The resistance memory device according to any one of the above.
(Appendix 16)
16. The resistance memory device according to any one of appendices 1 to 15, wherein elements are grouped and the second writing means is performed for each group.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2011-062170 for which it applied on March 22, 2011, and takes in those the indications of all here.

１ 第１の書き込み端子
２ 第２の書き込み端子
３ 第１の読み出し端子
４ 第２の読み出し端子
５ 第１の可変抵抗体
６ 第２の可変抵抗体DESCRIPTION OF SYMBOLS 1 1st write-in terminal 2 2nd write-in terminal 3 1st read-out terminal 4 2nd read-out terminal 5 1st variable resistor 6 2nd variable resistor

Claims (10)

第１の書き込み端子と、第２の書き込み端子と、第１の読み出し端子と、第２の読み出し端子と、前記第１の書き込み端子と前記第２の書き込み端子とを電気的に接続する第１の可変抵抗体と、前記第１の読み出し端子と前記第２の読み出し端子とを電気的に接続する第２の可変抵抗体とを有し、前記第１の書き込み端子と前記第２の書き込み端子との間に電圧を印加することで前記第１の可変抵抗体と前記第２の可変抵抗体の抵抗値がそれぞれ変化する抵抗記憶素子を複数有し、前記第１の可変抵抗体を低抵抗から高抵抗に変化させる書き込み手段を有し、前記書き込み手段は、単数もしくは複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の書き込み手段と、前記第１の書き込み手段による書き込みの後、複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の書き込み手段であり、さらに第２の書き込み手段での選択素子数が第１の書き込み手段での選択素子数より多く、かつ前記第２の書き込み時間が前記第１の書き込み時間より長時間であることを特徴とする抵抗記憶装置。   A first write terminal, a second write terminal, a first read terminal, a second read terminal, a first write terminal that electrically connects the first write terminal and the second write terminal. And a second variable resistor for electrically connecting the first read terminal and the second read terminal, the first write terminal and the second write terminal. A plurality of resistance memory elements that change the resistance values of the first variable resistor and the second variable resistor by applying a voltage between the first variable resistor and the first variable resistor. Writing means for changing the resistance from high to low, wherein the writing means selects one or a plurality of resistance memory elements and applies a first write voltage between the first write terminal and the second write terminal. Applying the first writing time to the first After writing by the write-in means and the first writing means, a plurality of resistance memory elements are selected, and a second write voltage is applied between the first write terminal and the second write terminal. A second writing means for applying a writing time; the number of selected elements in the second writing means is greater than the number of selected elements in the first writing means; and the second writing time is the first writing time. A resistance memory device characterized by being longer than time. 前記第２の書き込み電圧が前記第１の書き込み電圧より大きいことを特徴とする請求項１に記載の抵抗記憶装置。   The resistance memory device according to claim 1, wherein the second write voltage is larger than the first write voltage. 前記第１の書き込み手段により電圧が印加された前記抵抗記憶素子の抵抗値は前記第２の書き込み手段による書き込みの後の抵抗値より小さいことを特徴とする請求項１に記載の抵抗記憶装置。   2. The resistance memory device according to claim 1, wherein a resistance value of the resistance memory element to which a voltage is applied by the first writing unit is smaller than a resistance value after writing by the second writing unit. 前記第２の書き込み時間が１０ｎｓ〜１００μｓであることを特徴とする請求項１から３のいずれか１項に記載の抵抗記憶装置。   The resistance memory device according to claim 1, wherein the second write time is 10 ns to 100 μs. 前記第１の書き込み時間が０．１ｎｓ〜１μｓであることを特徴とする請求項１から４のいずれか１項に記載の抵抗記憶装置。   5. The resistance memory device according to claim 1, wherein the first write time is 0.1 ns to 1 μs. 6. 複数の前記抵抗記憶素子でクロスバースイッチを構成していることを特徴とする請求項１から５のいずれか１項に記載の抵抗記憶装置。   The resistance memory device according to claim 1, wherein a plurality of the resistance memory elements form a crossbar switch. 前記第１の書き込み端子と前記第３の読み出し端子とが共通であることを特徴とする請求項１から６のいずれか１項に記載の抵抗記憶装置。   7. The resistance memory device according to claim 1, wherein the first write terminal and the third read terminal are common. 前記第１の書き込み端子と前記第１の読み出し端子とが共通であり、かつ前記第２の書き込み端子と前記第２の読み出し端子とが共通であることを特徴とする請求項１から６のいずれか１項に記載の抵抗記憶装置。   7. The device according to claim 1, wherein the first write terminal and the first read terminal are common, and the second write terminal and the second read terminal are common. The resistance memory device according to claim 1. 前記第１の可変抵抗体と前記第２の可変抵抗体とが電気的に接続されていることを特徴とする請求項１から６のいずれか１項に記載の抵抗記憶装置。   7. The resistance memory device according to claim 1, wherein the first variable resistor and the second variable resistor are electrically connected. 第１の書き込み端子と、第２の書き込み端子と、第１の読み出し端子と、第２の読み出し端子と、前記第１の書き込み端子と前記第２の書き込み端子とを電気的に接続する第１の可変抵抗体と、前記第１の読み出し端子と前記第２の読み出し端子とを電気的に接続する第２の可変抵抗体とを有し、前記第１の書き込み端子と前記第２の書き込み端子との間に電圧を印加することで前記第１の可変抵抗体と前記第２の可変抵抗体の抵抗値がそれぞれ変化する抵抗記憶素子を複数有する抵抗記憶装置に対し、前記第１の可変抵抗体が低抵抗から高抵抗に変化する書き込み処理において、単数もしくは複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第１の書き込み電圧を第１の書き込み時間印加する第１の処理と、複数の抵抗記憶素子を選択し前記第１の書き込み端子と前記第２の書き込み端子との間に第２の書き込み電圧を第２の書き込み時間印加する第２の処理を順に行う書き込み方法であって、さらに第２の処理での選択素子数が第１の処理での選択素子数より多く、かつ前記第２の書き込み時間が前記第１の書き込み時間より長時間であることを特徴とする抵抗記憶装置の書き込み方法。   A first write terminal, a second write terminal, a first read terminal, a second read terminal, a first write terminal that electrically connects the first write terminal and the second write terminal. And a second variable resistor for electrically connecting the first read terminal and the second read terminal, the first write terminal and the second write terminal. For the resistance memory device having a plurality of resistance memory elements that change the resistance values of the first variable resistor and the second variable resistor by applying a voltage between the first variable resistor and the first variable resistor, In a writing process in which the body changes from a low resistance to a high resistance, one or a plurality of resistance memory elements are selected, and a first write voltage is applied between the first write terminal and the second write terminal. Apply the first write time And a writing method of sequentially performing a second process of selecting a plurality of resistance memory elements and applying a second writing voltage between the first writing terminal and the second writing terminal for a second writing time. The number of selected elements in the second process is larger than the number of selected elements in the first process, and the second write time is longer than the first write time. To write resistance memory device.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101535A (en) * 2003-08-27 2005-04-14 Nec Corp Semiconductor device
JP2007294592A (en) * 2006-04-24 2007-11-08 Sony Corp Method for driving storage device
JP2007310956A (en) * 2006-05-18 2007-11-29 Sharp Corp Semiconductor memory device
WO2007145199A1 (en) * 2006-06-13 2007-12-21 Panasonic Corporation Nonvolatile storage device, nonvolatile data recording media, nonvolatile device, and method for writing data into nonvolatile storage device
JP2008146740A (en) * 2006-12-08 2008-06-26 Sharp Corp Semiconductor memory
JP2008243263A (en) * 2007-03-26 2008-10-09 Sharp Corp Semiconductor memory device
JP2008244090A (en) * 2007-03-27 2008-10-09 Nec Corp Switching device and method for manufacturing switching device
JP2010114231A (en) * 2008-11-06 2010-05-20 Fujitsu Ltd Variable resistance element and method for manufacturing the same
JP2012216724A (en) * 2011-04-01 2012-11-08 Nec Corp Resistance storage device, and writing method thereof
JP2012216725A (en) * 2011-04-01 2012-11-08 Nec Corp Resistive storage device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4460552B2 (en) * 2006-07-04 2010-05-12 シャープ株式会社 Semiconductor memory device
JP5197448B2 (en) * 2009-03-13 2013-05-15 株式会社東芝 Resistance change memory device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101535A (en) * 2003-08-27 2005-04-14 Nec Corp Semiconductor device
JP2007294592A (en) * 2006-04-24 2007-11-08 Sony Corp Method for driving storage device
JP2007310956A (en) * 2006-05-18 2007-11-29 Sharp Corp Semiconductor memory device
WO2007145199A1 (en) * 2006-06-13 2007-12-21 Panasonic Corporation Nonvolatile storage device, nonvolatile data recording media, nonvolatile device, and method for writing data into nonvolatile storage device
JP2008146740A (en) * 2006-12-08 2008-06-26 Sharp Corp Semiconductor memory
JP2008243263A (en) * 2007-03-26 2008-10-09 Sharp Corp Semiconductor memory device
JP2008244090A (en) * 2007-03-27 2008-10-09 Nec Corp Switching device and method for manufacturing switching device
JP2010114231A (en) * 2008-11-06 2010-05-20 Fujitsu Ltd Variable resistance element and method for manufacturing the same
JP2012216724A (en) * 2011-04-01 2012-11-08 Nec Corp Resistance storage device, and writing method thereof
JP2012216725A (en) * 2011-04-01 2012-11-08 Nec Corp Resistive storage device and manufacturing method thereof

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