WO2007145199A1

WO2007145199A1 - Nonvolatile storage device, nonvolatile data recording media, nonvolatile device, and method for writing data into nonvolatile storage device

Info

Publication number: WO2007145199A1
Application number: PCT/JP2007/061791
Authority: WO
Inventors: Ken Kawai
Original assignee: Panasonic Corporation
Priority date: 2006-06-13
Filing date: 2007-06-12
Publication date: 2007-12-21

Abstract

A nonvolatile storage device includes a nonvolatile storage element (138) having a changing resistance value and a write-in device (111) for writing multi-value data into the nonvolatile storage element by changing a resistance value of the nonvolatile storage element to a resistance value corresponding to a multi-value data value which may have a plurality of values. The write-in device (111) includes: a temporary write-in device (106) for performing a temporary write-in for changing the resistance value of the nonvolatile storage element (138) from a resistance value corresponding to an old value (a value written in) to a temporary write-in resistance value existing between the resistance value corresponding to the old value and the resistance value corresponding to a new value (a value to be written in); an additional write-in device (108) for performing additional write-in for changing the resistance value of the resistance change type element (138) which has been changed to the temporary write-in resistance value, to a resistance value corresponding to the new value; and a write-in switching device (110) for performing switching between the temporary write-in device (106) and the additional write-in device (108) so as to write in multi-value data into the resistance change type element.

Description

Specification

Nonvolatile storage device, nonvolatile data recording medium, nonvolatile device, and method of writing data to nonvolatile storage device

Technical field

[0001] The present invention relates to a nonvolatile memory device. More specifically, the present invention relates to a nonvolatile memory device using a nonvolatile memory element, a nonvolatile data recording medium, a nonvolatile device, and a method for writing data to the nonvolatile memory device.

Background art

There is a flash EEPROM disclosed in Patent Document 1 as a conventional nonvolatile storage device. In this flash EEPROM, the binary data is stored in correspondence with the threshold voltage of each value memory cell of the binary data. That is, the low threshold state is assigned to the value “1” of the binary data, and the high threshold state is assigned to the value “0” of the binary data. When erasing data, electrons are extracted from the floating gate, so that data needs to be erased in batches in a predetermined unit such as a sector having a plurality of memory cells.

In the data read operation, data stored in a desired cell is read by using ONZOFF of the transistor in the memory cell and comparing the current flowing through the memory cell with a reference current.

Data write operations generally require a longer time than read operations. Therefore, in order to perform the writing operation more quickly, the flash EEPROM of Patent Document 1 performs two-stage writing. That is, first, while data is being input, temporary provisional writing is performed using short time pulses. Next, when the data input is completed, additional data storage writing is performed using a long pulse. According to the operation, the storability of the data written by the temporary writing only needs to be such that the data can be temporarily maintained until additional writing is performed even if it is not guaranteed for a long time. Therefore, the temporary writing speed can be increased, and the data writing speed is apparently improved. In the additional write operation, the memory cell is reduced to a level that can guarantee long-term data storage at the timing when the system load decreases. The threshold voltage is changed.

FIG. 18 is a graph schematically showing the relationship between the threshold voltage V and the write time Tp in the flash EEPROM. FIG. 19 is a diagram showing threshold voltage distributions in the erase state and the write state (temporary write state and additional write state) of the flash EEPROM. As shown in FIGS. 18 and 19, when the read voltage Vr is 4 V, the minimum write time T p (= lms) necessary for the initial read to operate normally is set as the temporary write time. Temporary writing is performed in an order of magnitude shorter than the normal writing time Tp (= 10 ms) considering reliability assurance. Due to the temporary write, electrons are injected into the floating gate, and the threshold value of the memory cell increases in the positive direction according to the temporary write time Tp (= lms). After temporary writing, the difference between the threshold voltage and the read voltage Vr is the margin necessary for temporary storage until the additional write operation (initial read operation margin Ml).

[0004] When temporary writing is completed for a series of data, additional writing is performed. In the additional write operation, the write time Tp (= 9 ms) is set as the additional write time in consideration of normal reliability assurance. After additional writing, the difference between the threshold voltage and the read voltage Vr becomes the margin (reliability guarantee margin M2) necessary to guarantee long-term storage (eg, 10 years)! / .

[0005] By performing the two-stage writing in this way, data is written in a seemingly shorter writing time (about lms) than a normal writing time (about 10 ms). However, the time required for temporary writing (approximately lms) is much longer than the read Z write time (20-60ns) of a general volatile storage device (DRAM, etc.). Therefore, when writing to the flash EEPROM, a nota memory is provided to temporarily store the data.

FIG. 20 is a block diagram showing a configuration of a memory system including a semiconductor memory device using a flash EEPROM. As shown in FIG. 20, in order to shorten the time required for rewriting from the host device, the memory system 700 includes a semiconductor storage device 701, a flash EEPRO M interface circuit 702, a buffer memory 703 (DRAM), and a buffer memory And an interface circuit 704. When a rewrite command having a higher-level device capability is sent, the data is once written into the buffer memory 703 via the notch memory interface circuit 704 at a high speed. When the data rewrite command for the higher-level device is completed, first, the semiconductor memory device 701 is erased in a predetermined unit. Next, the data stored in the nother memory 703 is written at high speed by the temporary write operation via the buffer memory interface circuit 704 and the flash EEPROM interface circuit 702. Finally, when the semiconductor memory device 701 is deactivated, additional write to the semiconductor memory device 701 is performed in response to an additional write command from the host device.

[0006] When data in the buffer memory 703 is read in response to a read instruction from the host device, the data is read through the nother memory interface circuit 704. Similarly, when the semiconductor memory device 701 is read, data is read via the flash EEPROM interface circuit 702.

As a nonvolatile memory device developed in recent years, there is a resistance change type memory device disclosed in Patent Document 2. This resistance change memory device uses, as a memory cell, a resistance change element using a resistance change material such as an oxide having a base bumite structure containing manganese. The resistance change material changes greatly in resistance value by application of a positive or negative voltage pulse. Utilizing powerful physical properties, data can be converted into element resistance values and stored to operate as a storage device.

FIG. 21 is a diagram showing the relationship between the resistance value of the variable resistance material disclosed in Patent Document 2 and the number (length) of applied voltage pulses. As shown in the figure, the resistance value of the variable resistance material changes greatly at the start of voltage pulse application, and the amount of change gradually decreases as the number of pulses increases.

Patent Document 1: Japanese Patent Laid-Open No. 2004-253093

Patent Document 2: JP 2004-185755 A

Disclosure of the invention

Problems to be solved by the invention

[0008] The configuration of the conventional flash EEPROM still has a problem that the data rewrite speed is still slow. In addition, the circuit area is reduced due to the need for a nother memory. There was also a problem that it was difficult to achieve a high integration density. In addition, since a buffer memory interface circuit and the like are required, the configuration of the apparatus becomes complicated and the manufacturing cost increases.

[0009] The present invention has been made to solve the above-described problems. A nonvolatile memory device, a resistance variable type, and the like, which can reduce the circuit area and simplify the device configuration with high data writing speed. For the purpose of providing data recording media, variable resistance devices, and methods for writing data to variable resistance elements! Speak.

Means for solving the problem

[0010] The inventors diligently studied for the purpose of improving the operation speed and simplifying the circuit design in the nonvolatile memory device. As a result, it has been clarified that the write speed can be dramatically improved by using two steps of writing, temporary writing and additional writing, using a resistance variable element. According to the powerful configuration, it was expected that it would be possible to write at a speed comparable to that of a general volatile storage device (DRAM, etc.), and a configuration without a buffer memory could be realized. Such a configuration is very effective for downsizing and cost reduction of the device because the circuit can be miniaturized and simplified. That is, in order to solve the above-described problem, a nonvolatile memory device according to the present invention includes a nonvolatile memory element whose resistance value changes and data that can take a plurality of values for the resistance value of the nonvolatile memory element. A non-volatile memory device having a writing device for writing the multi-value data into the non-volatile memory element by changing to a resistance value corresponding to the value data value, wherein the writing device is written When the value of multi-value data is called the old value and the value of multi-value data to be written is called the new value, the resistance value of the nonvolatile memory element corresponds to the old value, such as the resistance value corresponding to the old value. A temporary writing device for performing temporary writing to be changed to a temporary writing resistance value between the resistance value corresponding to the new value and the resistance value corresponding to the new value, and the nonvolatile device that has been changed to the temporary writing resistance value. The additional writing device for performing additional writing to change the resistance value of the volatile memory element to the resistance value corresponding to the new value, the temporary writing device, and the additional writing device are switched to duplicate the nonvolatile memory element. And a write switching device for writing value data. With such a configuration, the data writing speed is increased, and the circuit area can be reduced and the device configuration can be simplified.

In the above nonvolatile memory device, the difference between the resistance value corresponding to the old value and the temporary write resistance value is the difference between the resistance value corresponding to the old value and the resistance value corresponding to the new value. It may be 20% or more and 98% or less of the difference.

[0012] With such a configuration, a suitable temporary write resistance value can be set according to the ratio with the resistance value corresponding to the new value.

In the non-volatile memory device, the non-volatile memory element has a resistance value that changes according to a cumulative amount of energy input in a predetermined mode, and the writing device inputs energy in the predetermined mode. Accordingly, the resistance value of the nonvolatile memory element may be changed.

[0013] With such a configuration, by controlling the cumulative amount of energy input in a predetermined mode, the resistance value of the nonvolatile memory element can be changed, and multi-value data can be stored in the nonvolatile memory element. .

In the non-volatile memory device, the cumulative amount of energy input in the predetermined mode is a cumulative voltage pulse application amount, and the writing device applies a voltage pulse to the non-volatile memory element. The resistance value may be changed.

[0014] With such a configuration, by controlling the cumulative application amount of voltage noise, the resistance value of the nonvolatile memory element can be changed, and multi-value data can be stored in the nonvolatile memory element.

In the non-volatile memory device, the resistance value of the non-volatile memory element may change so as to be saturated with respect to a cumulative amount of energy input in a predetermined mode.

[0015] With such a configuration, the resistance value changes greatly at the start of energy input. Using this large amount of change, the resistance value is changed to a level necessary for temporary retention of data. Subsequent additional writes will change the resistance to a level sufficient for long-term data storage. Therefore, it is possible to realize a storage device with high apparent writing speed and high reliability in terms of data storage. [0016] In the above nonvolatile memory device, the width of a voltage pulse applied to perform the temporary writing may be 60 ns or less! /.

In such a configuration, by reducing the width of the applied voltage pulse below a predetermined value, it is possible to more reliably reduce the circuit area and simplify the device configuration.

[0018] In the above nonvolatile memory device, the width of the voltage pulse applied to perform the temporary writing may be equal to or less than the width of the voltage pulse applied to perform the reading.

In such a configuration, since the speed of temporary writing is the same as or lower than the speed of reading, buffer memory is not necessary when reading and writing data between nonvolatile storage devices.

[0020] In addition, a nonvolatile device of the present invention includes the above-described nonvolatile memory device, a control device, and a volatile memory device, and the width of a voltage pulse applied to perform the temporary writing is It is set to be equal to or smaller than the width of the read pulse of the volatile memory device.

In such a configuration, since the speed of temporary writing to the nonvolatile memory device is the same as or lower than the speed of reading from the volatile memory device, the buffer memory inside the resistance variable device can be reduced.

[0022] In the nonvolatile memory device, the width force of the voltage pulse applied to perform the temporary writing may be shorter than the width of the voltage pulse applied to perform the additional writing. Further, a voltage pulse applied to perform the temporary write may be equal to a voltage pulse applied to perform the additional write.

In such a configuration, temporary writing can be performed at higher speed by shortening the pulse width for temporary writing. In addition, additional writing can be performed over time, data can be stored for a long time, and the reliability of the storage device is improved.

[0024] In the nonvolatile memory device, a voltage force of a voltage pulse applied to perform the temporary writing may be higher than a voltage pulse voltage applied to perform the additional writing. Further, the width force of the voltage pulse applied to perform the temporary writing may be equal to the width of the voltage pulse applied to perform the additional writing.

[0025] In such a configuration, the voltage of the voltage Norse for temporary writing is increased, so that the temporary writing is performed. Can be performed at a higher speed. In addition, the power consumption can be reduced by lowering the voltage for additional writing.

[0026] Further, a nonvolatile data recording medium of the present invention includes the nonvolatile storage device and a control device, and the control device switches the temporary writing device and the additional writing device so as to switch between the temporary writing device and the additional writing device. Control the switching device.

[0027] With such a configuration, a resistance variable data recording medium can be realized as a high-speed and small non-volatile data recording medium.

The nonvolatile memory device includes a memory cell including a memory cell including the nonvolatile memory element, a memory cell array having a plurality of memory cell sections each having a plurality of the memory cells, and one flag nonvolatile for each memory cell section. A non-volatile memory element belonging to the memory cell section, which has a memory element, and that is written to the non-volatile memory element for flag corresponding to the temporary write to the non-volatile memory element belonging to the memory cell section In addition, a temporary write flag area may be provided in which the fact is written in the flag non-volatile memory element corresponding to the additional write. The nonvolatile data recording medium includes the nonvolatile memory device and a control device, and the control device includes a nonvolatile memory element in which the additional writing is not completed for each of the memory cell sections. Whether the memory cell section is the additional write target memory cell section is determined based on the value of the temporary write flag area, and the additional write target memory is written using the data written to the additional write target memory cell section. Additional writing may be performed on the nonvolatile memory element belonging to the cell section.

In such a configuration, based on the value of the temporary write flag area, it is possible to easily determine whether there is a memory cell in each memory cell section after the additional write is completed. Therefore, it is possible to easily determine whether or not it is necessary to perform additional writing to the memory cell section.

[0028] The nonvolatile storage device further includes a write data storage device that temporarily records data written in at least a part of the nonvolatile storage elements belonging to the memory cell section for additional writing. May be. In addition, the nonvolatile data recording A medium includes the nonvolatile memory device and a control device, and the control device includes a nonvolatile memory element that completes the additional writing for each of the memory cell sections. Whether or not the memory cell section is the additional write target memory cell section is determined based on the value of the temporary write flag area, and at least a part of the data of the additional write target memory cell section is stored in the write data storage device. Further, additional writing may be performed on the non-volatile storage element belonging to the additional write target memory cell section using data stored in the write data storage device.

[0029] With such a configuration, additional write data can be temporarily stored in the write data storage device. Therefore, the additional write operation can be performed efficiently.

The nonvolatile storage device includes an additional write sequence control circuit that controls the write switching device so as to switch between the temporary writing device and the additional writing device, and the additional write sequence control circuit is input from an external device. The write switching device may be controlled to perform the additional writing when the control signal indicates that a non-volatile storage device is not selected.

In such a configuration, an additional write operation is performed autonomously when data input of external device power is stopped. Therefore, the control by the external control device is simplified, and the convenience for the user (such as a manufacturer that manufactures a system using a nonvolatile storage device) is improved. A nonvolatile data recording medium of the present invention includes the nonvolatile storage device and a control device, and the control device is the external device.

Even in such a configuration, when data input by an external device is stopped, an additional write operation is performed autonomously. Therefore, control by an external control device is simplified, and a data recording medium capable of executing additional writing with a simple configuration can be obtained.

[0030] The nonvolatile memory device has a function of outputting an additional write execution flag signal for prohibiting input of write data from an external device when writing by the additional write device is performed. Also good. The resistance change type data recording medium includes the nonvolatile memory device and a control device, and the additional write execution flag signal output from the nonvolatile memory device indicates an input prohibited state. The control device may stop data input to the nonvolatile memory device. In such a configuration, when an additional write operation is performed, an external control device or the like can easily determine that fact, so that a malfunction can be prevented.

In addition, the nonvolatile data recording medium of the present invention includes a control device, a nonvolatile storage element whose resistance value changes, and multi-value data which is data that can take a plurality of resistance values of the nonvolatile storage element. A non-volatile data recording medium having a writing device for writing the multi-value data to the non-volatile memory element by changing to a resistance value corresponding to the value, wherein the value of the multi-value data being written is When the value of the multi-value data to be written is called a new value, the control device updates the value stored in the nonvolatile memory element from the old value to the new value. Write so that the resistance value of the element is changed from the resistance value corresponding to the old value to the temporary write resistance value between the resistance value corresponding to the old value and the resistance value corresponding to the new value. The controller then changes the resistance value of the nonvolatile memory element that has been changed to the temporary write resistance value to a resistance value corresponding to the new value. Control the writing device to do.

In such a configuration, since the data writing speed is increased, the circuit area can be reduced and the device configuration can be simplified.

In the nonvolatile data recording medium, the control device controls the writing device so as to temporarily write the plurality of nonvolatile storage elements, and then the control device includes the plurality of nonvolatile storage elements. The writing device may be controlled to perform additional writing. The data writing method to the nonvolatile memory device of the present invention is a data writing method to the nonvolatile memory device including a plurality of nonvolatile memory elements, and corresponds to each value of the multi-value data to be written. When the resistance value of the nonvolatile memory element is set, the value of the written multi-value data is referred to as an old value, and the value of the multi-value data to be written is referred to as a new value. When the old value written in the element is updated to the new value, the resistance value of each of the nonvolatile memory elements is changed from the resistance value corresponding to the old value to the resistance value corresponding to the old value. Temporary writing is performed to change to a temporary writing resistance value between the resistance value corresponding to the new value, and then the resistance value of each nonvolatile memory element is determined from the temporary writing resistance value. Additional writing may be performed to change to a resistance value corresponding to the new value.

In such a configuration, since the temporary writing is first performed on the data to be written, and then additional writing is performed, the apparent writing speed can be improved.

The nonvolatile memory device may further include an additional write sequence control device that controls the writing device to perform the additional writing.

[0032] With such a configuration, additional writing is autonomously performed by the additional writing sequence control device, so that convenience for the user (higher system) is improved.

[0033] In the non-volatile storage device, the additional write sequence control device may be configured to control the writing device to perform the additional writing at regular intervals.

In such a configuration, additional write operations occur sporadically over a relatively long period of time (1 day, 1 week, 1 year, etc.), so apparently the additional write time has little impact on system performance. That is, normally, data is written at high speed only by temporary writing, so that a nonvolatile memory device capable of high-speed response is realized. On the other hand, since the data storability is improved by the additional writing, a highly reliable nonvolatile storage device is realized.

In the non-volatile memory device, the additional write sequence control device may include a timer that outputs a signal for performing the write operation for a predetermined time in a period of the predetermined period.

With a powerful configuration, it is possible to adjust the timing for autonomously performing an additional write operation using a timer.

In the non-volatile memory device, the additional write sequence control device may be configured to control the writing device to perform the additional writing when the power is turned off.

In such a configuration, when the power is turned off, additional writing is completed for the memory cell in which all data has been recorded, and the data is reliably saved even when the power is turned off. Will be. On the other hand, no additional writing is performed while the power is on (during normal operation), and all data writing is handled by temporary writing. So look Overwriting speed becomes faster. In other words, since no additional writing is performed during normal operation, the additional writing operation does not substantially affect the performance of the entire system.

In the non-volatile memory device, the additional write sequence control device may be configured to control the write device to perform the additional write when a power supply is turned on.

In such a configuration, when the power is turned on, additional writing is performed on all the memory cells including the memory cell in which the writing state is deteriorated, so that data storage and reading accuracy are improved. On the other hand, after the power is turned on (during normal operation), no additional writing is performed, and all data writing is processed by temporary writing. Therefore, the apparent writing speed is increased. In other words, since no additional writing is performed during normal operation, the additional writing operation does not substantially affect the performance of the entire system.

In the nonvolatile memory device, the additional write sequence control device controls the writing device to perform the additional writing at regular intervals, and controls the writing device to perform the additional writing when the power is turned off. It may be configured to control.

In such a configuration, periodic additional writing using a timer and additional writing when the power is turned off are used in combination. Since additional writing is performed periodically during normal operation, data deterioration can be prevented from occurring in memory cells that do not happen to be written with data while the power is on. In addition, additional writing is performed for all memory cells when the power is turned off, so additional memory writing can be performed before the power is turned off even for memory cells that have been temporarily written after the last periodic additional writing. State. Therefore, it is possible to reliably prevent the data storage state from deteriorating below the allowable limit while the power is off.

In the non-volatile memory device, the additional write sequence control device may include a timer.

The timing to perform an additional write operation autonomously using a timer with a powerful configuration Can be adjusted.

In the nonvolatile memory device, the certain period is set so that the difference between the resistance value of the nonvolatile memory element in the temporarily written state and the resistance value of the reference resistance after the certain period is equal to or greater than a read guarantee margin. May be.

In such a configuration, after the additional writing is completed, the resistance value and the timing of the temporary writing to be performed next time are set before the storage state of the data temporarily written first deteriorates, and the temporary writing is performed. Sufficient reliability can be ensured for the preservation of data in the state.

In the non-volatile memory device, the additional write sequence control device executes additional write for prohibiting input of write data from an external device while controlling the write device to perform the additional write. It may be configured to output a middle flag signal.

The non-volatile memory device further includes a memory cell array including the non-volatile memory element, a memory cell array including a plurality of memory cell sections including the plurality of memory cells, and a temporary write flag region, and the temporary write flag The area includes one flag nonvolatile memory element for each memory cell section, and when the temporary write is performed to the nonvolatile memory element belonging to the memory cell section, the corresponding flag nonvolatile memory element When the additional writing is performed to the nonvolatile memory element belonging to the memory cell section when the fact is written to the memory element, the fact is written to the corresponding flag nonvolatile memory element. Also good. In such a configuration, based on the value of the temporary write flag area, it is possible to easily determine whether there is a memory cell in each memory cell section after the additional write is completed. Therefore, it is possible to easily determine whether or not it is necessary to perform additional writing to the memory cell section.

In the nonvolatile memory device, the additional write sequence control device is configured to control the writing device to perform the additional write based on the information written in the temporary write flag area. Moyo!

In such a configuration, a determination is made based on the value of the temporary write flag area, and additional writing is performed. Since additional writing is performed only to the memory cell section that needs to be included, the efficiency of the additional writing operation is improved.

The above object, other objects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments with reference to the accompanying drawings.

The invention's effect

[0035] The present invention has the above-described configuration and has the following effects. In other words, non-volatile storage devices, non-volatile data recording media, non-volatile devices, and methods for writing data to non-volatile storage devices that can reduce the circuit area that speeds up data writing and simplify the device configuration are provided. It becomes possible to do.

Brief Description of Drawings

[0036] FIG. 1 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a resistance change type data recording medium and a resistance change type device according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram showing a schematic configuration of the memory cell array in the first embodiment of the present invention.

FIG. 4 is a diagram showing a schematic configuration of a circuit for writing and reading data to and from a memory cell in the first embodiment of the present invention.

FIG. 5 is a graph schematically showing the relationship between the length (Tp) of the applied voltage pulse and the absolute value (ΔR) of the change amount of the resistance value indicated by the resistance change material.

FIG. 6 is a flowchart showing an outline of a temporary write operation in the first embodiment of the present invention.

FIG. 7 is a flowchart showing an outline of an additional write operation in the first embodiment of the present invention.

[FIG. 8] FIG. 8 is a diagram showing a relationship between a resistance application time and a resistance value in an example of the present invention.

FIG. 9 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 2 of the present invention. FIG. 10 is a timing chart showing a write operation by the resistance change memory device according to the second embodiment of the present invention.

FIG. 11 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 3 of the present invention.

FIG. 12 is a diagram showing an example of a change with time of the resistance value of the resistance variable element.

FIG. 13 is a flowchart showing an outline of an additional write operation in the third embodiment of the present invention.

FIG. 14 is a diagram showing a timing of an additional write operation enable signal AP and an additional write execution flag FG.

FIG. 15 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 4 of the present invention.

FIG. 16 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 5 of the present invention.

FIG. 17 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 6 of the present invention.

[FIG. 18] FIG. 18 is a graph schematically showing the relationship between the threshold voltage V and the write time Tp in the flash EEPROM.

FIG. 19 is a diagram showing threshold values and value voltage distributions in the erase state and the write state (temporary write state and additional write state) of the flash EEPROM.

FIG. 20 is a block diagram showing a configuration of a memory system including a semiconductor memory device using a flash EEPROM.

FIG. 21 is a diagram showing the relationship between the resistance value of the variable resistance material disclosed in Patent Document 2 and the number (length) of applied voltage pulses.

Explanation of symbols

100 resistance change memory

102 Control circuit

104 Input data latch

106 Short pulse generator for temporary writing 108 Long pulse generator for additional writing

110 Pulse switching circuit for writing

111 Writing device

112 Write circuit

114 row decoder

116 Temporary write flag area

118 Memory cell array

120 sense amplifier

122 Output data latch

130 bit line

132 Source line

134 Word line

136 Select transistor

138 Resistance change element

139 Memory Senore

140 Voltage application circuit

142 Voltage application circuit

144 NMOS transistor

146 Comparator

148 Reference resistance

170 Resistance change data recording media

180 Controller

190 system

192 Volatile storage devices

194 Resistance change device

200 Resistance change memory

202 Control circuit

204 Input data latch 206 Short pulse generator for temporary writing

208 Long pulse generator for additional writing

210 Pulse switching circuit for writing

211 Writing device

212 Write circuit

214 Roude: π-da

216 Temporary write flag area

218 Memory cell array

220 sense amplifier

222 Output data latch

224 Additional write sequence control circuit

300 resistance change memory

302 Control circuit

304 Input data latch

306 Short pulse generator for temporary writing

308 Long pulse generator for additional writing

310 Pulse switching circuit for writing

311 Writing device

312 Write circuit

314 Roude: Dada

316 Temporary write flag area

318 memory cell array

320 sense amplifier

322 Output data latch

324 Additional write sequence control circuit

326 Additional write timer

400 resistance change memory

402 Control circuit 404 Input data latch

406 Short pulse generator for temporary writing

408 Long Norse Generation Circuit for Additional Writing

410 Pulse switching circuit for writing

411 writing device

412 Write circuit

414 row decoder

416 Temporary write flag area

418 Memory cell array

420 sense amplifier

422 Output data latch

424 Power-down sequence control circuit

500 resistance change memory

502 Control circuit

504 Input data latch

506 —Short pulse generator for time writing

508 Additional writing length generation circuit

510 Pulse switching circuit for writing

511 Writing device

512 Write circuit

514 row decoder

516 Temporary write flag area

518 Memory cell array

520 sense amplifier

522 Output data latch

524 Power-on sequence control circuit

600 resistance change memory

602 control circuit 604 Input data latch

606 Short pulse generator for temporary writing

608 Long pulse generator for additional writing

610 Write pulse switching circuit

611 writing device

612 writing circuit

614 Roude: π-da

616 Temporary write flag area

618 memory cell array

620 sense amplifier

622 Output data latch

624 Additional write sequence control circuit

626 Additional write timer

628 Power-down sequence control circuit

700 memory system

701 Semiconductor memory device

702 Flash EEPROM interface circuit

703 Nota memory

704 Interface circuit for buffer memory

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(First embodiment)

[Device configuration]

FIG. 1 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 1 of the present invention. Hereinafter, an outline of the configuration and operation of the resistance change storage device according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, the resistance change storage device 100 (nonvolatile storage device) of the present embodiment includes a control circuit 102, an input data latch 104, and a temporary write short pulse generation circuit 106. Additional write long pulse generation circuit 108, write pulse switching circuit 110, write circuit 112, row decoder 114, temporary write flag area 116, memory cell array 118, sense amplifier 120, and output data latch 122.

[0040] The control circuit 102 receives a command (chip select CS, external control signal CTL, address AD, write pulse WP) via an external control device 180 (described later) via a pin, etc. Control signals (address, write mode, timing signal, etc.) are output to control each part of the resistance change memory device 100. Note that the number of control circuits 102 is not necessarily one. For example, distributed control may be performed by a plurality of control circuits specialized for each function performed by the control circuit.

The input data latch 104 includes an internal control signal from the control circuit 102 and a control device 180.

An input data signal input from a data input terminal DIN (described later) is received, the data is latched, and the input data signal is output to the write circuit 112 as a write data signal at a predetermined timing.

[0042] The temporary write short pulse generation circuit 106 (the time write device) receives the internal control signal from the control circuit 102, and when the internal control signal indicates the temporary write mode, the temporary write short pulse ( (Voltage voltage) is output, otherwise the output is stopped to save power consumption.

[0043] The additional write long pulse generation circuit 108 (additional write device) receives the internal control signal from the control circuit 102, and when the internal control signal indicates the additional write mode, the additional write long pulse (voltage Output), otherwise the output is stopped to save power consumption.

[0044] The write pulse switching circuit 110 (write switching device) is configured to receive the outputs of both the temporary write short pulse generation circuit 106 and the additional write long pulse generation circuit 108. Is electrically connected to the output terminal. The write pulse switching circuit 110 receives the internal control signal from the control circuit 102, and when the internal control signal indicates the temporary write mode, selects the output of the temporary write short pulse generation circuit 106 and outputs it to the write circuit 112. When the internal control signal indicates the additional write mode, the output of the additional write long pulse generation circuit 108 is selected. And output to the write circuit 112.

In the present embodiment, the writing device 111 includes the temporary writing short pulse generation circuit 106, the additional writing long pulse generation circuit 108, and the writing pulse switching circuit 110.

The memory cell array 118 includes a plurality of bit lines and a plurality of word lines that are orthogonal to each other, and has a memory cell that also has a transistor and a resistance variable element force at the intersection of the bit line and the word line. In the resistance variable element, the resistance state (resistance value) is largely changed by an applied voltage pulse. The resistance change storage device 100 stores data using the transition of the resistance state. The detailed configuration of the memory cell array 118 will be described later.

The temporary write flag area 116 has the same configuration as that of the memory cell array 118 and shares a word line with the memory cell array 118. The temporary write flag area 116 includes one memory cell (flag variable resistance element) per sector (memory cell section) of the memory cell array 118. In the present embodiment, a sector is a unit in which one or a plurality of word lines of the memory cell array 118 are collected. That is, cells connected to one word line belong to the same sector.

The row decoder 114 is connected to each word line of the memory cell array 118. The row decoder 114 receives the internal control signal from the control circuit 102, selects a word line corresponding to the address of the memory cell array 118 to be written or read and the temporary write flag area 1 16 at a predetermined timing, and Activate.

Based on the internal control signal received from the control circuit 102, the sense amplifier 120 detects (reads) and amplifies the data signal (bit line data) from the memory cell array 118, and this read data signal (at a predetermined timing) Read data signal) to output data latch 122.

[0048] The output data latch 122 latches data based on the internal control signal received from the control circuit 102 and the read data signal received from the sense amplifier 120, and switches the output destination at a predetermined timing. A read data signal is output to the control device 18 0 (described later) or the write circuit 112 via DOUT. Ie When the internal control signal indicates the data read mode, the read data signal is output as an output data signal to the data output terminal DOUT, and when the internal control signal indicates the additional write mode, the read data signal is written. Write to circuit 112 and output as data signal.

The write circuit 112 is connected to each bit line of the memory cell array 118. The write circuit 112 receives the internal control signal from the control circuit 102 and writes to the memory cell at a predetermined timing. That is, when the internal control signal indicates the temporary write mode, the corresponding bit line is selected based on the write data signal received from the input data latch 104 and the address information included in the internal control signal, and the write data is written. The temporary write short pulse input from the read pulse switching circuit 110 is applied and temporarily written to a predetermined address in the data memory cell array 118 (described later). At the same time, “0” is written to the memory cell in the temporary write flag area 116 corresponding to the sector of the address where the data is written, and the flag information power is set to the “H” level. When the additional write mode is indicated, the corresponding bit line is selected based on the write data signal received from the output data latch 122 and the address information included in the internal control signal, and is input from the write pulse switching circuit 110. Is added to the data memory cell array 118 (described later), and if the additional writing is completed for the memory cell included in the sector, the sector is supported. “1” is written to the temporary write flag area 116 to be set, and the flag information is set to the “L” level. It is configured so as to apply a voltage pulse simultaneously to the cell, Ru.

FIG. 2 is a block diagram showing a schematic configuration of the resistance change type data recording medium and resistance change type device according to the first embodiment of the present invention. Hereinafter, the configuration and operation of the resistance change type data recording medium 170 and the resistance change type device 194 of this embodiment will be described with reference to FIG.

As shown in FIG. 2, the resistance change type data recording medium 170 includes a resistance change type storage device 100 and a control device 180. Further, the resistance change type device 194 includes a resistance change type data recording medium 170, a system 190 (for example, a mobile computer, a mobile phone, etc.) The system 190 includes a volatile storage device 192 (for example, DRAM) therein. The control device 180 receives the input data signal and the address signal from the system 190 and, at a predetermined timing, converts the chip select CS, the external control signal CTL, the address AD, the write pulse WP, and the input data signal into a resistance change type. Output to storage device 100. In addition, the control device 180 receives the output data signal from the resistance change storage device 100 and outputs the output data signal to the system 190. The value of the temporary write flag area 116 is determined by the control device 18 0 via the sense amplifier 120 and the output data latch 122 so that the control device 180 can detect the presence of temporarily written data in the memory cell array 118. Is output. The system 190 uses the volatile storage device 192 as a temporary storage means. In other words, write data to the resistance change storage device 100 and data read from the resistance change storage device 100 are temporarily stored in the volatile storage device 192, and data read from the volatile storage device 192 is stored in the resistance change storage device 192. Temporarily writes to storage device 100 at high speed. After that, when the resistance change type data storage medium 170 is not selected, the control device 180 performs additional writing for long-term storage in accordance with the signal of the temporary write flag area power in accordance with the signal of the temporary write flag area.

FIG. 3 is an equivalent circuit diagram showing a schematic configuration of the memory cell array in the first embodiment of the present invention. In this embodiment, the memory cell array 118 is a 1T1R type (one transistor, one resistance change element type), and bit lines 130 formed in parallel to each other at a predetermined interval and parallel to the bit lines 130 at a predetermined interval. A source line 132 formed and a bit line 130 and a word line 134 formed in parallel with each other at a predetermined interval so as to be orthogonal to the source line 132 are provided. The bit lines 130 and the source lines 132 are alternately arranged one by one, and the bit lines 130 and the source lines 132 are connected in series at each intersection of the bit lines 130 and the word lines 134. One select transistor 136 and one variable resistance element 138 are electrically connected to each other through a memory cell 139. The bit line 130 is the drain electrode of the selection transistor 1 36, the source electrode of the selection transistor 136 is one end of the resistance change element 138, the other end of the resistance change element 138 is the source line 132, and the gate electrode of the selection transistor 136 Are electrically connected to the word lines 134, respectively. The row decoder 114 is connected to each word line 134, and receives an internal control signal from the control circuit 102. Based on the above, the word line 134 to be accessed is selected and a voltage is applied (activated), and the selection transistor 136 is turned on. When writing and reading data, the target variable resistance element 1 38 is identified by the combination of the bit line 130, the source line 132, and the word line 134, and the bit line 130 and the source line 132 are A voltage is applied or the current flowing between them is detected. Data is stored in the memory cell 139 in association with the resistance value of the resistance variable element 138, and the low resistance (LR: about 50 kQ to 62 kQ) state is high in the binary data “0” value. The resistance (HR: approx. 1Μ to 2Μ Ω) state is assigned to the “1” value of the binary data.

The resistance change element 138 is configured by interposing a resistance change layer between electrode materials such as Pt. Various materials can be used for the variable resistance material of the variable resistance element 138 (material for the variable resistance layer). Iron oxide laminated compounds (Fe 2 O 3 / Ye 2 O and ZnFe 2 O 3 / Ye)

2 3 3 4 2 4 3

Transition metal oxides such as O 2) are particularly preferably used (see Examples). Variable resistance element

Four

138, for example, when the existing value (old value) is "1" and in a high resistance state, apply negative noise (eg, voltage: 3.3V, noise width: 120ns). The resistance value changes from the high resistance state to the low resistance state, and a new value (new value) “0” is written. In addition, when the existing value (old value) is "0" and in a low resistance state, applying a positive pulse (eg, voltage: + 3.3V, pulse width: 120ns) reduces the resistance. The resistance value changes from the state to the high resistance state, and a new value (new value) “1” is written. In the resistance change element, the polarity of the voltage pulse (low resistance pulse) applied to make the transition from the high resistance state to the low resistance state and the transition from the low resistance state to the high resistance state are required. The polarity of the voltage pulse (high resistance pulse) to be applied is the same or different. The configuration of this embodiment can be applied to the case where the polarity of the low resistance pulse and the polarity of the high resistance pulse are equal U. This is especially effective when the polarity is different.

FIG. 4 is a diagram showing a schematic configuration of a circuit that performs writing and reading of data with respect to the memory cell in the first embodiment of the present invention. Although not shown in FIG. 1, as shown in FIG. 4, the write circuit 112 includes a voltage application circuit 140 and a voltage application circuit 142, and the sense amplifier 120 includes a comparator 146 and a reference resistor 148. Memory cell An NMOS transistor 144 is disposed between the source line 132 of the array 118 and the voltage application circuit 142 of the write circuit 112. In the present embodiment, the write circuit 112 includes the same number of voltage application circuits 140 and voltage application circuits as the number of memory cells to which voltage pulses are applied simultaneously (the number of memory cells corresponding to one address: for example, 16). 142. In the present embodiment, the NMOS transistor 144 is provided at the peripheral edge of the memory cell array 118. One NMOS transistor 144 may be provided for a plurality of source lines 132, and one NMOS transistor 144 may be provided for one source line 132! /!

The temporary write short pulse generation circuit 106 and the additional write long pulse generation circuit 108 are selectively connected to the write circuit 112 by the write pulse switching circuit 110. The pulse output from the write pulse switching circuit 110 is input to the voltage application circuit 140 and the voltage application circuit 142. When the internal control signal received by the write circuit 112 is in the temporary write mode and the additional write mode, the voltage application circuit 140 is selected according to the data to be written while the input pulse is H. The high voltage (+ 3.3V) and 0V are switched and output to the bit line 130, and the voltage application circuit 142 is selected according to the data to be written while the input noise is H. Switch between 0V and high voltage (+ 3.3V) and output to source line 132 corresponding to bit line 130. On the other hand, when the internal control signal received by the write circuit 112 is in the read mode, the voltage application circuit 140 sets its output terminal to a high impedance state (non-conductive state), and the voltage application circuit 142 supplies 0 V to the source line 132. Is output.

The output terminal of the voltage application circuit 140 is connected to one end of the bit line 130 of the memory cell array 118. The other end of the bit line 130 is connected to the input terminal of the comparator 146 included in the sense amplifier 120. A reference resistor 148 is connected to the other input terminal of the comparator 146. On the other hand, the output terminal of the voltage application circuit 142 is connected to one end of the source line 132 via the NMOS transistor 144. A select transistor 136 and a resistance variable element 138 are connected in series between the bit line 130 and the source line 132 at each intersection of the bit line 130 and the word line 134. The gate of the selection transistor 136 is connected to the word line 134. The gate of the NMOS transistor 144 is connected to the row decoder 114 (see FIG. 1). [Voltage pulse and resistance change of variable resistance material]

FIG. 5 is a graph schematically showing the relationship between the length (Tp) of the applied voltage pulse and the absolute value of the change amount of the resistance value indicated by the resistance change material (AR: hereinafter simply referred to as the change amount). There are positive and negative voltage pulses, but the same change pattern is shown in either case. In other words, regardless of whether positive or negative noise is applied, the voltage pulse application time becomes longer and the amount of change in resistance value saturates (asymptotically) to a predetermined value.

As shown in FIG. 5, the amount of change (AR) in the resistance value indicated by the resistance change material increases as the applied voltage pulse becomes longer (according to the cumulative application amount of the voltage pulse). When the voltage pulse length (Tp) exceeds Tpc, AR begins to increase. The increase rate (slope) exceeds a very large Tpl at the start of increase (from Tpc to Tpl), and the increase rate (slope) decreases as Tp increases. In other words, the resistance value changes so as to saturate with respect to the cumulative applied voltage voltage. In the present embodiment, this change pattern is used to perform two-step writing to shorten the apparent writing time.

That is, a voltage pulse of Tpl (for example, 40 ns) is first applied as a short pulse. By applying a short pulse, the resistance value (resistance value corresponding to the old value) changes by AR1 to an intermediate resistance value (temporary writing resistance value), and data is temporarily written. The length of Tp 1 is preferably adjusted so that ARl is 20% or more and 98% or less of the AR target value (AR2). The target value of AR is appropriately adjusted according to the data retention characteristics of the resistance variable element. For example, if the target value of the data retention time is 10 years, the AR target value is set so that the written data can be read with sufficient accuracy even after 10 years.

[0059] The resistance value changes with time in a direction to cancel the written change. In view of this, it is preferable that the change in AR1 is sufficient to ensure the preservation of data for at least a short time (eg, 1 week, 1 month, 1 year, etc.). In other words, it is preferable that the temporarily written data is retained for at least the time until the additional writing is completed. Although it depends on the actual operation and system configuration, the guaranteed storage time of data by temporary writing is preferably one week or longer. Temporarily written data can be written in a more storable state by additional writes that are performed later. Get in. Therefore, the size of ARl may not be sufficient to guarantee the preservation of data over a long period of time (eg, 10 years).

[0060] In the present embodiment, the length of Tpl is preferably adjusted to a length that eliminates the need for a buffer memory. The length that eliminates the need for the buffer memory is applied to the variable resistance device 194 for reading out the volatile storage device 192 (such as DRAM) disposed outside the variable resistance memory device 100. It is equal to or shorter than the voltage pulse width (related to the read cycle). More specifically, although depending on the performance of the volatile memory device 192, the length of Tpl is preferably 60 ns or less in consideration of the general DRAM read speed. When using iron oxide laminated compound (Fe 2 O 3 / Fe 2 O 3), the length of Tpl

2 3 3 4

For example, it can be 40 ns. By adjusting the length of Tpl so that the writing speed is as fast as the reading speed and eliminating the need for a noffer memory, the circuit area is reduced, the system configuration is simplified, and the manufacturing cost is reduced. it can. The length of Tpl is preferably from Ins to 60 ns.

[0061] There is a correlation between the length of Tpl and the size of AR1, and generally there is a relationship that AR1 decreases as Tpl is shortened. The size of AR1 is secured to a level that can guarantee temporary data storage, and the length of Tpl is preferably shortened so that a buffer memory is unnecessary. In the present embodiment, Tp 1 and ΔR1 are determined to be suitable values by appropriately adjusting the intensity of the voltage pulse, the composition of the resistance change material, the manufacturing method and structure of the memory cell, and the like.

[0062] When the temporary writing by the short pulse is completed and the data transmission from the system is stopped, the additional writing is performed. In additional writing, as a long pulse, a voltage having a predetermined magnitude is applied so that the total application time of the short pulse and the long pulse becomes Τρ2 (for example, 120 ns). That is, the width of the long pulse is Tp2−Tpl (for example, 80 ns). By applying a long pulse, the amount of change in the resistance value becomes AR2 (the resistance value corresponds to the new value). Tp2 is preferably determined so that AR2 is large enough to guarantee the preservation of data over a long period of time (eg 10 years).

[0063] Note that when the time elapsed between the temporary write and the additional write becomes longer, the AR decreases due to the change over time. If the effect is a problem, it is preferable to make the long pulse longer than Τρ2−Tpl by a predetermined amount. Also, after starting to apply a long pulse, If there is a time difference until the resistance value starts to change, it is preferable to increase the pulse width accordingly.

[0064] [Operation]

Hereinafter, data reading and writing operations by the resistance change storage device 100 will be described in detail with reference to FIGS.

First, a data read operation will be described. At the time of data reading, a specific word line 134 is activated by the row decoder 114 according to the chip select CS and address AD input from the control device 180, and the selection transistor 136 connected to the word line is turned on. The The corresponding NMOS transistor 144 is also turned on by the row decoder 114. Next, the voltage application circuit 140 is set to a high impedance state (non-conductive state), and the voltage application circuit 142 is set to OV. With this control, a current path is formed from the comparator 146 through the selection transistor 136, the resistance change element 138, and the NMOS transistor 144 to reach the voltage application circuit 142. The comparator 146 includes a voltage applying circuit, and applies an equal voltage to both the current path and the reference resistor 148. The comparator 146 compares the currents flowing through the two, whereby the memory cell data (resistance value of the resistance variable element 138) is read out.

[0066] Hereinafter, this will be described more specifically. As an example, assume that the value of the reference resistor 148 is set to 200 kΩ. If the resistance variable element 138 of the selected memory cell 139 is in the low resistance state (corresponding to a value of “0”), the resistance value of the path (= 60 kQ) <the resistance value of the reference resistance (= 200 kΩ) ), The current flowing through the path becomes larger than the current flowing through the reference resistor 148, and the comparator 146 outputs a high level. Conversely, if the selected memory cell is in the high resistance state (corresponding to a value of "1"), the resistance value of the path (= 1.2ΜΩ)> the resistance value of the reference resistor (= 200kΩ ), The current flowing through the path becomes smaller than the current flowing through the reference resistor 148, and the comparator 146 outputs a low level. As a result of this operation, the state level of the selected memory cell is read as the output level (read data signal) of the comparator 146, and is output to the data output terminal DOUT as the output data signal via the output data latch 122. To the system 190 via the control device 180.

Next, the data write operation, which is a feature of the resistance change storage device 100, will be described. Light up. The write operation of the resistance change memory device 100 is divided into a temporary write operation and an additional write operation. FIG. 6 is a flowchart showing an outline of the temporary write operation in the first embodiment of the present invention. FIG. 7 is a flowchart showing an outline of the additional write operation in the first embodiment of the present invention.

At the time of data writing, a predetermined memory cell 139 is selected by the write circuit 112 and the row decoder 114 in accordance with the internal control signal, and writing is performed. That is, both ends (bit line 130 and source line 132) of the memory cell 139 are electrically connected to the voltage application circuit 140 and the voltage application circuit 142, respectively, and a desired voltage pulse is applied to the resistance variable element 138. Thus, the resistance value is switched.

First, the temporary write operation will be described with reference to FIG. When an input data signal and an address signal reach the control device 180 from the system 190, a command is sent from the control device 180 to the resistance change memory device 100. The data input to the data input terminal DIN is stored (latched) in the input data latch 104, the internal control signal output from the control circuit 102 is set to the temporary write mode, and the temporary write operation is started (start).

Next, an active voltage (eg, +5 V) is applied to the word line 134 corresponding to the address indicated by the address AD, and an inactive voltage (eg, 0 V) is applied to the other word lines 134. . With this operation, the selection transistor 136 at the address to which data is to be written is turned on (step S101). At this time, the corresponding NMOS transistor 144 is also turned on.

The data to be written is composed of binary numbers (bits) that take two values “1” and “0”, and a plurality of (for example, 16) bits are assigned to one address. Therefore, it is first determined whether or not “1” is present in the write data (step S102). If YES is determined, the write circuit 112 is written to the memory cell 139 to which “1” is to be written. Is set for positive pulse application (step S103). That is, for the memory cell, the write circuit 112 is set so that +3.3 V is applied to the voltage applying circuit 140 side and 0 V is applied to the voltage applying circuit 142 side.

Next, it is determined whether or not “0” is present in the write data (step S104). If it is determined as YE S, write to the memory cell 139 to which “0” is to be written. Circuit 112 Set for negative pulse application (step S105). That is, for the memory cell, the writing circuit 112 is set so that +3.3 V is applied to the voltage application circuit 140 side on the OV force voltage application circuit 142 side. If NO is determined in step S102, "0" is written in all the cells. Therefore, the process proceeds to step S105, and the write circuit 112 is negative for all the cells at the address. Set for pulse application.

Next, the voltage noise output from the temporary writing short pulse generation circuit 106 is applied to the memory cell 139 corresponding to the address to which data is to be written (step S106). Note that step S106 is also executed when NO is determined in step S104.

[0074] In step S106, for the cell to which "1" is to be written, +3.3 from the voltage application circuit 140 via the bit line 130 and the selection transistor 136 to one end of the resistance variable element 138. A voltage of 0 V is applied from the V, voltage application circuit 142 to the other end of the resistance variable element 138 via the NMOS transistor 144 and the source line 132 for a predetermined time (for example, 40 ns) (positive pulse temporary writing). By applying a strong voltage, the resistance state of the resistance variable element 138 changes from a low resistance state (for example, about 51 kQ) to a high resistance state (shallow high resistance state: Transition to approximately 287 kΩ). The high resistance state at this time is relatively shallow, and by applying more voltage in the additional write operation (described later), the resistance value is higher, that is, the target high resistance state (deep high resistance state). : For example, about 1.2ΜΩ).

In addition, for a cell in which “0” is to be written, 0 V is applied to one end of the resistance variable element 138 from the voltage application circuit 140 via the bit line 130 and the selection transistor 136, and the voltage application circuit 14 2 Then, a voltage of +3.3 V is applied to the other end of the resistance variable element 138 through the NMOS transistor 144 and the source line 132 for a predetermined time (for example, 40 ns). That is, a pulse having a polarity opposite to that of the positive pulse writing is applied (temporary negative Norse writing). By applying such a voltage, the resistance state of the resistance variable element 138 has a higher resistance value than the target low resistance state from the high and low resistance state (for example, about 1.2 MΩ). Transition to a low resistance state (eg, approximately 113 kΩ). The low resistance state at this time is relatively shallow, and the resistance value is lower by applying more voltage in the additional write operation (described later). Transition to a state, that is, a target low resistance state (deep, low resistance state: for example, about 60 kΩ).

[0076] When step S106 is completed, "0" is written to the resistance variable element for flag in the temporary write flag area 116 corresponding to the sector including the temporarily written address, and the temporary write flag is set to "H". "Set to level (step S107). Note that the write operation to the temporary write flag region 116 is the same as the write operation to the memory cell 139 of the memory cell array 118, and thus description thereof is omitted.

When the writing to the temporary writing flag is completed, the writing to the address ends (END). One temporary write takes about 40ns. The resistance change type storage device 100 repeats the temporary write operation from steps S 101 to S 107 to perform a temporary write of a series of data for each address.

Next, the additional write operation will be described with reference to FIG. When the temporary writing to each address is completed and the writing and reading commands to the resistance change data recording medium 170 received from the system 190 are stopped, the control circuit 102 selects the additional writing mode according to the control of the controller 180. Then, an additional write operation is started (start).

First, control circuit 102 is controlled by control device 180, and data in temporary write flag area 116 corresponding to each sector is read and a flag whose value is “0” (flag information is “H”). A determination is made as to whether or not there is a force "a flag that is" (step S201). Note that the data read operation of the temporary write flag area 116 is the same as the read operation of the memory cell array 118, and thus the description thereof is omitted. If NO is determined in step S201, no additional write operation is performed (end) because all memory cells are in a state that can withstand long-term storage. On the other hand, if YES is determined in step S201, a series of additional write operations are performed under the control of control device 180 (steps S202 and after).

First, all the data (“1” or “0”) recorded in the sector corresponding to the flag of “0” (hereinafter referred to as additional write target sector) is read out, and the output data latch 122. It is stored in (write data storage device) (step S202). [0081] Next, 0 is substituted for the variable N indicating the sector write address of the additional write target sector (step S203), and the data for the number of unit write bits (for example, 16 bits) is extracted from the stored data. The data is transferred from the output data latch 122 to the write circuit 112 (step S204).

When data is sent to the write circuit 112, an active voltage (for example, + 5V) is applied to the word line 134 corresponding to the Nth sector write address of the sector, and an inactive signal is applied to the other word lines 134. A voltage (eg OV) is applied. With this operation, the selection transistor 136 of the cell to which additional data is to be written becomes conductive (step S205). At this time, the corresponding NMOS transistor 144 is also turned on.

Next, it is determined whether or not “1” is present in the write data transferred to the write circuit 112 (data stored in the cell at the sector write address N) (step S206). Then, the write circuit 112 is set for applying a positive pulse to a cell (a cell in the memory cell array 218) to which “1” is to be additionally written (step S207). That is, for the cell, the write circuit 112 is set so that +3.3 V is applied to the voltage application circuit 140 side and OV is applied to the voltage application circuit 142 side.

Next, it is determined whether or not “0” is present in the write data (step S 208). If it is determined as YE S, a cell to be additionally written with “0” (in the memory cell array 218). For the cell), the write circuit 112 is set to apply a negative pulse (step S209). In other words, for the cell, the write circuit 112 is set so that OV force is applied to the voltage application circuit 140 side and +3.3 V is applied to the voltage application circuit 142 side. If NO is determined in step S206, “0” is additionally written to all the cells. Therefore, the process proceeds to step S209, and the writing circuit 112 is written to all the cells. Is set for negative pulse application.

Next, the voltage noise output from the additional write long pulse generation circuit 108 is applied to the memory cell 139 corresponding to the address to which data is to be written (step S210). Note that step S210 is also executed when it is determined NO in step S208. In step S210, for the cell to which "1" is to be written, the voltage application circuit 140 passes through the bit line 130 and the selection transistor 136 to one end of the resistance variable element 138 +3.3. A voltage of 0 V is applied from the V, voltage application circuit 142 to the other end of the resistance variable element 138 via the NMOS transistor 144 and the source line 132 for a predetermined time (for example, 80 ns) (positive pulse additional writing). By applying a voltage, the resistance state of the resistance variable element 138 changes from a shallow high resistance state (for example, about 287 kΩ) to a deep high resistance state (for example, about 1.2 MΩ). By additional writing, the resistance state of the resistance variable element 138 can be stably maintained at a high resistance state, and the data storage property is improved.

In addition, for a cell to which “0” is to be written, 0 V is applied to one end of the resistance variable element 138 from the voltage application circuit 140 via the bit line 130 and the selection transistor 136, and the voltage application circuit 14 2 Then, a voltage of +3.3 V is applied to the other end of the resistance variable element 138 through the NMOS transistor 144 and the source line 132 for a predetermined time (for example, 80 ns). That is, a pulse having a polarity opposite to that of the positive pulse additional write is applied (negative pulse additional write). By applying such a voltage, the resistance state of the resistance variable element 138 changes from a shallow low resistance state (for example, about 113 kΩ) to a deep low resistance state (for example, about 60 kΩ). By additional writing, the resistance state of the resistance variable element 138 can be stably maintained at the low resistance state, and the data storage property is improved.

When step S210 ends, 1 is added to N (step S211), and it is determined whether N exceeds Nmax (step S212). If not, the process returns to step 204. By additional operation, additional writing is performed in sequence up to the sector write address N = 1, 2, ..., Nmax. If N exceeds Nmax, additional writing has been completed for the sector, so it is reset by writing 1 to the flag variable resistance element corresponding to the sector (step S213), and step S201 is entered. Return. Note that the write operation to the temporary write flag area 116 is the same as the write operation to the cells of the memory cell array 218, and thus description thereof is omitted.

[0085] By performing the operation, the resistance change memory device 100 repeats the operations from step S201 to step S213, thereby sequentially performing additional writing until the flag becomes 1 ("L" level) for all sectors. Do.

By the operation and configuration as described above, the resistance change type storage device 100 can perform a desired change according to the input chip select CS, external control signal CTL, address AD, and write pulse WP. Read and write operations (temporary write and additional write) to memory cell 139 are performed.

[Effect]

According to the resistance change type memory device 100, “1” or “0” can be selectively written to each memory cell 139 individually (simultaneously and in parallel) by applying a single pulse. The batch erase operation, which was necessary with conventional flash memory, is no longer necessary, and the programming speed is dramatically improved.

In addition, the resistance change storage device 100 includes the temporary write short pulse generation circuit 106 and the additional write long pulse generation circuit 108 to perform writing in two stages. In other words, when writing data, first, a short pulse voltage is applied to write data in a shallow and short time. In temporary writing, all data to be written is first temporarily written using a short pulse. According to the operation, the temporary writing requires only a very short time (for example, about 40 ns) to write one unit, and the writing speed is almost the same as the reading speed.

In the present embodiment, when a command for writing to and reading from the resistance change storage device 100 does not come from the system 190, an additional writing operation is executed under the control of the control device 180. In the additional write operation, a long pulse voltage is applied to the additional write target cell, and the cell resistance state transitions to the target resistance level from the viewpoint of data stability and storage stability. Since such additional writing can be performed in a time zone where the load on the entire system is small, apparently the additional writing time hardly affects the performance of the system. Further, additional writing improves data storability and realizes a nonvolatile storage device having high reliability.

[0088] The powerful configuration and operation significantly reduces the apparent write time seen by the host system while maintaining the data guarantee time, enabling a dramatic improvement in memory system performance (speeding up). Become. In particular, by setting the width of the short pulse for temporary writing so that the writing speed is almost the same as the reading speed, DRAM and DRAM interface that were conventionally required separately as a buffer memory for data Circuits can be eliminated. Therefore, reduction of circuit area, downsizing of equipment, reduction of manufacturing cost Is possible.

[0089] [Example 1]

FIG. 8 is a diagram showing the relationship between the pulse application time and the resistance value in the example. In this example, an iron oxide laminated compound (Fe 2 O 3 / Ye 2 O 3) was used as the resistance variable element. Figure

2 3 3 4

The square indicates the resistance value after the positive pulse is applied, and the triangle indicates the resistance value after the negative pulse is applied.

[0090] The resistance variable element of this example was manufactured by the following method. First, the lower electrode (Pt) was formed on the substrate by sputtering so as to have a thickness of lOOnm. The resistance change layer is a Fe O target material that has a thickness of 95 nm on the lower electrode.

3 4 3 4 Formed by sputtering using a material, and a layer with Fe O force on it has a thickness of 5 nm.

twenty three

It was formed by sputtering using a Fe 2 O target material. Fe O?

On the layer made of 2 3 2 3, the upper electrode (Pt) was formed by sputtering so as to have a thickness of 50 nm. The diameter of the element was about 0.

[0091] The resistance variable element obtained by the above method was subjected to multiple positive voltage pulses to change into a deep high resistance state (1.18 Ω). Next, a voltage pulse (negative pulse) with a pulse width of 20 ns and a voltage value of −3.3 V was applied to the resistance variable element in the deep high resistance state. The polarity of the voltage is described as the voltage of the upper electrode with respect to the lower electrode (the same applies hereinafter). When the voltage is applied twice, the resistance value changes to 113 kΩ, when it is applied three times, the resistance value changes to 84 kΩ, and when it is applied six times, the resistance value is about 60 kΩ (deep Changed to a low resistance state). If the amount of change in resistance from a deep high-resistance state to a deep low-resistance state is ΔR12 (= 1120kΩ), and the amount of change in resistance due to twice-applied Nors is ΔRll (= 1067kΩ) The ratio of ΔR11 to ΔR12 is 95%. If the amount of change in resistance by applying three pulses is A Rll '(= 1096k Q), the ratio of ΔRll to ΔR12 is 98%. It was.

[0092] Thereafter, a voltage pulse with a pulse width of 20 ns and a voltage value of +3.3 V is applied to a resistance variable element in a deep low resistance state (approximately 51 kQ) to which a negative pulse has been applied 10 times in total. (Positive pulse) was applied. When the voltage pulse is applied twice, the resistance value changes to 287 kΩ, when the voltage pulse is applied three times, the resistance value changes to 550 kΩ, and when the voltage pulse is applied six times, the resistance value becomes 1.18ΜΩ (depth V, high resistance state). If the amount of change in resistance from the deep low resistance state to the deep! High resistance state is ΔR12 (= 1129k Ω), and the amount of change in resistance due to two pulse applications is ΔRh l (= 236kQ) The ratio of ARhl to ARh2 was 21%, and the ratio of ARll 'to AR12 was 44%, assuming that the amount of change in resistance by applying three pulses was ARll' (= 499kQ).

Thus, in the resistance variable element of this example, the resistance value gradually increased as the positive pulse application time increased, and the resistance value gradually decreased as the negative pulse application time increased. In other words, the resistance value first changed rapidly with respect to the cumulative amount of voltage pulses applied, and then gradually changed (saturated to a predetermined value). In order to realize the target resistance change (1129 kΩ), it was found that it was necessary to apply a pulse for a length of 120 ns or longer, for example. On the other hand, even with short pulses (40 ns or 60 ns), it was possible to achieve a change equivalent to 20 to 98% of the target change in resistance.

[0093] According to the results, it was inferred that high-speed write operation can be performed by temporarily writing with a short pulse (40 ns or less, or 60 ns or less). In addition, when extra time was obtained, it was speculated that additional data could be written with a long pulse of about 80 ns to improve data storage.

[0094] It should be noted that the amount of change in the resistance value was almost equal between the case where the pulse having a predetermined time width was divided and applied and the case where the pulse was applied with a single pulse. For example, when the 20 ns pulse is applied twice and when the 40 ns pulse is applied once, the amount of change in resistance is almost equal.

[Example 2]

In Example 2, instead of Fe 2 O in Example 1, ZnFe 2 O was used as the resistance change material.

2 3 2 4 In other words, the variable resistance layer consists of a layer with a thickness of 95 nm that is Fe O force and ZnFe O force.

3 4 2 4 was formed as a layer having a thickness of 5 nm (other configurations and formation methods are the same as in Example 1). O With this configuration, the same results as in Example 1 were obtained. That is, the resistance value gradually increased as the positive pulse application time increased, and the resistance value gradually decreased as the negative pulse application time increased. Therefore, as in Example 1, it was presumed that a high-speed write operation could be performed by temporarily writing with a short pulse. Also, when extra time is available It was speculated that the data storage stability could be improved by writing additional pulses.

[0095] [Modification]

Various modifications can be made to the invention of the present embodiment, and an example is shown below.

[0096] In the above description, pulse width for temporary writing (Tpl) <pulse width for additional writing

The force of (Tp2-Tpl) The two types of pulse width can be set arbitrarily, including the magnitude relationship. For example, similarly to the above, the pulse voltage may be made equal, and the pulse width for temporary writing may be shorter than the pulse width for additional writing. In such a configuration, since the applied voltages are equal, the circuit configuration can be simplified. Alternatively, the pulse widths may be made equal to make the pulse voltage for temporary writing larger than the pulse voltage for additional writing. In such a configuration, by increasing the voltage by the pulse for temporary writing, it is possible to balance the speed of the temporary writing operation and the power consumption. Alternatively, Tpl (—pulse width for hourly writing) ≥Tp2—Tpl (pulse width for additional writing) may be used. In other words, the pulse width and voltage may be any value as long as the desired AR and writing speed can be realized.

The temporary write flag may be provided for an arbitrary memory cell section such as a word line unit, a mat unit, or a bank unit, which is not necessarily provided for each sector. The temporary write flag area 116 may be provided in the control device 180. In addition to the output data latch 122, a data latch dedicated to additional writing may be provided separately.

[0098] In the above description, sectors to be additionally written are collectively stored in the output data latch 122, and then additional writing is performed on all cells in the sector for each writing unit (sector writing address). Carried out. However, the same number of output data latches as the number of sense amplifiers 120 may be prepared, and the target data in the sector may be read in smaller units, and additional writing may be performed each time. According to the configuration, the circuit area can be reduced and the device can be downsized.

In the above description, the resistance variable element is used as a memory cell for storing binary data. Using. However, the resistance level (AR2) can vary depending on the intensity (voltage) and length (pulse width) of the applied voltage pulse. Therefore, the data stored in the resistance change storage device may be any data as long as it can take a plurality of values discretely (multi-value data). For example, a plurality of AR2 may be set, and each memory cell may be configured as a so-called “multi-value memory” that can store a value larger than 2 (for example, 4 or 8). With such a configuration, further integration of the circuit becomes possible.

[0099] The temporary writing and the additional writing do not necessarily have to be performed by a single voltage pulse, and each writing may be performed in a plurality of times. However, for high-speed writing, it is preferable to configure voltage voltage to be printed only once, at least for temporary writing.

[0100] It is not always necessary to provide the two pulse generation circuits of the temporary write short pulse generation circuit 106 and the additional write long pulse generation circuit 108. For example, the configuration may include one pulse generation circuit. . For example, the pulse width for temporary writing may be equal to the pulse width for additional writing. With same width pulse

By changing the number of times of application, the depth of the temporary write and the additional write (resistance change width) may be adjusted. When there is one pulse generation circuit, the write pulse switching circuit 110 is not essential. The temporary write operation and the additional write operation may be switched under the control of the control circuit 102.

[0101] In the above description, a voltage pulse is applied to the resistance variable element, the resistance value changes based on the cumulative amount of voltage pulse applied, and data is written. However, the method of changing the resistance value is not necessarily limited to the application of a voltage pulse. Any method may be used as long as the resistance value is changed according to the cumulative amount of energy input in a predetermined mode. For example, data may be written by changing the resistance value based on the cumulative amount of current.

[0102] There are various resistance value change patterns, but generally the resistance value monotonically increases with the cumulative energy input. In such a change pattern, temporary writing is performed by short-time energy input, and additional writing is performed when the load on the system is reduced. Improvement).

In the two-stage writing, if the value of the written data is updated (changed) from "0" to "1" or from "1" to "0", the same data can be written. If it is a value, writing may not be performed. It is possible to determine before writing whether the value to be written and the value to be written have the same power or not, and if the values are the same, the writing may not be performed. In order to simplify the operation, writing may be performed even if the data to be written has the same value. In the case where power is applied, the resistance value hardly changes even by the temporary write operation and the additional write operation. That is, there are cases where the resistance value hardly changes during the temporary write operation and the additional write operation.

As the material of the resistance change layer, as the width of the applied voltage pulse is longer, the amount of change in the resistance value becomes larger, and the resistance value first changes rapidly with respect to the cumulative applied voltage pulse, and then gradually. Any material that changes so as to saturate (converge to a predetermined value) may be used. This embodiment is particularly suitable when a material made of iron oxide or a material containing a transition metal such as zinc (Zn) as an impurity in the iron oxide is used as the material of the resistance change layer.

[0103] The resistance value achieved by the additional writing and the resistance value achieved by the temporary writing can be appropriately determined based on the required data retention time, the data retention characteristics of the element, and the like. The resistance value achieved by additional writing does not necessarily have to be the resistance value when the amount of change is saturated. Realize the amount of change in resistance value that is smaller than the target amount of change (achieved by additional writing) but sufficient for temporary data retention by applying a shorter voltage pulse. Thus, high-speed temporary writing becomes possible.

In this embodiment, a resistance variable element whose resistance value is changed by application of a voltage pulse is used as the nonvolatile memory element. However, by changing the resistance value using a magnetic field as the nonvolatile memory element. You can use MRAM (Magnetic RAM) to store information, OUM (Ovonic Unified Memory) or PRAM, etc. to store information by changing resistance values using heat! ,.

(Second embodiment)

[Device configuration] FIG. 9 is a block diagram showing a schematic configuration of the resistance variable memory apparatus according to Embodiment 2 of the present invention. The outline of the configuration and operation of the resistance change type storage device of the present embodiment will be described below with reference to FIG. Note that the resistance change type storage device of the second embodiment adds an additional write sequence control circuit 224 to the control circuit of the resistance change type storage device of the first embodiment, and the control circuit power is also added to the control device as an additional write execution flag. FG is output, and other configurations are the same as in the first embodiment. Therefore, common components are given the same names and description thereof is omitted.

[0105] The additional write sequence control circuit 224 is a circuit for controlling the additional write operation. In the first embodiment, the control of the additional write operation performed by the control device 180 is performed in the resistance change type storage device. This is what is achieved.

The additional write execution flag FG is output to a control device outside the control circuit 202 (not shown: corresponding to the control device 180 of the first embodiment) based on whether additional writing is being performed. This is a binary signal. When the additional writing execution flag is at the FG force level, it indicates that the resistance change type storage device 200 is performing additional writing and data reception from the outside is impossible. When the additional write execution flag FG is at the “L” level, it indicates that the resistance change storage device 200 can accept data from outside (temporary write) during the additional write.

Also in this embodiment, as shown in FIG. 2, it can be configured as a resistance change type data recording medium or resistance change type storage device provided with a control device.

[Operation]

Since the data read operation by the resistance change storage device 200 is the same as that of the first embodiment, the description thereof is omitted. A feature of the resistance change type storage device 200 of the present embodiment is that additional writing is autonomously performed using the sequence control circuit 224 and the additional writing execution flag FG. Hereinafter, the write operation of the resistance change storage device 200 will be described.

FIG. 10 is a timing chart showing a write operation by the resistance change memory device according to the second embodiment of the present invention. As shown in the figure, when chip select CS is at "H" level, temporary writing is performed according to the input via the external system power controller. It is. That is, the input data DIN (DO, Dl, D2-... Is written to the memory cell of the input address AD (A 0, Α1, Α2,...) In accordance with the timing of the write pulse WP. Since the temporary write operation to the memory cell is the same as that of the first embodiment (FIG. 6), description thereof is omitted.

When the chip select CS becomes “L” level, the additional write sequence control circuit 224 performs an additional write operation. During the additional write operation, the additional write sequence control circuit 224 reads the data in the normal write flag area 216 via the output data latch 222 (corresponding to step S201 in FIG. 7). At this time, if even one temporary read flag area 216 includes the value of “0” (“H”), at least one sector including a temporarily written cell is included. It means to exist. Therefore, the control circuit 202 outputs “H” level as the additional write execution flag FG, and performs the additional write operation. Note that the additional write operation is the same as that of the first embodiment (FIG. 7), and a description thereof will be omitted. When the additional write operation is completed, the control circuit 202 outputs “L” level as the additional write execution flag FG. While the “H” level is being output as the additional write execution flag FG, the external control device or system does not input data (write command) to the resistance change storage device 200! / ヽ.

As described above, in resistance change memory device 200, temporary writing and additional writing are performed in accordance with chip select CS. In this case, a resistance change type storage device array including a plurality of resistance change type storage devices 200 may be configured. In such a configuration, a control device outside the resistance change type storage device array inputs the chip select CS to each resistance change type storage device 200. The control device selects one of the plurality of resistance change storage devices 200 by switching the chip select CS. That is, an “H” level signal is input as the chip select CS to the selected resistance change storage device 200, and temporary writing is performed according to the input of the control device. The resistance change type memory device 200 that has not been selected receives an “L” level signal as the chip select CS, and the additional write sequence control circuit 224 performs additional writing.

[Effect]

The resistance change type memory device 200 has the same effect as the resistance change type memory device 100. In addition, the following effects are achieved. That is, it is not necessary to control the additional write operation by an external control device, so that convenience for the user is improved. In addition, while the "H" level is being output as the additional write execution flag FG, malfunctions can be prevented by preventing the external controller or system from issuing a data write command.

[Modification]

In the above description, the power of performing an additional write operation using the period when the chip select is at the “L” level. For example, BGO (Back Ground Operation), while reading a certain bank, separate it in the knock ground. Write additional banks, and in effect, make additional write operations invisible.

[0109] In the above description, the additional write execution flag is used during the additional write operation, and the control signal and new write data cannot be received. If a read or write command is input during the additional write operation, the additional write operation is interrupted, the read or temporary write operation is preferentially executed, and interrupted after the interrupted read or temporary write operation is completed. The additional write operation may be resumed. With this powerful operation, write data does not stay in the host system.

[0110] Also in this embodiment, a resistance change type data recording medium may be configured by combining a resistance change type storage device and a control device, and a resistance change type device is configured by adding a system. May be.

[0111] Needless to say, the present invention can be variously modified and implemented without departing from the scope of the invention.

(Third embodiment)

[Device configuration]

FIG. 11 is a block diagram showing a schematic configuration of the resistance variable memory apparatus according to Embodiment 3 of the present invention. Hereinafter, with reference to FIG. 11, an outline of the configuration and operation of the resistance change storage device according to the present embodiment will be described. The resistance change type storage device of the second embodiment performs additional writing based on a signal from the outside, whereas the resistance change type storage device of the second embodiment is the resistance change type of the third embodiment. The changeable storage device is equipped inside Additional writing based on the timer (calendar). The resistance change type storage device of the third embodiment adds an additional write sequence control circuit 324 to the control circuit of the resistance change type storage device of the first embodiment, and further adds an additional write write timer 326. The other configurations are the same as those in the first embodiment. Therefore, common components are given the same names and description thereof is omitted.

The additional write sequence control circuit 324 is a circuit incorporated in the control circuit 302 for controlling an additional write operation (described later).

The control circuit 302 is the same as the control circuit 102 except that it includes an additional write sequence control circuit 324 and outputs a temporary write execution flag FG signal to an external control device.

[0114] The additional write timer 326 (for example, an odd number of inverters connected in series) outputs an additional write operation enable signal AP (described later) to the control circuit 302 (additional write sequence control circuit 324). . The additional write timer 326 may be a circuit configured to detect a long cycle by using date and time information possessed by a system such as a personal computer! /.

In this embodiment, the additional write sequence control circuit 324 and the additional write timer 326 constitute an additional write sequence control device.

Also in this embodiment, the resistance variable data storage medium and the resistance variable device as shown in FIG. 2 are configured.

FIG. 12 is a diagram showing an example of a change with time of the resistance value of the resistance variable element. In Fig. 12, the horizontal axis plots elapsed time (T) with a logarithmic axis (logT). As shown in Fig. 12, the resistance value changes (decays) with time in a direction that cancels the written change. If the absolute value of the attenuation is AR ', AR' is almost proportional to logT, and the resistance value changes linearly with respect to logT. Therefore, it is preferable that the change in AR1 is set so that at least a short period of data (for example, one week, one month, one year, etc.) can be secured. In other words, it is preferable that the temporarily written data is retained at least during the period from the completion of the temporary writing to the additional writing. Depending on the actual operation and system configuration, the power is turned off in the temporary write state, and the resistance value decreases. Considering that there may be cases, it is preferable that the guarantee period Ttau for data storage by temporary writing is one week or longer. Temporarily written data is written in a more storable state by additional writing performed later. Therefore, the size of ARl may not be sufficient to guarantee the preservation of data over a long period (eg, 10 years).

[0118] When a predetermined period arrives and temporary writing with a short pulse is not performed, additional writing is performed (details of timing adjustment will be described later). In additional writing, a voltage of a predetermined magnitude is applied as a long pulse so that the total application time of the short pulse and the long pulse is Tp2. That is, the width of the long pulse is Τρ2-Tpl. By applying a long pulse, the amount of change in the resistance value becomes AR2 (the resistance value becomes a value corresponding to the new value). Tp2 is preferably determined so that AR2 is large enough to guarantee data storage over a long period of time (eg, 10 years). A state in which additional writing is performed and data storage stability is guaranteed is hereinafter referred to as an additional writing state.

[0119] Note that if the time elapsed between the temporary write and the additional write becomes longer, will decrease due to the change over time (see Fig. 12). If the effect is strong, it is preferable to make the long pulse longer than Tp2-Tpl by a predetermined amount. If there is a time difference from the start of applying a long pulse until the resistance value starts to change, it is preferable to increase the pulse width accordingly.

Also in the present embodiment, as shown in FIG. 2, it can be configured as a resistance change type data recording medium or resistance change type storage device provided with a control device.

[0121] [Operation]

Since the data read operation by the resistance change type storage device 300 is the same as that of the first embodiment, the description thereof is omitted. Since the temporary write operation is the same as that in the first embodiment, a detailed description thereof is omitted (see FIG. 6). In the present embodiment, the temporary write operation is performed at any time by data input from the control device 180.

[0122] The variable resistance storage device 300 of the present embodiment is characterized in that the write sequence control circuit 124 and the additional write timer 126 are autonomously added without being based on a command from the external control device 180 or the like. The point is to perform a write operation. FIG. 13 is a flowchart showing an outline of the additional write operation in the third embodiment of the present invention. Hereinafter, the additional write operation in the third embodiment will be described with reference to FIG. In the present embodiment, the additional write sequence control circuit 324 and the additional write timer 326 are not based on a command from an external control device (corresponding to the control device 180 in FIG. 2) or the like and autonomously perform an additional write operation. I do. That is, the additional write timer 326 outputs the additional write operation enable signal AP while power is supplied to the resistance change storage device 300. The additional write operation enable signal AP is pulsed at the “H” level for a predetermined period (several seconds, minutes, etc.) with a fixed period (1 day, 1 week, 1 month, 1 year, etc.). And others are set to the "L" level. The period is preferably set to a period during which the variable resistance element in the temporarily written state can hold data with sufficient reliability. When the additional write operation enable signal AP becomes “L” level, the additional write operation is forcibly terminated. Therefore, it is preferable that the time during which the “H” level is maintained be adjusted to a time during which additional writing can be performed for the Mori cell 139. When the additional write operation enable signal AP becomes “H” level, the control circuit 302 selects the additional write mode, and the additional write operation is controlled according to the control of the additional write sequence control circuit 324 in the control circuit 302. Start (Start).

First, the additional write execution flag FG output from the control circuit 302 is set to the “H” level (step S301), and the data in the temporary write flag area 116 corresponding to each sector is read. Thus, a determination is made as to whether or not there is a flag having a value of “0” (flag information flag “Η”) (step S302). The description is omitted because it is the same as the read operation of the memory cell array 118. If NO is determined in step S302, all the memory cells are in the additional write state, so the additional write execution flag FG is set to “ L "level is set (step S315), and the additional write operation is terminated (end). On the other hand, if YES is determined in step S302, a series of additional operations are performed according to the control of the controller 180. Operation is performed write attempts (step S303~).

[0125] First, it is recorded in the sector corresponding to the flag that is "0" (hereinafter referred to as additional write target sector). All the data (“1” or “0”) read is read and stored in the output data latch 122 (write data storage device) (step S303).

[0126] Next, 0 is assigned to the variable N indicating the sector write address of the additional write target sector.

(Step S304) Of the stored data, data corresponding to the number of unit write bits (for example, 16 bits) is extracted and transferred from the output data latch 122 to the write circuit 112 (Step S305).

[0127] When data is sent to the write circuit 112, an active voltage (eg, 3.3V) is applied to the word line 134 corresponding to the Nth sector write address (sector write address N) of the sector, An inactive voltage (for example, OV) is applied to the other word line 134. With this operation, the selection transistor 136 of the cell to which additional data is to be written is turned on (step S306). At this time, the corresponding NMOS transistor 144 is also turned on.

[0128] Next, it is determined whether or not "1" is present in the write data transferred to the write circuit 112 (data stored in the cell at the sector write address N) (step S307). If it is determined as S, the write circuit 112 is set for applying a positive pulse to the cell to which “1” is to be additionally written (cell of the memory cell array 218) (step S308). That is, for the cell, the write circuit 112 is set so that +3.3 V is applied to the voltage application circuit 140 side and OV is applied to the voltage application circuit 142 side.

Next, it is determined whether or not “0” is present in the write data (step S309). If it is determined as YE S, a cell to be additionally written with “0” (in the memory cell array 218). For the cell), the write circuit 112 is set to apply a negative pulse (step S310). In other words, for the cell, the write circuit 112 is set so that OV force is applied to the voltage application circuit 140 side and +3.3 V is applied to the voltage application circuit 142 side. If NO is determined in step S307, “0” is additionally written to all the cells. Therefore, the process proceeds to step S310, and the writing circuit 112 is written to all the cells. Is set for negative pulse application.

Next, the voltage pulse output from the additional write long pulse generation circuit 108 is applied to the memory cell 139 corresponding to the sector write address N (step S 311). In addition, Step S311 is also executed if NO is determined in step S309.

[0131] In step S311, for the cell to which "1" is to be written, +3.3 from the voltage application circuit 140 via the bit line 130 and the selection transistor 136 to one end of the resistance variable element 138. A voltage of 0 V is applied from the V and voltage application circuit 142 to the other end of the resistance variable element 138 via the NMOS transistor 144 and the source line 132 (positive Norse tracking write). By applying such a voltage, the resistance state of the resistance variable element 138 changes from a shallow high resistance state (for example, 287 kΩ) to a deep high resistance state (for example, 1.18ΜΩ). By the additional writing, the resistance state of the resistance variable element 138 can be stably maintained in the high resistance state, and data storability is improved.

[0132] For the cell to which "0" is to be written, 0 V is applied to one end of the resistance variable element 138 from the voltage application circuit 140 via the bit line 130 and the selection transistor 136, and the voltage application circuit 14 2 Then, a voltage of +3.3 V is applied to the other end of the resistance variable element 138 via the NMOS transistor 144 and the source line 132. That is, a pulse having a polarity opposite to that of the positive pulse additional write is applied (negative pulse additional write). By applying a voltage, the resistance state of the resistance variable element 138 changes from a shallow low resistance state (for example, 113 kΩ) to a deep low resistance state (for example, 60 kΩ). By additional writing, the resistance state of the resistance variable element 138 can be stably maintained at the low resistance state, and the data storability is improved.

[0133] When step S311 ends, 1 is added to N (step S312), and it is determined whether or not N exceeds Nmax (step S313). If not, the process returns to step S305. Due to the operation, additional writing is performed sequentially until the sector write address N = 1, 2, ..., Nmax. If N exceeds Nmax, additional writing has been completed for the sector, so it is reset by writing 1 to the flag variable resistance element corresponding to the sector (step S314), and step S302. Return to. Note that the write operation to the temporary write flag area 316 is the same as the write operation to the cell of the memory cell array 318, and thus the description is omitted.

[0134] By performing the operation, the resistance change memory apparatus 300 repeats the operations from step S302 to step S314, thereby sequentially performing additional writing until the flags become 1 ("L" level) for all sectors. Do. [0135] With the operation and configuration as described above, the resistance change type storage device 300 performs the read operation of a desired memory cell 139 according to the input chip select CS, external control signal CTL, address AD, and write pulse WP. And temporary write operation. Further, the resistance change type memory device 300 autonomously performs an additional write operation at regular intervals without being based on a signal input from an external force.

[Relationship between additional writing and temporary writing data guarantee period]

FIG. 14 is a diagram showing the timing of the additional write operation enable signal AP and the additional write execution flag FG. The additional write operation enable signal AP is periodically set to the “H” level. The cycle Tea (additional write cycle: the interval from when the additional write operation enable signal AP becomes “H” level to “H” level again) corresponds to the interval between additional write operations. After additional writing is completed, Tea is set so that the next additional writing is performed before the storage state of the data that was temporarily written first deteriorates. Alternatively, the depth of temporary writing (temporary writing resistance value) is set so as to guarantee at least storability during a period corresponding to the additional writing cycle. In other words, Ttau> Tca, where Ttau is the guarantee period for data storage by temporary writing (temporary writing data guarantee period). Alternatively, after entering the temporary write state, Tea is set so that the difference (gap) force between the resistance value of the resistance variable element and the resistance value of the reference resistance in the state where only Tea has passed is equal to or greater than the reading guarantee margin. The By ensuring a certain read guarantee margin, data can be read reliably. This powerful setting guarantees sufficient data storage by temporary writing.

[0137] [Effect]

Also in this embodiment, the same effect as the first embodiment can be obtained.

Further, in this embodiment, the additional write timer 326 and the additional write sequence control circuit 324 are in a temporary write state or an additional write state for all the memory cells every predetermined period (additional write cycle). If there is a memory cell in the temporary write state, the sector containing that memory cell is selected! Then, an additional write operation is performed. In the additional write operation, a long pulse voltage is applied to the additional write target cell, and the target resistance from the viewpoint of data stability and storage stability. The resistance state of the cell transitions to the value level. Since this additional write operation is performed sporadically over a relatively long period (1 day, 1 week, 1 year, etc.), the additional write time hardly affects the system performance. That is, normally, data is written at high speed only by temporary writing, so that a nonvolatile memory device capable of high-speed response is realized. On the other hand, since the data storability is improved by the additional writing, a highly reliable nonvolatile memory device is realized.

[0139] Note that the additional write cycle is set to a period during which data storage by temporary writing is sufficiently guaranteed. Alternatively, the depth of temporary writing (temporary writing resistance value) is set so as to guarantee at least data storability during a period corresponding to the interval between additional writing operations. That is, after the completion of the additional writing, the resistance value and the timing of the temporary writing are set so that the next additional writing is performed before the storage state of the data temporarily written temporarily deteriorates. This powerful configuration makes it possible to ensure sufficient reliability for the storability of data that is temporarily written.

[0140] The temporary write operation is performed as needed according to the input of the external control device force, but the additional write operation is autonomously performed by the resistance change type storage device regardless of the external force signal. In such a configuration, since it is not necessary for an external system to perform control in consideration of additional writing, the convenience of the user (system designer, etc.) is enhanced. In addition, when the additional write execution flag FG is output, when the resistance change type storage device is busy (additional write operation is in progress: the additional write execution flag is "H" level), the external system It becomes possible to stop input, and malfunction can be prevented.

[0141] [Modification]

Various modifications can be made to the invention of the present embodiment, and an example is shown below. Needless to say, the present embodiment can be modified in the same manner as in the first embodiment.

[0142] In the above description, when the additional write operation enable signal AP is at the "H" level, the force for performing the additional write operation is set to the "H" level. Additional writing may be performed for. That is, the additional write operation enable signal AP does not need to be at the “H” level during the additional write period. Even after you return to the bell, additional writing may be done. The additional write operation enable signal AP can be any signal as long as it controls the timing so that the additional write sequence control circuit 124 can perform the additional write operation at a fixed period.

[0143] In the above description, the additional write execution flag is used during the additional write operation, and the control signal and new write data cannot be received. If a read or write command is input during an additional write operation, the additional write operation is interrupted, the read or temporary write operation is preferentially executed, and the interrupted read operation or temporary write operation is completed after completion. The additional write operation may be resumed. According to this mode, write data does not stay in the host system.

[0144] In the above description, the power for performing the additional write operation using the period when the additional write operation enable signal AP is set to the "H" level. For example, BGO (Back Ground Operation) As described above, another bank may be additionally written in the background while one bank is being read, so that the additional write operation is effectively invisible.

[0145] Needless to say, the present invention can be variously modified and implemented without departing from the scope of the invention.

(Fourth embodiment)

[Device configuration]

FIG. 15 is a block diagram showing a schematic configuration of the resistance variable memory apparatus according to Embodiment 4 of the present invention. The outline of the configuration and operation of the resistance change storage device according to the present embodiment will be described below with reference to FIG. Note that the resistance change type storage device of the fourth embodiment is obtained by replacing the additional write sequence control circuit of the resistance change type storage device of the third embodiment with a power down sequence control circuit and deleting the additional write timer. In other respects, the configuration is the same as that of the third embodiment. Therefore, common constituent elements are given the same names and description thereof is omitted.

[0146] The power-down sequence control circuit 424 (additional write sequence control device) is a circuit incorporated in the control circuit 402, and the power-down sequence control circuit 400 is powered down. Sometimes it is a circuit that performs an additional write operation. The resistance change type storage device 400 is driven by electric power supplied from the outside. For this reason, the power-down of the resistance change type storage device 400 is started based on an external control signal that is not autonomously performed. Specifically, the power is turned off by the following steps. First, when the power of the system (corresponding to the system 190 in FIG. 2) is turned off, the system power is also sent to the control device (corresponding to the control device 180 in FIG. 2). When the control device receives the power-down notification signal, it sends a power-down signal to the resistance change type storage device 400. When the power-down sequence control circuit 424 receives the power-down signal, the power-down sequence control circuit 424 executes the power-down sequence, and additional writing is performed in the operation. Note that the additional write operation in the power-down sequence is the same as the additional write operation in the third embodiment, and a description thereof will be omitted.

[0147] [Effect]

In this embodiment, additional writing is performed collectively when the power is turned off. Therefore, when the power is turned off, all the data is recorded in the memory cell, and the additional writing is completed, and the data is reliably saved even when the power is turned off. become. On the other hand, no additional writing is performed while the power is on (during normal operation), and all data writing is processed by temporary writing. Therefore, the apparent writing speed is increased. In other words, since no additional writing is performed during normal operation, the additional writing operation does not substantially affect the performance of the entire system.

It goes without saying that this embodiment also has the same effect as that of the first embodiment.

[0149] [Modification]

Also in this embodiment, the same modification as that in the first embodiment is possible.

(Fifth embodiment)

FIG. 16 is a block diagram showing a schematic configuration of a resistance variable memory apparatus according to Embodiment 5 of the present invention. Hereinafter, with reference to FIG. 16, an outline of the configuration and operation of the resistance change storage device according to the present embodiment will be described. Note that the resistance change type storage device of the fifth embodiment is a power down sequence control circuit of the resistance change type storage device of the fourth embodiment. The one-on-sequence control circuit is replaced, and other configurations are the same as those in the fourth embodiment. Therefore, common components are given the same names and description thereof is omitted.

[0150] The No.1 on-sequence control circuit 524 (additional write sequence control device) is a circuit incorporated in the control circuit 502, and performs an additional write operation when the resistance change memory device 500 is powered on. It is. The resistance change type storage device 500 is driven by electric power supplied from the outside. When the switch of the system (equivalent to system 190 in FIG. 2) is turned on and the power is turned on, the system power is also supplied to the control unit (equivalent to control unit 180 in FIG. 2) and the resistance change type storage device 500. Is started. The power-on sequence control circuit 524 detects the start of power supply, executes a power-on sequence, and additional writing is performed in the operation. Note that the additional write operation in the power-on sequence is the same as the additional write operation in the first embodiment, and a description thereof will be omitted.

[0151] [Effect]

In the present embodiment, additional writing is performed at a time when the power is turned on. Therefore, when the power is turned on, additional writing is performed on all the memory cells including the memory cell in which the writing state is deteriorated, and the data storage stability and reading accuracy are improved. On the other hand, no additional writing is performed after the power is turned on (during normal operation), and all data writing is processed by temporary writing. Therefore, the apparent writing speed is increased. In other words, since additional writing is not performed during normal operation, the additional writing operation does not substantially affect the performance of the entire system.

[0152] Needless to say, this embodiment has the same effects as those of the first embodiment.

[0153] [Modification]

(Sixth embodiment)

FIG. 17 is a block diagram showing a schematic configuration of the resistance variable memory apparatus according to Embodiment 6 of the present invention. Hereinafter, with reference to FIG. 17, the configuration of the resistance change storage device according to the present embodiment. An outline of the operation will be described. Note that the resistance change type storage device of the sixth embodiment is obtained by adding a power down sequence control circuit of the resistance change type storage device of the fourth embodiment to the resistance change type device of the third embodiment. Therefore, the same name is attached | subjected about the component which is common in 3rd Embodiment and 4th Embodiment, and description is abbreviate | omitted.

In the resistance change storage device 600 of the present embodiment, the additional write operation enable signal AP force output from the additional write timer 626 AP power S When it is at the S “H” level, the additional write sequence control circuit Under the control of 624, an additional write operation is performed. In the resistance change memory device 600, an additional write operation is performed under the control of the power-down sequence control circuit 628 when the power is turned off. The details of the operations of the additional write timer 626, the additional write sequence control circuit 624, and the power-down sequence control circuit 628 are the same as those in the third and fourth embodiments, and thus the description thereof is omitted.

[0155] [effect]

In the resistance change type storage device of the present embodiment, periodic additional writing using a timer and additional writing at the time of power-off are used in combination. In such a configuration, additional writing is performed periodically during normal operation, so that data is not accidentally written while the power is on, so that data deterioration occurs due to memory cells. Can be prevented. In addition, since additional writing is performed for all memory cells when the power is turned off, additional writing can be performed before the power is turned off even for memory cells that are temporarily written after the last periodic additional writing. State. Therefore, it is possible to reliably prevent the data storage state from deteriorating to the allowable limit or less (the difference from the reference resistance value is less than the reading guarantee margin) while the power is off. In this way, by combining the components of the third embodiment and the fourth embodiment, it is possible to simultaneously prevent deterioration of the data storage state when the power is turned on and deterioration of the data storage state when the power is turned off.

[0156] Needless to say, this embodiment also has the same effects as those of the third and fourth embodiments.

[0157] [Modification] In the present embodiment, the additional write timer and additional write sequence control circuit of the third embodiment are combined with the power down sequence control circuit of the fourth embodiment. The write timer and additional write sequence control circuit may be combined with the power-on sequence control circuit of the fifth embodiment. Alternatively, the power-down sequence control circuit of the fourth embodiment may be combined with the power-on sequence control circuit of the fifth embodiment.

[0158] Also in this embodiment, the same modification as in the third embodiment is possible.

From the above description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. Details of its structure and Z or function can be substantially changed without departing from the spirit of the present invention.

Industrial applicability

[0159] The nonvolatile memory device according to the present invention is a nonvolatile memory device, a resistance change type data recording medium, and a resistance change type capable of reducing the circuit area where the data writing speed is high and simplifying the device configuration. It is useful as a device and a method for writing data to a resistance variable element.

Claims

The scope of the claims

[1] a nonvolatile memory element whose resistance value changes;

A writing device for writing the multi-value data to the non-volatile memory element by changing the resistance value of the non-volatile memory element to a resistance value corresponding to a value of multi-value data which is data that can take a plurality of values; A non-volatile storage device comprising:

When the value of multi-value data that is written is called the old value and the value of multi-value data to be written is called the new value,

Temporary writing that changes the resistance value of the nonvolatile memory element to a resistance value corresponding to the old value and a resistance value corresponding to the old value and a resistance value corresponding to the new value. A temporary writing device for performing

An additional writing device for performing additional writing to change the resistance value of the nonvolatile memory element changed to the temporary writing resistance value to a resistance value corresponding to the new value;

A nonvolatile storage device comprising: a write switching device for switching between the temporary writing device and the additional writing device to write multi-value data to the nonvolatile storage element.

[2] The difference between the resistance value corresponding to the old value and the temporary write resistance value is 20% to 98% of the difference between the resistance value corresponding to the old value and the resistance value corresponding to the new value. The non-volatile memory device according to claim 1, wherein

[3] The resistance value of the nonvolatile memory element changes according to the cumulative amount of energy input in a predetermined mode,

The nonvolatile memory device according to claim 1, wherein the writing device changes a resistance value of the nonvolatile memory element by inputting energy of the predetermined mode.

[4] The cumulative input amount power of the energy of the predetermined mode is the cumulative application amount of the voltage pulse, and the writing device changes the resistance value by applying the voltage pulse to the nonvolatile memory element. The non-volatile storage device according to claim 3.

[5] The nonvolatile memory element saturates with respect to the cumulative input amount of energy in a predetermined mode. The non-volatile memory device according to claim 3, wherein the resistance value thereof changes.

[6] The nonvolatile memory device according to claim 5, wherein a width of a voltage pulse applied to perform the temporary writing is 60 ns or less.

7. The nonvolatile memory device according to claim 5, wherein a width force of a voltage pulse applied for performing the temporary writing is equal to or less than a width of a voltage pulse applied for performing the reading.

[8] The nonvolatile memory device according to claim 5,

A control device;

A volatile storage device,

A non-volatile device, wherein a width of a voltage pulse applied to perform the temporary writing is set to be equal to or less than a width of a read pulse of the volatile memory device.

[9] The nonvolatile memory device according to [1], wherein a width force of a voltage pulse applied to perform the temporary writing is shorter than a width of a voltage pulse applied to perform the additional writing.

10. The nonvolatile memory device according to claim 9, wherein a voltage force of a voltage pulse applied for performing the temporary writing is equal to a voltage of a voltage pulse applied for performing the additional writing.

11. The nonvolatile memory device according to claim 1, wherein the voltage force of the voltage pulse applied to perform the temporary write is higher than the voltage of the voltage pulse applied to perform the additional write.

12. The nonvolatile memory device according to claim 11, wherein the width force of the voltage pulse applied to perform the temporary writing is equal to the width of the voltage pulse applied to perform the additional writing.

[13] The nonvolatile memory device according to claim 1,

A control device,

A nonvolatile data recording medium, wherein the control device controls the write switching device so as to switch between the temporary writing device and the additional writing device.

[14] A memory cell array comprising the nonvolatile memory element, and a memory cell array having a plurality of memory cell sections each having a plurality of the memory cells; Each of the memory cell sections includes one flag non-volatile memory element, and the flag non-volatile memory element corresponding to the temporary write to the non-volatile memory element belonging to the memory cell section. And a temporary write flag area in which the fact is written to the flag non-volatile memory element when the additional writing is performed to the non-volatile memory element belonging to the memory cell section. The non-volatile storage device according to 1.

[15] The nonvolatile memory device according to claim 14,

A control device,

In the temporary write flag area, the control device determines whether or not the additional write is completed for each memory cell section and is an additional write target memory cell section including a nonvolatile memory element. A determination is made based on the value, and additional writing is performed on the nonvolatile memory element belonging to the additional writing target memory cell section using the data written to the additional writing target memory cell section. Non-volatile data recording media.

[16] The write data storage device according to claim 14, further comprising: a write data storage device that temporarily records data written in at least a part of the nonvolatile storage element belonging to the memory cell section for additional writing. Nonvolatile storage device.

[17] The nonvolatile memory device according to claim 16,

A control device,

In the temporary write flag area, the control device determines whether or not the additional write is completed for each memory cell section and is an additional write target memory cell section including a nonvolatile memory element. Determining based on the value, storing at least part of the data of the additional write target memory cell section in the write data storage device, and using the data stored in the write data storage device, the additional write target memory A non-volatile data recording medium for performing additional writing to the non-volatile storage element belonging to a cell section.

[18] An additional write sequence control circuit for controlling the write switching device so as to switch between the temporary writing device and the additional writing device, The additional write sequence control circuit controls the write switching device to perform the additional write when a control signal input from an external device indicates that a nonvolatile storage device is not selected. The non-volatile storage device according to 1.

[19] The nonvolatile memory device according to claim 18,

A control device,

A non-volatile data recording medium, wherein the control device is the external device.

[20] The additional write execution flag signal output function for prohibiting input of write data from an external device when writing by the additional writing device is performed. Non-volatile storage device.

[21] The nonvolatile memory device according to claim 20,

A control device,

A non-volatile data recording medium in which the control device stops data input to the non-volatile storage device when the additional write execution flag signal output from the non-volatile storage device indicates an input prohibited state.

[22] a control device;

A nonvolatile memory element having a variable resistance value;

A writing device for writing the multi-value data to the non-volatile memory element by changing the resistance value of the non-volatile memory element to a resistance value corresponding to a value of multi-value data which is data that can take a plurality of values; A non-volatile data recording medium having

When the value written in the nonvolatile memory element is updated to the old value force new value, the control device

Temporary writing is performed to change the resistance value of the nonvolatile memory element from the resistance value corresponding to the old value to the temporary writing resistance value between the resistance value corresponding to the old value and the resistance value corresponding to the new value. Control the writing device to do and

Then, the control device Controlling a writing device to perform additional writing to change the resistance value of the nonvolatile memory element changed to the temporary writing resistance value to a resistance value corresponding to the new value;

Non-volatile data recording media.

[23] The control device comprises:

Controlling a writing device to perform temporary writing to the plurality of nonvolatile memory elements;

Then, the control device

23. The nonvolatile data recording medium according to claim 22, wherein a writing device is controlled to perform additional writing to the plurality of nonvolatile storage elements.

[24] A method for writing data to a nonvolatile memory device including a plurality of nonvolatile memory elements,

A resistance value of the nonvolatile memory element is set corresponding to each value of the multi-value data to be written,

When updating an old value written in a plurality of nonvolatile memory elements to a new value, the resistance value of each nonvolatile memory element corresponds to the old value from the resistance value corresponding to the old value. Temporary writing to change to the temporary writing resistance value between the resistance value corresponding to the new value and the resistance value corresponding to the new value,

Then, additional writing is performed to change the resistance value of each of the nonvolatile memory elements from the temporary write resistance value to the resistance value corresponding to the new value.

25. The nonvolatile memory device according to claim 1, further comprising an additional write sequence control device that controls the writing device to perform the additional writing.

26. The nonvolatile memory device according to claim 25, wherein the additional write sequence control device is configured to control the write device to perform the additional write at regular intervals.

27. The nonvolatile memory device according to claim 26, wherein the additional write sequence control device includes a timer that outputs a signal for performing the write operation for a predetermined time period in the period of the predetermined period.

[28] After the predetermined period, the temporary write resistance value and the temporary write resistance value so that a difference between the resistance value of the nonvolatile memory element in the temporarily written state and the resistance value of the reference resistance is equal to or greater than a read guarantee margin. Is set! 27. The nonvolatile memory device according to claim 26.

29. The nonvolatile memory device according to claim 25, wherein the additional write sequence control device is configured to control the write device to perform the additional write when a power supply is turned off.

30. The nonvolatile memory device according to claim 25, wherein the additional write sequence control device is configured to control the write device to perform the additional write when a power supply is turned on.

[31] The additional writing sequence control device controls the writing device that performs the additional writing at regular intervals, and controls the writing device that performs the additional writing when the power is turned off. 26. The nonvolatile memory device according to claim 25, which is configured.

32. The nonvolatile memory device according to claim 31, wherein the additional write sequence control device includes a timer.

[33] After the predetermined period, the predetermined period is set so that a difference between the resistance value of the nonvolatile memory element in the temporarily written state and the resistance value of the reference resistance is equal to or greater than a reading guarantee margin! 32. The nonvolatile memory device according to claim 31.

[34] While the additional write sequence control device controls the write device to perform the additional write, the additional write sequence control device outputs an additional write execution flag signal for prohibiting input of write data by an external device. The nonvolatile memory device according to claim 25, configured as described above.

[35] A memory cell array comprising the nonvolatile memory element, and a memory cell array having a plurality of memory cell sections each having a plurality of the memory cells, A temporary write flag area,

The temporary write flag area includes one flag non-volatile storage element for each memory cell section, and corresponds to the case where the temporary write is performed on the non-volatile storage element belonging to the memory cell section. When the fact is written in the nonvolatile memory element for flag and the additional writing is performed on the nonvolatile memory element belonging to the memory cell section, the fact is written in the corresponding nonvolatile memory element for flag. 26. The nonvolatile memory device according to claim 25, configured to be configured as described above.

36. The nonvolatile memory according to claim 35, wherein the additional write sequence control device is configured to control the write device to perform the additional write based on information written in the temporary write flag area. Sex memory device.