JP5835174B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a first semiconductor chip on which a battery voltage detection analog circuit and an analog circuit using a band gap are formed, and is formed by resin molding.

  A semiconductor device 1 having the configuration shown in FIG. 13 is known. In this semiconductor device 1, a semiconductor chip 2 made of a silicon chip is mounted via a silver paste 4 on an island 3 of a lead frame made of copper, for example. Then, after the electrodes on the upper surface of the semiconductor chip 2 and the lead terminals 5 of the lead frame are connected by the bonding wires 6, the periphery of the semiconductor chip 2 is molded with epoxy resin to form the resin mold layer 7. In the semiconductor chip 2, an analog circuit 2a such as a battery voltage detection circuit or a power supply circuit using a band gap reference voltage is formed, for example, on the upper surface side.

  By the way, in the semiconductor device 1 having the above-described configuration, when subjected to a temperature variation such as a thermal cycle, heat is generated on the upper surface side of the semiconductor chip 2 due to a difference in thermal expansion coefficient between the semiconductor chip 2 and the resin mold layer 7. Stress acts. At the same time, due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the island 3, there is a situation in which a thermal stress different from the upper surface side acts on the lower surface side of the semiconductor chip 2. As described above, since the thermal stress applied to the entire semiconductor chip 2 becomes non-uniform, the semiconductor chip 2 is warped and the characteristics of the transistors constituting the semiconductor chip 2 (analog circuit 2a) are changed. Will occur. For example, in a current mirror circuit, the same characteristics are required for two transistors in a pair, but such a variation in characteristics causes an error in output, leading to a decrease in reliability.

  Therefore, for example, in Patent Document 1, in a semiconductor device having a stack structure in which a second semiconductor chip is mounted on a first semiconductor chip mounted on a wiring board, the first semiconductor chip, the second semiconductor chip, The structure which provides a spacer between is disclosed. At this time, the spacer is made of the same material (silicon) as that of the first semiconductor chip, and the size of the first semiconductor chip on the digital cell is smaller than the formation range of the digital cell. It is provided to overlap.

JP 2008-187076 A

  However, in the configuration of Patent Document 1 described above, no consideration has been given to the stress from below the first semiconductor chip due to the difference in thermal expansion between the wiring board and the first semiconductor chip. In addition, since a spacer is provided on the digital cell of the first semiconductor chip and the resin mold layer is in contact with the upper surface of the analog cell in the first semiconductor chip, the problem of characteristic fluctuation in the analog cell is Still remains. As a result, the configuration of Patent Document 1 cannot sufficiently suppress fluctuations in circuit characteristics of the semiconductor chip due to thermal stress.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to configure a semiconductor chip on which an analog circuit is formed by resin molding, and to change the characteristics of the analog circuit caused by thermal stress. An object of the present invention is to provide a semiconductor device that can be suppressed.

  In order to achieve the above object, the semiconductor device (11, 31, 41, 51, 61, 71, 81, 91) of claim 1 of the present invention is formed by the battery voltage detection analog circuit (12a, 32a, 32b). The first semiconductor chip (12, 32) is formed by resin molding (17, 24), and the analog surface of the first semiconductor chip (12, 32) is formed on the upper surface of the analog chip. A second semiconductor chip (13, 33, 42, 43, 43) made of the same material as the first semiconductor chip (12, 32) is positioned so as to cover the entire formation region of the circuit (12a, 32a, 32b). 62, 72) are arranged via adhesive members (18, 34, 44, 45), and the analog circuits (12a, 32a, 32b) formation region A third semiconductor chip (14, 52, 53, 63, 73) of the same kind and the same thickness as the second semiconductor chip (13, 33, 42, 43, 62) is located so as to cover the body. The adhesive member (18, 34, 44, 45) is characterized by being disposed through the same kind of adhesive member (19.82).

  According to the above configuration, the first semiconductor chip (12, 32) and the first semiconductor chip (12, 32) are formed on the upper surface side of the first semiconductor chip (12, 32) on which the battery voltage detection analog circuit (12a, 32a, 32b) is formed. The second semiconductor chips (13, 33, 42, 43, 62) having the same thermal expansion coefficient are arranged via the adhesive members (18, 34, 44, 45), and the first semiconductor chips (12, 32) are arranged. The third semiconductor chip (14, 52, 53, 63, 73) having the same coefficient of thermal expansion is also disposed on the lower surface side of () via the adhesive member (19.82).

  As a result, the thermal stress applied to the upper and lower surfaces of the first semiconductor chip (12, 32) due to the temperature variation becomes equal, and the influence of the stress on each element constituting the circuit can be made uniform on the upper and lower surfaces. Thus, the characteristic variation difference between the elements can be suppressed. At this time, the second semiconductor chip (13, 33, 42, 43, 62) and the third semiconductor chip (14, 52, 53, 63, 73) are located above and below the first semiconductor chip (12, 32). Since it is provided on both sides so as to cover the entire area where the battery voltage detection analog circuit (12a, 32a, 32b) is formed, it is possible to suppress characteristic fluctuations in the battery voltage detection analog circuit (12a, 32a, 32b). it can.

  Therefore, according to the first aspect of the present invention, the first semiconductor chip (12, 32) on which the battery voltage detection analog circuit (12a, 32a, 32b) is formed is formed by resin molding (17, 24). Therefore, it is possible to suppress the characteristic fluctuation of the battery voltage detection analog circuit (12a, 32a, 32b) due to thermal stress, and to obtain an excellent effect that the reliability can be improved. it can.

  A semiconductor device (21, 31, 41, 51) according to claim 2 of the present invention includes a first semiconductor chip (22, 32) on which an analog circuit (22a, 32a, 32b) using a band gap is formed. The first semiconductor chip (22, 32) covers the entire area where the analog circuit (22a, 32a, 32b) is formed. The second semiconductor chip (13, 33, 42, 43) made of the same kind of material as the first semiconductor chip (22, 32) is positioned via the adhesive member (18, 34, 44, 45). And the second semiconductor chip (22, 32) is also disposed on the lower surface of the first semiconductor chip (22, 32) so as to cover the entire formation region of the analog circuit (22a, 32a, 32b). Semiconductor chip (1 , 33, 42, 43) and a third semiconductor chip (14, 52, 53) of the same type and the same thickness through the same type of adhesive member (19) as the adhesive member (18, 34, 44, 45). It is characterized by being arranged.

  According to the above configuration, the first semiconductor chip (22, 32) is formed on the upper surface side of the first semiconductor chip (22, 32) on which the analog circuit (22a, 32a, 32b) using the band gap is formed. The second semiconductor chip (13, 33, 42, 43) having a thermal expansion coefficient equivalent to that of the first semiconductor chip (22, 32) is disposed via the adhesive member (18, 34, 44, 45). The third semiconductor chip (14, 52, 53) having an equivalent coefficient of thermal expansion is also disposed on the lower surface side of () via an adhesive member (19).

  Thereby, the thermal stress applied to the upper and lower surfaces of the first semiconductor chip (22, 32) due to temperature fluctuation is equalized, and the influence of the stress on the elements constituting the circuit can be made uniform on the upper and lower surfaces. Differences in characteristic variation between elements can be suppressed. At this time, the second semiconductor chip (13, 33, 42, 43) and the third semiconductor chip (14, 52, 53) are on the upper and lower surfaces of the first semiconductor chip (22, 32), and the band Since it is provided so as to cover the entire formation region of the analog circuit (22a, 32a, 32b) using the gap, characteristic fluctuations in the analog circuit (22a, 32a, 32b) using the band gap can be suppressed.

  Therefore, according to the invention of claim 2, the first semiconductor chip (14, 52, 53) on which the analog circuit (22a, 32a, 32b) using the band gap is formed is resin-molded (17, 24). It is possible to suppress the characteristic fluctuation of the analog circuit (22a, 32a, 32b) caused by thermal stress, and to obtain an excellent effect that the reliability can be improved. Can do.

  Examples of the analog circuit using the band gap include a band gap reference voltage circuit, a power supply circuit, a voltage / current sensing circuit, an A / D conversion circuit, and a D / A conversion circuit. In addition, the “resin mold” in the present invention includes a so-called half mold type in which a part of an island (die pad) of the lead frame is exposed on the outer surface of the resin mold layer. Further, as the adhesive member, a special adhesive film used for mounting and laminating semiconductor chips, that is, a well-known DAF (Die Attach Film) or the like can be employed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a longitudinal front view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. Plan view of semiconductor device showing resin mold layer in perspective state The figure which shows the relationship between the detection cell voltage of a battery voltage detection analog circuit, and SOC. FIG. 1 equivalent view showing a second embodiment of the present invention. The figure which shows the experimental result which investigated the temperature characteristic of the power circuit FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. FIG. 1 equivalent view showing a sixth embodiment of the present invention. FIG. 1 equivalent view showing a seventh embodiment of the present invention FIG. 1 equivalent diagram showing an eighth embodiment of the present invention. FIG. 1 equivalent view showing a ninth embodiment of the present invention. 1 equivalent diagram showing a conventional example

  Several embodiments embodying the present invention will be described below with reference to FIGS. In each embodiment described below, parts common to the embodiments are denoted by the same reference numerals, and repeated description is omitted. Further, in the cross-sectional views of the respective semiconductor devices, hatching of the semiconductor chip and the resin mold layer is omitted for convenience.

(1) First Embodiment A first embodiment (corresponding to claim 1) of the present invention will be described with reference to FIGS. 1 and 2 schematically show a configuration of a semiconductor device 11 according to the first embodiment. In this semiconductor device 11, semiconductor chips 12 to 14, which will be described later, are mounted on a lead frame 15 and electrically connected by bonding wires 16 such as Au and Al, and the whole is rectangular, for example, made of epoxy resin. The resin mold layer (package) 17 is sealed with resin.

  The lead frame 15 is formed by punching a thin plate of metal, for example, copper, a rectangular island 15a on which the semiconductor chips 12 to 14 are mounted, and a plurality of lead terminals 15b protruding outside the semiconductor device 11. Are connected to each other by a frame part (connecting part) (not shown) on the outer side. The frame part is cut and removed after resin sealing. Each lead terminal 15b is led out from the side surface of the resin mold layer 17 to the outside and is shaped.

  In this embodiment, on the island 15a, three semiconductor chips, a first semiconductor chip 12, a second semiconductor chip 13, and a third semiconductor chip 14, are provided in a stacked state. Among them, the first semiconductor chip 12 is formed in a rectangular chip shape from, for example, silicon, and is located on the surface (upper surface) side slightly to the right of the center, and a battery voltage detection analog circuit 12a is formed.

  The second semiconductor chip 13 is made of the same material (silicon) as that of the first semiconductor chip 12 and is formed in a rectangular chip shape smaller than the first semiconductor chip 12. In the present embodiment, the second semiconductor chip 13 has a thickness equivalent to that of the first semiconductor chip 12. The second semiconductor chip 13 is positioned so as to cover the entire formation region of the battery voltage detection analog circuit 12a on the upper surface of the first semiconductor chip 12, and is a first DAF (Die Attach Film) as an adhesive member. 18 is bonded. The first DAF 18 is a well-known special adhesive film used for mounting and laminating semiconductor chips.

  The third semiconductor chip 14 is made of the same material (silicon) as the second semiconductor chip 13 and has the same thickness, and is configured in a rectangular chip shape larger than the first semiconductor chip 12. In this case, the third semiconductor chip 14 is positioned so as to cover the entire lower surface side of the first semiconductor chip 12, and a second DAF 19 made of the same material as the first DAF 18 as an adhesive member is provided. Is glued through. The third semiconductor chip 14 is mounted on the island 15a via, for example, silver paste 20.

  As a result, the third semiconductor chip 14 is laminated on the island 15 a via the silver paste 20, and the first semiconductor chip 12 is laminated on the third semiconductor chip 14 via the second DAF 19. The second semiconductor chip 13 is stacked on the first semiconductor chip 12 via the first DAF 18 so as to cover the entire region where the battery voltage detection analog circuit 12a is formed. In addition, as shown in FIG. 2, the electrode part is provided in the peripheral part of the upper surface of each 1st-3rd semiconductor chip 12-14, between the electrode parts of each semiconductor chip 12-14, A bonding wire 16 connects between the electrode portion and each lead terminal 15b.

  Although detailed description is omitted, in manufacturing the semiconductor device 11, for example, the third semiconductor chip 14 is mounted on the island 15a via the silver paste 20, and the third semiconductor chip 14 is mounted on the third semiconductor chip 14. The first semiconductor chip 12 is laminated via the second DAF 19, and the second semiconductor chip 13 is laminated on the first semiconductor chip 12 via the first DAF 18, and then the wire bonding process is performed. Then, the process of the resin mold using a shaping | molding die is performed. It is also possible to perform the semiconductor chip stacking process in the state of a wafer and then cut the chip.

  In the semiconductor device 11 of the present embodiment configured as described above, heat equivalent to that of the first semiconductor chip 12 is formed on the upper surface side of the first semiconductor chip 12 on which the battery voltage detection analog circuit 12a is formed. A second semiconductor chip 13 having an expansion coefficient is disposed via the first DAF 18, and a third semiconductor chip 14 having an equivalent thermal expansion coefficient is also provided on the lower surface side of the first semiconductor chip 12. It is arranged via a second DAF 19 equivalent to the DAF 18.

  As a result, the thermal stress applied to the upper and lower surfaces of the first semiconductor chip 12 becomes equal to the temperature variation of the semiconductor device 11, and the influence of the stress on the battery voltage detection analog circuit 12a is made uniform on the upper and lower surfaces. it can. At this time, the second semiconductor chip 13 and the third semiconductor chip 14 are provided on the upper and lower surfaces of the first semiconductor chip 12 so as to cover the entire formation region of the battery voltage detection analog circuit 12a. The characteristic fluctuation in the battery voltage detection analog circuit 12a can be effectively suppressed.

  Therefore, according to the present embodiment, in the semiconductor device 11 configured by molding the first semiconductor chip 12 in which the battery voltage detection analog circuit 12a is formed in the resin mold layer 17, it is caused by thermal stress. The characteristic fluctuation of the battery voltage detection analog circuit 12a can be suppressed, and as a result, the excellent effect that the reliability can be improved can be obtained.

  Incidentally, FIG. 3 shows the relationship between the cell voltage (V) of the secondary battery (assembled battery) detected by the battery voltage detection analog circuit (battery voltage monitoring circuit) and the SOC (remaining charge:%). It is. Here, in the conventional battery voltage detection analog circuit (semiconductor device), the battery voltage cannot be monitored with such high accuracy, and the SOC is in the range of s1% to s2% (cell voltage is in the range of v1 to v2). It was used in. For this reason, the range of SOC that can be actually used is relatively narrow, and the capacity of the battery cannot be utilized to the maximum.

  On the other hand, in the semiconductor device 11 of the present embodiment, the characteristic fluctuation of the battery voltage detection analog circuit 12a caused by the thermal stress can be effectively suppressed, and the battery voltage can be monitored with high accuracy. We were able to expand the range of use. That is, in this embodiment, in FIG. 3, the range of use can be expanded to the range of s1% to s3% (the range of cell voltages v1 to v3) in SOC, and the battery capacity at the full charge of the secondary battery is further increased. It can be increased and the capacity of the battery can be fully utilized.

(2) Second Embodiment Next, a second embodiment (corresponding to claim 2) of the present invention will be described with reference to FIGS. FIG. 4 shows a semiconductor device 21 according to the second embodiment of the present invention. The difference from the first embodiment is as follows. In other words, in the second embodiment, the first semiconductor chip 22 is formed in a rectangular chip shape from, for example, silicon, and is located on the surface (upper surface) side slightly to the right of the center and uses an analog circuit 22a using a band gap. For example, a power supply circuit is formed.

  On the upper surface side of the first semiconductor chip 22, a second semiconductor chip 13 having the same material and thickness as the first semiconductor chip 22 is located so as to cover the entire formation region of the analog circuit 22 a. These are bonded through the first DAF 18 as an adhesive member. On the lower surface side of the first semiconductor chip 22, a third semiconductor chip 14 having the same thickness and the same material as the second semiconductor chip 13 is positioned so as to cover the entire lower surface side of the first semiconductor chip 22. The first DAF 18 and the second DAF 19 made of the same material are bonded together.

  The lead frame 23 includes a rectangular island 23a on which the semiconductor chips 22, 13, and 14 are mounted, and a plurality of lead terminals 23b protruding outside the semiconductor device 21 (resin mold layer 24). Yes. The third semiconductor chip 14 is mounted on the island 23a via, for example, silver paste 20. The resin mold layer 24 seals the periphery of the semiconductor chips 22, 13, and 14 except for the lower surface of the island 23 a in order to improve heat dissipation, for example, the lower surface of the island 23 a from the resin mold layer 24. It is an exposed so-called half mold type.

  In the semiconductor device 21 having the above-described configuration, a second thermal expansion coefficient equivalent to that of the first semiconductor chip 22 is provided on the upper surface side of the first semiconductor chip 22 on which the analog circuit 22a such as a power supply circuit is formed. The semiconductor chip 13 is arranged via the first DAF 18, and the third semiconductor chip 14 having the same thermal expansion coefficient is also provided on the lower surface side of the first semiconductor chip 22. Arranged via the DAF 19.

  Thereby, the thermal stress applied to the upper and lower surfaces of the first semiconductor chip 22 becomes equal with the temperature fluctuation of the semiconductor device 21, and the influence of the stress on the analog circuit 22a can be made uniform on the upper and lower surfaces. At this time, the second semiconductor chip 13 and the third semiconductor chip 14 are provided on the upper and lower surfaces of the first semiconductor chip 22 so as to cover the entire formation region of the analog circuit 22a. The characteristic fluctuation in 22a can be effectively suppressed.

  Accordingly, as in the first embodiment, in the second embodiment as well, the semiconductor device 21 configured by molding the first semiconductor chip 22 on which the analog circuit 22a is formed in the resin mold layer 24. Thus, it is possible to obtain the excellent effect that the characteristic fluctuation of the analog circuit 22a caused by the thermal stress can be suppressed, and as a result, the reliability can be improved.

  Incidentally, FIG. 5 shows a result of an experiment conducted by the present inventor on the temperature characteristics of the power supply circuit in the semiconductor device 21 including the semiconductor chip 22 in which the power supply circuit is formed as the analog circuit 22a using the band gap. is there. The horizontal axis indicates the temperature (−40 ° C. to 120 ° C.), and the vertical axis indicates the voltage value measured after assembly (resin molding) and the voltage value measured in the semiconductor chip alone (before resin molding) in each semiconductor device. The difference is taken.

  In the figure, A shows the experimental results for the semiconductor device 21 of this example, and B shows the experimental results for the semiconductor device 1 having the configuration shown in FIG. As a reference example, C is a semiconductor device 21 in which the second semiconductor chip 13 and the first DAF 18 are not provided (the third semiconductor chip 14 is provided only on the lower surface side of the first semiconductor chip 22). This is the result of manufacturing the same and experimenting in the same way. D represents an ideal state (a state in which there is no characteristic variation due to temperature).

  As is clear from the experimental results, in the conventional semiconductor device 1 of B, the characteristic fluctuation is particularly large at a low temperature. On the other hand, in the semiconductor device 21 of the present embodiment of A, the characteristic fluctuation can be suppressed very little (about 30% of the conventional example), and it can be almost close to the ideal state of D. Further, in the reference example of C in which the third semiconductor chip 14 is provided only on the lower surface side of the first semiconductor chip 22, an improvement is seen as compared with the conventional example of B, but the results are as good as those of the example of A. Was not obtained. From this, it can be inferred that the second and third semiconductor chips 13 and 14 are arranged on the upper and lower surfaces of the first semiconductor chip 22, respectively, in order to suppress the characteristic fluctuation.

(3) Third to Fifth Embodiments FIG. 6 shows a semiconductor device 31 according to a third embodiment (corresponding to claims 1 and 2) of the present invention. This is different from the first embodiment. That is, in this embodiment, a plurality of, for example, two analog circuits 32a and 32b are formed in the first semiconductor chip 32 in the left and right regions on the surface (upper surface) side. Specific examples of these analog circuits 32a and 32b include, for example, a battery voltage detection analog circuit, a band gap reference voltage circuit, a power supply circuit, a voltage / current sensing circuit, an A / D conversion circuit, a D / A conversion circuit, and the like. An analog circuit using a band gap of

  A second semiconductor chip 33 is bonded to the upper surface side of the first semiconductor chip 32 via a first DAF 34. The second semiconductor chip 33 is formed in a rectangular chip shape slightly smaller than the first semiconductor chip 32 from a material (silicon) of the same type and thickness as the first semiconductor chip 32. The second semiconductor chip 33 is positioned and laminated so as to cover the entire region including (including) both the formation regions of the two analog circuits 32 a and 32 b on the upper surface of the first semiconductor chip 32. On the lower surface side of the first semiconductor chip 32, the third semiconductor chip 14 is positioned so as to cover the entire lower surface side of the first semiconductor chip 32, and is bonded via the second DAF 19. .

  Even with this configuration, the thermal stress applied to the upper and lower surfaces of the first semiconductor chip 32 due to the temperature fluctuation of the semiconductor device 31 is equalized, and the influence of the stress on the analog circuits 32a and 32b can be made uniform on the upper and lower surfaces. it can. At this time, the second semiconductor chip 33 and the third semiconductor chip 14 are provided on the upper and lower surfaces of the first semiconductor chip 32 so as to cover the entire formation region of the analog circuits 32a and 32b. Variations in characteristics in the analog circuits 32a and 32b can be effectively suppressed.

  Accordingly, in the third embodiment, the semiconductor device 31 is formed by molding the first semiconductor chip 32 formed with the plurality of analog circuits 32a and 32b in the resin mold layer 17, and the above-mentioned first As in the first and second embodiments, it is possible to suppress fluctuations in the characteristics of the analog circuits 32a and 32b due to thermal stress, and thus to obtain excellent effects such as improvement in reliability. it can.

  FIG. 7 shows a semiconductor device 41 according to a fourth embodiment (corresponding to claim 3) of the present invention. The fourth embodiment differs from the third embodiment in that the first embodiment On the upper surface of the semiconductor chip 32, a plurality of, for example, two second semiconductor chips 42, 43 are provided on the left and right sides in the drawing, corresponding to the analog circuits 32a, 32b, respectively.

  That is, the second semiconductor chip 42 on the left side in the drawing is made of a material (silicon) of the same type and the same thickness as the first semiconductor chip 32 and is slightly larger than the analog circuit 32a (covers the entire formation region of the analog circuit 32a). It is configured in a rectangular chip shape. The second semiconductor chip 42 is positioned so as to cover the entire formation region of the analog circuit 32 a and is bonded to the upper surface of the first semiconductor chip 32 via the first DAF 44. The second semiconductor chip 43 on the right side in the drawing is made of a material (silicon) of the same type and the same thickness as the first semiconductor chip 32 and is slightly larger than the analog circuit 32b (can cover the entire formation region of the analog circuit 32b). It is configured in a rectangular chip shape. The second semiconductor chip 43 is positioned so as to cover the entire formation region of the analog circuit 32 b and is bonded to the upper surface of the first semiconductor chip 32 via the first DAF 45.

  Also in the fourth embodiment, similarly to the third embodiment, the first semiconductor chip 32 formed with the plurality of analog circuits 32a and 32b may be molded in the resin mold layer 17. In the semiconductor device 41, it is possible to suppress fluctuations in the characteristics of the analog circuits 32a and 32b caused by thermal stress, and thus to obtain excellent effects such as improvement of reliability. In addition, the second semiconductor chips 42 and 43 can be provided only in necessary portions where it is desired to suppress the characteristic fluctuation, and the second semiconductor chips 42 and 43 can be prevented from becoming larger than necessary. .

  FIG. 8 shows a semiconductor device 51 according to a fifth embodiment (corresponding to claim 4) of the present invention, which differs from the fourth embodiment in the following points. That is, in the present embodiment, the lower surface side of the first semiconductor chip 32 corresponds to the plurality of (two left and right in the figure) second semiconductor chips 42 and 43, that is, the analog circuits 32a and 32b. A plurality (two on the left and right in the figure) of third semiconductor chips 52 and 53 are provided so as to cover the lower surface side of the formation region. Note that the two third semiconductor chips 52 and 53 are bonded to the lower surface of the first semiconductor chip 32 via one second DAF 19. These third semiconductor chips 52 and 53 are mounted on the island 15a of the lead frame 15 via silver paste 54, respectively.

  Also in the fifth embodiment, similarly to the fourth embodiment, a semiconductor constituted by molding the first semiconductor chip 32 in which the plurality of analog circuits 32a and 32b are formed in the resin mold layer 17. In the device 51, it is possible to suppress the characteristic fluctuation of the analog circuits 32a and 32b due to the thermal stress, and as a result, it is possible to obtain excellent effects such as improvement of reliability. In addition, the third semiconductor chips 52 and 53 can be provided only in necessary portions where it is desired to suppress the characteristic variation, and the third semiconductor chips 52 and 53 can be prevented from becoming larger than necessary.

(4) Sixth and Seventh Embodiments FIG. 9 shows a semiconductor device 61 according to a sixth embodiment (corresponding to claim 5) of the present invention, which is different from the first embodiment. Is in the following points. That is, on the upper surface of the first semiconductor chip 12 on which the battery voltage detection analog circuit 12a is formed, the second semiconductor chip 62 made of a dummy chip on which no circuit is formed has a region where the battery voltage detection analog circuit 12a is formed. It is located so as to cover the whole, and is bonded via a first DAF 18 as an adhesive member. The second semiconductor chip 62 is configured to cover the entire region where the battery voltage detection analog circuit 12a is formed from a material (silicon) of the same type and thickness as the first semiconductor chip 12.

  Further, on the lower surface of the first semiconductor chip 12, a third semiconductor chip 63 made of a dummy chip in which no circuit is formed is positioned so as to cover the entire lower surface side of the first semiconductor chip 12 and bonded. It is bonded via a second DAF 19 as a member. The third semiconductor chip 63 is made of the same kind of material (silicon) as the second semiconductor chip 13 and has the same thickness, and is configured in a rectangular chip shape larger than the first semiconductor chip 12. The third semiconductor chip 63 is mounted on the island 15 a of the lead frame 15 via the silver paste 20.

  In this case, since the second and third semiconductor chips 62 and 63 are dummy chips, no electrical connection is made between the first semiconductor chip 12 and the lead terminals 15b. Accordingly, the bonding wire 64 is provided so as to connect only the first semiconductor chip 12 and the lead terminal 15b.

  Also in the semiconductor device 61 having the above-described configuration, the thermal stress applied to the first semiconductor chip 12 can be made equal on both the upper and lower surfaces as the temperature fluctuates, and the influence of the stress on the battery voltage detection analog circuit 12a can be reduced. It can be made uniform. Therefore, also in the sixth embodiment, there is a semiconductor device 61 configured by molding the first semiconductor chip 12 on which the battery voltage detection analog circuit 12a is formed in the resin mold layer 17, and the thermal stress is prevented. It is possible to suppress the characteristic variation of the battery voltage detection analog circuit 12a due to this, and to obtain an excellent effect that the reliability can be improved.

  FIG. 10 shows a semiconductor device 71 according to a seventh embodiment (corresponding to claim 6) of the present invention, which differs from the sixth embodiment in the following points. That is, in the present embodiment, the second semiconductor chip 72 made of a dummy chip on which no circuit is formed covers the entire formation region of the battery voltage detection analog circuit 12a on the upper surface of the first semiconductor chip 12. In position, it is bonded via the first DAF 18. Further, on the lower surface of the first semiconductor chip 12, a third semiconductor chip 73 made of a dummy chip on which no circuit is formed is positioned so as to cover the entire lower surface side of the first semiconductor chip 12. The two DAFs 19 are bonded together.

  At this time, the second semiconductor chip 72 is made of the same material (silicon) as that of the first semiconductor chip 12, but the thickness thereof is smaller than that of the first semiconductor chip 12. Further, the third semiconductor chip 73 is also composed of the same kind of material (silicon) as the second semiconductor chip 72 with the same thickness (thinner than the first semiconductor chip 12). In this case, even if the second semiconductor chip 72 and the third semiconductor chip 73 are configured to be relatively thin, it is possible to sufficiently obtain a function of making the thermal stress applied to the first semiconductor chip 12 equal on both the upper and lower surfaces. Has been confirmed.

  Also in the seventh embodiment, similarly to the sixth embodiment, the semiconductor device configured by molding the first semiconductor chip 12 on which the battery voltage detection analog circuit 12a is formed in the resin mold layer 17 71, the characteristic fluctuation of the battery voltage detection analog circuit 12a due to the thermal stress can be suppressed, and as a result, the excellent effect that the reliability can be improved can be obtained. The second semiconductor chip 72 and the third semiconductor chip 73 made of dummy chips are configured to be thinner than the first semiconductor chip 12, so that the semiconductor device 71 can be obtained while obtaining necessary functions and effects. The advantage that the whole can be kept thin can be obtained.

(5) Eighth and Ninth Embodiments and Other Embodiments FIG. 11 shows a semiconductor device 81 according to an eighth embodiment (corresponding to claim 7) of the present invention. The difference from the embodiment is as follows. In other words, in the present embodiment, the second semiconductor chip 13 made of the same material is positioned on the upper surface of the first semiconductor chip 12 so as to cover the entire formation region of the battery voltage detection analog circuit 12a. The DAF 18 is bonded. The third semiconductor chip 14 is positioned on the lower surface of the first semiconductor chip 12 so as to cover the entire lower surface side of the first semiconductor chip 12, and is bonded via the second DAF 82 as an adhesive member. Has been.

  The second DAF 82 is configured by combining two types of adhesive films having different elastic moduli, and as shown by changing the direction of hatching in the figure, the portion corresponding to the formation region of the analog circuit 12a is elastic. The low elastic modulus portion 82a has a relatively low modulus, and the other portion (the peripheral portion of the low elastic modulus portion 82a) is a high elastic modulus portion 82b having a higher elastic modulus.

  That is, in the second DAF 82, the portion (low elasticity portion 82a) corresponding to (projected) the formation area of the analog circuit 12a on the lower surface of the first semiconductor chip 12 is the other portion (high elasticity). The elastic modulus is smaller than that of the rate portion 82b). The low elastic modulus portion 82 a is of the same type as the first DAF 18, that is, the elastic modulus of the low elastic modulus portion 82 a is equivalent to the elastic modulus of the first DAF 18.

  Here, when an adhesive film (DAF) is adopted as an adhesive member for adhering semiconductor chips, a relatively small elastic modulus (soft material) is effective in reducing the generated stress. However, on the other hand, there is a situation where it is desirable that the elastic modulus of the pressure-sensitive adhesive film (DAF) to be used is higher from the viewpoint of the stability of the work in the wire bonding process at the time of assembly.

  In the present embodiment, of the second DAF 82 to be bonded to the third semiconductor chip 14 on the lower surface side of the first semiconductor chip 12, the portion corresponding to the formation region of the analog circuit 12 a is the first DAF 18. Therefore, the influence of stress on the analog circuit 12a can be made uniform on both the upper and lower sides.

  Therefore, according to this embodiment, in the semiconductor device 81 configured by molding the first semiconductor chip 12 in which the analog circuit 12a is formed in the resin mold layer 17, the analog circuit 12a caused by thermal stress is provided. Therefore, it is possible to obtain the excellent effect that the reliability can be improved. In addition, in the second DAF 82, the portion other than the low elastic modulus portion 82a is a high elastic modulus portion 82b having a relatively high elastic modulus (the material is hard). The advantage that the stability in the wire bonding process can be ensured can also be obtained.

  FIG. 12 shows a semiconductor device 91 according to a ninth embodiment (corresponding to claim 7) of the present invention. In this embodiment, similarly to the first embodiment, a battery voltage detection analog circuit 12a is formed on the surface portion of the first semiconductor chip 12 so as to be located on the right side in the drawing. On the right side of the upper surface of the semiconductor chip 12, a second semiconductor chip 13 made of the same kind of material is positioned so as to cover the entire formation region of the analog circuit 12a, and is bonded via a first DAF 18.

  A fourth semiconductor chip 92 is stacked via a third DAF 93 in a region where the analog circuit 12 a on the upper left side in the drawing of the first semiconductor chip 12 does not exist. The third DAF 93 has a relatively high elastic modulus (hard material) compared to the first DAF 18. In other words, the first DAF 18 disposed in the formation region of the analog circuit 12a has a smaller elastic modulus than the third DAF 93 disposed in other portions. A third semiconductor chip 14 is disposed on the lower surface side of the first semiconductor chip 12 via a second DAF 19 made of the same material as the first DAF 18. Further, the fourth semiconductor chip 92 is electrically connected to the lead terminal 15b by a bonding wire 94.

  In the present embodiment, as in the eighth embodiment, the first DAF 18 having the same low elastic modulus is formed on the upper and lower surfaces corresponding to the formation area of the analog circuit 12a of the first semiconductor chip 12, Since the second DAF 19 is arranged, the influence of stress on the analog circuit 12a can be made relatively small and uniform on both the upper and lower surfaces.

  Therefore, according to the present embodiment, in the semiconductor device 91 configured by molding the first semiconductor chip 12 in which the analog circuit 12a is formed in the resin mold layer 17, the analog circuit 12a caused by thermal stress is provided. Therefore, it is possible to obtain the excellent effect that the reliability can be improved. In addition, since the third DAF 93 for bonding the fourth semiconductor chip 92 has a relatively high elastic modulus, the stability of the fourth semiconductor chip 92 portion during assembly in the wire bonding process is improved. The advantage that it can be secured can also be obtained.

  In each of the above embodiments, an analog circuit is provided at one or two locations of the first semiconductor chip. However, an analog circuit may be provided at three or more locations, and the present invention is similarly implemented. can do. In the sixth and seventh embodiments described above, both the second semiconductor chip and the third semiconductor chip are constituted by dummy chips. However, only one of the second and third semiconductor chips is a dummy chip. It is also possible to configure from In addition, for example, the adhesive member is not limited to the DAF, and other adhesive members can be adopted. The present invention is not limited to the embodiments described above and shown in the drawings, and does not depart from the gist. It can be implemented with appropriate modifications within the range.

  In the drawing, 11, 21, 31, 41, 51, 61, 71, 81, 91 are semiconductor devices, 12, 22, 32 are first semiconductor chips, 12a is a battery voltage detection analog circuit, 13, 33, 42, 43 is a second semiconductor chip, 14, 52 and 53 are third semiconductor chips, 17 and 24 are resin mold layers, 18, 34, 44 and 45 are first DAF (adhesive members), and 19 and 82 are first molds. 2 DAF (adhesive member), 22a, 32a and 32b are analog circuits, and 62.63, 72 and 73 are dummy chips.

Claims (7)

A semiconductor device (11, 31, 41, 41) including a first semiconductor chip (12, 32) on which a battery voltage detection analog circuit (12a, 32a, 32b) is formed and formed by resin molding (17, 24). 51, 61, 71, 81, 91),
On the upper surface of the first semiconductor chip (12, 32), the first semiconductor chip (12, 32) and the first semiconductor chip (12, 32) are positioned so as to cover the entire formation region of the analog circuit (12a, 32a, 32b). The second semiconductor chip (13, 33, 42, 43, 62, 72) made of the same material is disposed via the adhesive member (18, 34, 44, 45),
The lower surface side of the first semiconductor chip (12, 32) is also located so as to cover the entire formation region of the analog circuit (12a, 32a, 32b), and the second semiconductor chip (13, 33, 42, 43, 62) and a third semiconductor chip (14, 52, 53, 63, 73) of the same type and the same thickness as the adhesive member (18, 34, 44, 45) of the same type. . 82). A semiconductor device (21, 31,) including a first semiconductor chip (22, 32) in which analog circuits (22a, 32a, 32b) using band gaps are formed and resin molds (17, 24). 41, 51)
On the upper surface of the first semiconductor chip (22, 32), the first semiconductor chip (22, 32) and the first semiconductor chip (22, 32) are positioned so as to cover the entire formation region of the analog circuit (22a, 32a, 32b). Second semiconductor chips (13, 33, 42, 43) made of the same kind of material are arranged via adhesive members (18, 34, 44, 45),
Also on the lower surface side of the first semiconductor chip (22, 32), it is positioned so as to cover the entire formation region of the analog circuit (22a, 32a, 32b), and the second semiconductor chip (13, 33, 42, 43) and a third semiconductor chip (14, 52, 53) of the same type and equivalent thickness are arranged via an adhesive member (19) of the same type as the adhesive member (18, 34, 44, 45). A semiconductor device characterized by that.   In the first semiconductor chip (32), the analog circuits (32a, 32b) are formed at a plurality of locations, and the second semiconductor chip (42, 43) includes the analog circuits (42, 43). The semiconductor device according to claim 1, wherein a plurality of semiconductor devices are provided corresponding to each of 32 a and 32 b). The third semiconductor chip (52, 53), the semiconductor device according to claim 3, wherein the respectively corresponding to a plurality are provided in the plurality of second semiconductor chips (42, 43).
  The second semiconductor chip (62, 72) and / or the third semiconductor chip (63, 73) is a dummy chip in which a circuit is not formed. The semiconductor device described.   Both the second semiconductor chip (72) and the third semiconductor chip (73) are dummy chips in which no circuit is formed, and are thicker than the first semiconductor chip (12, 22, 32). 6. The semiconductor device according to claim 1, wherein the semiconductor device is thin.   The adhesive member (18, 19, 82, 93) is made of an adhesive film, and the portion corresponding to the formation region of the analog circuit (12a) is configured to have a smaller elastic modulus than the other portions. The semiconductor device according to claim 1, wherein:

Images