JP5834647B2 - Lead frame and manufacturing method thereof - Google Patents

Description

  The present invention relates to a lead frame used for mounting a semiconductor element and a method for manufacturing such a lead frame.

  In recent years, mobile devices such as mobile phones have increased. In such a portable device, power consumption increases due to an increase in the functions thereof, and it is a problem to increase the duration of the battery. For this reason, in such a portable device, the battery is increased in capacity, and a power control semiconductor element is arranged for each functional unit of the portable device to save power of the entire portable device. Specifically, for each function of the portable device, a non-insulated DC-DC converter is used together with a power management IC, and a stable voltage is supplied from the immediate side of the functional unit.

  In general, an IC for a converter and an inverter is called a power IC. Since a large current flows through a semiconductor element composed of such a power IC, the back surface thereof serves as a terminal (drain), and the semiconductor element is mounted on a die pad of a lead frame. In this case, for the purpose of improving heat dissipation and reducing connection resistance, a semiconductor element is connected to a die pad with solder.

  On the other hand, thin and small semiconductor devices have been required for portable devices. This is no exception in the power IC semiconductor device used for portable devices. For this reason, the form of the package of the semiconductor device is changing to a thin package with high heat dissipation such as QFN, and accordingly, the die pad for mounting the semiconductor element is also becoming smaller.

Japanese Patent No. 4620584

  As described above, in a semiconductor device for a power IC, a semiconductor element is connected to a die pad by soldering. However, when the die pad becomes small, the amount of solder and connection conditions are used to prevent solder flow. Must be strictly managed. Even if the amount of solder and connection conditions are strictly controlled, solder may flow to the side surface of the die pad and the back surface of the die pad (referred to as solder flow), resulting in not only poor appearance but also package reliability. There is a problem of worsening.

  In addition, in order to reduce the size of semiconductor devices, module packages in which driver ICs and converter ICs are combined into one package have been increasing. In such module packages, the surface where the semiconductor element and the die pad are connected by soldering. There is also a problem that wire bonding is hindered by the solder flow.

  The present invention has been made in consideration of such points, and an object thereof is to provide a lead frame capable of preventing a problem that solder flows to the side surface of the die pad and the back surface of the die pad, and a method of manufacturing the lead frame. And

  The present invention provides a lead frame, a metal die pad including a mounting region on which a semiconductor element is mounted, and a solder outflow prevention region for preventing solder outflow surrounding the mounting region in a band shape, and a lead portion provided around the die pad And the solder outflow prevention region is roughened with respect to the mounting region.

  The present invention is a lead frame characterized in that an Ag plating layer is provided on the mounting region.

  The present invention is the lead frame characterized in that the die pad has an outer region located outside the solder outflow prevention region.

  The present invention is the lead frame characterized in that the solder outflow prevention region corresponds to the periphery of the die pad.

  The present invention is the lead frame characterized in that the die pad has a plurality of mounting areas each surrounded by a solder outflow prevention area.

  The present invention is a lead frame in which a plurality of die pads are provided.

  The present invention relates to a lead frame manufacturing method, a step of preparing a lead frame material having an outer shape of a die pad and a lead portion, a step of forming a plating layer on the entire outer surface of the lead frame material, and an entire outer surface of the lead frame material. The part of the plating layer formed on the surface corresponding to the solder outflow prevention region is partially peeled off, and the area of the lead frame material surface where the plating layer is partially peeled is roughened to form a solder outflow prevention region. A lead frame manufacturing method comprising the steps of: and a step of peeling the entire plating layer.

  The present invention relates to a method for manufacturing a lead frame, a step of preparing a lead frame material having an outer shape of a die pad and a lead portion, and a plating layer having an opening corresponding to a solder outflow prevention region on the outside of the lead frame material A lead frame comprising: a step of roughening a plating layer opening region of the lead frame material surface to form a solder outflow prevention region; and a step of peeling the plating layer entirely. It is a manufacturing method.

  According to the present invention, the die pad is provided with the solder outflow prevention region for preventing the solder outflow surrounding the mounting region in a band shape, and the solder outflow prevention region is roughened with respect to the mounting region. As a result, it is possible to prevent a problem that the solder flows to the side surface of the die pad and the back surface of the die pad.

1 is a plan view showing a lead frame according to a first embodiment of the present invention. Sectional drawing which shows the lead frame by the 1st Embodiment of this invention (II-II sectional view taken on the line of FIG. 1). FIG. 5 is a diagram showing a part of the manufacturing method of the lead frame according to the first embodiment of the present invention. FIG. 5 is a diagram showing a part of the manufacturing method of the lead frame according to the first embodiment of the present invention. FIG. 5 is a diagram showing a part of the manufacturing method of the lead frame according to the first embodiment of the present invention. The figure which shows the some modification of the manufacturing method of a lead frame. The top view which shows the lead frame by the 2nd Embodiment of this invention. The top view which shows the lead frame by the 3rd Embodiment of this invention. The top view which shows the lead frame by the 4th Embodiment of this invention.

First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

Construction of the lead frame initially, to FIG. 1 and FIG. 2, the outline of the lead frame according to the present embodiment. 1 and 2 are views showing a lead frame according to the present embodiment.

  The lead frame 10 shown in FIGS. 1 and 2 is provided with a planar rectangular die pad 11 on which a semiconductor element 21 (virtual line) is mounted, around the die pad 11, and includes the semiconductor element 21 and an external circuit (not shown). And a plurality of elongated leads 12 to be connected.

  Among these, an outer frame 13 that supports the die pad 11 and the lead portion 12 is provided around the lead portion 12. Further, suspension leads 14 are coupled to the four corners of the die pad 11, and the die pad 11 is coupled and supported to the outer frame 13 via the four suspension leads 14.

  Such a lead frame 10 is made of a metal such as copper (Cu) or a copper (Cu) alloy as a whole. The lead frame 10 can have a thickness of 0.05 mm to 0.5 mm, although it depends on the configuration of the semiconductor device to be manufactured.

  On the other hand, the die pad 11 has a planar rectangular mounting area 15 on which the semiconductor element 21 is mounted via a solder portion 22 (virtual line in FIG. 2) and solder outflow prevention for preventing solder outflow surrounding the mounting area 15 in a band shape. Region 16. Further, an outer region 17 is provided outside the solder outflow prevention region 16. The mounting area 15, the solder outflow prevention area 16, and the outer area 17 are formed on the surface side of the die pad 11.

The solder outflow prevention region 16 is roughened with respect to the mounting region 15 and the outer region 17 by roughening the surface (for example, a microetching process described later). That is, the roughness of the solder outflow prevention region 16 is rougher than that of the mounting region 15 and the outer region 17. The average roughness of the solder outflow prevention region 16 can be set to Ra = 0.3 μm to 0.6 μm, for example. The average roughness Ra is an arithmetic average roughness defined in JIS B0601. In FIG. 1, the length (L ₁ , L ₂ ) of one side of the solder outflow prevention region 16 can be determined based on the size of the semiconductor element 21 and the mounting accuracy of the semiconductor element 21. Moreover, the width (w) of the solder outflow prevention area | region 16 can be 0.5 mm-2 mm, for example.

  In FIG. 1, the solder outflow prevention region 16 has a planar annular shape, specifically, a planar rectangular shape, but is not limited thereto, and has, for example, a planar circular shape or a planar polygonal shape. You may do it. In FIG. 1, the width of the solder outflow prevention region 16 is uniform over the entire circumference. However, the width is not limited to this, and the width of the solder outflow prevention region 16 may be uneven depending on the location. For example, in the solder outflow prevention region 16, the width of a portion where solder outflow is particularly desired to be prevented may be increased, and the width of other portions may be decreased. Further, all portions of the die pad 11 other than the mounting region 15 may be used as the solder outflow prevention region 16.

  On the other hand, the mounting area 15 and the outer area 17 maintain a smooth surface without being roughened. The shape of the mounting region 15 is not particularly limited. For example, the mounting region 15 may have substantially the same shape as the outer shape of the semiconductor element 21 corresponding to the shape of the semiconductor element 21 to be mounted. An Ag plating layer 18 is provided on the mounting region 15. Although the thickness of this Ag plating layer 18 is not specifically limited, For example, it is good also as 0.1 micrometer-10 micrometers. By providing the Ag plating layer 18 in this manner, when the semiconductor element 21 is mounted, the bonding property of the solder part 22 to the mounting region 15 can be improved. Further, an Ag plating layer 18a for wire bonding is also provided at the tip of each lead portion 12 (end portion on the die pad 11 side). The thickness of the Ag plating layer 18a is not particularly limited, but may be 0.1 μm to 10 μm, for example, similarly to the Ag plating layer 18 on the mounting region 15.

  In FIG. 1, only one die pad 11 is shown for convenience, but in actuality, a single lead frame 10 is manufactured with a plurality of die pads 11 attached thereto. In FIG. 1, a region S (virtual line) indicates a region corresponding to one semiconductor device in the lead frame 10.

Manufacturing Method of Lead Frame Next, regarding the manufacturing method of the lead frame 10 shown in FIGS. 1 and 2, FIGS. 3 (a)-(d), FIGS. 4 (a)-(f) and FIG. 5 (a)-( This will be described using c).

  First, as shown in FIG. 3A, a flat substrate 31 is prepared. As this board | substrate 31, the board | substrate which consists of metals, such as copper or copper alloy, can be used. In addition, it is preferable to use what the board | substrate 31 performed the degreasing | defatting etc. to the both surfaces, and performed the washing process.

  Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the substrate 31, respectively, and dried (FIG. 3B). As the photosensitive resists 32a and 33a, conventionally known resists can be used.

  Subsequently, the substrate 31 is exposed through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 3C).

  Next, the etching resist layers 32 and 33 are used as an anticorrosion film, and the substrate 31 is etched with an etching solution (FIG. 3D). Thereby, the external shape of the die pad 11 and the lead part 12 is formed. The corrosive liquid can be appropriately selected according to the material of the substrate 31 to be used. For example, when copper is used as the substrate 31, a ferric chloride aqueous solution is usually used and spray etching is performed from both sides of the substrate 31. It can be carried out.

  Next, the etching resist layers 32 and 33 are peeled and removed to obtain the lead frame material 30 having the outer shape of the die pad 11 and the lead portion 12 (not roughened) (FIG. 4A). ). Instead of the steps shown in FIGS. 3A to 3D, the lead frame material 30 may be obtained by pressing and punching the substrate 31 using a mold.

  Next, a plating layer 34 is formed on the entire outer surface (front surface, back surface, and side surfaces) of the lead frame material 30 by electrolytic plating (FIG. 4B). The plating layer 34 serves as a mask for microetching described later, and can be composed of, for example, an Ag plating layer. Furthermore, the plating layer 34 only needs to have a thickness that can withstand micro-etching, and the thinner the better from the viewpoint of production efficiency, the better the thickness can be 0.05 μm to 1 μm. When the plating layer 34 is composed of an Ag plating layer, an electrolytic plating solution containing silver cyanide (AgCN) and potassium cyanide (KCN) as main components can be used.

  Next, the plating layer 34 formed on the entire outer surface of the lead frame material 30 is partially peeled off. In this case, first, the lead frame material 30 on which the plating layer 34 is formed on the entire surface is held by using the jig 37 so as not to touch the electrolytic stripping solution except the portion corresponding to the solder outflow prevention region 16. (FIG. 4C). In the jig 37, an opening 37a is formed in a portion of the lead frame material 30 corresponding to the solder outflow prevention region 16, and only the portion corresponding to the solder outflow prevention region 16 through the opening 37a is used as an electrolytic stripping solution. It comes to touch.

  Thereafter, the lead frame material 30 held by the jig 37 is immersed in an electrolytic stripping solution and energized to partially peel the plating layer 34 corresponding to the solder outflow prevention region 16 of the lead frame material 30 (FIG. 4D). )). After the plating layer 34 is partially peeled in this way, the energization for electrolytic peeling is stopped and the lead frame material 30 is removed from the jig 37. The electrolytic stripper may be any electrolytic stripper that dissolves and strips the plating layer 34 and does not dissolve the lead frame material 30. For example, in order to peel the Ag plating layer, an electrolytic stripping solution containing succinimide as a main component can be used.

  Next, a region of the lead frame material 30 where the plating layer 34 is partially peeled is roughened to form a solder outflow prevention region 16 for preventing solder outflow (FIG. 4E). At this time, a microetching solution is supplied to the lead frame material 30 from which the plating layer 34 has been partially peeled, and a rough surface is formed in a portion of the lead frame material 30 corresponding to the solder outflow prevention region 16. Here, the microetching liquid is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. When the lead frame material 30 made of copper or a copper alloy is roughened, a microetching solution mainly composed of hydrogen peroxide and sulfuric acid is suitable.

  Thereafter, the entire plating layer 34 is peeled off (FIG. 4F). In this case, the entire surface of the lead frame material 30 may be brought into contact with the electrolytic stripping solution, and electrolytic stripping may be performed by the same method as the above-described partial stripping step (FIG. 4D).

  Subsequently, plating resist layers 38 and 39 are provided on the front and back surfaces of the lead frame material 30 (FIG. 5A). Of these, the plating resist layer 38 on the surface side has openings 38a and 38b formed at locations corresponding to the formation sites of the Ag plating layers 18 and 18a. The mounting area 15) is exposed. On the other hand, the plating resist layer 39 on the back surface side covers the entire back surface of the lead frame material 30.

  Next, electrolytic plating is performed on the surface side of the lead frame material 30 covered with the resist layers 38 and 39 for plating (FIG. 5B). As a result, metal (silver) is deposited on the lead frame material 30 to form the Ag plating layers 18 and 18 a on the mounting region 15 of the die pad 11. As an electroplating solution used for forming the Ag plating layers 18 and 18a, a solution containing silver cyanide (AgCN) and potassium cyanide (KCN) as main components can be used.

  Next, the lead resist layer 38 shown in FIGS. 1 and 2 can be obtained by removing the plating resist layers 38 and 39 (FIG. 5C).

Modified Example of Lead Frame Manufacturing Method Next, a modified method of the lead frame 10 manufacturing method will be described with reference to FIGS.

  First, the lead frame material 30 having the outer shape of the die pad 11 and the lead portion 12 is manufactured by the steps shown in FIGS. 3A to 3D described above (FIG. 6A). In addition, as described above, the lead frame material 30 may be manufactured by press working.

  Next, a plating layer 44 having an opening corresponding to the solder outflow prevention region 16 is formed outside the lead frame material 30 (FIGS. 6B to 6D). In this case, first, a portion corresponding to the solder outflow prevention region 16 in the lead frame material 30 is held by the jig 47 (FIG. 6B). The jig 47 holds only the solder outflow prevention region 16 in the lead frame material 30, and the portion other than the portion corresponding to the solder outflow prevention region 16 is exposed to the outside.

  Next, a plating layer 44 is formed by electrolytic plating on the outside of the lead frame material 30 held by the jig 47 (FIG. 6C). In this case, the plating layer 44 is formed on the entire portion of the outside of the lead frame material 30 other than the portion covered with the jig 47. The configuration of the plating layer 44 and the method of forming the plating layer 44 are substantially the same as in the case of the plating layer 34 described above (see FIG. 4B). After forming the plating layer 44 in this way, the lead frame material 30 is removed from the jig 47. At this time, an opening 45 corresponding to the solder outflow prevention region 16 is formed in a portion of the plating layer 44 corresponding to the solder outflow prevention region 16 (that is, a portion covered with the jig 47) (FIG. 6D). ).

  Subsequently, a portion of the surface of the lead frame material 30 exposed from the opening 45 of the plating layer 44 is roughened to form the solder outflow prevention region 16 (FIG. 6E). In this case, a rough surface is formed in a portion corresponding to the solder outflow prevention region 16 of the lead frame material 30 using a microetching solution. Note that the method of roughening the lead frame material 30 with a microetching solution is substantially the same as the above-described step (see FIG. 4E).

  Next, the entire surface of the plating layer 44 is peeled off (FIG. 6F). The method of peeling the entire surface of the plating layer 44 is substantially the same as the above-described step (see FIG. 4F).

  Thereafter, similarly to the steps shown in FIGS. 5A to 5C described above, the Ag plating layers 18 and 18a are formed on the mounting region 15 of the die pad 11 to thereby form the lead frame 10 shown in FIGS. Is obtained.

Operation and Effect of the Present Embodiment Next, the operation of the present embodiment having such a configuration will be described.

  As shown in FIG. 2, in the lead frame 10 according to the present embodiment, the semiconductor element 21 is mounted on the mounting region 15 of the die pad 11 via a solder portion 22 made of a solder material such as a solder paste and bonded. Is done. Thus, when the semiconductor element 21 is joined to the mounting region 15, the solder (solder part 22) is heated and melted.

  According to the present embodiment, the solder outflow prevention region 16 for preventing the solder outflow that surrounds the mounting region 15 in a band shape is provided, and the solder outflow prevention region 16 is roughened with respect to the mounting region 15. Yes. By the way, it is generally known that when the solid surface becomes rough, the surface wetted by the liquid becomes wetter, and the surface that repels the liquid becomes more repellent (Wenzel model). Therefore, in the present embodiment, the melted liquid solder is bounced in the roughened solder outflow prevention region 16 and stays in the mounting region 15 and does not flow outside the solder outflow prevention region 16. Accordingly, it is possible to prevent a problem that the molten solder flows on the side surface of the die pad 11 and the back surface of the die pad 11.

  In particular, when the semiconductor element 21 is made of a power IC, the back surface of the semiconductor element 21 serves as a terminal (drain), and the solder portion 22 extends on the mounting region 15 so as to cover the entire back surface of the semiconductor element 21. According to the present embodiment, even when the semiconductor element 21 is composed of a power IC, the flow of solder is stopped at the solder outflow prevention region 16 and there is no possibility of flowing out to the side surface or the back surface of the die pad 11. Thereby, the appearance defect of the semiconductor device due to the solder flow can be prevented, and the reliability of the semiconductor device can be improved.

  Moreover, according to this Embodiment, the structure for preventing the malfunction which a solder flows into the side surface and back surface of the die pad 11 can be implement | achieved cheaply and easily. Moreover, since the shape of the solder outflow prevention region 16 can be determined by the jigs 37 and 47, the shape of the solder outflow prevention region 16 can be freely set according to the shape of the die pad 11 or the semiconductor element 21. .

  Furthermore, according to the present embodiment, by providing the Ag plating layer 18 on the mounting region 15, the bonding property of the solder part 22 to the mounting region 15 can be favorably maintained.

  Furthermore, according to the present embodiment, since the solder outflow prevention region 16 is provided, there is no possibility that the solder flows on the side surface or the back surface of the die pad 11, so that wire bonding can also be performed on the die pad 11. . Since the number of lead portions 12 can be reduced by the amount of wire bonding to the die pad 11, the semiconductor device can be reduced in size.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing a second embodiment of the present invention. The second embodiment shown in FIG. 7 is different in that the solder outflow prevention region 16 corresponds to the peripheral edge of the die pad 11, and the other configuration is substantially the same as the first embodiment described above. is there. In FIG. 7, the same parts as those in the embodiment shown in FIGS.

  As shown in FIG. 7, in the lead frame 10A according to the present embodiment, the die pad 11 includes a planar rectangular mounting area 15 on which the semiconductor element 21 is mounted, and solder for preventing solder outflow surrounding the mounting area 15 in a band shape. And an outflow prevention region 16. Among these, the solder outflow prevention region 16 is roughened with respect to the mounting region 15 by roughening the surface thereof. In this case, the solder outflow prevention region 16 corresponds to the entire periphery of the die pad 11, and the outer region 17 is not provided outside the solder outflow prevention region 16.

  In addition, since the configuration of the lead frame 10A shown in FIG. 7 is substantially the same as that of the lead frame 10 shown in FIGS. 1 and 2, detailed description thereof is omitted here.

  According to the present embodiment, since the solder outflow prevention region 16 is provided, there is no possibility that the solder flows on the side surface or the back surface of the die pad 11, so that wire bonding can be performed on the die pad 11. Since the number of lead portions 12 can be reduced by the amount of wire bonding to the die pad 11, the semiconductor device can be reduced in size.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a third embodiment of the present invention. The third embodiment shown in FIG. 8 is different in that the die pad 11 has a plurality of solder outflow prevention regions 16a and 16b, and other configurations are substantially the same as those of the first embodiment described above. Are the same. In FIG. 8, the same parts as those in the embodiment shown in FIGS.

  As shown in FIG. 8, in the lead frame 10B according to the present embodiment, a plurality (two) of semiconductor elements 21 are mounted on one die pad 11. In this case, the die pad 11 includes a plurality of mounting regions 15a and 15b on which the semiconductor elements 21 are mounted, and solder outflow prevention regions 16a and 16b for preventing solder outflow that surround the mounting regions 15a and 15b in a band shape. ing. Among these, the solder outflow prevention regions 16a and 16b are roughened with respect to the mounting regions 15a and 15b by roughening their surfaces. Further, an outer region 17 is provided outside the solder outflow prevention regions 16a and 16b.

  In addition, since the configuration of the lead frame 10B shown in FIG. 8 is substantially the same as that of the lead frame 10 shown in FIGS. 1 and 2, detailed description thereof is omitted here.

  According to the present embodiment, since the flow of solder is stopped at each solder outflow prevention region 16a, 16b, even when a plurality of semiconductor elements 21 are mounted on one die pad 11, each semiconductor element 21 is bonded. Soldering solders come into contact with each other, and wetting and spreading of solder due to a synergistic effect can be prevented.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a diagram showing a fourth embodiment of the present invention. The fourth embodiment shown in FIG. 9 is different in that a plurality of die pads 11 are provided. In FIG. 9, the same parts as those of the embodiment shown in FIGS.

  As shown in FIG. 9, the lead frame 10C according to the present embodiment is provided with a plurality of die pads 11a, 11b, and 11c. Of these, the die pads 11a and 11b are planar rectangular mounting areas 15c and 15d on which the semiconductor element 21 is mounted, respectively, and solder outflow prevention areas 16c and 16d for preventing solder outflow surrounding the mounting areas 15c and 15d in a strip shape. Is included. The solder outflow prevention regions 16c and 16d are roughened with respect to the mounting regions 15c and 15d by roughening the surfaces thereof. In this case, the solder outflow prevention regions 16c and 16d correspond to the entire peripheries of 11a and 11b, respectively.

  On the other hand, in FIG. 9, the semiconductor element 21 is not mounted on the die pad 11 c and the solder outflow prevention region is not provided. However, the present invention is not limited thereto, and the die pad 11c may be provided with a mounting region and a solder outflow prevention region, and an additional semiconductor element 21 may be mounted on the mounting region of the die pad 11c.

  In FIG. 9, the die pads 11 a, 11 b, and 11 c are connected to the outer frame 13 by connecting leads 19 that are arranged in parallel with the lead portions 12 in addition to the suspension leads 14. In FIG. 9, the solder outflow prevention regions 16c and 16d are provided in the die pad 11a and the die pad 11b, respectively, so that the solder does not flow out toward the suspension lead 14 and the connecting lead 19.

  In addition, since the configuration of the lead frame 10C shown in FIG. 9 is substantially the same as that of the lead frame 10 shown in FIGS. 1 and 2, detailed description thereof is omitted here.

  According to the present embodiment, since the flow of solder is stopped at the solder outflow prevention regions 16c and 16d, even if the lead frame 10C has a plurality of die pads 11a, 11b, and 11c, the die pads 11a and 11b. , 11c can prevent a problem that the solder flows to the side surface and the back surface. Further, since the solder outflow prevention regions 16c and 16d are provided, there is no possibility that the solder flows to the side surface or the back surface of the die pads 11a and 11b, or the suspension leads 14 and the connecting leads 19, so that the solder pads are also formed on the die pads 11a and 11b. Wire bonding can be performed. Since the number of lead portions 12 can be reduced by the amount of wire bonding to the die pads 11a and 11b, the semiconductor device can be reduced in size.

  7 to 9, the lead frames 10A, 10B, and 10C can be manufactured in the same manner as the manufacturing method shown in FIGS. 3 to 6 described above.

  A plurality of constituent elements disclosed in the above-described embodiment can be appropriately combined as necessary. Or you may delete a some component from all the components shown by the said embodiment. For example, the embodiment shown in FIG. 9 and the embodiment shown in FIG. 8 are combined so that each die pad 11a, 11b shown in FIG. 9 has a plurality of mounting regions each surrounded by a solder outflow prevention region. Also good.

10, 10A-10C Lead frame 11, 11a-11c Die pad 12 Lead part 13 Outer frame 14 Hanging lead 15, 15a-15d Mounting area 16, 16a-16d Solder outflow prevention area 17 Outer area 18, 18a Ag plating layer 21 Semiconductor element 22 Solder part 30 Lead frame material 31 Substrate 34 Plating layer 37 Jig 44 Plating layer 45 Opening 47 Jig

Claims (6)

In the lead frame,
A metal die pad including a mounting region on which a semiconductor element is mounted and a solder outflow prevention region for preventing solder outflow surrounding the mounting region in a strip shape;
A lead portion provided around the die pad,
The solder outflow prevention area is roughened with respect to the mounting area ,
The die pad has an outer region located outside the solder outflow prevention region .   The lead frame according to claim 1, wherein an Ag plating layer is provided on the mounting region. 3. The lead frame according to claim 1, wherein the die pad has a plurality of mounting areas each surrounded by a solder outflow prevention area. The die pad, a lead frame of any one of claims 1 to 3, characterized in that provided in plural. In the manufacturing method of the lead frame according to claim 1,
A step of preparing a lead frame material having an outer shape of a die pad and a lead portion; a step of forming a plating layer on the entire outer surface of the lead frame material;
Of the plating layer formed on the entire outer surface of the lead frame material, a step of partially peeling the portion corresponding to the solder outflow prevention region;
Of the lead frame material surface, the process of roughening the area where the plating layer is partially peeled to form a solder outflow prevention area;
And a step of peeling the entire surface of the plating layer. In the manufacturing method of the lead frame according to claim 1,
A step of preparing a lead frame material having an outer shape of a die pad and a lead portion; a step of forming a plating layer having an opening corresponding to a solder outflow prevention region on the outside of the lead frame material;
Of the lead frame material surface, roughening the opening area of the plating layer, forming a solder outflow prevention area,
And a step of peeling the entire surface of the plating layer.

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