JP5823729B2 - Semiconductor device and data processing system - Google Patents

Description

  The present invention relates to a semiconductor device that detects signals by driving a touch sensor panel having intersection capacitances formed in a matrix, and relates to a technique that is effective when applied to, for example, a touch sensor panel controller.

  The touch sensor panel corresponding to the multi-point touch based on the mutual capacitance method is disposed, for example, such that the drive electrode and the detection electrode are orthogonal to each other with a dielectric interposed therebetween, and the cross coupling capacitance at each intersection constitutes the intersection capacitance. When there is a finger or hand capacitance in the vicinity of the intersection capacitance, the mutual capacitance of the node is reduced by the combined capacitance of the finger or hand. The touch sensor panel controller detects the intersection capacitance at which this change in mutual capacitance occurs, and sequentially drives the drive electrodes to perform charge operation in units of pulses, and changes in the charge charges are detected via the detection electrodes. The signal corresponding to the change in the mutual capacitance of the intersection capacitances arranged in a matrix is acquired by repeating the sequential detection operation. For example, Patent Document 1 discloses a controller that detects a signal by driving a touch sensor panel using such a mutual capacitance method.

US Patent Publication No. 2007 / 0257890A1

  The present inventor has paid attention to the fact that the storage capacity of the work RAM or buffer RAM used for signal detection is remarkably increased as the touch sensor panel becomes larger. In order to perform an operation of removing noise components by digital filter processing such as FIR (Finite Impulse Response Filter) on the detected signal, a detection signal detected by scanning the entire surface of the touch sensor panel according to the filter order. This is because it is necessary to store frames (detection signal distribution data) in a RAM over a plurality of time-series frames.

  However, if the microprocessor that performs the digital filter operation or the like is a microprocessor for a subsystem specialized in the control of the touch sensor panel controller as a sensor IC or the like, if the microprocessor requires a large RAM Accordingly, it has been found by the present inventor that it is necessary to use a microprocessor whose peripheral functions and data processing capabilities are increased accordingly, which contributes to an increase in cost.

  In addition, as the size of the touch sensor panel increases, the burden of the RAM access control by the microprocessor unit increases. Therefore, if the detection response of the touch event that occurs in the touch sensor panel is to be maintained well, the data processing capability is reduced. A high microprocessor unit must be adopted, which also contributes to an increase in cost.

  An object of the present invention is to provide a semiconductor device capable of improving the detection accuracy of a contact event that occurs on a touch sensor panel at a reduced cost.

  Another object of the present invention is to provide a data processing system that can reduce the burden on a microprocessor unit that processes detection signals from a touch sensor panel.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the intersection capacitances formed in a matrix on the touch sensor panel are scanned and driven through the scanning electrodes, and signals are sequentially acquired from the scanned and driven intersection capacitances through the detection electrodes, and the obtained signals are written to the memory unit. In addition, when the written signal is read from the memory unit, read control for reading the acquired signal from the memory unit in a predetermined order is performed for each of a plurality of acquired signals related to the same intersection capacity.

  As described above, an access control function for reading detection signals in an order suitable for digital filter operation is provided, so that the load on the circuit performing the digital filter operation is reduced and the data processing capability such as digital filter operation is substantially improved. To do.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to improve the detection accuracy of the contact event that occurs on the touch sensor panel while reducing the cost.

  It is possible to reduce the burden on the microprocessor unit that processes the detection signal from the touch sensor panel.

FIG. 1 is a block diagram illustrating a data processing system such as a portable terminal to which a touch sensor panel controller according to an embodiment of the invention is applied. FIG. 2 is an explanatory diagram illustrating a principle configuration for driving and detecting the touch sensor panel. FIG. 3 is a block diagram illustrating a specific configuration of the touch sensor panel controller and the microprocessor. FIG. 4 is an explanatory view exemplifying an address generation form in the write control by the sequence control circuit. FIG. 5 is a timing chart relating to the write operation of FIG. FIG. 6 is an explanatory view exemplifying an address generation form in read control by read access control. FIG. 7 is a timing chart relating to the read operation of FIG. FIG. 8 is a block diagram illustrating a circuit configuration for write control by the sequence control circuit and read control by the read access control circuit. FIG. 9 is an explanatory diagram illustrating the control logic of the sequence logic SQNCLGC for write control by the sequence control circuit and read control by the read access control circuit. FIG. 10 is a block diagram illustrating a data processing system such as a portable terminal to which a touch sensor panel controller according to another embodiment of the present invention is applied. FIG. 11 is a block diagram illustrating a data processing system such as a portable terminal to which the touch sensor panel controller 1 according to still another embodiment of the present invention is applied.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Reading detection signals related to the same intersection capacity from the memory in time series>
A semiconductor device according to a representative embodiment of the present invention scans and drives the scan electrodes of the touch sensor panel (3) in which intersection capacitances (Cc) are formed at a plurality of intersections by a plurality of drive electrodes and detection electrodes. , A detection unit (100) that sequentially acquires signals from the detection electrodes via a scan-driven intersection capacitance, a memory unit (110) that stores an acquisition signal acquired by the detection unit, and writing to the memory unit And a control unit (120) for controlling reading. The said control part performs the read-out control which reads the said acquisition signal from the said memory part in the predetermined order for every several acquisition signal which concerns on the same intersection capacity | capacitance.

  As described above, an access control function for reading detection signals in an order suitable for digital filter operation is provided, so that the load on the circuit performing the digital filter operation is reduced and the data processing capability such as digital filter operation is substantially improved. To do. Therefore, it is possible to improve the detection accuracy of the contact event that occurs on the touch sensor panel while reducing the cost. In addition, the burden on the microprocessor unit that processes the detection signal from the touch sensor panel can be reduced.

[2] <Wrap around selection of data for each same intersection capacity in read control>
In the semiconductor device according to Item 1, the memory unit includes a plurality of memory areas (RAM0 to RAM3). The control unit stores the acquisition signal in a different memory area in a time series for each of a plurality of scan driving operations that make a round of the entire touch sensor panel, and in the readout control, a predetermined value is acquired for each acquisition signal related to the same intersection capacity. The memory areas are selected in order for wraparound.

  As described above, the read control for reading out the acquired signal from the memory unit for each acquired signal related to the same intersection capacity can be easily realized by the memory area selection control.

[3] <Read control is performed asynchronously with writing of a new detection signal>
In the semiconductor device according to Item 2, the memory unit has more memory areas than the number of memory areas selected in the wraparound. The control unit performs the read control in parallel with the write control for writing the acquisition signal acquired by the detection unit into the memory unit.

  As described above, since the acquisition signal write control to the memory unit can be performed in parallel with the acquisition signal read control, the digital filter operation using the read signal can be efficiently performed without interruption. .

[4] <Current acquisition data is written in one memory area, and a plurality of written memory areas are allocated to wraparound selective reading>
In the semiconductor device according to Item 3, in the write control, the control unit stores the acquisition signal in a time series in a different memory area for each of a plurality of scan driving operations that make a round of the entire touch sensor panel. In the read control, the selection of a plurality of memory areas that have already been written is wrapped around in a predetermined order for each acquired signal related to the same intersection capacity. Switch to control.

  As described above, the memory area to which the acquisition signal is to be written is controlled to be switched to wrap around in units of the acquisition signal frame, and the memory area from which the acquisition signal is read for each acquisition signal related to the same intersection capacity is determined in a predetermined order for each reading. Therefore, the switching control of the memory area in the write control and the read control can be easily realized.

[5] <Digital filter operation with on-chip microprocessor unit>
The semiconductor device according to Item 1, further comprising a microprocessor unit (2) that performs digital filter operation using the acquired signal read from the memory unit.

  From the above, the system on chip of the semiconductor device can contribute to the miniaturization of the system.

[6] <Reading detection signals related to the same intersection capacity from the memory in time series>
A data processing system according to another embodiment of the present invention includes a touch sensor panel (3) in which intersection capacitances are formed at a plurality of intersections by a plurality of drive electrodes and detection electrodes, and the drive electrodes are scanned and driven. A touch sensor panel controller (1) that sequentially acquires signals from the detection electrodes, and a microprocessor unit (2) connected to the touch sensor panel controller. The touch sensor panel controller includes a memory unit (110) that stores acquisition signals sequentially acquired by scanning and driving the intersection capacitance (Cc), and a control unit (110) that controls writing to and reading from the memory unit, Have The said control part performs the read-out control which reads the said acquisition signal from the said memory part in the predetermined order for every several acquisition signal which concerns on the same intersection capacity | capacitance.

  As described above, since the touch sensor panel controller has an access control function for reading out detection signals in an order suitable for digital filter calculation, the burden on the microprocessor unit performing digital filter calculation is reduced, and the digital filter by the microprocessor unit is reduced. Data processing capability such as computation is substantially improved. Therefore, it is possible to improve the detection accuracy of the contact event that occurs on the touch sensor panel while reducing the cost. In addition, the burden on the microprocessor unit that processes the detection signal from the touch sensor panel can be reduced.

[7] <Wrap around selection of data for each intersection capacity in read control>
In the data processing system according to item 6, the memory unit includes a plurality of memory areas (RAM0 to RAM3). The control unit stores the acquired signal in a time series in different memory areas for each of a plurality of scan driving operations that make a round of the entire touch sensor panel, and in the readout control, for each of a plurality of acquired signals related to the same intersection capacity. The memory area is selected in a predetermined order for wraparound.

  As described above, the read control for reading out the acquired signal from the memory unit for each of the plurality of acquired signals related to the same intersection capacity can be easily realized by the memory area selection control.

[8] <Read control is performed asynchronously with writing of a new detection signal>
In the data processing system according to item 7, the memory unit has a memory area larger than the number of memory areas selected in the wraparound. The control unit performs the read control in parallel with the write control for writing the acquisition signal acquired by the detection unit into the memory unit.

  As described above, since the acquisition signal write control to the memory unit can be performed in parallel with the acquisition signal read control, the digital filter operation using the read signal can be efficiently performed without interruption. .

[9] <Current acquisition data is written in one memory area, and a plurality of written memory areas are assigned to wraparound selective reading>
In the data processing system according to item 8, in the write control, the control unit stores the acquisition signal in a time series in a different memory area for each of a plurality of scan driving operations that make a round of the entire touch sensor panel. In the read control, the selection of a plurality of memory areas that have already been written is performed in a predetermined order for each of a plurality of acquisition signals related to the same intersection capacity. To switch to wraparound.

  As described above, the memory area to which the acquisition signal is to be written is controlled to be switched to wrap around for each frame of the acquisition signal, and the memory area from which the acquisition signal is read for each of the plurality of acquisition signals related to the same intersection capacity is wrapped for each reading. Since the switching control is performed around, the memory area switching control in the writing control and the reading control can be easily realized.

[10] <Digital filter operation with on-chip microprocessor unit>
The data processing system according to Item 7, wherein the microprocessor unit performs a digital filter operation using an acquisition signal received from the touch sensor panel controller, and coordinates on the touch sensor panel where a contact event has occurred based on the operation result. Is calculated.

  From the above, it is possible to contribute to a higher copy ratio between the digital filter calculation by the microprocessor unit and the coordinate calculation on the touch sensor panel in which the touch event has occurred.

[11] <DISP>
In the data processing system according to item 10, the touch sensor panel has transparency. It further has a bitmap display (4) arranged under the touch sensor panel and a display driver (6) for performing display driving on the bitmap display.

  Drive control of the touch sensor panel and detection of a touch event can be performed integrally with the display.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates a data processing system such as a portable terminal to which a touch sensor panel controller (TPC) 1 according to an embodiment of the present invention is applied. The touch sensor panel controller 1 drives the touch sensor panel (TCHPNL) 3 based on the control of the subsystem microprocessor (MPU) 2 and sequentially acquires signals from the intersection capacitance of the intersection of the drive electrode and the detection electrode. The accumulated signals are returned to the microprocessor 2 in an order suitable for the digital filter operation. Although not particularly limited, the touch panel controller 1 and the microprocessor 2 constituting the touch sensing subsystem are formed on separate semiconductor substrates such as single crystal silicon by a CMOS integrated circuit manufacturing technique.

  The touch sensor panel 3 is configured using a transmissive (translucent) electrode or a dielectric film, and is disposed, for example, on the display surface of a liquid crystal display (LCDDSP) 4 in a bitmap display form. The host processor (HST) 5 generates display data, and the liquid crystal display driver (LCDDRV) 6 performs display control for displaying the display data received from the host processor 5 on the liquid crystal display 4.

  The microprocessor 2 performs a digital filter operation on the signal received from the touch sensor panel controller 1, and calculates coordinates when a touch event occurs on the touch sensor panel 1 based on the signal from which the noise has been removed. To the host processor 5. For example, the host processor 5 analyzes the input by the touch sensor panel 1 from the relationship between the display screen given to the liquid crystal display driver 6 and the coordinate data given from the microprocessor 2.

  FIG. 2 illustrates a principle configuration for driving and detecting the touch sensor panel. The touch sensor panel 3 corresponds to multi-point touch by a mutual capacitance method. For example, the drive electrode Lx and the detection electrode Ly are arranged so as to be orthogonal to each other with a dielectric (not shown) interposed therebetween. The coupling capacitance Cc constitutes the intersection capacitance. FIG. 2 representatively shows one place. An integration circuit using the operational amplifier AMP as a virtual ground amplifier is configured for the detection electrode Ly, and Cfb is an integration capacitor. If there is a finger or hand capacitance in the vicinity of the intersection capacitance Cc, the mutual capacitance of the intersection capacitance Cc decreases by the combined capacitance of the finger or hand. In order to detect at which intersection capacitance Cc this change in mutual capacitance has occurred, the touch sensor panel controller 1 sequentially drives the drive electrodes Lx with an AC pulse to perform charging operation in units of pulses, and charge charges (mutual capacitance). The operation of accumulating the change in the product of the pulse drive voltage in the integration capacitor Cfb in units of pulses from the detection electrode Ly is repeated each time the drive electrode Lx driven by the AC pulse is switched. As a result, a signal corresponding to a change in mutual capacitance of the intersection capacitance Cc arranged in a matrix is acquired as an accumulated charge signal by the integration circuit of each detection electrode Ly every time the drive electrode Lx driven by the AC pulse is switched.

  FIG. 3 illustrates specific configurations of the touch sensor panel controller 1 and the microprocessor 2. The touch sensor panel controller 1 includes a detection unit (SNSU) 100, a memory unit (MRY) 110, a control unit (CNTU) 120, and a processor interface unit (MPIF) 130.

  The detection unit 100 includes a driver (DRV) 101 for scanning and driving the intersection capacitors formed in a matrix on the touch sensor panel, a detection circuit (SNS) 102 and a detection circuit for sequentially obtaining detection signals from the scanned and driven intersection capacitors. An AD conversion circuit (ADC) 103 that converts the signal detected at 102 into a digital signal is provided.

  The driver 101 sequentially drives the drive electrodes Lx illustrated in FIG. 2 with a pal voltage in accordance with control from the control unit 120. The number of drive pulses is at least the number of detection electrodes Ly.

  The detection circuit 102 outputs a detection signal from the operational amplifier AMP while switching the detection electrode Ly in units of pulses in synchronization with the pulse drive of the drive electrode Lx.

  The AD conversion circuit 103 converts the output of the operational amplifier AMP into a digital signal in units of pulses and outputs the digital signal to the memory unit 110.

  The memory unit 110 includes, for example, four memory areas RAM0 to RAM3 as memory areas which are a plurality of random access memory areas that store digital signals output from the AD conversion circuit 103 in synchronization with the detection operation. The memory areas RAM0 to RAM3 may be constituted by different memory mats with a common peripheral circuit, or may be constituted by a plurality of memory modules in which the peripheral circuits are individualized. For example, the memory unit 110 may have a dual access port that can parallelize write access and read access to one of the different memory areas of the memory areas RAM0 to RAM3. Although details will be described later, the memory areas RAM0,..., RAM3 are switched in units of digital signals obtained by scanning the entire surface of the touch sensor panel 3 by driving the electrode Lx and detecting the electrode Ly with respect to the touch sensor panel 3. Digital data is stored in the memory areas RAM0 to RAM3. The provision of the four memory areas RAM0 to RAM3 assumes that data necessary for, for example, the second-order FIR filter operation can be accumulated.

  The control unit 120 includes a sequence control circuit (SQNCCNT) 121, a read access control circuit (RACCNT) 122, and a register circuit (REGC) 123. The sequence control circuit 121 performs drive timing control of the electrode Lx and detection timing control of the electrode Ly with respect to the detection unit 100, and write control for writing a digital signal output from the AD conversion circuit 103 to the memory unit 110 in synchronization with the detection operation. And so on. The read access control circuit 122 performs control to read out the data in the three memory areas that have been written in an order suitable for the secondary FIR filter calculation. In the register circuit 123, the start address of the memory areas RAM0 to RAM3 is set by the microprocessor 2.

  The processor interface unit (MPIF) 130 performs command input and data input / output with the microprocessor 2, and the input command and other control data are given to the control unit 120 and detected from the memory unit 110. Data is provided to the microprocessor 2.

  The microprocessor 2 is not particularly limited, but the CPU (central processing unit) 200 sequentially fetches the program in the flash memory (FROM) 204 connected via the bus bridge (BBRDG) 203 and performs predetermined data processing. The RAM 205 is used as a work memory for data processing, and a timer (TMR) 207 is used when a timer / counter operation is required. Command output and detection data input to the touch sensor panel controller 1 are performed via a parallel input / output circuit (GPIO) 206. High-speed serial communication may be used instead of the parallel input / output circuit (GPIO). The microprocessor 2 is operated in synchronization with the clock signal generated by the clock generation circuit (CPG) 202 using the oscillation frequency of the vibrator. Interrupt control is performed by the interrupt controller (INTC) 201, and a reset function by the watchdog timer (WDT) 208 can be used for the runaway of the CPU 200. The host processor 5 is connected via a serial interface circuit (I2C) 209. The data processing by the CPU 200 is, for example, FIR filter calculation using detection data supplied from the touch sensor panel controller 1, and calculation processing of coordinates for generating a contact event based on the calculation result data.

  Hereinafter, writing and reading control with respect to the memory unit 110 by the control unit 120 of the touch sensor panel controller 1 will be described in detail. Here, as described above, the case corresponding to the second-order FIR filter calculation is taken as an example, and new detection data is sequentially applied to one memory area sequentially selected from the four memory areas RAM0 to RAM3. The sequence control circuit 121 performs the write control to accumulate, and performs control to read the detection data in time series for each detection data related to the same intersection capacity from the three memory areas in which the detection data for the past three planes have already been written. Performed by the read access control circuit 122.

  As the write control, the sequence control circuit 121 generates a head address for selecting one of the memory areas RAM0 to RAM3, and uses this as a base point to determine the number of intersection capacitances of the touch sensor panel 3. The write address is generated by incrementing the address by an equal number. For example, detection data is sequentially written from the head address A3 to one memory area RAM3 selected as illustrated in FIGS. When X3 is a row address and Y3 is a column address, if the leading address A3 is X3 = 0 and Y3 = 0, the write address is (X3 = 0, Y3 = 0), (X3 = 1, The memory area RAM3 is enabled for writing (write selection) each time it is changed to (Y3 = 0), (X3 = 2, Y3 = 0),.

  The address increment of the write address starting from the head address is performed in synchronization with the timing at which the detection signal is obtained from the detection electrode Ly by pulse driving with respect to the drive electrode Lx. The top address is updated each time a detection signal is acquired by scanning the entire surface of the touch sensor panel 3 by driving the electrode Lx with respect to the touch sensor panel 3 and detecting the electrode Ly. For example, when the top addresses of the memory areas RAM0 to RAM3 are A0, A1, A2, and A3, the top addresses are changed in wraparound order. That is, when the head address is changed to A3, the head address is changed to address A0 again.

  As the read control, the read access control circuit 122 generates a common local memory address for the three memory areas that follow the wraparound after the one memory area selected as the write control target, and generates the generated one memory area. One local address is added to each of the top addresses of the three memory areas, thereby generating a memory read address for sequentially selecting a plurality of detection data relating to the same intersection capacity. For example, as shown in FIGS. 6 and 7, when three memory areas RAM0 to RAM2 are subjected to read control, the read addresses for these areas are A0 + 1, A1 + 1 starting from the top addresses A0, A1, A2. , A2 + 1, A0 + 2, A1 + 2, A2 + 2,. When X0, X1, and X2 are the RAM area RAM0, RAM1, and RAM2 row addresses, and Y0, Y1, and Y2 are the column addresses of the RAM areas RAM0, RAM1, and RAM2, the head address A0 is X0 = 0, Y0 = 0, the head address Assuming that A1 is X1 = 0, Y1 = 0, and the head address A2 is X2 = 0, Y2 = 0, the read address is (X0 = 0, Y0 = 0) and (X1 = 0, Y1 = 0), (X2 = 0, Y2 = 0), (X0 = 1, Y0 = 0),..., The memory area is sequentially read-enabled around RAM0, RAM1, and RAM3 (read selection) ).

  Read data D (A0) at address A0 is the secondary delay data of the first detection node that is the head, read data D (A1) of address A1 is the primary delay data of the first detection node that is the head, and readout of address A2 Data D (A2) is used for the FIR filter calculation as 0th-order delay data of the first detection node that is the head. Similarly, the read data D (A0 + 1) at the address A0 + 1 is the secondary delay data at the second detection node, the read data D at the address A1 + 1 is the primary delay data at the second detection node, and the read data D (at the address A2 + 1). A2 + 1) is used for the FIR filter calculation as 0th-order delay data of the second detection node. The read timing may be performed asynchronously with the detection timing for writing. That is, it may be performed at a timing according to the data processing capability of the microprocessor unit 2 that performs FIR filter calculation and the like. However, the read control must be started when the detection data is ready in the three memory areas. The order of reading may be 0th order, 1st order, 2nd order, or the like, as long as it corresponds to the coefficient by which each delay data is multiplied by FIR filter calculation.

  FIG. 8 illustrates a circuit configuration for write control by the sequence control circuit 121 and read control by the read access control circuit 122.

  The register circuit 123 includes start address registers SAREG0 to SAREG3 in which the start addresses A0 to A3 of the memory areas RAM0 to RAM3 are designated, and a count width register CUNTWDT. In the count width register CUNTWDT, a number (CUNTWDT #) equal to the number of intersection capacitors arranged in a matrix on the touch sensor panel 3 is set.

  The sequence control circuit 121 includes a selector WSLCT, a write address counter WACOUNT and an address adder WAADD to generate the write address. The write address counter WACUNT counts the count clock WCLK, and adds the head address selected by the selector WSDLCT to the count value WACUNT # by the adder WAADD to generate the write address WADDRS.

  The read address control circuit 122 includes a selector RSLCT, a read address counter RACUNT, and an address adder RADD to generate the read address. The read address counter RACUNT counts the count clock RCLK, and the adder RADD adds the start address selected by the selector RSLCT to the count value RACUNT # to generate a read address RADDRS.

  The sequence logic SQNCLGC starts address generation control in synchronization with the clock CLK when the address generation start signal STRT is activated. The sequence logic SQNCLGC receives the address count values RACUNT #, WACUNT #, and the count width CUNTWDT #, and generates the selector RSLCT selection signal RSTS and the read clock RCLK according to the input values, and also selects the selector WSLCT selection signal WSTS. And write clock WCLK.

  FIG. 9 illustrates the control logic of the sequence logic SQNCLGC for write control by the sequence control circuit 121 and read control by the read access control circuit 122. When the address generation operation is started, the access states ACSTS0 to ACSTS3 of FIG. 9 are repeated as the states of the memory areas RAM0 to RAM3. The access state ACSTS0 is a state in which the memory areas RAM0 to RAM2 are read (READ) and the memory area RAM3 is written (WRITE). The access state ACSTS1 is a state in which the memory areas RAM1 to RAM3 are read (READ) and the memory area RAM0 is written (WRITE). The access state ACSTS2 is a state in which the memory areas RAM0, RAM2, and RAM3 are read (READ) and the memory area RAM1 is written (WRITE). The access state ACSTS3 is a state in which the memory areas RAM0, RAM1, and RAM3 are read (READ) and the memory area RAM2 is written (WRITE).

  In the access state ACSTS0, the read access mode (RDSTS0) is a state in which the start addresses A0, A1, and A2 are selected to wrap around and the read addresses A0 to A2 + ai are generated. Similarly, in the access state ACSTS0, the write access mode (WTTSTS0) is set to a state in which addresses from the start address A3 to A3 + ai are generated. Here, ai is the count width CUNTWDT # of the counters RACUNT and WACUNT, and ra is the direction of the wraparound selection of the top address.

  In the access state ACSTS1, the read access mode (RDSTS1) is a state in which the start addresses A1, A2, and A3 are selected to wrap around and the read addresses A1 to A3 + ai are generated. Similarly, in the access state ACSTS1, the write access mode (WTSTS1) is a state in which addresses from A0 + ai starting from the start address A0 are generated.

  In the access state ACSTS2, the read access mode (RDSTS2) is a state in which the start addresses A2, A3, A0 are selected to wrap around and the read addresses A2 to A0 + ai are generated. Similarly, in the access state ACSTS2, the write access mode (WTSTS2) is a state in which addresses from the start address A1 to A1 + ai are generated.

  In the access state ACSTS3, the read access mode (RDSTS3) is a state in which the start addresses A3, A0, A1 are selected to wrap around and the read addresses A3 to A1 + ai are generated. Similarly, in the access state ACSTS3, the write access mode (WTTSTS3) is a state in which addresses from the start address A2 to A2 + ai are generated.

  In order to first read the detected data by the read access mode RDSTS0, first, the write access modes WTSTS1 to WTSTS3 must be executed to store the detected data in the memory areas RAM0 to RAM2. Thereafter, the control of the access states ACSTS0, ACSTS1, ACSTS2, and ACSTS3 may be repeated in wraparound.

  The sequence logic SQNCLGC includes logic for realizing such a control sequence. When the address generation start signal STRT is activated, the sequence logic SQNCLGC selects the address A0 as the selection signal WSTS for the selector WSLCT to realize the write access form WTSTS1, and generates the write clock WCLK in synchronization with the clock CLK. The operation of sequentially generating the write address WADDRS by adding the count value WACOUNT # to A0 is continued until WACOUNT # becomes COUNTWDT #. Similarly, write access modes WTSTS2 and WTSTS3 are realized, and the detection data is stored in the memory areas RAM0 to RAM2. Thereafter, the sequence logic SQNCLGC realizes the read access form RDSTS0 and the write access form WTSTS0. In other words, the sequence logic SQNCLCC selects the address A3 by the selection signal WSTS for the selector WSLCT, generates the write clock WCLK in synchronization with the clock VCLK, and sequentially generates the write address WADDRS by adding the count value WACOUNT # to A3. The operation of storing new detection data for one frame in the touch sensor panel 3 in the memory area RAM3 is controlled until WACOUNT # becomes COUNTWDT #. In parallel with this, the sequence logic SQNCLGC selects the addresses A0, A1, and A2 sequentially and repeatedly in synchronization with the clock CLK by the selection signal RSTS for the selector RSLCT, and the read clock RCLK every time the addresses A0, A1, and A2 make a round. Then, the read address counter RACUNT is incremented, and the count value RACUNT # is added to the addresses A0, A1, A2 selected by the selector RSLCT to sequentially generate the read addresses RADDRS. This operation is continued until RACOUNT # becomes COUNTWDT #, and the data is read out in time series from the memory areas RAM0, RAM1, and RAM2 for each of a plurality of detected data relating to the same intersection capacity, and is sent to the microprocessor 2. Supplied. When the operation of the access state ACSTS0 is completed, the operation control of the subsequent access state ACSTS1 is performed in the same manner, and the same processing is sequentially repeated as many times as necessary.

  The following effects are obtained from the above.

  (1) Since the touch sensor panel controller 1 has an access control function for reading detection data in an order suitable for digital filter calculation, the burden on the microprocessor 12 that performs the digital filter calculation is reduced, and the digital by the microprocessor 2 is reduced. Data processing capability such as filter operation is substantially improved. Therefore, it is possible to improve the detection accuracy of a contact event that occurs on the touch sensor panel 3 while suppressing costs. In addition, the burden on the microprocessor unit 2 that processes the detection data from the touch sensor panel 3 can be reduced.

  (2) Since the detection data write control and the detection data read control to the memory unit 110 can be performed in parallel, the digital filter operation using the detection data can be efficiently performed without interruption, The detection responsiveness using the touch sensor panel 3 can be improved.

  (3) A memory area to which detection data is to be written is controlled to be switched to wraparound in units of detection data frames, and a memory area for reading out the data in time series for each of a plurality of detection data related to the same intersection capacity Since switching control is performed in wraparound every reading, it is possible to easily realize switching control of memory areas in detection data writing control and detection data reading control.

  FIG. 10 illustrates a data processing system such as a portable terminal to which a touch sensor panel controller (TPC) 1 according to another embodiment of the present invention is applied. In the figure, a touch sensor panel controller (TPC) 1 is mounted on a single semiconductor substrate together with a microprocessor (MPU) 7 and is configured as a system-on-chip semiconductor device SOC_1. The circuit configuration is denoted by the same reference numeral, and detailed description thereof is omitted.

  FIG. 11 illustrates a data processing system such as a portable terminal to which a touch sensor panel controller (TPC) 1 according to still another embodiment of the present invention is applied. In the figure, a touch sensor panel controller (TPC) 1 is mounted on a single semiconductor substrate together with a microprocessor (MPU) 7 and a liquid crystal display driver (LCDDRV) 6 and is configured as a system-on-chip semiconductor device SOC_2. 1, and the other same circuit configuration is denoted by the same reference numeral, and detailed description thereof is omitted.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the order of reading the acquired signals from the memory unit for each of a plurality of acquired signals related to the same intersection capacity may be ascending order or descending order, and the order may be any order that can be grasped by subsequent arithmetic processing.

  The digital filter operation for the data read from the memory unit is not limited to FIR, but may be IIR (Infinite impulse response) or the like.

  The touch sensor panel is not limited to the mutual capacitance method, and the size thereof is not limited.

  The storage capacity of the memory unit and the number and size of the memory areas can be changed as appropriate. What is necessary is just to determine in the range which can hold | maintain the data amount required for the required digital filter calculation. The size and number of memory areas may be fixed. In that case, the function that allows the start address of each area to be set in a programmable manner by a register may be abolished.

1 Touch sensor panel controller (TPC)
2 Microprocessor (MPU)
3 Touch sensor panel (TCHPNL)
4 Liquid crystal display (LCDDSP)
5 Host processor (HST)
6 Liquid crystal display driver (LCDDRV)
Lx drive electrode Ly detection electrode Cc intersection capacity 100 detection unit (SNSU)
110 Memory unit (MRY)
120 Control unit (CNTU)
130 Processor Interface (MPIF)
101 Driver (DRV)
102 Detection circuit (SNS)
103 AD conversion circuit (ADC)
RAM0 to RAM3 Memory area 121 Sequence control circuit (SQNCCNT)
122 Read access control circuit (RACCNT)
123 Register circuit (REGC)
200 CPU (Central Processing Unit)
A0, A1, A2 Start address SAREG0 to SAREG3 Start address register CUNTWDDT Count width register WSLCT selector WACUNT write address counter WADD address adder WCLK count clock WACUNT # count value RSLCT selector RACUNT read address counter RADD address adder RCLK count clock RACUNT Value RADDRS read address SQNCLGC Sequence logic ACSTS0 to ACSTS3 Access state RDSTS0 to RDSTS3 Read access mode WTSTS0 to WTSTS3 Write access mode SOC_1, SOC_2 System-on-chip semiconductor device

Claims (7)

A detection unit that scans and drives the drive electrodes of a touch sensor panel in which intersection capacitances are formed at a plurality of intersections by a plurality of drive electrodes and detection electrodes, and sequentially obtains signals from the detection electrodes via the scan-driven intersection capacitances When,
A memory unit for storing an acquisition signal acquired by the detection unit;
A control unit that controls writing and reading to and from the memory unit,
The memory unit has a plurality of memory areas, and each memory area has a storage capacity for storing an acquisition signal acquired by the detection unit for the intersection capacity of all the intersections of the touch sensor panel;
The control unit performs write control for writing the acquisition signal to the selected memory area while sequentially selecting the memory areas for wraparound, and in parallel with the write control, a plurality of the acquisition signals already written A semiconductor device that performs read-out control for sequentially reading out acquired signals related to the same intersection from each of the memory regions in parallel . N memory areas are provided (n is a positive integer);
The control unit performs write control for writing the acquisition signal to the selected memory area while sequentially selecting the memory areas for wraparound, and in parallel with the write control, n pieces of the acquisition signals that have already been written 2. The semiconductor device according to claim 1, wherein the memory regions are selected in parallel, and read control is performed in which the acquisition signals relating to the same intersection are sequentially read out in parallel . The semiconductor device according to claim 1 , further comprising a microprocessor unit that performs digital filter operation using acquisition signals read in parallel from the plurality of memory areas .   A touch sensor panel in which intersection capacitances are formed at a plurality of intersections by a plurality of drive electrodes and detection electrodes; a touch sensor panel controller that scans and drives the drive electrodes to sequentially acquire signals from the detection electrodes; and the touch sensor panel A microprocessor unit connected to the controller,
  The touch sensor panel controller scans the drive electrodes and stores an acquisition signal sequentially acquired from the detection electrodes;
  A control unit that controls writing and reading to and from the memory unit,
  The memory unit has a plurality of memory areas, and each memory area has a storage capacity for storing an acquisition signal acquired by the detection unit for the intersection capacity of all the intersections of the touch sensor panel;
  The control unit performs write control for writing the acquisition signal to the selected memory area while sequentially selecting the memory areas for wraparound, and in parallel with the write control, a plurality of the acquisition signals already written A data processing system that performs read-out control for sequentially reading out acquisition signals related to the same intersection from each of the memory areas in parallel. N memory areas are provided (n is a positive integer);
The control unit performs write control for writing the acquisition signal to the selected memory area while sequentially selecting the memory areas for wraparound, and in parallel with the write control, n pieces of the acquisition signals that have already been written 5. A data processing system according to claim 4, wherein said memory areas are selected in parallel, and readout control for sequentially reading the acquired signals related to the same intersection from each of them is performed. The microprocessor unit receives an acquisition signal read in parallel from the plurality of memory areas from the touch sensor panel controller, performs a digital filter calculation, and a touch sensor in which a touch event occurs based on the calculation result The data processing system according to claim 4, wherein coordinates on the panel are calculated . The touch sensor panel has transparency.
The data processing system according to claim 6, further comprising: a bitmap display disposed under the touch sensor panel; and a display driver that performs display driving for the bitmap display .

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