JP5807361B2 - Wiring board manufacturing method and liquid jet head manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring board and a method for manufacturing a liquid jet head.

  For example, a liquid ejecting head may be used as the wiring board having the wiring portion patterned on the substrate. In Patent Document 1 below, as a liquid ejecting head, a flow path forming substrate having a pressure generating chamber communicating with a nozzle opening for ejecting ink and a piezoelectric element for displacing the pressure generating chamber, and the flow path forming substrate are joined. And a protective substrate having a driving IC or the like for driving a piezoelectric element.

  This piezoelectric element is a multilayer wiring structure in which a lower electrode, a piezoelectric layer, and an upper electrode are sequentially stacked, and for the formation thereof, it is necessary to repeat a photolithography process and an etching process a plurality of times. In this etching step, a dry etching method that does not immerse the substrate in an etching solution, such as a wet etching method, may be employed. As the dry etching method, there are various means such as an ion milling method, a plasma etching method, a reactive ion etching method, a sputter etching method, and an inductively coupled plasma method.

  Patent Document 2 below discloses a dry etching apparatus having a holder for holding a peripheral portion of a substrate. This dry etching apparatus is designed to prevent a groove from being formed in a boundary region between a holder and a resist by an ion beam when patterning a substrate using an ion milling method among dry etching methods. A configuration is adopted in which a collar is formed in the holder, the holder is extended on the resist, and the boundary region is covered. According to this configuration, since the groove is not formed even if the photolithography process and the etching process are repeated a plurality of times, it is possible to eliminate a cause (deep groove) in which the substrate is cracked or chipped.

JP 2007-152913 A JP 2006-222127 A

  However, when the holder is extended onto the resist and dry etching is performed using an ion beam or the like, the resist on the tip of the extended portion of the holder and the region below the holder may be changed to black. is there. This occurs when a metal component (for example, iron (Fe), etc.) contained in the holder penetrates into the resist in the overlapping area with the holder by an ion beam or the like. There is a problem that it cannot be removed by ashing. Furthermore, even if a resist stripping solution is used thereafter, the deteriorated resist does not dissolve and may reattach to the substrate in the liquid tank, resulting in a product defect and a decrease in yield.

  SUMMARY An advantage of some aspects of the invention is that it provides a method for manufacturing a wiring board and a method for manufacturing a liquid jet head that can suppress residual resist and improve yield.

In order to solve the above-described problems, the present invention provides a photolithography process for forming a resist having a predetermined shape on a substrate, a peripheral portion of the substrate, and extending on the resist formed on the substrate. A dry etching step of forming a pattern using the holder having a possible shape using the resist as a mask, a plurality of times, and forming a multilayer wiring structure on the substrate, wherein the dry etching step In the process, at least a part of the holder and the resist is repeatedly formed in the direction along the surface of the substrate in a pattern to form the pattern, and the photolithography process and the dry etching process are repeated a plurality of times. Once, after the photolithography process, before the dry etching process, A resist removal step of removing the resist in the region including the region to be a state, to adopt the technique of including.
By adopting such a technique, in the present invention, in order to form a multilayer wiring structure on the substrate, the photolithography process and the dry etching process are repeated a plurality of times, and at least once, the holder and the resist are formed. A pattern is formed by removing the resist in a region including a region where a part of the substrate overlaps in a direction along the surface of the substrate. As described above, the resist remaining in the overlapping region can be prevented by removing the resist in advance before dry etching, that is, before the resist is altered. In this case, a boundary region is created between the holder and the resist, and a groove is formed in the boundary region. However, as long as the process is performed at least once, the other part of the holder and the resist is conventionally used. By forming the pattern in an overlapping state in the direction along the surface of the substrate, the depth of the groove can be suppressed to such an extent that the substrate is not cracked or chipped.

In the present invention, a positive resist is formed on the substrate in the photolithography step before the resist removing step, and the second step of the substrate including the overlapping region is performed in the resist removing step. A technique of performing peripheral exposure for exposing the peripheral part of the image is employed.
By adopting such a method, in the present invention, the resist is made positive, and the second peripheral portion of the substrate including the overlapping region is subjected to peripheral exposure, and the resist is removed.

In the present invention, the multilayer wiring structure includes a piezoelectric element formed by sequentially laminating a lower electrode, a piezoelectric layer, and an upper electrode, and the resist removing step includes at least the piezoelectric layer together with the upper electrode. A method of forming the film is performed after the photolithography process and before the dry etching process.
By adopting such a method, in the present invention, when the upper electrode constituting the piezoelectric element is formed together with the piezoelectric layer, the irradiation time of the ion beam or the like is long, the temperature is increased, and the resist is altered. In this case, in this case, a resist removing process is performed, and the resist in the overlapping region is removed in advance.

In the present invention, the dry etching process employs a technique of using an ion milling method.
By adopting such a technique, in the present invention, by adopting an ion milling method in the dry etching process, the processing accuracy is high, and the ion beam is exclusively composed of argon (Ar) ions, and there is a problem with the patterned wiring portion. Never give.

In the present invention, a method of selecting whether or not to perform the resist removal step is adopted based on each total energy amount used for the pattern formation in the dry etching step.
By adopting such a method, in the present invention, the larger the total energy amount (ion beam irradiation time, milling rate, temperature, etc.) in the dry etching step, the easier the metal component of the holder enters the resist and changes its quality. Therefore, the production efficiency can be improved by selecting whether or not to perform the resist removal step based on the total energy amount.

The present invention also provides a method of manufacturing a liquid ejecting head having a pressure generating chamber communicating with a nozzle opening for ejecting a liquid and a flow path forming substrate having a piezoelectric element that displaces the pressure generating chamber. As a method for manufacturing the formation substrate, a method of using the above-described method for manufacturing a wiring substrate is employed.
By adopting such a method, in the present invention, a method for manufacturing a liquid ejecting head that can suppress residual resist and improve yield can be obtained.

1 is an exploded perspective view showing a configuration of an ink jet recording head including a flow path forming substrate manufactured by a manufacturing method according to an embodiment of the present invention. 2A and 2B are a plan view and a cross-sectional view illustrating a configuration of an ink jet recording head according to an embodiment of the invention. It is a schematic flowchart of the manufacturing process of the flow-path formation board | substrate in embodiment of this invention. It is a figure which shows the process of forming the lower electrode film in embodiment of this invention with time. It is a top view which shows the structure of the dry etching apparatus in embodiment of this invention. It is arrow XX sectional drawing in FIG. It is a figure which shows the process of forming the piezoelectric material layer and upper electrode film in embodiment of this invention with time. It is sectional drawing which shows the wafer after the resist removal process in embodiment of this invention, and the wafer in a dry etching process. It is sectional drawing which shows the wafer in the dry etching process at the time of not passing through the resist removal process in embodiment of this invention. It is sectional drawing which shows the structure of the holder in another embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, an ink jet recording head will be described as an example.

FIG. 1 is an exploded perspective view showing a configuration of an ink jet recording head including a flow path forming substrate (wiring substrate) manufactured by the manufacturing method according to the embodiment of the present invention. FIG. 2 is a plan view and a cross-sectional view showing the configuration of the ink jet recording head in the embodiment of the present invention.
As shown in the figure, the flow path forming substrate 10 is composed of a silicon single crystal substrate having a plane orientation (110) in this embodiment, and an elastic film 50 made of silicon dioxide previously formed by thermal oxidation is formed on both surfaces thereof. Yes.

  A plurality of pressure generating chambers 12 partitioned by a plurality of partition walls are arranged in parallel in the width direction on the flow path forming substrate 10 by anisotropic etching from the other side. A communication portion 13 constituting a reservoir 100 serving as a common ink chamber for each pressure generation chamber 12 is formed outside each pressure generation chamber 12, and one end in the longitudinal direction of each pressure generation chamber 12 and each ink supply path 14. It is communicated through.

  Further, on one opening surface side of the flow path forming substrate 10, a nozzle plate 20 having a nozzle opening 21 communicating with the side opposite to the ink supply path 14 of each pressure generating chamber 12 is provided with an adhesive or heat welding. It is fixed via a film or the like. The nozzle plate 20 is made of, for example, glass ceramics, a silicon single crystal substrate, or stainless steel (SUS).

As described above, the elastic film 50 made of silicon dioxide is formed on the opposite side of the flow path forming substrate 10 from the opening surface, and the elastic film 50 is made of, for example, zirconium oxide (ZrO ₂ ). Insulator film 55 is laminated. A piezoelectric element (multilayer wiring structure) 300 including a lower electrode film (lower electrode) 60, a piezoelectric layer 70, and an upper electrode film (upper electrode) 80 is formed on the insulator film 55. Here, the piezoelectric element 300 refers to a portion including the lower electrode film 60, the piezoelectric layer 70, and the upper electrode film 80.

  In general, one electrode of the piezoelectric element 300 is used as a common electrode, and the other electrode and the piezoelectric layer 70 are patterned for each pressure generating chamber 12. For example, in this embodiment, the lower electrode film 60 is used as a common electrode for the piezoelectric element 300 and the upper electrode film 80 is used as an individual electrode for the piezoelectric element 300. Absent.

  A lead electrode 90 made of, for example, gold (Au), platinum (Pt), iridium (Ir), or the like is connected near the end of each upper electrode film 80 that is an individual electrode of the piezoelectric element 300. Are connected to a driving IC (driving unit) 220 for driving the piezoelectric element 300 via a driving wiring 200. The drive wiring 200 is made of a bonding wire, and electrically connects the end of each lead electrode 90 drawn out of the piezoelectric element holding unit 31 and the drive IC 220.

  On the flow path forming substrate 10 on which such a wiring structure is formed, a protective substrate 30 is bonded via an adhesive layer 35. The protective substrate 30 has a piezoelectric element holding portion 31 that is a space for protecting the piezoelectric element 300 in a region facing the piezoelectric element 300, and the piezoelectric element 300 is disposed in the piezoelectric element 300. The piezoelectric element holding portion 31 may be sealed or not sealed.

  Further, the protective substrate 30 is provided with a reservoir portion 32 that is a penetrating portion that penetrates the protective substrate 30 in the thickness direction in a region facing the communication portion 13. As described above, the reservoir section 32 communicates with the communication section 13 of the flow path forming substrate 10 and constitutes a reservoir 100 that serves as a common ink chamber for the pressure generation chambers 12. The protective substrate 30 is preferably formed of a material substantially the same as the coefficient of thermal expansion of the flow path forming substrate 10. For example, in this embodiment, a silicon single crystal substrate of the same material as the flow path forming substrate 10 is used. It is formed using.

  On the protection substrate 30, a region facing the reservoir portion 32 is configured with, for example, a sealing film 41 made of a flexible material such as a PPS film and a fixing plate 42 made of a hard material such as a metal material. The compliance substrate 40 to be used is bonded. Since the region of the fixing plate 42 that faces the reservoir 32 is an opening 43 that is completely removed in the thickness direction, one surface of the reservoir 32 is sealed only with a flexible sealing film 41. It has been stopped.

  On the protective substrate 30, a driving IC 220 for selectively driving each piezoelectric element 300 is mounted. A connection wiring 210 patterned in a predetermined shape is provided on the protective substrate 30, and the drive IC 220 is mounted on the connection wiring 210. For example, an external wiring (not shown) such as an FPC is electrically connected to the connection wiring 210, and a drive signal and a drive voltage from the external wiring are supplied to each drive IC 220 via the connection wiring 210. It has become.

  In the ink jet recording head having the above configuration, after taking ink from an external ink supply means (not shown) and filling the interior from the reservoir 100 to the nozzle opening 21, the ink is supplied to the pressure generating chamber 12 in accordance with a drive signal from the drive IC 220. A drive voltage is applied between the corresponding lower electrode film 60 and upper electrode film 80 to cause the elastic film 50, the lower electrode film 60, and the piezoelectric layer 70 to bend and deform, so that The pressure can be increased and ink droplets can be ejected from the nozzle openings 21.

Hereinafter, the step of forming the piezoelectric element 300 on the flow path forming substrate 10 in the manufacturing method of the ink jet recording head having the above-described configuration, in particular, the manufacturing method of the flow path forming substrate 10 will be described in detail.
FIG. 3 shows a schematic flow diagram of the manufacturing process of the flow path forming substrate 10 in the embodiment of the present invention.

In step S1, the surface of the silicon wafer on which the flow path forming substrate 10 is formed is thermally oxidized in a diffusion furnace at about 1100 ° C., for example, to form the elastic film 50 made of silicon dioxide (SiO ₂ ). Then, after forming a zirconium (Zr) layer on the elastic film 50 by sputtering or the like, the zirconium layer is thermally oxidized in, for example, a diffusion furnace at 500 to 1200 ° C., thereby insulating the zirconium oxide (ZrO ₂ ). A body film 55 is formed to constitute a diaphragm.

In step S2, as shown in FIG. 4A, for example, platinum (Pt) and iridium (Ir) are stacked on the insulator film 55 by sputtering or the like to form the lower electrode film 60 on the entire surface. Film.
Next, as shown in FIG. 4B, a resist 160 having a predetermined shape is formed on the lower electrode film 60 (photolithography process). Specifically, for example, a positive resist is applied on the lower electrode film 60 by a spin coating method or the like, and then a resist 160 having a predetermined pattern is formed by performing exposure / development using a mask having a predetermined shape. To do.

Next, as shown in FIG. 4C, using the resist 160 as a mask, the lower electrode film 60 is dry-etched to pattern the lower electrode film 60 into a predetermined shape (dry etching process). In this step, the dry etching apparatus 110 shown in FIGS. 5 and 6 is used.
FIG. 5 is a plan view showing the configuration of the dry etching apparatus 110 in the embodiment of the present invention. 6 shows a cross-sectional view taken along the line XX in FIG. In the figure, reference numeral 101 denotes a wafer on which the flow path forming substrate 10 is formed. The wafer 101 has an orientation flat portion (hereinafter referred to as an orientation flat portion 101a) in which a part of the circumference is cut out linearly.

  The dry etching apparatus 110 of this embodiment is configured to use an ion milling method as a dry etching method. The ion milling method has high processing accuracy, and the ion beam is exclusively composed of argon (Ar) ions, and does not give a problem to the patterned wiring portion. The dry etching apparatus 110 includes a holder 120 that holds a peripheral portion 102 (see FIG. 6) of the wafer 101 and has a shape that can extend to a resist 160 formed on the wafer 101. The holder 120 has a holding part 121 and a flange part 122.

  The holding unit 121 is configured to press and hold the peripheral portion 102 of the wafer 101. Note that the resist 160 on the peripheral portion 102 is previously removed by peripheral exposure separately from the exposure in the photolithography process. As the peripheral exposure, a known peripheral exposure apparatus in which an exposure unit that rotates the wafer 101 together with the stage and exposes exposure light with a predetermined width corresponding to the peripheral portion 102 can be used.

  The flange 122 is configured such that the resist 160 and a part thereof can overlap with each other in the direction along the surface of the wafer 101. The overlapping state in which the holder 120 (the flange 122) and a part of the resist 160 are in the direction along the surface of the wafer 101 means that the coordinates in the direction along the surface of the wafer 101 are common. Therefore, when viewed from the ion beam irradiation direction (vertical direction shown in FIG. 6), the holder 120 (the flange 122) extends on the resist 160 and covers a part of the resist 160 (overlapping state).

  According to the holder 120 configured as described above, since the wafer 101 is held by the holding unit 121 and the resist 160 and the flange 122 are overlapped with each other, the holder 120 (an area along the tip of the flange 122). ), The wafer 101 can be protected from the ion beam (indicated by an arrow in FIG. 6). Therefore, only the lower electrode film 60 exposed from the resist 160 can be milled without forming a groove in the holder 120.

Thereafter, the resist 160 is peeled off by oxygen plasma (ashing process). Specifically, for example, the inside of the chamber containing the wafer 101 is evacuated, and then a gas containing oxygen (O ₂ ) is introduced to make it plasma. The gas converted into plasma decomposes and removes the resist 160 as carbon dioxide (CO ₂ ), water vapor (H ₂ O), or the like. In the pattern forming step of the lower electrode film 60, since the film thickness to be milled is small (for example, about 0.2 micrometers (μm)), the milling time is short and the temperature of the holder 120 is not increased. The resist 160 under 122 hardly changes in quality, and the resist peeling can be completed only by the oxygen plasma ashing process.

Next, in step S3, as shown in FIG. 7A, for example, a piezoelectric layer 70 made of lead zirconate titanate (PZT) or the like, and an upper electrode film 80 made of iridium, for example, by sputtering or the like. Are sequentially stacked on the lower electrode film 60.
The material of the piezoelectric layer 70 constituting the piezoelectric element 300 is, for example, a ferroelectric piezoelectric material such as lead zirconate titanate (PZT), or niobium, nickel, magnesium, bismuth, yttrium, or the like. A relaxor ferroelectric or the like to which a metal is added is used. The composition may be appropriately selected in consideration of the characteristics, application, etc. of the piezoelectric element 300. For example, PbTiO ₃ (PT), PbZrO ₃ (PZ), Pb (Zr _x Ti _1-x ) O ₃ (PZT) ), Pb (Mg _1/3 Nb _2/3 ) O ₃ -PbTiO ₃ (PMN-PT), Pb (Zn _1/3 Nb _2/3 ) O ₃ -PbTiO ₃ (PZN-PT), Pb (Ni ₁ ) _{/ 3 Nb 2/3) O 3 -PbTiO} 3 (PNN-PT), Pb (In 1/2 Nb 1/2) O 3 -PbTiO 3 (PIN-PT), Pb (Sc 1/2 Ta 1/2 _{) O 3 -PbTiO 3 (PST-} PT), Pb (Sc 1/2 Nb 1/2) O 3 -PbTiO 3 (PSN-PT), BiScO 3 -PbTiO 3 (BS-PT), BiYbO 3 -PbTiO 3 (BY PT), and the like. The method for forming the piezoelectric layer 70 is not particularly limited. For example, in this embodiment, a so-called sol in which a metal organic material is dissolved and dispersed in a catalyst is applied, dried, gelled, and further fired at a high temperature. The piezoelectric layer 70 is formed by using a so-called sol-gel method for obtaining the piezoelectric layer 70 made of an oxide.

Next, as shown in FIG. 7B, a resist 160 having a predetermined shape is formed on the upper electrode film 80 (photolithographic process: second time). Specifically, for example, a positive resist is applied on the lower electrode film 60 by a spin coating method or the like, and then a resist 160 having a predetermined pattern is formed by performing exposure / development using a mask having a predetermined shape. To do.
Next, as shown in FIG. 7C, using this resist 160 as a mask, the upper electrode film 80 and the piezoelectric layer 70 are dry-etched and patterned into a predetermined shape (dry etching step: second time).

In this process, the dry etching apparatus 110 shown in FIG. 5 is used. However, after the photolithography process and before the dry etching process, the resist 160 in a region overlapping with the holder 120 in the direction along the surface of the wafer 101 is used. Is removed (resist removal step).
FIG. 8 is a cross-sectional view showing the wafer 101 after the resist removal process and the wafer 101 during the dry etching process in the embodiment of the present invention. FIG. 9 is a cross-sectional view showing the wafer 101 during the dry etching process when the resist removal process is not performed in the embodiment of the present invention. 8 and 9 show positions corresponding to the cross-sectional view taken along the line XX in FIG.

  In the resist removing process, the peripheral exposure apparatus is used to expose the second peripheral portion 103 (see FIG. 8A) including the region overlapping with the holder 120 in the direction along the surface of the wafer 101. Perform exposure. The second peripheral portion 103 includes a region on the tip of the extending portion of the holder 120 (the flange portion 122) and a region under the holder 120. Therefore, in the second peripheral exposure, the exposure width (corresponding to the width of the second peripheral portion 103) is adjusted larger than the exposure width (corresponding to the width of the peripheral portion 102) of the first peripheral exposure. The adjustment is performed, for example, by adjusting the diaphragm of the illumination optical system of the exposure unit. Since the resist 160 is a positive type, the resist 160 in the second peripheral portion 103 is removed by the peripheral exposure.

  After this resist removal process, the holder 120 is installed and a dry etching process is performed as shown in FIG. According to the present embodiment, in order to form a multilayer wiring structure including the piezoelectric element 300 on the wafer 101, the photolithography process and the dry etching process are repeated a plurality of times. A pattern is formed by removing the resist 160 in a region where a part of is overlapped in the direction along the surface of the wafer 101.

  In this way, the metal component (for example, iron (Fe), etc.) contained in the holder 120 enters the resist 160 in the overlapping region before dry etching, that is, as shown in FIG. 9, by the ion beam. By doing so, before the alteration of the resist 160 (indicated by reference numeral 160A in FIG. 9: so-called black registration) occurs, this portion is removed in advance to prevent the occurrence of the altered resist 160A. For this reason, ashing of the resist 160 can be performed by using only oxygen plasma without using a resist stripping solution or the like and causing no resist residue.

  In this case, as shown in FIG. 8B, a boundary region is created between the holder 120 and the resist 160, and a groove 104 is formed in the boundary region. However, the resist removal process is limited to at least once. As described above, a part of the holder 120 and the resist 160 is patterned in the overlapping state in the direction along the surface of the wafer 101, so that the depth of the groove 104 is reduced, such as cracking or chipping of the wafer 101. It can be suppressed to the extent that it is not. The depth of the groove 104 formed after the dry etching step is about 1.4 μm. The depth of the groove 104 is experimentally known to affect the product yield at 6.2 μm or more, but is sufficiently smaller than the value.

  Moreover, it is preferable to perform the resist removal process as in this embodiment after the photolithography process for forming the piezoelectric layer 70 together with the upper electrode film 80 and before the dry etching process. That is, in the pattern forming step of forming the upper electrode film 80 constituting the piezoelectric element 300 together with the piezoelectric layer 70, the film thickness to be milled is large (for example, the film thickness of the upper electrode film 80 is about 0.05 μm, 70 has a film thickness of about 1.0 μm), so that the irradiation time of the ion beam or the like is long, the temperature is also high, and the resist 160 is easily deteriorated. The resist 160 in the region to be formed is removed in advance.

  The selection of whether or not to perform the resist removal step is preferably performed based on the total amount of energy used for pattern formation in the dry etching step. That is, as the total energy amount (ion beam irradiation time, milling rate, temperature, etc.) in the dry etching process increases, the metal component of the holder 120 easily enters the resist 160 and changes its quality. By selecting whether or not to perform the resist removal step (not performed in the pattern formation of the lower electrode film 60 as in the present embodiment, but performed in the pattern formation of the upper electrode film 80 and the piezoelectric layer 70), the product yield is determined. And manufacturing efficiency can be improved.

  Returning to FIG. 3, in step S <b> 4, a metal layer is formed on the entire surface of the wafer 101 on which the piezoelectric element 300 is formed by, for example, sputtering. Here, in order to improve the adhesion between the metal layer and the silicon dioxide film, nickel chrome (NiCr) or the like may be formed as a base layer of the metal layer. Thereafter, a resist having a predetermined shape is formed on the metal layer (photolithography process), and patterning is performed using this resist as a mask. In this embodiment, the wet etching method is used for the patterning, and the above-described resist deterioration does not occur.

In step S5, the wafer 101 of the flow path forming substrate 10 thus formed and the wafer of the protective substrate 30 on which the piezoelectric element holding portion 31, the reservoir portion 32, and the like are formed are bonded via the adhesive layer 35. To do.
In step S6, the flow path forming substrate 10 on the side opposite to the bonded side is polished and etched to a predetermined thickness by etching with hydrofluoric acid, and then a mask made of silicon nitride is formed, and anisotropic etching is performed through this mask. Thus, the pressure generation chamber 12 and the communication portion 13 are formed, and the reservoir 100 is formed by further communicating the communication portion 13 and the reservoir portion 32.

Here, when the protective substrate is bonded, since the groove 104 (see FIG. 8B) is present in the wafer 101, the adhesive accumulates in the groove 104, and the thickness of the adhesive layer 35 at that portion increases. It is possible to prevent an etchant such as potassium hydroxide (KOH) from entering between the bonded wafers in the path forming step.
Thereafter, the drive IC 220 is mounted on the connection wiring 210, and the drive IC 220 and the lead electrode 90 are connected via the drive wiring 200. Further, the nozzle plate 20 is joined to the flow path forming substrate 10, the compliance substrate 40 is joined to the protective substrate 30, and these are divided into one chip size from the wafer. An ink jet recording head having the structure shown is manufactured.

  Therefore, according to the above-described embodiment, the photolithography process for forming the resist 160 having a predetermined shape on the wafer 101, and the resist 160 formed on the wafer 101 while holding the peripheral portion 102 of the wafer 101. A method of manufacturing the flow path forming substrate 10 that forms a multilayer wiring structure on the wafer 101 by repeating a dry etching step of forming a pattern using the holder 120 having a shape that can be extended and using the resist 160 as a mask. In the dry etching process, there are a plurality of pattern forming processes in which a part of the holder 120 and the resist 160 forms a pattern overlapping in the direction along the surface of the wafer 101, and the photolithography process and the dry etching process. Of the above, at least once By adopting a method including a resist removal step of removing the resist 160 in the region including the overlapped region after the lithography process and before the dry etching step, the remaining resist is suppressed and the yield is increased. Can be improved.

  As mentioned above, although preferred embodiment of this invention was described referring drawings, this invention is not limited to the said embodiment. Various shapes, combinations, and the like of the constituent members shown in the above-described embodiments are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

For example, in the above-described embodiment, it has been described that in the resist removal process, the peripheral exposure is performed and the resist 160 in the second peripheral portion 103 including the region overlapping with the holder 120 is removed. It is not limited to the method. For example, the overlapping region resist 160 may be removed by polishing or the like.
Further, in the case of performing a dry etching process that does not go through the resist removal process, a negative resist 160 may be used instead of a positive type.

For example, in the above-described embodiment, it has been described that the photolithography process and the dry etching process are repeated twice, but the present invention is not limited to this method. For example, when a protective layer (for example, Al ₂ O ₃ ) is further formed to protect the piezoelectric element 300 from moisture or the like, necessary portions of the lower electrode film 60, the insulator film 55, and the elastic film 50 are etched. In some cases, it is necessary to repeat the photolithography process and the dry etching process. Even in this case, in each step, it is preferable to select whether or not to perform the resist removal step based on the total energy amount.

  Further, for example, in the above-described embodiment, the holder 120 has been described as having the flange portion 122, but the present invention is not limited to this configuration. For example, as in another embodiment shown in FIG. 10, the holder 120 may be in contact with the resist 160 directly. Even in this configuration, the resist 160 may be deteriorated at the time of the holder 120 and the resist 160 (indicated by the region 105). Therefore, it is preferable to perform the resist removal process described above as necessary.

  Furthermore, in the above-described embodiment, the ink jet recording head has been described as an example of the liquid ejecting head. However, the present invention is widely intended for all liquid ejecting heads and ejects liquids other than ink. Of course, the present invention can also be applied to a method of manufacturing a liquid jet head. Other liquid ejecting heads include, for example, various recording heads used in image recording apparatuses such as printers, color material ejecting heads used in the manufacture of color filters such as liquid crystal displays, organic EL displays, and FEDs (surface emitting displays). Examples thereof include an electrode material ejection head used for electrode formation, a bioorganic matter ejection head used for biochip production, and the like.

  Needless to say, the present invention is applicable not only to such a liquid jet head but also to the manufacture of any wiring substrate having a multilayer wiring structure on the substrate.

  DESCRIPTION OF SYMBOLS 10 ... Channel formation board | substrate (wiring board), 12 ... Pressure generation chamber, 21 ... Nozzle opening, 60 ... Lower electrode film (lower electrode), 70 ... Piezoelectric layer, 80 ... Upper electrode film (upper electrode), 90 ... Lead electrode (multilayer wiring structure), 101 ... wafer (substrate), 102 ... peripheral part, 103 ... second peripheral part, 120 ... holder, 160 ... resist, 300 ... piezoelectric element (multilayer wiring structure)

Claims (6)

A photolithography process for forming a resist having a predetermined shape on the substrate, and a mask that holds the periphery of the substrate and has a shape that can be extended on the resist formed on the substrate, and masking the resist And a dry etching step of forming a pattern as a plurality of times, and a method of manufacturing a wiring board that forms a multilayer wiring structure on the substrate,
In the dry etching step, a pattern forming step in which a part of the holder and the resist forms the pattern in an overlapping state in a direction along the surface of the substrate;
Among the steps of repeating the photolithography process and the dry etching process a plurality of times, at least one time after the photolithography process and before the dry etching process, the resist in the region including the overlapping region is removed. A method of manufacturing a wiring board, comprising: a resist removing step. In the photolithography process before the resist removing process, a positive resist is formed on the substrate,
2. The method of manufacturing a wiring board according to claim 1, wherein in the resist removing step, peripheral exposure is performed to expose a second peripheral portion of the substrate including the overlapping region. The multilayer wiring structure includes a piezoelectric element formed by sequentially laminating a lower electrode, a piezoelectric layer, and an upper electrode,
3. The method of manufacturing a wiring board according to claim 1, wherein the resist removing step is performed at least between the photolithography step and the dry etching step of forming the piezoelectric layer together with the upper electrode. .   The method for manufacturing a wiring board according to claim 1, wherein an ion milling method is used in the dry etching step.   5. The method according to claim 1, wherein whether or not to perform the resist removal step is selected based on each total energy amount used for the pattern formation in the dry etching step. A method for manufacturing a wiring board. A method of manufacturing a liquid ejecting head having a pressure generating chamber communicating with a nozzle opening for ejecting liquid and a flow path forming substrate having a piezoelectric element for displacing the pressure generating chamber,
A method of manufacturing a liquid jet head, wherein the method of manufacturing a wiring substrate according to claim 1 is used as a method of manufacturing the flow path forming substrate.

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