JP5795503B2 - Pulse width modulation system and audio signal output device - Google Patents

Description

  The present invention relates to pulse width modulation (PWM) technology, and in particular, pulse width modulation for preventing interference between a PWM output and a frequency of medium wave broadcasting (AM broadcasting) by improving a PWM modulation method. The present invention relates to a system and an audio signal output device.

  PWM is a modulation method for controlling current and voltage by changing the duty cycle of the pulse width (ratio of H to L of the pulse width) in accordance with the magnitude of the pulse signal having a constant period. By the way, when an integer multiple of the frequency of the PWM output and the frequency of the AM broadcast shipping wave are close to each other, the PWM output interferes with the radio tuner, and as a result, beat noise is added to the radio output. Here, AM broadcasting generally refers to medium-wave radio broadcasting, and is defined as “broadcast that transmits sound and other sounds using radio waves with a frequency from 526.5 kHz to 1,606.5 kHz” ( Radio Law Enforcement Regulations Article 2, Paragraph 1, Item 24, Broadcast Law, Article 2, Paragraph 2, Item 3)

  In relation to such a technique, a technique for adjusting the PWM frame rate in accordance with the tuning frequency of the AM tuner is disclosed (for example, see Patent Document 1).

US Patent Application Publication No. 2006/0247810

  In general, the frequency of the PWM output is fixed to a predetermined multiple (for example, eight times) of the sampling frequency of the original signal. Therefore, when the integer multiple frequency of the PWM output frequency and the frequency of the AM broadcast shipping wave are close to each other, it is difficult to avoid the interference of the PWM output to the radio tuner.

  An object of the present invention is to provide a pulse width modulation system and an audio signal output device capable of flexibly avoiding frequency interference between an integer multiple of a PWM output frequency and a frequency of an AM broadcast shipping wave.

According to one aspect, (a) a PLL circuit that generates and transmits an operation clock by varying a system clock in accordance with the value of a variable k held in the circuit, and (b) is transmitted from the PLL circuit. And an oversampling filter that oversamples data at a frequency k times the sampling frequency of the input signal, and (c) operates with the operation clock sent from the PLL circuit, A noise shaper for performing noise shaping processing on the signal output from the oversampling filter; and (d) operating with the operation clock sent from the PLL circuit, and converting the pulse width of the signal output from the noise shaper to the operation clock . By expanding or narrowing by one period, the pulse width corresponding to the input signal is increased. One pulse width modulation system comprising a PWM modulator for generating a pulse signal. According to another aspect, (a) a PLL circuit that generates and transmits an operation clock by varying a system clock according to the value of a variable k held in the circuit; and (b) from the PLL circuit. An oversampling filter that operates based on the transmitted operation clock and oversamples data at a frequency k times the sampling frequency of the input signal, and (c) the oversampling filter has a Chebyshev characteristic and an inverse Chebyshev characteristic And a pulse width modulation system composed of simultaneous Chebyshev. According to still another aspect, (a) a PLL circuit that generates and transmits an operation clock by varying a system clock according to the value of a variable k held in the circuit; and (b) the PLL circuit. And an oversampling filter that operates on the basis of the operation clock transmitted from and oversamples data at a frequency k times the sampling frequency of the input signal, and (c) the variable k is an integer of 1 to 8. The pulse width modulation system is provided in which the PLL circuit generates the operation clock by multiplying the system clock by k / 8.

  According to another aspect, an audio signal output device comprising the pulse width modulation system is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the pulse width modulation system and audio | voice signal output device which can avoid flexibly the frequency interference of the integer multiple frequency of PWM output frequency and the frequency of the dispatch wave of AM broadcast can be provided.

The typical block diagram which illustrates the pulse width modulation system concerning a comparative example. The figure for demonstrating the outline | summary of a pulse width modulation system. The figure for demonstrating the beat noise which generate | occur | produces when the integral multiple frequency of the frequency of PWM output and the frequency of the dispatch wave of AM broadcast adjoin. It is a figure which illustrates the PWM output timing by the pulse width modulation system which concerns on embodiment, Comprising: (a) When the frequency of PWM output is 8 fs (b) When the frequency of PWM output is 7 fs (c) Frequency of PWM output The figure which illustrates the case where is 6fs. The figure which illustrates the integer multiple frequency value of the frequency of PWM output at the time of fluctuating the frequency of PWM output. 1 is a schematic block diagram illustrating a pulse width modulation system according to an embodiment. The figure which illustrates the calculation timing at the time of the oversampling in case the frequency of PWM output is 8fs and 7fs.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the dimensions and the like of each component are different from actual ones. Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments shown below exemplify an apparatus for embodying the technical idea of the present invention, and the embodiments of the present invention include materials, shapes, structures, and arrangements of components. Etc. are not specified below. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[Embodiment]
(Pulse width modulation system in comparative example)
FIG. 1 illustrates a schematic block diagram illustrating a pulse width modulation (PWM) system according to a comparative example. As illustrated in FIG. 1, the pulse width modulation system according to the comparative example includes a synchronous sampling rate converter (synchronous SRC) 10, an audio digital signal processor (DSP) 12, an 8 × oversampling filter 14, and a noise shaper 16. , A PWM modulator (pulse width modulator) 18.

  A synchronous sampling rate converter (synchronous SRC) 10 inputs a digital signal (for example, a digital audio signal) having a specific sampling rate in synchronization with a clock, and converts it into a sampling frequency different from the original sampling rate. Output to an audio digital signal processor (DSP) 12. Here, the synchronous sampling rate converter (SRC) 10 sets 8/12/16/24/32/48/96 kHz to a frequency of 48 kHz, and 44 sets 11.025 / 22.05 / 44.1 / 8 / 88.2 kHz to 44 kHz. .Sampling conversion to a frequency of 1 kHz.

  The audio digital signal processor (DSP) 12 receives the digital signal output from the synchronous sampling rate converter (synchronous SRC) 10, performs audio signal processing such as gain control and tone control, and performs PCM (Pulse Code Modulation). ) Type digital audio signal is generated and output to the 8-times oversampling filter 14.

  The 8-times oversampling filter 14 oversamples the digital signal and outputs it to the noise shaper 16. More specifically, the 8-times oversampling filter 14 samples data at a frequency (8 fs) that is eight times the sampling frequency fs of the original input signal, for example, a sampling frequency of 48 kHz or 44.1 kHz is 384 kHz or Convert to PWM frequency of 352.8 kHz.

  The 8-times oversampling filter 14 includes FIR (Finite Impulse Response) filters 20, 22, 24 configured by 2 × 3 stages. Each FIR filter 20, 22, 24 samples at a frequency twice as high as the sampling frequency of the input signal (original). Here, the 8 × oversampling process in the 1fs period in the 8 × oversampling filter 14 is realized by the calculation timings A to N as illustrated in FIG.

  Each calculation timing A to N performs a calculation operation as follows.

Arithmetic timing A: 2 times oversampling 1st time (2fs)
Calculation timing B: 2nd oversampling second time (2 fs)
Calculation timing C: 2 times oversampling first time (4 fs)
Calculation timing D: 2 times oversampling second time (4 fs)
Arithmetic timing E: 3rd oversampling (4fs)
Calculation timing F: 4 times oversampling (4fs)
Arithmetic timing G: 2 times oversampling 1st time (8fs)
Calculation timing H: Second oversampling second time (8 fs)
Calculation timing I: 2 times oversampling third time (8 fs)
Arithmetic timing J: Double oversampling 4th time (8fs)
Calculation timing K: 5 times oversampling (8 fs)
Calculation timing L: 6 times oversampling (8 fs)
Arithmetic timing M: 7 times oversampling twice (8fs)
Calculation timing N: 2 times oversampling 8th time (8fs)
The noise shaper 16 performs noise shaping processing to reduce the level of quantization error noise of the digital audio signal output from the 8-times oversampling filter 14 and outputs the result to the PWM modulator 18.

  The PWM modulator 18 expands or narrows the pulse width of the signal output from the noise shaper 16 by one period of the master clock, and generates and outputs a pulse signal having a pulse width corresponding to the input data.

  Here, as illustrated in FIG. 1, the PWM modulator 18 operates with a system clock of 2048 fs, a synchronous sampling rate converter (synchronous SRC) 10, an audio digital signal processor (DSP) 12, and an 8 × oversampling filter. 14 and the noise shaper 16 operate with a clock of 1024 fs which is 1/2 of 2048 fs.

  In such a pulse width modulation system according to the comparative example, for example, if the sampling frequency of the original input signal is 48 kHz, the PWM output frequency is 8 times 48 kHz, that is, 386 kHz. When the integer multiple frequency of the PWM output frequency 386 kHz at this time is close to the frequency of the AM broadcast shipping wave, the PWM output interferes with the radio tuner, as illustrated in FIG. 3, and as a result, the radio output (audio output) is generated. Beat noise is added. Further, in the pulse width modulation system according to the comparative example, as illustrated in FIG. 2, the PWM output frequency Ts is fixed to 8 times (8 fs) the sampling frequency fs of the original signal. If the frequency that is an integral multiple of the frequency and the frequency of the AM broadcast wave are close to each other, it is difficult to avoid interference of the PWM output to the radio tuner.

(Pulse width modulation system in the embodiment)
FIG. 6 is a schematic block diagram illustrating a pulse width modulation (PWM) system according to the embodiment. In the pulse width modulation system according to the embodiment, a multiple k (k is an integer of 1 to 8) at the time of oversampling with respect to the sampling frequency fs of the original signal can be made variable, and the PWM output frequency is fixed to 8 fs. It is a system that can be varied such as 8 fs, 7 fs, 6 fs. As illustrated in FIG. 6, the pulse width modulation system according to the embodiment includes a synchronous sampling rate converter (synchronous SRC) 10, an audio digital signal processor (DSP) 12, a k-times oversampling filter 26, and a noise shaper 16. And a PWM modulator (pulse width modulator) 18 and a PLL (Phase Locked Loop) circuit 28.

  Similar to the synchronous sampling rate converter (synchronous SRC) 10 in the comparative example, the synchronous sampling rate converter (synchronous SRC) 10 synchronizes with the clock and outputs a digital signal (for example, a digital audio signal) having a specific sampling rate. The input signal is converted to a sampling frequency different from the original sampling rate and output to the audio digital signal processor (DSP) 12. Here, the synchronous sampling rate converter (SRC) 10 sets 8/12/16/24/32/48/96 kHz to a frequency of 48 kHz, and 44 sets 11.025 / 22.05 / 44.1 / 8 / 88.2 kHz to 44 kHz. .Sampling conversion to a frequency of 1 kHz.

  Similar to the audio digital signal processor (DSP) 12 in the comparative example, the audio digital signal processor (DSP) 12 inputs the digital signal output from the synchronous sampling rate converter (synchronous SRC) 10 and, for example, gain control or Audio signal processing such as tone control is performed, and a PCM (Pulse Code Modulation) digital audio signal is generated and output to the k-times oversampling filter 26.

  The synchronous sampling rate converter (synchronous SRC) 10 and the audio digital signal processor (DSP) 12 according to the embodiment operate with a system clock of 1024 fs, similarly to the pulse width modulation system in the comparative example. Circuits equivalent to the synchronous sampling rate converter (synchronous SRC) 10 and the audio digital signal processor (DSP) 12 can be used.

  For example, the PLL circuit 28 generates clock signals having various frequencies by changing the frequency division ratio. The PLL circuit 28 generates an operation clock by multiplying each system clock used by the k-times oversampling filter 26, the noise shaper 16, and the PWM modulator 18 by k / 8 (k is an integer of 1 to 8), and k-times. This is sent to the oversampling filter 26, the noise shaper 16, and the PWM modulator 18. Specifically, the PLL circuit 28 sends an operation clock of 1024 × (k / 8) fs to the k-times oversampling filter 26 and the noise shaper 16 according to the value of the variable k held in the circuit, A clock of 2048 × (k / 8) fs is sent to the PWM modulator 18. Therefore, for example, when k = 8, the PLL circuit 28 sends an operation clock of 1024 fs to the k-times oversampling filter 26 and the noise shaper 16 and sends an operation clock of 2048 fs to the PWM modulator 18. Further, when k = 7, an operating clock of 896 fs is sent to the k-times oversampling filter 26 and the noise shaper 16, and an operating clock of 1792 fs is sent to the PWM modulator 18. When k = 6, the operating clock is k times over. An operation clock of 768 fs is sent to the sampling filter 26 and the noise shaper 16, and an operation clock of 1536 fs is sent to the PWM modulator 18. Note that the value of the variable k held in the PLL circuit 28 can be changed from the outside by the user, for example.

  The k-times oversampling filter 26 operates with an operation clock of 1024 × (k / 8) fs sent from the PLL circuit 28, oversamples the digital signal, and outputs it to the noise shaper 16. More specifically, the k-times oversampling filter 26 oversamples data at a frequency (kfs) that is k times (k is an integer of 1 to 8) the sampling frequency fs of the original input signal, for example, 48 kHz. Alternatively, the sampling frequency of 44.1 kHz is converted into a PWM frequency of (48 × k) kHz or (44.1 × k) kHz.

  The k-times oversampling filter 26 includes a simultaneous Chebyshev 30 configured by k-times × 1 stage. For example, when K = 7, the FIR filters 20, 22, and 24 used in the comparative example have insufficient calculation steps. Therefore, the simultaneous Chebyshev 30 is employed in the k-times oversampling filter 26 in the embodiment. The simultaneous Chebyshev 30 is a filter that combines the concepts of Chebyshev characteristics and inverse Chebyshev characteristics, and is suitable for applications that frequently change the sampling frequency. The simultaneous Chebyshev 30 is, for example, an IIR (Infinite Impulse Response) filter.

  The simultaneous Chebyshev 30 performs oversampling at a frequency that is k times the sampling frequency of the input signal (original) by operating with an operation clock of 1024 × (k / 8) fs sent from the PLL circuit 28. Here, the k-times oversampling process of the 1-fs period in the k-times oversampling filter 26 in the case of k = 7 is realized by the calculation timings from O to U as illustrated in FIG.

  Each calculation timing O to U performs a calculation operation as follows.

Calculation timing O: 7 times oversampling first time (7 fs)
Calculation timing P: 7 times oversampling second time (7 fs)
Calculation timing Q: 7 times oversampling 3rd time (7fs)
Calculation timing R: 7 times oversampling fourth time (7 fs)
Calculation timing S: 7 times oversampling 5th time (7 fs)
Calculation timing T: 7 times oversampling 6th time (7 fs)
Arithmetic timing U: 7 times oversampling 7th time (7fs)
The noise shaper 16 operates with an operation clock of 1024 × (k / 8) fs sent from the PLL circuit 28 and reduces the level of quantization error noise of the digital audio signal outputted from the k-times oversampling filter 26. Then, noise shaping processing is executed and output to the PWM modulator 18.

  The PWM modulator 18 operates with an operation clock of 2048 × (k / 8) fs sent from the PLL circuit 28, and expands or narrows the pulse width of the signal output from the noise shaper 16 by one cycle of the operation clock. Then, a pulse signal having a pulse width corresponding to the input signal is generated and output.

  It should be noted that the noise shaper 16 and the PWM modulator 18 according to the embodiment are merely operated with the operation clock of 1024 × (k / 8) fs sent from the PLL circuit 28, and the noise shaper 16 and the PWM modulator 18 in the comparative example. An equivalent circuit can be used.

  FIG. 4 is a diagram illustrating the PWM output timing by the pulse width modulation system according to the embodiment. Since the multiple k at the time of oversampling can be made variable, the PWM output frequency is 8 fs (FIG. 4A), the PWM output frequency is 7 fs (FIG. 4B), and the PWM output. When the frequency is 6 fs (FIG. 4C), the periods A, B, and C can be made variable. Here, cycle A: cycle B = 7: 8, and cycle A: cycle C = 6: 8.

  In the pulse width modulation system according to such an embodiment, for example, if the sampling frequency of the original input signal is 48 kHz and k = 8, the PWM output frequency is 8 times the input sampling frequency 48 kHz, that is, 386 kHz. Become. Here, assuming that the frequency of the AM broadcast shipping wave is, for example, 768 kHz, as illustrated in FIG. 5, the integer multiple frequency (in this case, double frequency) of the PWM output frequency 386 kHz is also 768 kHz. Since it is close to the frequency of the shipping wave, the PWM output interferes with the radio tuner, and as a result, beat noise is added to the radio output (audio output). However, in the pulse width modulation system according to the embodiment, the multiple k at the time of oversampling with respect to the sampling frequency fs of the original signal can be made variable. Therefore, by switching the variable k in the PLL circuit 28 to k = 7 (7 fs), k = 6 (6 fs), etc., when the frequency of the AM broadcast dispatch wave is close when k = 8 (8 fs), Proximity to AM broadcast wave frequency can be easily avoided.

  Note that, by incorporating the pulse width modulation system according to the embodiment illustrated in FIG. 6 into, for example, an audio signal output device, frequency interference between an integer multiple of the PWM output frequency and the frequency of the AM broadcast dispatch wave can be flexibly reduced. An audio signal output device that can be avoided can also be realized.

  Thus, according to the pulse width modulation system according to the embodiment, even if the integer multiple frequency of the PWM output frequency is close to the frequency of the AM broadcast dispatch wave, by switching the variable k in the PLL circuit 28, AM broadcast Proximity to the shipping wave frequency can be easily avoided.

  As described above, according to the embodiment, the pulse width modulation system and the audio signal output device capable of flexibly avoiding the frequency interference between the integer multiple of the PWM output frequency and the frequency of the AM broadcast dispatch wave. Can be provided.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  The pulse width modulation system and the audio signal output device according to the present invention can be widely applied to all devices that receive and output AM broadcasts, such as radios, radio cassettes, car audios, audio components, mobile phones, game machines, and personal computers. .

10: Synchronous sampling rate converter (synchronous SRC)
12. Audio digital signal processor (DSP)
14 ... 8 times oversampling filter 16 ... noise shaper 18 ... PWM modulator (pulse width modulator)
26 ... k times oversampling filter 28 ... PLL circuit 30 ... simultaneous Chebyshev

Claims (7)

A PLL circuit that generates and sends out an operation clock by varying the system clock according to the value of the variable k held inside the circuit;
An oversampling filter that operates based on the operation clock sent from the PLL circuit and oversamples data at a frequency k times the sampling frequency of the input signal;
A noise shaper that operates with the operation clock transmitted from the PLL circuit and executes noise shaping processing of the signal output from the oversampling filter;
It operates with the operation clock sent from the PLL circuit, and has a pulse width corresponding to the input signal by expanding or narrowing the pulse width of the signal output from the noise shaper by one period of the operation clock. And a PWM modulator that generates a pulse signal. A PLL circuit that generates and sends out an operation clock by varying the system clock according to the value of the variable k held inside the circuit;
An oversampling filter that operates based on the operation clock sent from the PLL circuit and oversamples data at a frequency k times the sampling frequency of the input signal;
The oversampling filter is constituted by a simultaneous Chebyshev in which a Chebyshev characteristic and an inverse Chebyshev characteristic are combined. A PLL circuit that generates and sends out an operation clock by varying the system clock according to the value of the variable k held inside the circuit;
An oversampling filter that operates based on the operation clock sent from the PLL circuit and oversamples data at a frequency k times the sampling frequency of the input signal;
The variable k is an integer of 1 to 8, and the PLL circuit generates the operation clock by multiplying the system clock by k / 8.   2. The pulse width modulation system according to claim 1, wherein the oversampling filter includes a simultaneous Chebyshev in which a Chebyshev characteristic and an inverse Chebyshev characteristic are combined.   The pulse width modulation system according to claim 2, wherein the simultaneous Chebyshev is an infinite impulse response filter.   The variable k is an integer of 1 to 8, and the PLL circuit generates the operation clock by multiplying the system clock by k / 8. The pulse width modulation system according to claim 1.   An audio signal output device comprising the pulse width modulation system according to claim 1.

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