KR20070022262A - Method and apparatus having a digital pwm signal generator with integral noise shaping - Google Patents

Abstract

A method and apparatus 100 are provided having a digital pulse width modulation (PWM) generator 110 with integrated noise shaping. The apparatus for generating the digital PWM signal includes a random periodic signal generator 130, a noise shaping unit 147, a duty ratio quantizer 134, and a PWM counter 172. The random periodic signal generator 130 generates a random periodic signal 132. The noise shaping unit 142 is responsive to at least the digital signal 106, the random period signal 132, and the delay digital signal 162 to produce the corrected signal 168. The duty ratio quantizer 134 is responsive to the calibrated digital signal, the random periodic signal, and the quantization clock signal 190, and generates a first duty ratio signal 136 and a second duty ratio signal 137. The PWM counter 172 is responsive to the first and second duty ratio signals 136 and 137 and the quantization clock signal 190, and generates positive and negative PWM signals 180 and 184, respectively.

Digital Amplifiers, PWM Generators, Integrated Noise Shaping, Random Period Signal Generators, Duty Ratio Quantizers, PWM Counters, Quantized Clock Signals, PCM / PDM Signals, Estimated Error Signals, Adaptive Coefficients

Description

METHOD AND APPARATUS HAVING A DIGITAL PWM SIGNAL GENERATOR WITH INTEGRAL NOISE SHAPING}

TECHNICAL FIELD The present invention relates to digital amplifiers and, more particularly, to interference and noise reduction of pulse width modulation (PWM) signals.

In digital audio amplifiers, PWM is often used to convert a digital signal into its analog component. Digital audio amplifiers of that kind are often referred to as digital PWM audio amplifiers. Digital PWM audio amplifiers can be used in a variety of applications, such as, for example, cellular telephones and high performance digital audio devices.

Many digital PWM audio amplifiers follow a special class of amplifiers known as Class D digital amplifiers. In a typical class D digital amplifier, a fixed frequency signal generator, such as a triangular oscillator, is used in conjunction with the digital audio input to perform PWM. The PWM signal is amplified and provided to a low pass filter to reduce electromagnetic interference (EMI). Although the use of a low pass filter is a viable way to eliminate EMI interference, it also requires the use of additional board space and adds cost to the digital audio amplifier. In many low performance cellular telephone applications, increasing unit cost is not a viable option, so other methods that can be used to reduce the cost while improving signal quality are often considered as examples.

Therefore, there is a need for an improved digital amplifier that reduces EMI and quantization noise in the digital amplifier.

The invention is illustrated by way of example and is not limited by the accompanying drawings, in which like symbols indicate like elements.

1 is a block diagram illustrating a PWM digital amplifier according to an embodiment of the present invention.

2 is a block diagram illustrating a PWM digital amplifier according to an embodiment of the present invention.

3 is a block diagram illustrating an integrated error amplifier according to an embodiment of the present invention.

4 shows in a flowchart a method used in one embodiment of the invention.

5 shows a frequency spectrum of an amplifier according to an embodiment of the present invention as compared to the frequency spectrum of a known amplifier.

6 illustrates various signals associated with a PWM in accordance with an embodiment of the present invention in a timing diagram.

Those skilled in the art will appreciate that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help understand embodiments of the invention.

In one embodiment of the invention, the digital amplifier device comprises a digital PWM signal generator and a power stage with integrated noise shaping to generate a digital PWM signal. The PWM signal generator is responsive to the digital signal input and the random periodic signal to redistribute the quantization noise of the digital signal input corrected to the outer band of the audio band of interest in digital PWM signal generation. The power stage is responsive to the digital PWM signal to provide an amplified digital PWM signal.

In one embodiment of the present invention, an apparatus for generating a digital PWM signal includes a random periodic signal generator, a noise shaping unit, a duty ratio quantizer, and a PWM counter. The random periodic signal generator generates a random periodic signal. The noise shaping unit is responsive to at least the digital signal, the random periodic signal, and the delayed digital signal to produce a calibrated signal. The duty ratio quantizer is responsive to the calibrated digital signal, the random periodic signal, and the quantized clock signal, and generates a first duty ratio signal and a second duty ratio signal. The PWM counter is responsive to the first and second duty ratio signals and the quantized clock signal and generates positive and negative PWM signals, respectively.

In one embodiment of the present invention, a method for digital PWM signal generation is provided. The digital signal is received. A random period signal is generated using a random period generator, and the random period signal includes a left half-cycle and a right half-cycle. Adaptive coefficients are calculated based on a random period. The first generator is used to calculate the first functions for the left half-cycle of the random period. The second generator is used to calculate second functions for the left half-cycle of the random period. The error signal is estimated using the second functions for the left half-cycle. The received digital signal is added with the estimated error signal for the left half-cycle. The first and second duty ratios are quantized for the left half-cycle to set the quantization clock count for the left half-cycle of the positive and negative PWM signals. The first generator is used to calculate the first functions for the right half-cycle of the random period. The second generator is used to calculate second functions for the right half-cycle of the random period. The error signal is estimated using the second functions for the right half-cycle. The received digital signal is added with the error signal estimated for the right half-cycle. The first and second duty ratios are quantized for the right half-cycle to set the quantization clock count for the right half-cycle of the positive and negative PWM signal.

1 shows a digital amplifier 100 according to an embodiment of the present invention. Digital amplifier 100 includes a digital source 102, a digital pulse width modulated signal generator (DPSG) 110 with integrated noise shaping, a power stage 18, and a load 126. Digital source 102 may include devices such as a CD player, a digital audio tape player, a cell phone, a digital car radio, and the like. In one embodiment, rod 126 may be an audio speaker. Other embodiments of the present invention may use other types of rods.

In operation, digital source 102 provides digital signal 106 to DPSG 110. The digital signal 106 can be, for example, a digital input in the form of a pulse code modulated (PCM) signal or a pulse density modulated (PDM) signal. DPSG 110 receives digital signal 106, reduces electromagnetic interference (EMI) using a random period generator, and reduces the amount of quantization noise by quantization using integrated noise shaping. DPSG 110 provides digital PWM signal 114 to power stage 118 for amplification. The power stage 118 amplifies the digital PWM signal 114 and provides the load 126 with the amplified PWM signal 122 as an audio output.

2 shows a digital amplifier 100 according to an embodiment of the invention. The DPSG 110 of the digital amplifier 100 includes a noise shaping unit 147, a random period generator 130, a duty ratio quantizer 134, and a PWM counter 172. The noise shaping unit 147 includes a delay block 146, an integrated error amplifier 142, a summer 164, and an adaptive coefficient generator 143.

In operation, DPSG 110 receives digital signal 106 from digital source 102. The digital signal 106 is provided to the delay block 146, the summer 164, and the integrated error amplifier 142 of the noise shaping unit 147. In one embodiment, delay block 146 receives digital signal 106 and is limited by the duration of random period signal 132 (random period 132) generated by random period generator 130. Delay the digital signal 106 by the amount of delay. In one embodiment, the random periodic signal 132 may include a frequency signal that varies independently, and may change every cycle. The amount of delay in the integrated error amplifier 142 is normalized using half of the random period 132 (random half-period 132). The normalized delay amount may be referred to as the delay ratio. The delayed digital signal 162 is provided to the integrated error amplifier 142.

In addition to providing the random period 132 in the delay block 146, the random period generator 130 provides a random period (a) in the duty ratio quantizer 134, the integrated error amplifier 142, and the adaptive coefficient generator 143. 132). Adaptive coefficient generator 143 generates adaptive coefficients 145 using random period 132. The adaptation coefficients 145 are then provided to the integrated error amplifier 142.

The integrated error amplifier 142 of the noise shaping unit 147 includes a random period 132, a delay digital signal 162 from the delay block 146, a digital signal 106 from the digital source 102, an adaptive coefficient generator 143. ) Receives an adaptation coefficient 145, a PWM signal 184 from a PWM counter 172, and a PWM signal 180 from a PWM counter 172. The integrated error amplifier 142 performs a series of noise shaping operations (described further in the description of FIG. 3) to generate an error signal 176 (estimated error). Estimation error 176 represents a noise shaping error between delayed digital signal 162 and the PWM signal difference (ie, the difference between PWM signal 180 and PWM signal 184). In one embodiment, the error between the delay digital signal 162 and the PWM signal difference is noise shaped by the integrated portion of the integrated error amplifier 142 using the adaptation coefficients 145 and the digital signal 106. In one embodiment, the duty ratios according to duty ratio 136 and duty ratio 137 may be derived by integrated error amplifier 142 using PWM signal 180 and PWM signal 184. In another embodiment, duty ratio 136 and duty ratio 137 may be provided directly to integrated error amplifier 142 (not shown). Summer 164 receives estimation error 176 and digital signal 106 and performs a summation operation to generate a calibrated digital signal 168. The calibrated digital signal 168 is provided to the duty ratio quantizer 134 with a random period 132 and a quantized clock signal 190.

Duty ratio quantizer 134 receives digital signal 168 corrected from summer 164, random period 132 from random period generator 130, and quantized clock signal 190 from quantization clock 191. The duty ratio 136 and the duty ratio 137 are generated. In one embodiment, the duty ratio 136 and the duty ratio (136) for both the left half (left half-cycle) of the cycle of the random period 132 and the right half (right half-cycle) of the cycle of the random period 132 ( 137) is calculated. In one embodiment, the duty ratio quantizer 134 is coupled with the duration of the predicted quantization version of the PWM signal 180 (according to the calibrated digital signal 168 for the left half-cycle of the random period 132). Generate a random half-cycle (half of the random period 132 corresponding to the left half-cycle). Similarly, duty ratio quantizer 134 is random half and the duration of the predicted quantization version of PWM signal 184 (according to calibrated digital signal 168 for the left half-cycle of random period 132). Generates duty ratio 136 using a period (half of random period 132 corresponding to the left half-cycle). For the right half-cycle, the duty ratio quantizer 134 is dependent on the duration of the predicted quantization version of the PWM signal 180 (corrected digital signal 168 for the right half-cycle of the random period 132). ) And the random half-cycle (half of the random period 132 corresponding to the right half-cycle) to generate the duty ratio 137. Similarly, the duty ratio quantizer 134 is a random half and the duration of the predicted quantization version of the PWM signal 184 (according to the corrected digital signal 168 for the right half-cycle of the random period 132). Generates duty ratio 136 using the period (half of random period 132 corresponding to the right half-cycle).

In one embodiment, for example, the quantization noise by duty ratio quantizer 134 is redistributed outside of the audio band of interest by noise shaping unit 147 to produce a desired signal at the output of power stage 118. Ensure that the noise-to-noise ratio criteria are met. In one embodiment, as for CD quality audio, the desired signal-to-noise ratio criterion may be 96 dB. In other embodiments, noise shaping unit 147 may have other signal-to-noise criteria that may be correspondingly adjusted.

The PWM counter 172 receives the duty ratio 136 from the duty ratio quantizer 134, the duty ratio 137 from the duty ratio quantizer 134, and the quantization clock signal 190 from the quantization clock 191. The PWM signal 180 and the PWM signal 184 are generated. In one embodiment, PWM signal 180 is generated by counting the number of quantization clock cycles represented by duty ratio 137, and PWM signal 184 is generated by counting the number of quantization clock cycles represented by duty ratio 136. It is generated by counting numbers. The PWM signal 180 and the PWM signal 184 which are all square waveforms are provided to the integrated error amplifier 142 and the power stage 118. The power stage 118 amplifies the PWM signal 180 and the PWM signal 184 to provide an amplified PWM signal 120 and an amplified PWM signal 121. The amplified PWM signal 120 and the amplified PWM signal 121 are provided to the load 126 to represent the audio output of the digital amplifier 100.

3 illustrates an integrated error amplifier 142 in accordance with one embodiment of the present invention. In one embodiment, estimation error 176 is generated using Equations 1-15 corresponding to the block diagram shown in FIG. The estimated error 176 is calculated for both the left half-cycle and the right half-cycle of the random period 132 generated by the random period generator 130. The f generator produces the f functions f1, f2, f3, f4 for the left half-cycle and the right half-cycle, and the I generator produces the I functions I1, I2, I3, I4 for the left half-cycle and the right half-cycle. Create

One embodiment of the present invention is mathematically described using the following variables:

Half-cycle index, k

Cycle index, n

Nominal half-cycle, T ₀ [n]

Random half-cycle, T [n]

Gain constant, C1, C2, C3, C4

Delay digital signal 162 for left half-cycle, xr [n-1]

Delay digital signal 162 for the right half-cycle, xl [n]

Digital signal 106 for the left half-cycle, xl [n]

Digital signal 106 for the right half-cycle, xr [n]

Delay ratio for left half-cycle, dl [n]

Delay ratio for right half-cycle, dr [n]

Duty ratio of PWM signal 180 for left half-cycle, dl ₁ [n]

Duty ratio of PWM signal 180 for right half-cycle, dr ₁ [n]

Duty ratio of PWM signal 184 for left half-cycle, dl ₂ [n]

Duty ratio of PWM signal 184 for right half-cycle, dr ₂ [n]

Using Equation 1, the cycle index n can be calculated.

, 좌측 반-사이클

, Left half-cycle

, 우측 반-사이클

, Right half-cycle

Equation 2 may be used to calculate the adaptation coefficients 145.

Equations 3-6 can be used to calculate the f functions f1, f2, f3, f4 for the left half-cycle.

Equations 7-10 can be used to calculate the f functions f1, f2, f3, f4 for the right half-cycle.

Equations 11-14 can be used to calculate the I functions I1, I2, I3, and I4 for both the right half-cycle and the left half-cycle.

Estimation error 176 can be calculated using equation (15).

4 shows in a flowchart a function performed by one embodiment of the present invention. In one embodiment, the flowchart 401 begins at the beginning of the DPSG 110. Flow 401 then proceeds to step 404 where a random period is generated by the random period generator 130. Flow 401 then proceeds to step 408, where the adaptation coefficients are calculated based on the random period. Flow 401 then proceeds to step 412 where the f generator calculates the f functions f1, f2, f3, f4 for the left half-cycle of the random period generated by the random period generator 130. do. The f function (Equation 3-6) is a function of the digital signal 106, the random period 132, the delay digital signal 162, the PWM signal 180, and the PWM signal 184. Flow 401 then proceeds to block 416, where the I functions I1, I2, I3, I4 are calculated for the left half-cycle. The I function (Equations 11-14) are the f functions for the left half-cycle, the adaptation coefficients 145, and the functions of the previous I functions for the left half-cycle. Flow 401 then proceeds to block 420 where the estimation error 176 is estimated using the I functions and gain constants C1, C2, C3, C4. Flow 401 then proceeds to block 424 where the digital signal 106 is added with an estimation error 176. Flow 401 then proceeds to block 428 where the duty ratio for the left half-cycle is quantized to set the quantization clock count for the left half-cycle of the PWM signals 180,184. Flow 401 then proceeds to decision diamond 432, where a determination is made as to whether the end of the left half-cycle has been completed. When the end of the left half-cycle is not complete, the decision diamond 432 is repeated until the end of the left half-cycle is completed. When the end of the left half-cycle is complete, flow 401 causes the f generator to perform the f functions f1, f2, f3, f4 for the right half-cycle of the random period generated by the random period generator 130. The calculation proceeds to block 436. The f functions (Equation 7-10) for the right half-cycle are functions of the digital signal 106, the random period 132, the delay digital signal 162, the PWM signal 180, and the PWM signal 184. admit. Flow 104 then proceeds to block 440 where the I functions I1, I2, I3, I4 are calculated for the right half-cycle. The I functions for the right half-cycle (Equations 11-14) are the f functions for the right half-cycle, the adaptation coefficients 145, and the functions of the previous I functions for the right half-cycle. Flow 104 then proceeds to block 444 where the estimation error 176 is estimated using the I functions for the right half-cycle and gain constants C1, C2, C3, C4. Flowchart 401 then proceeds to block 448, where the digital signal 106 is added with an estimation error 176. Flow 401 then proceeds to block 452 where the duty ratio for the right half-cycle is quantized to set the quantization clock count for the right half-cycle of the PWM signals 180,184. Flow 401 then proceeds to decision diamond 456 where a determination is made as to whether the end of the right half-cycle has been completed. When the end of the right half-cycle is not complete, the decision diamond 456 repeats until the end of the right half-cycle is complete. When the end of the right half-cycle is complete, flow 401 proceeds to block 404.

5 shows a simulation (high peak value 502) of a fixed period generator with a fixed switching frequency as compared to a simulation using a random period generator with a random switching frequency (low peak value 504). At the high peak value 502, a large portion of the spectral content lies at 125 kHZ. Using the random period generated by the random period generator 130, the switching frequency noise is distributed over a wide frequency spectrum (as shown by the low peak value 504), so that the low pass filter needs to perform a similar operation. There should be no.

6 shows a time domain representation of some signals used and / or generated in digital amplifier 100 (shown in FIGS. 1 and 2). The digital input signal 106 is a PCM signal represented as the input PCM signal 106. Sample points 1A and 1B are shown as intersections between the random period signal 132 and the calibrated digital signal 168, displayed as a random period trigonometric function. Sample point 1A corresponds to the first original sample point in the left half-cycle of the calibrated digital signal 168. Sample point 2A corresponds to the negative of the first original sample point (relative to the center point 1 of the random period trigonometric function) in the left half-cycle of the calibrated digital signal 168. Sample point 1B corresponds to the first original sample point in the right half-cycle of the calibrated digital signal 168. Sample point 2B corresponds to the negative point of the first original sample point of the right half-cycle of the calibrated digital signal 168. In one embodiment, since both the left half-cycle and the right half-cycle have a half-cycle duration of T [n], the random period of the random period trigonometric function has a period duration of 2T [n]. The quantized predictive PWM signal 180 represents the output of the PWM signal 180 by the PWM counter 172, and the quantized PWM signal 184 represents the output of the PWM signal 184 by the PWM counter 172. Predictive PWM signal 180 and predictive PWM signal 184 represent unquantized versions of PWM signal 180 and PWM signal 184 respectively.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. Any benefit, advantage, solution of a problem, and any device that could cause any benefit, advantage, or solution to occur or become more known may be construed as an important, essential, or fundamental feature or device of any or all claims Should not be. As used herein, the terms "comprises", "comprising" or any other variation thereof are intended to encompass non-exclusive comprehensiveness, thus forming a list of devices. It is intended that the process, method, article, or apparatus that is described not only includes those elements, but may also include other elements that are not explicitly listed or unique to such processes, methods, products, or devices.

Claims (20)

As digital amplifier 110, Digital PWM signal generator 110 with integrated noise shaping to generate a digital pulse width modulation (PWM) signal-digitally calibrated with the outer band of the audio band of interest in the digital PWM signal generation The PWM signal generator is responsive to the digital signal input 106 and the random period signal 132 to redistribute the quantized noise of the signal input 168; And A power stage 118 responsive to the digital PWM signal to provide an amplified digital PWM signal 122 Digital amplifier comprising a. 2. The digital signal input of claim 1, further comprising a digital source (102) providing said digital signal input (106), said digital signal input (106) comprising a pulse code modulated (PCM) signal or a pulse density modulated (PDM) signal. Digital amplifier included. 2. The digital amplifier of claim 1 wherein the digital PWM signal generator (110) reduces the effects of electromagnetic interference on the digital PWM signal using the random period signal (132). 2. The digital amplifier of claim 1 wherein the digital PWM signal generator (110) uses the integrated noise shaping to reduce the amount of noise due to quantization of the calibrated digital signal in the digital PWM signal generation. An apparatus 110 for generating a digital PWM signal, A random periodic signal generator 130 for generating a random periodic signal; A noise shaping unit (147) responsive to at least the digital signal (106), the random periodic signal (132), and the delay digital signal (162) for generation of a calibrated digital signal (168); The calibrated digital signal 168, the random periodic signal 132, and the quantized clock signal 190 to generate a first duty ratio signal 136 and a second duty ratio signal 137. A duty ratio quantizer 134 responsive to; And PWM counter 172 responsive to first and second duty ratio signals 136 and 137 and quantization clock signal 190 to generate positive and negative PWM signals 180 and 184, respectively. Device comprising a. 6. The apparatus of claim 5, wherein the random periodic signal (132) further comprises an independently variable frequency signal, wherein the independently variable frequency signal is variable on a cycle-by-cycle basis. 6. The noise shaping unit 147 of claim 5 further comprising a delay 146, an adaptive coefficient generator 143, an integrated error amplifier 142, and a summer 164, wherein the delay 146 Is responsive to the digital signal 106 and the random periodic signal 132 to further generate a delayed digital signal 162, and the adaptive coefficient generator 143 is adapted to generate the adaptive coefficients 132 to generate adaptive coefficients. And the integrated error amplifier (142) performs a series of noise shaping operations to produce an estimated error signal (176). 8. The integrated error amplifier 142 according to claim 7, wherein the integrated error amplifier 142 is adapted to perform the series of noise shaping operations to produce the estimated error signal 176: adaptive coefficients, the random period signal 132, the Responsive to delayed digital signal 162, the digital signal 106, and positive and negative PWM signals 180, 184, wherein the estimation error signal 176 is coupled between the positive and negative PWM signals 180, 184. Representing a noise shaped error between the difference and the delayed digital signal, wherein the noise shaped error between the PWM signal difference and the delayed digital signal is obtained using the adaptive coefficient and the digital signal. Device that is noise shaped by an integrated portion of 6. The noise shaping unit 147 according to claim 5, wherein the noise shaping unit 147 functions as a function of the first and second duty ratio signals 136 and 137 to the duty ratio quantizer 134 as an outer band of the audio band of interest. A device for further redistributing quantization noise. 6. The duty ratio quantizer 134 is configured to generate the first and second duty ratio signals 136, 137 for both the left half-cycle and the right half-cycle of the random periodic signal 132. And for the left half-cycle, the duty ratio quantizer 134 is configured to calculate a first duration and a first random half-cycle signal of the predicted quantized version of the positive and negative PWM signals 180, 184. To generate the first and second duty ratio signals 136 and 137, the first random half-cycle signal corresponding to the left half-cycle of the random period signal 132, and the positive and negative The first duration of the predicted quantized version of a PWM signal (180, 184) corresponds to the calibrated digital signal (168) for the left half-cycle of a random periodic signal (132). (None) 11. The method of claim 10, wherein for the right half-cycle, the duty ratio quantizer 134 is configured to generate a second duration and a second random half-of the predicted quantized version of the positive and negative PWM signals 180, 184. Using the periodic signal to generate the first and second duty ratio signals 136 and 137, the second random half-cycle signal corresponding to the right half-cycle of the random period signal 132, and The second duration of the predicted quantized version of the positive and negative PWM signal (180, 184) corresponds to the calibrated digital signal (168) for the right half-cycle of a random period signal (132). 6. The noise shaping unit 147 of claim 5 wherein the noise shaping unit 147 redistributes the quantization noise by the duty ratio quantizer 134 to the outside of the audio band of interest, thereby providing a desired signal-to-band at the output of the power stage 118. -Devices that match the noise rate standard. 6. The PWM counter 172 according to claim 5, wherein the PWM counter 172 counts the number of quantized clock cycles represented by the first and second duty ratio signals 136 and 137, respectively, to indicate positive and negative PWM signals 180 and 184. Device to generate. A method for generating a digital PWM signal, Receiving a digital signal; Generating a random period signal using a random period generator (130), wherein the random period signal has a random period and includes a left half-cycle and a right half-cycle; Calculating adaptive coefficients based on the random period (132); Using a first generator to calculate first functions for the left half-cycle of the random period (132); Using a second generator to calculate second functions for the left half-cycle of the random period (132); Estimating an error signal (176) using the second functions for the left half-cycle; Summing the digital signal (106) and the estimation error signal (176) for the left half-cycle; Quantizing the first and second duty ratios for the left half-cycle to set a quantization clock count for the left half-cycle of the positive and negative PWM signals (180, 184); Using the first generator to calculate first functions (f1, f2, f3, f4) for the right half-cycle of the random period (132); Using the second generator to calculate second functions (I1, I2, I3, I4) for the right half-cycle of the random period (132); Estimating an error signal (176) using the second functions for the right half-cycle; Summing the digital signal and the estimation error signal for the right half-cycle; And Quantizing a first and second duty ratio for the right half-cycle to set a quantization clock count for the right half-cycle of positive and negative PWM signals 180, 184. How to include. The method of claim 15, The first functions for the left half-cycle are functions of the digital signal (106), random period (132), delay digital signal (162), and positive and negative PWM signal (180, 184). 16. The method of claim 15, wherein the second functions are functions of the first functions for the left half-cycle, adaptation coefficients (145), and previous second functions for the left half-cycle. 16. The method of claim 15, wherein the first functions for the right half-cycle include: the digital signal 106, the random period 132, the delayed digital signal 162, and a positive and negative PWM signal 180, 184) functions. 16. The method of claim 15, wherein the second functions for the right half-cycle are the first functions for the right half-cycle, adaptation coefficients 145, and a previous second for the right half-cycle. A method that is a function of functions. The method of claim 15, In response to obtaining the end of the right half-cycle, repeating the method beginning with the generation of a new random period signal instead of a previous random period signal. How to include more.

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