JP2006101531A - Variable degree type delta sigma modulator and da converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set the optimal degree for a sampling frequency used when employing a delta sigma modulator while changing the sampling frequency . <P>SOLUTION: For a delta sigma modulator of three or more degrees, in a combination of two continuous arbitrary integrators which constitute this modulator, the modulator includes a means which intermittently connects a first integrator and a second integrator at a connection part therebetween to the side of the second integrator or a means which switches a connection relation thereof. By intermittently connecting the integrators using the foregoing means or switching the connection relation the degree of the delta sigma modulator is made the optimal degree for the sampling frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a delta sigma modulator, and more particularly to a delta sigma modulator that can be switched to an optimum order with respect to a sampling frequency.

  Currently, DA converters are widely used in mobile phones, PDAs (personal digital assistants), portable music playback, etc., but DA converters equipped with delta-sigma modulators are widely known as DA converters. It has been. This D / A converter equipped with a delta-sigma modulator performs quantization with a small number of bits such as 1-bit quantization by an oversampling circuit and a noise shaping circuit to reduce aliasing, quantization noise, and low-frequency noise. ing.

In the delta-sigma modulator used in the noise shaping circuit, there is a specific relationship between the SN ratio and the order of the delta-sigma modulator for each sampling frequency as shown in FIG. 9 as an example. In the figure, the X axis represents the order of the delta-sigma modulator, and the Y axis represents the SN ratio.
According to this figure, when the sampling frequency is 8 kHz, the SN ratio is about 57 dB when the order of the delta-sigma modulator is third order, and the SN ratio is 55 dB when the order increases to the fourth order and fifth order. It decreases to 40 dB.
On the other hand, when the sampling frequency is 16 kHz, the SN ratio is about 62 dB when the order of the delta-sigma modulator is second order, and when the third order and fourth order, the SN ratio increases to about 72,73 dB, and the fifth order. It decreases to about 69 dB.
Further, when the sampling frequency is 32 kHz, when the order of the delta-sigma modulator is 2, the S / N ratio increases when the order is 80 dB and when the order is 3rd, and when the order is 4th and 5th, the peak is about 90 dB.
As is clear from this, when the order increases with the sampling frequency, there are cases where the S / N ratio increases or decreases, and a higher order always does not give a high S / N ratio. FIG. 9 shows an example, and the pattern shown in FIG. 9 is not always obtained.

Conventionally, since the delta-sigma modulator used for the DA converter is designed assuming a constant sampling frequency, its order is fixed and cannot be freely changed. However, as seen in mobile phones in recent years, there are cases where the phone is used in a voice mode for calling or in an audio mode for outputting downloaded music, and the number of cases where a DA converter is used at a different frequency has increased. ing.
In this case, when the DA converter is used in the audio band (20 kHz), the fourth order delta-sigma modulation which is the optimum order is used in order to maximize the SN ratio in accordance with the sampling frequency (44.1 kHz) as described above. Or a 5th order delta sigma modulator, but if this delta sigma modulator is used at a low sampling frequency (8 kHz) for handling speech, the order is compared to a 2nd or 3rd order delta sigma modulator As a result, the S / N ratio becomes worse.
Conversely, when using the modulator at a low sampling frequency (8 kHz), the third-order delta-sigma modulator, which is the optimal order, is selected. Therefore, when the modulator is used at a high sampling frequency of 44.1 kHz, the order is The SN ratio is worse than that of the 4th and 5th order.
Thus, there is a fixed relationship between the sampling frequency and the optimum order. For example, when the sampling frequency is 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, and 48 kHz, it is apparent that the second order, fourth order, fifth order, fourth order (or fifth order), and fifth order are optimum. This is shown in FIG.

  In order to deal with the above problem and always set the optimum order even if the sampling frequency is changed, for example, a delta sigma modulator from the first order to the nth order is made in advance as the delta sigma modulator, It is conceivable that the selection can be made by switching. However, in such a method, the circuit scale increases, the cost increases, and there is a lot of waste. In addition, regarding the order switching operation, it is very troublesome to manually perform the order switching at each sampling frequency switching, and erroneous operations are likely to occur.

The present invention has been made to solve the above-described problem, and its object is to always set an optimal order for a sampling frequency to be used when a plurality of sampling frequencies are switched in a delta-sigma modulator. In other words, the variable delta sigma modulator is realized with a circuit configuration as simple as possible.
Another object of the present invention is to realize a delta-sigma modulator capable of detecting a new sampling frequency when the sampling frequency changes and automatically switching to the optimum order.
Another object of the present invention is to realize a DA modulator having an optimum S / N ratio with respect to a sampling frequency to be used by using a variable-order delta-sigma modulator as a noise shaper.

A first to kth (where k is an integer of 2 or more) quantized signal generation comprising an integrator and a quantizer that quantizes an output signal of the integrator, respectively. Means, (k-1) differential signal generators cascaded to the output side of the kth quantized signal generating means, and the quantization error of the (k-1) th quantized signal generating means Or a switching means that switches the 0 signal to be an input signal of the integrator of the k-th quantized signal generating means, an output signal of the first quantized signal generating means, and a cascaded final stage differential signal An adder for adding the output signal of the generator, and the switching means is switched so as to have an optimum order for the sampling frequency of the input signal of the integrator of the first quantized signal generating means. This is a variable order type delta-sigma modulator.
According to a second aspect of the present invention, there are provided a plurality of integrators connected in cascade via switching means, a quantizer that quantizes the output signal of the final stage integrator, an input signal, and an output signal of the quantizer. And a means for supplying the output signal of the subtractor to the first-stage integrator, wherein the switching means outputs the output signal of the previous-stage integrator or A variable-order delta-sigma modulator configured to switch and supply a signal obtained by multiplying the output signal by a predetermined coefficient or a zero signal, wherein the switching is performed so that the order becomes optimum for the sampling frequency of the input signal. A variable order type delta-sigma modulator characterized by switching means.
According to a third aspect of the present invention, in the variable-order delta-sigma modulator according to the first or second aspect, a table showing a relationship between a sampling frequency and an optimal order as the sampling frequency is switched, and a switching state and order of the switching means. The variable-order delta-sigma modulator is provided with control means for performing switching control of the switching means based on a table showing the relationship between
According to a fourth aspect of the present invention, there is provided means for changing the order of the delta sigma modulator by changing a combination of a plurality of integrators constituting the delta sigma modulator, and the order of the delta sigma modulator is provided by the changing means. Is a variable order type delta sigma modulator whose order is in accordance with the sampling frequency of the input signal, wherein the variable order type delta sigma modulator is changed to an order that maximizes the SN ratio at the sampling frequency. is there.
A fifth aspect of the present invention is a DA converter including the delta-sigma modulator according to any one of the first to fourth aspects.

According to the first, second, and fourth aspects of the present invention, it is possible to realize a delta-sigma modulator having an optimum order for each sampling frequency to be used in a device that can switch the sampling frequency. As a result, it is possible to maintain a characteristic that always gives the highest S / N ratio.
According to the invention of claim 3, since the order of the delta-sigma modulator can be automatically switched in accordance with the switching of the sampling frequency, the best characteristic is always obtained without the user having to manually switch the order of the delta-sigma modulator. Can be obtained.
According to the invention of claim 5, it is possible to realize a DA modulator having an optimum S / N ratio with respect to a sampling frequency to be used.

  FIG. 1 is a block diagram showing a delta-sigma modulator according to a first embodiment of the present invention. In the figure, an adder 1 adds a digital input signal X and a delayed signal of a post-quantization error -Q1, and a quantizer 2 is supplied with the output of the adder 1 and outputs a quantized signal Y1. 3 adds the quantized signal Y1 and the output of the adder 9 described later, and outputs a delta-sigma modulation output Y. The subtracter 4 subtracts the quantized signal Y1 from the output U1 of the adder 1, The quantization error -Q1 is output, and the delay circuit 5 is provided between the subtracter 4 and the adder 1, and generates a delay signal of the quantization error -Q1. Here, the adder 1, the subtractor 4, and the delay circuit 5 constitute an integrator. That is, this integrator is configured to add a one-sample delay signal of quantization error of its own integration output to the input signal. The same applies to the integrator in the next stage.

  The adder 6 adds the first quantization error −Q1 which is the output of the subtractor 4 and the signal obtained by delaying the output of the subtractor 10 described later, and outputs an addition output U2. A selector Se <b> 1 that selects the output of the terminal 18 that supplies the 0 signal is provided between the adder 6 and the subtractor 4. The quantizer 7 quantizes the added output U2 and outputs a quantized signal Y2. The difference signal generator 8 generates a quantized signal Y2 and a delayed output difference signal. An adder 9 adds the difference signal and a postscript. The signal from the difference signal generator 15 is added, and the subtracter 10 subtracts the output Y2 of the quantizer 7 from the output U2 of the adder 6, and outputs a second quantization error -Q2. The delay circuit 11 is provided between the subtracter 10 and the adder 6, and generates a delay signal of the second quantization error -Q2.

  The adder 12 adds the second quantization error −Q2 that is the output of the subtracter 10 and the signal obtained by delaying the output of the subtractor 16 described later, and outputs an addition output U3. A selector Se <b> 2 that selects the output of the subtracter 10 and the output of the terminal 19 that supplies a 0 signal is provided between the adder 12 and the subtractor 10. The quantizer 13 quantizes the addition output U3 and outputs a quantized signal Y3. The difference signal generator 14 generates a difference signal between the quantized signal Y3 and its delayed output. The difference signal generator 15 outputs a difference signal. A difference signal between the signal from the generator 14 and its delayed output is generated, and the subtracter 16 subtracts the output Y2 of the quantizer 7 from the output U3 of the adder 12. The delay circuit 17 is provided between the subtracter 16 and the adder 12, and generates a delay signal of the third quantization error -Q3.

  In this circuit, the relationship between the selector and the order will be described. When the selector Se1 is connected to the output side of the subtractor 4 and the selector Se2 is connected to the output side of the subtractor 10, a modulator composed of three integrators is formed, and a third-order delta-sigma modulator is configured. Further, when the selector Se1 is connected to the output side of the subtractor 4 and the selector Se2 is connected to the terminal 19 for supplying the 0 signal, the circuit block of the delay circuit 17 is disconnected from the adder 12, so that the secondary circuit Delta-sigma modulators are configured. Further, when the selectors Se1 and Se2 are connected to the terminals 18 and 19 for supplying the 0 signal, the circuit block extending from the adder 6 to the delay circuit 11 is also cut off, so that a primary delta-sigma modulator is obtained.

In this way, a delta-sigma modulator configured to supply quantization error to the next-stage integrator realizes a variable-order delta-sigma modulator by interposing a selector in the connection circuit that transmits the quantization error to the next stage. can do.
In this embodiment, the third-order delta-sigma modulator of the type that supplies the quantization error to the integrator of the next stage has been described. Similarly, it is possible to construct a delta sigma modulator of the fourth order or higher by supplying the quantization error to the integrator of the next stage. Similarly, in the delta sigma modulator of the fourth order or higher, the quantization error is similarly applied to the integrator of the next stage. It is obvious that the order can be made variable by providing a selector for interrupting the circuit in the connection section supplied to the circuit.

FIG. 2 is a block diagram of a fifth-order delta-sigma modulator circuit showing the second embodiment of the present invention.
In the figure, 101 is an input terminal, 102 is an output terminal, 103 is a quantizer, S1 to S7 are selectors, 111, 114, 117, 119, 122 and 124 to 130 are multipliers, 112, 115 and 120 are subtractors, Reference numerals 135 to 138 denote adders, 113, 116, 118, 121, and 123 denote integrators, and 131 to 134 denote 0 terminals (hereinafter referred to as 0 output terminals) that supply 0 signals. The modulator is configured as follows. Has been.
The multiplier 111 is connected to the input terminal 101, the output is supplied to the addition input terminal of the subtractor 112, the signal from the subtractor 112 is supplied to the first integrator 113, and the signal of the integrator 113 is the multiplier 114. And supplied to the multiplier 124. The signal of the first integrator 113 and the signal of the multiplier 114 are selected by the selector S1, and the selected signal is input to the addition input terminal of the subtractor 115. The subtractor 115 is connected to the second integrator 116, and the output of the second integrator 116 and the first 0 output terminal 131 are selected by the selector S 5, and the signal of the selector S 5 passes through the multiplier 117 to the third integration. Connected to the instrument 118. The signal from the third integrator 118 is supplied to the multiplier 119, the output of the multiplier 119 and the 0 input terminal 132 are selected by the selector 6, and the selected signal is supplied to the addition input terminal of the subtractor 120. The The signal of the subtractor 120 is supplied to the fourth integrator 121, the output thereof and the 0 output terminal 133 are selected by the selector S 7, and further input to the fifth integrator 123 via the multiplier 122. The signal from the integrator 123 is input to the first input terminal of the adder 136 via the multiplier 128, and the signal from the adder 136 is supplied to the output terminal 102 via the quantizer 103.

The signal Y from the quantizer 103 is supplied to the subtraction input terminal of the subtractor 112. The signal from the quantizer 103 and the signal from the third integrator 118 via the multiplier 129 are selected by the selector S4 and input to the subtraction input terminal of the subtractor 115.
The signal of the fifth integrator 123 is fed back to the subtraction input terminal of the subtractor 120 through the multiplier 130.

Further, the signal from the first integrator 113 through the multiplier 124 and the 0 input terminal 134 are selected by the second selector S 2 and input to the input terminal of the adder 135. The signal from the second integrator 116 through the multiplier 125 and the signal from the second integrator 116 are selected by the selector S 3, and the selected signal is input to the input terminal of the adder 135.
Further, the signal of the third integrator 118 passes through the multiplier 126 and is input to the adder 136 together with the signal of the adder 135. The signal from the adder 136 is input to the adder 137 together with the signal that has passed through the multiplier 127 from the integrator 121. Finally, the output signal of the adder 137 is input to the second input terminal of the adder 138.
The above is the circuit configuration of FIG.

Next, in the delta sigma modulator, the point of switching the order using a selector will be described. Here, when the N terminal and F terminal of each selector are defined, the N terminal is the output terminal of the multiplier 114 and the F terminal is the output terminal of the integrator 113 for the selector S1.
In the selector S2, the N terminal is the output terminal of the multiplier 124, and the F terminal is the output terminal of the 0 output 134.
For the selector S3, the N terminal refers to the output terminal of the multiplier 125, and the F terminal refers to the output terminal of the second integrator 116.
For the selector S4, the N terminal refers to the output terminal of the multiplier 129, and the F terminal refers to the output 102 terminal.
Regarding the selector S5, the N terminal refers to the output terminal of the integrator 116, and the F terminal refers to the 0 output 131 terminal.
For the selector S6, the N terminal refers to the output terminal of the multiplier 119, and the F terminal refers to the 0 output 132 terminal.
For the selector S7, the N terminal refers to the output terminal of the integrator 121, and the F terminal refers to the 0 output 133 terminal.

  In the case where the selectors 1 to 7 are connected to the F terminal in FIG. 2 based on the definition as described above, FIG. That is, the rewritten delta-sigma modulator has an input terminal 101, a multiplier 111, an adder 112, an integrator 113, an adder 115, an integrator 116, a quantizer 103, and an output terminal 102 connected in cascade. Y is fed back to the two adders 112 and 115 as a subtraction input. This delta-sigma modulator is a second-order delta-sigma modulator because integrators 113 and 116 are provided in the feedback loop.

Next, when the selectors S1 to S5 are connected to the N terminal and the selectors S6 and S7 are connected to the F terminal, FIG. 2 in this case can be rewritten as shown in FIG. In other words, the new delta sigma modulator has a multiplier 117 and an integrator 118 cascaded as components in the second order delta sigma modulator of FIG. 3 and the integrator 118 outputs the multiplier 129. Is fed back to the adder as a subtraction input.
The outputs of the integrator 113 and the integrator 116 are input to the adder 135 via the multipliers 124 and 125, respectively. The output of the adder 135 is supplied to the adder 136 together with the output of the integrator 118 via the multiplier 126. Entered. Next, the output of the adder 136 is supplied to the quantizer 103 to output a quantized output Y, and the output Y is fed back to the adder 112 as a subtraction input. Since the delta-sigma modulator has three integrators 113, 116, 118, the order of the delta-sigma modulator is the third order.

Similarly, when the selectors S1 to S6 are connected to the N terminal and the selector S7 is OFF at the N terminal, the delta sigma modulator has four integrators and becomes a fourth order delta sigma modulator.
Further, when all the selectors S1 to S7 are connected to the N terminal, since there are five integrators, a fifth-order delta sigma modulator is obtained.

These are summarized as shown in the table of FIG. 5, and a table showing the relationship between the order and the selector selection terminal can be created.
As described above, in the present embodiment, by providing the selectors S1 to S7 and changing the connection relationship of the circuits, a variable-order delta-sigma modulator can be realized without increasing the circuit scale.

FIG. 7 shows a delta-sigma modulator having control means for automatically switching to the optimum order in accordance with the sampling frequency switching according to the third embodiment of the present invention. In the figure, a delta-sigma modulator 40 is a variable-order modulator having a selector means, a CPU 41 performs control to realize an optimum-order modulator according to a sampling frequency, and a sampling frequency detector 42 is a current sampling frequency. The storage device 43 stores a table M and a table N. Table M is a table of combinations of the sampling frequency created from the order-to-SNR graph shown in FIG. 9 and the optimum order (according to FIG. 9, the sampling frequency is 8 kHz, 16 kHz, 32 kHz, 44.1 kHz). , 48 kHz, the second order, the fourth order, the fifth order, the fourth order (or fifth order), and the fifth order are optimal, and if this is used as a table, the table of FIG. Is a table showing the connection relationship of integrators by means for changing the combination of the order of the modulator and a plurality of integrators (for example, the connection relationship between the order of the delta-sigma modulator shown in FIG. 5 and the selection terminal of the selector Can be listed).
The sampling frequency detector 42 detects the switched sampling frequency and notifies this to the CPU. The CPU refers to the sampling frequency and the table M stored in the storage device to determine the optimum order for the sampling frequency, and then to implement the delta sigma modulator of this order. Based on N, the connection relation of the selector is determined. Next, a control signal for determining the connection relation of the selectors is sent to the delta sigma modulator 40, and the variable order delta sigma modulator realizes the optimum order delta sigma modulator based on this signal.
In this embodiment, an example is shown in which the sampling frequency is detected by the sampling frequency detection means. However, the present invention is not limited to this, and the sampling frequency is set and the numerical value of the set sampling frequency is used. It is not excluded.

  FIG. 8 shows a DA converter according to the fourth embodiment of the present invention. The digital input signal is input to the oversampling circuit 50, which increases the sampling frequency of the digital signal and supplies the output signal to the noise shaper 51. The noise shaper 51 reduces low-frequency noise and supplies a noise shape signal to the waveform shaping circuit 52 and the LPF 53. The digital signal is converted into an analog signal by the waveform shaping circuit 52 and the LPF 53. By using the variable-order delta-sigma modulator as the noise shaper 51, a DA modulator having an optimum SN ratio with respect to the sampling frequency to be used can be realized.

1 is a circuit block diagram of a variable order delta sigma modulator according to a first embodiment of the present invention. It is a circuit block diagram of the variable order delta-sigma modulator which is the 2nd Embodiment of this invention. It is an equivalent circuit block diagram when all the selectors are connected to the F terminal in the variable-order delta-sigma modulator according to the second embodiment of the present invention. FIG. 6 is an equivalent circuit block diagram when selectors S1 to S5 are connected to an N terminal and adder selectors S6 and S7 are connected to an F terminal in a variable-order delta-sigma modulator according to a second embodiment of the present invention. . 6 is a table describing the relationship between the connection state of the selector and the order in the variable-order delta-sigma modulator according to the second embodiment of the present invention. It is a table describing the relationship between the sampling frequency and the optimum order. A delta-sigma modulator having means for automatically switching the order. It is a block diagram of a DA converter. It is a graph which shows the relationship between the order of a delta-sigma modulator for every sampling frequency, and SN ratio.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Adder, 2 ... Quantizer, 4 ... Subtractor, 5 ... Delay circuit, Se ... Selector, 113, 116, 118, 121, 123 ... Integrator 111, 114, 117 ... multipliers, S1-S7 ... selectors, 131-134 ... 0 signal supply terminals.

Claims (5)

First to k-th (where k is an integer of 2 or more) quantized signal generation means each including an integrator and a quantizer that quantizes the output signal of the integrator;
(K−1) differential signal generators cascaded to the output side of the kth quantized signal generating means;
Switching means for switching the quantization error or 0 signal of the (k-1) th quantized signal generating means to be an input signal of the integrator of the kth quantized signal generating means;
An adder for adding the output signal of the first quantized signal generating means and the output signal of the cascaded final stage differential signal generator;
A variable-order delta-sigma modulator characterized in that the switching means is switched so as to have an optimum order for a sampling frequency of an input signal of an integrator of the first quantized signal generating means. A plurality of integrators cascaded through switching means;
A quantizer that quantizes the output signal of the final-stage integrator;
A subtractor that outputs a difference signal between the input signal and the output signal of the quantizer;
Means for supplying the output signal of the subtractor to the first-stage integrator,
The switching means switches the variable-order delta-sigma modulation so that the output signal of the previous-stage integrator, the signal obtained by multiplying the output signal by a predetermined coefficient, or the zero signal is supplied to the subsequent-stage integrator. A vessel,
The variable order type delta-sigma modulator characterized in that the switching means is switched so as to have an optimum order for the sampling frequency of the input signal. The variable order type delta-sigma modulator according to claim 1 or 2,
Control means for performing switching control of the switching means based on a table indicating the relationship between the sampling frequency and the optimal order in accordance with the switching of the sampling frequency and a table indicating the relationship between the switching state of the switching means and the order. A variable-order delta-sigma modulator characterized by the above. There is provided means for changing the order of the delta sigma modulator by changing a combination of a plurality of integrators constituting the delta sigma modulator, and the means for changing the order of the delta sigma modulator to the sampling frequency of the input signal. A variable order delta-sigma modulator with a corresponding order,
The variable-order delta-sigma modulator is characterized in that the order is changed to the order in which the SN ratio at the sampling frequency is maximized.   A DA converter comprising the delta-sigma modulator according to any one of claims 1 to 4.

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