JP5789446B2 - MOS type solid-state imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to a solid-state image sensor on which a MOS transistor circuit is mounted as a signal readout circuit and an image pickup apparatus using the same.

  A solid-state imaging device used in an imaging apparatus such as a digital camera or a camera-equipped mobile phone is increased in number of pixels, and some of them have 10 million pixels or more. Each pixel (photoelectric conversion element: photodiode) of the solid-state imaging device is provided with a signal readout circuit that reads out a captured image signal detected by each pixel to the outside. By reducing the area of the signal readout circuit occupying the image sensor chip, it is possible to further increase the number of pixels of the solid-state image sensor, and to reduce the area and size of the image sensor chip.

  For example, in a CMOS type solid-state imaging device, a signal readout circuit having a three-transistor configuration and a signal readout circuit having a four-transistor configuration described in FIG. 2 of Patent Document 1 are provided for each pixel. Compared to a CCD solid-state image sensor that requires a vertical charge transfer path or a horizontal charge transfer path as a signal readout circuit, a CMOS solid-state image sensor can form a smaller transistor, so that the area of the photodiode in the image sensor chip is widened. There is an advantage that it can be taken. However, as illustrated in FIG. 10 of Patent Document 1, the transistor provided on the side of the photodiode also requires a required area.

  In recent solid-state image sensors, there are conflicting demands for downsizing the image sensor chip and increasing the number of pixels. Also for the CMOS type solid-state imaging device, it is required to reduce the number of transistors in order to reduce the area occupied by the signal readout circuit.

  Therefore, in the prior art described in Patent Document 2 below, two pixels share one signal readout circuit to reduce the number of transistors per pixel. However, even in the configuration in which two pixels share one signal readout circuit, the number of transistors is still large, and further reduction in the number of transistors is required.

  In the prior art described in FIGS. 9B and 9D of Patent Document 3 below, a common signal readout unit is provided in the central portion of the four adjacent pixels, and one signal readout circuit is shared by the four pixels. It has become. If one signal readout circuit can be shared by four pixels, the number of transistors can be reduced and the area of the photodiode can be increased.

  However, there is a solid-state imaging device having a pixel array and a color filter array to which the technique of Patent Document 3 cannot be applied as it is. FIG. 12 shows a schematic surface view of the solid-state imaging device (for example, FIG. 2 of Patent Document 4).

  This solid-state imaging device has a so-called honeycomb pixel arrangement in which even-numbered pixel rows are arranged with a 1/2 pixel pitch shifted in the row direction with respect to odd-numbered pixel rows. Further, in this solid-state imaging device, the three primary color filters mounted on the first group pixels in the square lattice arrangement composed of odd-numbered rows of pixels are arranged in a Bayer arrangement (lower case r (red) g (green) b (blue). It is indicated by.) In addition, the three primary color filters mounted on the second group of pixels in a square lattice array composed of pixels in even rows are also Bayer array (indicated by capital letters R (red) G (green) B (blue)). ing.

  In this solid-state imaging device, r pixels and R pixels, g pixels and G pixels, and b pixels and B pixels that are diagonally closest to each other constitute a pair pixel (two pixels indicated by each ellipse 3 in FIG. 12). Then, by performing mixed readout of signal charges between the paired pixels, the sensitivity of the captured image signal can be increased. Further, by performing mixed readout while changing one exposure time and the other exposure time of the paired pixels, it is possible to expand the dynamic range of the captured image signal.

  9 (b) and 9 (d) of Patent Document 3 is applied to the solid-state imaging device shown in FIG. 12, and one signal is read out to the four adjacent pixels shown by the dotted line frame 4 and the dotted line frame 5 shifted by one diagonal line in FIG. Consider the case where a circuit is applied. In this case, the relationship between the paired pixels is lost, and pixel mixing inside the solid-state imaging device becomes impossible.

JP 2007-81140 A JP 2008-99073 A JP 2009-290659 A JP 2007-124137 A

  In the solid-state imaging device having the pixel array and the color filter array shown in FIG. 12, as described above, when performing high-sensitivity imaging and wide dynamic range imaging, pixels can be mixed in the element and signals can be read at high speed. The technique of Patent Document 3 cannot be applied as it is. For this reason, it is necessary to reduce the number of transistors in the signal readout circuit without destroying the relationship of the paired pixels to be mixed with pixels.

  An object of the present invention is to provide a MOS type solid-state imaging device capable of reducing the number of transistors in a signal readout circuit without destroying the relationship of paired pixels, and an imaging device equipped with the solid-state imaging device.

The MOS type solid-state imaging device of the present invention includes a first pixel group in which three primary color filters are arranged in a Bayer array, and a three primary color color filter that is shifted by 1/2 pixel pitch in both the horizontal and vertical directions with respect to the first pixel group. A MOS type solid-state imaging device including a second pixel group arranged, having a first pixel belonging to the first pixel group, and a color filter of the same color as the first pixel, and oblique to the first pixel Is read out by a total of four pixels: a first pair pixel consisting of a pair with one second pixel belonging to the second pixel group adjacent to the second pixel group and a second pair pixel adjacent to the pair pixel in the vertical direction A unit is formed, and a signal readout circuit composed of one common MOS transistor circuit is provided for each of the four pixels. Between each of the pixels, a lattice-shaped element isolation region for separating each pixel is provided. The read unit Has 4 pixels each read transistor serving as said of said read unit and the device isolation region separating between two pixels for forming the first pair pixel, a pair of pixels of the first included The two pixels are connected via the readout transistor provided in each of the two pixels at the intersection of the element isolation region that separates the second pair pixel and the first pair pixel. The read transistor of the two pixels is provided at a corner facing the intersection of the element isolation region where the first floating diffusion exists, and the second pair of pixels the read units adjacent in a direction perpendicular to said read unit or said read out unit includes the element separation region, a pair of pixels of the second to separate between the two pixels forming the The intersection between the isolation region separating between the first pair pixel and the second pair of pixels, the two pixels that are connected to each other through said read transistor provided in each of the two pixels The readout transistor of the two pixels has a second floating diffusion, and is provided at a corner facing the intersection position of the element isolation region where the second floating diffusion exists, and constitutes the signal readout circuit. The reset transistor and the output transistor are provided at different lattice positions in the element isolation region.

  An imaging apparatus according to the present invention includes the MOS solid-state imaging device described above and a control unit that performs pixel addition reading of the paired pixels.

  According to the present invention, the number of transistors in the signal readout circuit can be reduced without destroying the relationship between the paired pixels, and the light receiving area of the pixel (photodiode) can be relatively widened.

It is a functional block diagram of the imaging device concerning one embodiment of the present invention. It is a figure which shows the pixel arrangement | sequence and color filter arrangement | sequence of the MOS type solid-state image sensor shown in FIG. It is the surface conceptual diagram which showed the arrangement position of the pixel (photodiode) and signal readout circuit of the solid-state image sensor shown in FIG. FIG. 4 is an enlarged view of one readout unit pixel group in the arrangement of readout unit pixel groups shown in FIG. 3. FIG. 5 is a circuit diagram of a readout unit pixel group shown in FIG. 4. It is the surface conceptual diagram which showed the arrangement position of the pixel of the solid-state image sensor which concerns on another embodiment of this invention, and a signal read-out circuit. FIG. 7 is an enlarged view of one readout unit pixel group in the arrangement of readout unit pixel groups shown in FIG. 6. It is the surface conceptual diagram which showed the arrangement position of the pixel of the solid-state image sensor which concerns on another embodiment of this invention, and a signal read-out circuit. FIG. 9 is an enlarged view of one readout unit pixel group in the arrangement of readout unit pixel groups shown in FIG. 8. FIG. 10 is a circuit diagram of the readout unit pixel group shown in FIG. 9. It is a figure which shows the pixel arrangement | sequence and color filter arrangement | sequence which concern on another embodiment of the MOS type solid-state image sensor shown in FIG. It is explanatory drawing at the time of applying a prior art to the MOS type solid-state image sensor of FIG.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block configuration diagram of a digital camera (imaging apparatus) equipped with a solid-state imaging device according to an embodiment of the present invention. A digital camera 10 shown in FIG. 1 includes a photographic optical system 21 that includes a photographic lens 21a, a diaphragm 21b, and the like, and an imaging element chip 22 that is disposed at a subsequent stage of the photographic optical system 21.

  The image pickup device chip 22 has a single image solid-state image pickup device 22a for color image pickup having a signal readout circuit constituted by a MOS transistor circuit, and automatic gain adjustment (AGC) for analog image data output from the solid-state image pickup device 22a. And an analog signal processing unit (AFE) 22b that performs analog processing such as correlated double sampling processing, and an analog / digital conversion unit (A / D) 22c that converts analog image data output from the analog signal processing unit 22b into digital image data With. The MOS transistor circuit is preferably a complementary MOS (CMOS) transistor circuit, for example.

  The digital camera 10 further includes a driving unit (timing generator TG) that controls driving of the photographing optical system 21, the solid-state imaging device 22a, the analog signal processing unit 22b, and the A / D 22c according to an instruction from a system control unit (CPU) 29 described later. 23) and a flash 25 that emits light in response to an instruction from the CPU 29. The drive unit 23 may be mounted together in the image sensor chip 22 in some cases.

  The digital camera 10 further takes in digital image data output from the A / D 22c and performs known image processing such as interpolation processing, white balance correction, RGB / YC conversion processing, and the image data in JPEG format. A compression / decompression processing unit 27 that compresses or reversely compresses image data such as a display, a display unit 28 that displays a menu or the like, displays a through image or a captured image, and system control that performs overall control of the entire digital camera A media interface (I / F) unit 31 that performs interface processing between a unit (CPU) 29, an internal memory 30 such as a frame memory, and a recording medium 32 that stores JPEG image data, and the like are connected to each other. The bus 34 is provided. The system control unit 29 is connected to an operation unit 33 for inputting instructions from the user.

  FIG. 2 is a schematic diagram of the surface of the solid-state imaging device 22a shown in FIG. 1, and shows a pixel array and a color filter array. In the example of FIG. 2, odd-numbered pixel rows (a square frame inclined by 45 degrees represents each pixel, and r (red), g (green), and b (blue) on each pixel represent the color of the color filter. In other words, a so-called honeycomb pixel array is formed in which even-numbered pixel rows are shifted by ½ pixel pitch.

  If only the pixels in the odd rows are viewed, the pixel arrangement is a square lattice arrangement, and the three primary color filters rgb are arranged in a Bayer arrangement. Further, even if only the pixels in even rows are viewed, the pixel arrangement is a square lattice arrangement, and the three primary color filters RGB are arranged in a Bayer arrangement. R = red, G = green, and B = blue, and the same color pixels diagonally adjacent form a pair pixel. On each pixel (on the color filter), microlenses having the same shape are mounted on all pixels (not shown).

  In the present embodiment, one signal readout circuit is provided for a total of four pixels: two pair pixels and two pair pixels adjacent to the pair pixel in the vertical direction. These four pixels form a readout unit pixel group, and the readout unit pixel group is arranged in the vertical direction and the horizontal direction. In FIG. 2, an example of the readout unit pixel group is surrounded by a dotted frame 7.

  A vertical scanning circuit (not shown) is provided on the left side portion of the solid-state imaging element 22a. A control signal line for applying a read signal and a reset signal to each pixel row is wired so as to meander between the pixel rows from the vertical scanning circuit. In this embodiment, since one signal readout circuit is provided for four pixels, the control signal lines are reset common to the readout signal lines tg1, tg2, tg3, and tg4 to the four pixels (rows). A signal line Rset is provided.

  A horizontal scanning circuit (not shown) is provided on the lower side of the solid-state imaging element 22a. From the horizontal scanning circuit, signal output lines os and power supply lines Vcc are wired to the pixel columns so as to meander between the pixel columns.

  FIG. 3 is a conceptual plan view in which each transistor constituting a signal readout circuit is provided for the readout unit pixel group arrangement of FIG. Since the drawing becomes complicated, FIG. 4 illustrates one readout unit pixel group in FIG. 3 (the rR pair pixel in the upper left of FIG. 3 and the gG pair pixel in the vertical direction thereof) and its signal readout circuit. FIG. 5 shows a circuit diagram of FIG.

  First, FIG. 5 will be described. The four pixels (photodiode: PD) of the readout unit pixel group are composed of paired pixels PD1 and PD2 and paired pixels PD3 and PD4. The pixel PD1 is connected to FD1 (first floating diffusion) via the read transistor Tr1. The pixel PD2 is connected to the FD1 through the readout transistor Tr2. The pixel PD3 is connected to FD2 (second floating diffusion) via the read transistor Tr3. Pixel PD4 is connected to FD2 via readout transistor Tr4. The read transistors Tr1 to Tr4 of this embodiment function as row read transistors and row select transistors.

  FD1 and FD2 are connected through wiring 8. The two FD1 and FD2 connected by the wiring 8 are connected by the wiring 9 to the gate electrode OG of the drive transistor (output transistor) Dr. The drain terminal of the output transistor Dr is connected to a power supply (Vcc) connection terminal OD. The source terminal of the output transistor Dr is connected to the imaging signal output terminal OS.

  A reset transistor RT is provided between the power supply (Vcc) connection terminal OD and FD1. The reset drain RD of the reset transistor RT is connected to the power supply connection terminal OD. The source region of the reset transistor RT is connected to FD1, that is, the gate electrode OG of the output transistor Dr.

  The gate electrode RG of the reset transistor RT is connected to the reset signal line Rset described with reference to FIG. The signal output terminal OS of the output transistor Dr is connected to the output signal line os in FIG. The gate electrodes TG1, TG2, TG3, TG4 of the read transistors Tr1, Tr2, Tr3, Tr4 are connected to the read signal lines tg1, tg2, tg3, tg4 in FIG. A power connection terminal OD is connected to a power source Vcc (not shown).

  In FIG. 4, PD1, PD2, PD3, and PD4 are configured, for example, by forming island-shaped n regions in a two-dimensional array on the surface p-well layer of the n-type semiconductor substrate or on the surface portion of the p-type semiconductor. The Each n region is separated by a p region. FD1, FD2, reset drain RD, and terminals OD, OS described in FIG. 5 are formed by the n region formed in the element isolation region.

  As shown in FIG. 4, an n region for forming FD1 is provided at a corner on the pixel PD3 side of the adjacent portion of the pixels PD1 and PD2 (intersection portion of a lattice separating each pixel in a lattice shape). The n region of PD1 and the n region of FD1 are separated by a p-type element isolation band. A gate electrode TG1 is formed by laminating an electrode film on the element isolation band via an insulating film. The n region of PD2 and the n region of FD1 are separated by a p-type element isolation band. A gate electrode TG2 is formed by laminating an electrode film on the element isolation band via an insulating film.

  An n region for forming FD2 is provided at a corner on the opposite side of the pixel PD2 adjacent to the pixels PD3 and PD4 (similarly, at the intersection of the lattice). The n region of PD3 and the n region of FD2 are separated by a p-type element isolation band. A gate electrode TG3 is formed by laminating an electrode film on the element isolation band via an insulating film. The n region of PD4 and the n region of FD2 are separated by a p-type element isolation band. A gate electrode TG4 is formed by laminating an electrode film on the element isolation band via an insulating film.

  An n region constituting the reset drain RD is formed at a position along the upper side of the pixel PD3 on the extension line of the boundary between the pixels PD1 and PD2. A gate electrode RG (reset gate) is formed by laminating an electrode film on the p-type element isolation band between the n region of the reset drain RD and the n region of the FD1 via an insulating film.

  An n region serving as an OD terminal (drain terminal of the output transistor) is formed in a portion along the lower side of the pixel PD4 (side opposite to the pixel PD3). Further, an n region that becomes an output terminal (source terminal of the output transistor) OS is formed at a position sandwiching the lower corner of the pixel PD4 with respect to the n region of the OD terminal. A gate electrode OG of the output transistor Dr is formed by laminating an electrode film via an insulating film on the p-type element isolation band between the n regions of the OD terminal and the OS terminal. FD1 and FD2 are connected by a wiring 8 formed in a “<” shape along the pixel boundary. Further, the FD 2 and the gate electrode OG of the output transistor Dr are connected by the wiring 9.

  The configuration of the readout unit pixel group shown in FIG. 4 is repeated in the horizontal direction and the vertical direction, so that the configuration of FIG. 3 is obtained. The gate electrodes TGi of the Tri (i = 1 to 4) of the readout unit pixel groups arranged on the same horizontal line are connected to the same readout signal line tgi (i = 1 to 4). Further, the gate electrode RG of the reset transistor RT of the readout unit pixel group arranged on the same horizontal line is connected to the reset signal line Rset.

  The signal output terminals OS of the readout unit pixel groups arranged on the same vertical line are connected to the same output signal line os, and the power connection terminals OD of the readout unit pixel groups arranged on the same vertical line are connected to the same power supply line Vcc.

  In the solid-state imaging device 22a having such a configuration, charges corresponding to the amount of incident light are accumulated in the pixels PD1 to PD4 of each readout unit pixel group. When the captured image signal for each pixel is read out to the outside, a read pulse is applied to the read signal line tgi. As a result, the corresponding readout transistor Tri becomes conductive, the signal charge of the corresponding pixel PDi is read out to FDi (i = 1, 2), and the signal charge moves to the gate electrode OG of the output transistor Dr. When the power supply voltage Vcc is applied to the OD terminal, the corresponding output transistor Dr is turned on, and a captured image signal corresponding to the amount of signal charge applied to the gate electrode OG of the output transistor Dr is output to the output terminal OS.

  By shifting the application timing of the readout pulse applied to each readout transistor Tr1, Tr2, Tr3, Tr4, the captured image signal of each pixel PD1, PD2, PD3, PD4 can be individually read out.

  The pixel PD1 and the pixel PD2 are stacked with the same color filter, and the pixel PD3 and the pixel PD4 are also stacked with the same color filter. Therefore, a read pulse is applied to the read transistors Tr1 and Tr2 at the same timing. As a result, the signal charges of the pixel PD1 and the pixel PD2 are simultaneously read out to the FD1 and mixed. By reading out the picked-up image signal corresponding to the signal charge amount mixed with the pixels from the output transistor Dr, it is possible to obtain a signal obtained by pixel addition in a short time.

  Next, the signal charge in the gate electrode OG of the output transistor Dr is discarded to the reset drain RD by turning on the reset transistor RT. Then, a read pulse is applied to the read transistors Tr3 and Tr4 at the same timing. As a result, the signal charges of the pixels PD3 and PD4 are mixed, and the captured image signal obtained by adding the pixels can be read, and a highly sensitive image can be captured.

  In the above description, the exposure time of the pixels PD1 and PD2 can be changed by setting the exposure start time of the paired pixels to be the same and shifting the exposure end time, that is, the application timing of the read pulse to the read transistors Tr1 and Tr2. As a result, it is possible to capture an image with a wide dynamic range. The exposure start timing of the paired pixels may be changed and the exposure end timing may be the same.

  According to the embodiment described above, it is possible to read a signal only by providing six transistors in four pixels of the readout unit pixel group, that is, by providing 1.5 transistors per pixel. The required area can be reduced. Further, it is only necessary to provide one horizontal reset signal line for two pixel rows, and one vertical output signal line and one power supply line for two pixel columns. Therefore, the area of the photodiode can be increased accordingly.

  Furthermore, in the present embodiment, the positions where the gate electrodes TG1 and TG2 of the pixels PD1 and PD2 are provided, that is, the positions where the light receiving surfaces of the pixels PD1 and PD2 are missing, and the positions of the gate electrodes TG3 and TG4 of the pixels PD3 and PD4 are determined. It will be the same. For this reason, the optical characteristics of the pixels [PD1 + PD2] and [PD3 + PD4] at the time of pixel addition can be made uniform, and there is an advantage that shading correction becomes easy.

  FIG. 6 is a conceptual diagram of the surface of a solid-state imaging device according to another embodiment of the present invention. FIG. 7 is a diagram in which one readout unit pixel group in FIG. 6 is extracted. The circuit diagram of the readout unit pixel group in FIG. 7 is the same as that in FIG.

  In the present embodiment, the positions of the gate electrodes TG1, TG2, FD1, the reset gate RG, and the reset drain RD are the same as those in the embodiment shown in FIG. However, the positions of FD2, gate electrodes TG3 and TG4, and output transistor Dr are different from those in FIG. In the example of FIG. 6, the FD2 is provided at the end of the boundary between the pixels PD3 and PD4 (intersection of the lattice) at the end opposite to the embodiment of FIG. Thereby, the length of the wiring 8 connecting FD1 and FD2 is the length of one side of the rectangular pixel PD3, which is half that of the embodiment of FIG.

  Furthermore, gate electrodes TG3 and TG4 are provided at the corners of the pixels PD3 and PD4 in the vicinity of the FD2. Further, a gate electrode OG, a drain OD (power supply terminal), and a source terminal (output terminal) OS of the output transistor Dr are provided at an end of the boundary portion between the pixel PD3 and the pixel PD4 opposite to the position where the FD2 is present. .

  Also according to this embodiment, the number of transistors provided for the readout unit pixel group can be reduced to 1.5 per pixel, and the light receiving area of the pixel can be relatively widened. Furthermore, in this embodiment, since the length of the wiring 8 can be shortened, the resistance and parasitic capacitance of the wiring 8 can be reduced, so that the charge detection sensitivity is improved, the S / N of the captured image is improved, and the sensitivity is increased. Can also be planned.

  FIG. 8 is a conceptual diagram of the surface of a solid-state imaging device according to still another embodiment of the present invention. FIG. 9 is a diagram in which one readout unit pixel group in FIG. 8 is extracted. A circuit diagram of the readout unit pixel group in FIG. 9 is shown in FIG. The difference between FIG. 5 and FIG. 10 is that a third floating diffusion FD3 is provided and a reset transistor RT and an output transistor Dr are connected to FD3. In the embodiment of FIG. 8, the drain OD (power supply terminal) and the reset drain RD are also used.

  The gate electrodes TG1, TG2, TG3, and TG4 provided in the readout unit pixel group of this embodiment are the same as those of the embodiment of FIG. 7, but the positions where the FD2 is provided in the embodiment of FIG. 4 (adjacent to the pixel PD3 and the pixel PD4). An FD 3 is provided at a boundary (a corner on the side opposite to the pixel PD 2), and FD 1, FD 2, and FD 3 are connected by a wiring 8.

  Then, the gate electrode RG and the reset drain RD of the reset transistor RT connected to the FD3 are provided on the extension line of the pixel boundary portion connecting the FD2 and the FD3. Further, an output transistor Dr is provided at a corner that is diagonally opposite the corner where the FD2 of the rectangular pixel PD4 is provided. The gate electrode OG and the FD 3 of the output transistor Dr are connected by the wiring 9.

  Even with this configuration, the number of transistors provided for the readout unit pixel group can be reduced to 1.5 per pixel, and the light receiving area of the pixel can be relatively increased. Although the parasitic capacitance increases because the number of FDs increases to three, the position of the read signal line connected to the gate electrodes TG1, TG2, TG3, and TG4 is shifted from the position of the reset signal line connected to the reset transistor RT. And the degree of freedom of design increases.

  In the above-described embodiment, the present invention is applied to the solid-state imaging device having the pixel array and the color filter array in FIG. 2, but in FIG. 2, the odd-numbered row in the odd-numbered pixel array is left unchanged. 4 and 7 in the same manner as before, even in each readout unit pixel group (an example is indicated by a dotted line frame 7 ') constituted by the pixel array and color filter array of FIG. , 9 can be applied if the left and right are reversed.

  As described above, the following items are disclosed in this specification.

  The disclosed MOS type solid-state imaging device includes a first pixel group in which three primary color filters are arranged in a Bayer array, and a three-primary color filter that is shifted by 1/2 pixel pitch in both the horizontal and vertical directions with respect to the first pixel group. A MOS type solid-state imaging device having a second pixel group arranged, and a pixel belonging to the first pixel group and a pixel belonging to the second pixel group (hereinafter, referred to as this) having diagonally adjacent color filters having the same color filter Two pixels are referred to as a pair pixel.) And a total of four pixels, which are adjacent to the pair pixel in the vertical direction, are used as a readout unit, and each of the four pixels is configured by one common MOS transistor circuit. A signal readout circuit is provided.

  The disclosed MOS type solid-state imaging device includes a plurality of floating diffusions provided for the four pixels serving as the readout unit, and the floating diffusions are connected to each other by wiring and constitute the signal readout circuit Connected to the gate of the output transistor.

  The disclosed MOS type solid-state imaging device is a readout transistor provided for each of the four pixels serving as the readout unit, and one of the two paired pixels constituting the four pixels serving as the readout unit. A first floating diffusion provided corresponding to one pair pixel and a second floating pixel provided corresponding to the other of the two pair pixels constituting the four pixels serving as the readout unit. The first pair of pixels is connected to the first floating diffusion via the two read transistors corresponding to the first pair of pixels, and the second pair of pixels Is connected to the second floating diffusion through the two readout transistors corresponding to the second pair of pixels. It is what is.

  The disclosed MOS-type solid-state imaging device has the same position of the first floating diffusion with respect to the first pair of pixels and the position of the second floating diffusion with respect to the second pair of pixels. Including.

  In the disclosed MOS solid-state imaging device, the reset transistor that constitutes the signal readout circuit is configured such that the first floating diffusion and the second floating diffusion that are connected to the gate of the output transistor that constitutes the signal readout circuit. Among them, a floating diffusion different from the floating diffusion closest to the output transistor is formed as a source region.

  The disclosed MOS type solid-state imaging device includes a third floating diffusion provided corresponding to the four pixels as the readout unit, and a reset transistor of the signal readout circuit is formed using the third floating diffusion as a source region. In addition, the third floating diffusion is connected to the gate of the output transistor of the signal readout circuit.

  In the disclosed MOS type solid-state imaging device, the reset transistor and the output transistor constituting the signal readout circuit are provided at different grid positions in the grid-shaped element isolation region that separates the pixels. .

  In the disclosed MOS type solid-state imaging device, the readout transistor provided for each pixel is provided at a corner of the grid facing the intersection of the grid provided with a floating diffusion.

  The disclosed imaging apparatus includes the MOS solid-state imaging device described above and a control unit that performs pixel addition reading of the paired pixels.

  According to the embodiment described above, the captured image signal of 4 pixels can be individually read out by one signal readout circuit for every 4 pixels, or the captured image signal of the paired pixels can be read out by adding the pixels within the element. In addition, the number of transistors per pixel can be reduced to increase the light receiving area of the pixel (photodiode). For this reason, it is possible to perform high-sensitivity imaging even if the imaging element chip is downsized and the pixels are miniaturized.

7, 7 'readout unit pixel group 8, 9 wiring 10 digital camera 22a MOS type solid-state imaging device 23 drive unit 29 system control unit PD1, PD2 photodiode (same color pair pixel as half of readout unit pixel group)
PD3, PD4 Photodiode (same color pair pixel that is half of the readout unit pixel group)
FD1, FD2, FD3 Floating diffusion RG Reset transistor reset gate RD Reset transistor reset drain Dr Output transistor OS Output terminal OD Power supply terminal TG1, TG2, TG3, TG4 Read transistor tg1, tg2, tg3, tg4 Read signal line Rset Reset signal Line os Output signal line Vcc Power line

Claims (6)

A first pixel group in which three primary color filters are arranged in a Bayer array; and a second pixel group in which color filters of three primary colors are shifted by a ½ pixel pitch in both the horizontal and vertical directions with respect to the first pixel group. A MOS type solid-state imaging device,
From a pair of one first pixel belonging to the first pixel group and one second pixel belonging to the second pixel group having a color filter of the same color as the first pixel and obliquely adjacent to the first pixel A readout unit is formed by a total of four pixels, a first pair of pixels and a second pair of pixels adjacent to the pair of pixels in the vertical direction,
A signal readout circuit composed of one common MOS transistor circuit is provided for each of the four pixels,
Between each of the pixels, there is a lattice-shaped element isolation region that separates the pixels,
Each of the four pixels as the readout unit has a readout transistor,
The element isolation region that separates the two pixels forming the first pair pixel; the second pair pixel of the readout unit including the first pair pixel; and the first pair pixel; A first floating diffusion connected to the two pixels via the readout transistor provided in each of the two pixels, at the intersection position with the element isolation region that separates the two,
The read transistors of the two pixels are provided at corners facing the intersection position of the element isolation region where the first floating diffusion exists,
The element isolation region that separates the two pixels forming the second pair pixel, and the readout unit including the second pair pixel or the readout unit adjacent to the readout unit in the vertical direction The two pixels are connected via the readout transistor provided in each of the two pixels at the intersection of the element isolation region that separates the first pair pixel and the second pair pixel. Having a second floating diffusion
The read transistors of the two pixels are provided at corners facing an intersection position of the element isolation region where the second floating diffusion exists,
A MOS type solid-state imaging device, wherein a reset transistor and an output transistor constituting the signal readout circuit are provided at different lattice positions in the element isolation region. The MOS type solid-state imaging device according to claim 1,
The MOS type solid-state imaging device in which the first floating diffusion and the second floating diffusion are connected to each other by wiring and connected to the gate of the output transistor. The MOS type solid-state imaging device according to claim 1,
A MOS type solid-state imaging device, wherein a position of the first floating diffusion with respect to the first pair of pixels and a position of the second floating diffusion with respect to the second pair of pixels are the same. The MOS type solid-state imaging device according to claim 1,
The reset transistor is formed with a floating diffusion different from the floating diffusion closest to the output transistor among the first floating diffusion and the second floating diffusion connected to the gate of the output transistor as a source region. MOS type solid-state imaging device. The MOS type solid-state imaging device according to claim 1,
A third floating diffusion provided corresponding to the four pixels serving as the readout unit;
A MOS type solid-state imaging device in which the reset transistor is formed using the third floating diffusion as a source region, and the third floating diffusion is connected to a gate of the output transistor.   An imaging apparatus comprising: the MOS solid-state imaging device according to any one of claims 1 to 5; and a control unit that performs pixel addition reading of the paired pixels.

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