JP5784991B2 - Electronics - Google Patents

Description

  The present invention relates to an electronic device that performs bus transfer between circuit units.

  As a technique for improving the processing capability of an electronic device, there is a method of increasing the clock speed of the electronic device. As the clock speed increases, electromagnetic radiation (EMI) due to higher harmonics of the clock speed tends to deteriorate.

  In order to suppress electromagnetic radiation, electronic devices equipped with a spread spectrum clock generator (SSCG) have been proposed. The spread spectrum clock generation circuit performs frequency spread (also referred to as spread spectrum) by slightly changing the clock frequency. With this spread spectrum, not only the peak of the clock frequency (fundamental wave) but also the peak of the harmonic can be suppressed. As a result, the electromagnetic radiation of electronic equipment is greatly suppressed.

  Incidentally, a plurality of circuit units (also referred to as circuit blocks) are provided in the electronic device. This circuit unit includes, for example, a control circuit unit such as a CPU that performs control of electronic equipment, a timer circuit unit that performs timekeeping processing as a resource, and a communication circuit unit that performs communication processing. There is. An example of a communication circuit unit is a UART (Universal Asynchronous Receiver Transmitter).

  Since the timer circuit unit is required to measure time with high accuracy, it is necessary to operate based on a high-accuracy clock whose clock frequency does not fluctuate. Similarly, a communication circuit unit is required to operate based on a high-accuracy clock because high-accuracy timing adjustment is required. For this reason, these circuit units must operate based on a clock having a constant frequency (hereinafter referred to as a PLL clock) generated by a phase locked loop (PLL), not a spread spectrum clock whose frequency varies. There is. On the other hand, a circuit unit that does not require high-precision timing and high-precision timing adjustment, such as a control circuit unit, operates based on a spread spectrum clock.

  Assume that communication is performed between a first circuit unit that operates based on a spread spectrum clock and a second circuit unit that operates based on a PLL clock. In this case, the first circuit unit and the second circuit unit perform communication via an asynchronous communication asynchronous bridge unit (also referred to as an asynchronous bus bridge) provided between the two circuit units.

JP 2006-195948 A

  The asynchronous bridge unit bridges communication between the first circuit unit and the second circuit unit by performing so-called clock transfer processing. That is, the asynchronous bridge unit executes a process of latching data transmitted from the first circuit unit in synchronization with the spread spectrum clock and outputting the data to the second circuit unit in synchronization with the PLL clock. The asynchronous bridge unit latches data transmitted from the second circuit unit in synchronization with the PLL clock, and executes processing for outputting to the first circuit unit in synchronization with the spread spectrum clock.

  When such a clock change process is performed, the latency of data communication by the clock change process increases, and the amount of data communication per unit time in the first circuit unit and the second circuit unit decreases.

  Therefore, an object of the present invention is to reduce the latency of data communication by clock transfer processing when communication is performed between a first circuit unit that operates based on a spread spectrum clock and a second circuit unit that operates based on a PLL clock. To provide an electronic device that is reduced in size and prevents a decrease in data communication volume per unit time.

The first aspect of the electronic device includes a first clock generation circuit that generates a first clock having a first frequency that varies in frequency with respect to the second frequency, and
A second clock generation circuit for generating a second clock having the second frequency;
A first circuit unit that operates based on the first clock;
A second circuit unit that operates based on the second clock;
A bus connecting the first circuit unit and the second circuit unit;
A detection unit for detecting whether a frequency difference between the first frequency and the second frequency is within a first predetermined range;
A synchronization bus that performs synchronous communication between the first circuit unit and the second circuit unit when the frequency difference is within the first predetermined range; and the frequency difference is the first predetermined range. A bus bridge unit having an asynchronous bridge unit for executing asynchronous communication between the first circuit unit and the second circuit unit when the range is out of the range.

  According to the first aspect, even when communication is performed between the first circuit unit that operates based on the spread spectrum clock and the second circuit unit that operates based on the PLL clock, the data per unit time A decrease in communication volume can be prevented.

It is a block diagram of the electronic device of this Embodiment. It is a block diagram of a bus bridge part. It is a block diagram of an asynchronous bridge part. It is a figure which shows the time change of the frequency of a PLL clock, and the frequency of a spread spectrum clock. It is a block diagram of a PLL circuit. It is a block diagram of an SSCG circuit. It is a figure which shows the relationship between the oscillator control voltage input into a voltage controlled oscillator, and the frequency of the clock which a voltage controlled oscillator outputs according to an oscillator control voltage. It is a figure explaining operation | movement of a detection part. It is an example of the block diagram of a detection part. It is another example of the block diagram of a detection part. It is another figure explaining operation | movement of a detection part. FIG. 5 is a first flowchart illustrating bus control of a bus control unit. FIG. 6 is a second flowchart illustrating bus control of the bus control unit. It is a timing chart explaining the bus control of a bus control part. FIG. 2 is a block diagram of a reference voltage supply unit described in FIG. It is a block diagram of a voltage generation part. It is a figure which shows an example of the table for voltage selection.

  FIG. 1 is a block diagram of the electronic device of this embodiment. The control circuit unit (first circuit unit) 1 of the electronic device E has a CPU, a bus interface for the bus B1, and the like. Note that the control circuit unit 1 may include a memory and the like, and the CPU and the memory may be connected via a bus in the unit. The control circuit unit 1 operates based on a first clock having a first frequency that varies with respect to the second frequency. The first clock is, for example, a spread spectrum clock SSCGCLK.

  The peripheral circuit unit (second circuit unit) 2 is a timer circuit unit or a communication circuit unit, and has a bus interface for the bus B2. The peripheral circuit unit 2 operates based on the second clock having the second frequency. The second clock is, for example, a PLL clock PLLCLK. In this case, the second frequency is a constant frequency.

  The bus B1 is a bus that connects the control circuit unit 1 to the bus control unit 4 and the reference voltage supply unit 6. The bus B2 is a bus that connects the peripheral circuit unit 2 and the bus bridge unit 3. The bus B3 is a bus that connects the bus bridge unit 3 and the bus control unit 4. That is, the buses B1, B2, and B3 are buses that connect the control circuit unit 1 and the peripheral circuit unit 2.

  The bus bridge unit 3 bridges bus communication between the control circuit unit 1 and the peripheral circuit unit 2.

  FIG. 2 is a block diagram of the bus bridge unit 3. Buses B21 and B22 correspond to bus B2, and buses B31 and B32 correspond to bus B3.

  The buses B31 and B22 are synchronous buses that execute synchronous communication between the control circuit unit 1 and the peripheral circuit unit 2. The bus B31 is connected to the input terminal of the asynchronous bridge unit 31 and the input terminal of the selector 32. The bus B22 is connected to the input terminal of the asynchronous bridge unit 33 and the input terminal of the selector 34.

  The asynchronous bridge units 31 and 33 are bus bridges that execute asynchronous communication between the control circuit unit 1 and the peripheral circuit unit 2. The output of the asynchronous bridge unit 31 is input to the selector 32 via the bus BN1. The output of the asynchronous bridge unit 33 is input to the selector 34 via the bus BN2.

  The bus B31, the asynchronous bridge unit 31, the bus BN1, the selector 32, and the bus B21 execute bus communication from the control circuit unit 1 to the peripheral circuit unit 2. On the other hand, the bus B22, the asynchronous bridge unit 33, the bus BN2, the selector 34, and the bus B32 execute bus communication from the peripheral circuit unit 2 to the control circuit unit 1.

  The selector 32 selects either the input from the synchronous bus B31 or the input from the bus BN1 connected to the output terminal of the asynchronous bridge unit 31 based on the bus switching signal BCHG input from the bus control unit 4, and the bus B21 Output to. That is, the selector 32 outputs the input from the synchronous bus B31 to the bus B21 in response to the bus switching signal BCHG instructing to switch to synchronous communication. In addition, the selector 32 outputs the input from the asynchronous bridge unit 31 to the bus B21 in response to the bus switching signal BCHG instructing to switch to asynchronous communication.

  The selector 34 selects either the input from the synchronous bus B22 or the input from the bus BN2 connected to the output terminal of the asynchronous bridge unit 33 based on the bus switching signal BCHG, and outputs it to the bus B32. That is, the selector 34 outputs the input from the synchronous bus B22 to the bus B32 in response to the bus switching signal BCHG instructing to switch to synchronous communication. Further, the selector 34 outputs the input from the asynchronous bridge unit 33 to the bus B32 in response to the bus switching signal BCHG instructing to switch to asynchronous communication.

  In other words, the bus bridge unit 3 performs synchronization communication between the control circuit unit 1 and the peripheral circuit unit 2 in a synchronization period in which the control circuit unit 1 and the peripheral circuit unit 2 operate in synchronization. Asynchronous bridge unit 31 that performs asynchronous communication between control circuit unit 1 and peripheral circuit unit 2 in the asynchronous period in which buses B31 and B22, control circuit unit 1 and peripheral circuit unit 2 operate asynchronously , 33. This synchronization period is a period in which the frequency difference between the frequency of the spread spectrum clock SSCGCLK and the frequency of the PLL clock PLLCLK is within a predetermined range with reference to the frequency of the PLL clock PLLCLK. This asynchronous period is a period in which the frequency difference between the frequency of the spread spectrum clock SSCGCLK and the frequency of the PLL clock PLLCLK is outside a predetermined range with reference to the frequency of the PLL clock PLLCLK.

  FIG. 3 is a block diagram of the asynchronous bridge unit 31. The asynchronous bridge unit shown in FIG. 3 is an example, and various other asynchronous bridge units have been proposed. The input unit 311 operates based on the spread spectrum clock SSCGCLK, and inputs control commands and data (hereinafter referred to as communication data) input from the bus B31 to the output unit 312 via the bus B311. The output unit 312 operates based on the PLL clock PLLCLK, and outputs communication data input from the bus B311 to the bus BN1.

  When the bus switching signal BCHG instructing to switch to asynchronous communication is input from the bus control unit 4, the asynchronous bridge unit 31 is activated in response to the bus switching signal BCHG. The input unit 311 latches a predetermined amount of communication data input from the bus B31 in synchronization with the rising edge of the spread spectrum clock SSCGCLK. In addition, the output unit 312 outputs a signal CS1 indicating that the communication data latched in the input unit 311 is instructed to be input to the output unit 312.

  In response to this signal CS1, the input unit 311 inputs the latched communication data to the output unit 312 in synchronization with the rising edge of the spread spectrum clock SSCGCLK. The output unit 312 takes the communication data input from the input unit 311 in synchronization with the rising edge of the PLL clock PLLCLK, and outputs it to the bus BN1. At the same time, a signal CS1 indicating that the communication data has been successfully fetched is output to the input unit 311. In response to the signal CS1, the input unit 311 fetches and latches the next communication data from the bus B31. In this way, the asynchronous bridge unit 31 executes asynchronous communication. The asynchronous bridge unit 33 has the same configuration.

  Returning to the description of FIG. The bus control unit 4 executes various controls for the bus B1, the bus B3, the control circuit unit 1, and the bus bridge unit 3. For example, the bus control unit 4 is a ready signal RDY that instructs the control circuit unit 1 to temporarily stop outputting communication data to the bus B1, or a bus that instructs the bus bridge unit 3 to switch between synchronous communication and asynchronous communication. Outputs switching signal BCHG.

  The detection unit 5 includes, for example, an SSCG circuit that generates the spread spectrum clock SSCGCLK and a PLL circuit that generates the PLL clock PLLCLK, and the frequency difference between the frequency of the spread spectrum clock SSCGCLK and the frequency of the PLL clock PLLCLK is first. It is detected whether it is in the predetermined range. Note that the SSCG circuit and the PLL circuit may not be provided inside the detection unit 5, but may be provided outside the detection unit 5.

  The reference voltage supply unit 6 supplies the detection unit 5 with the first reference voltage Vr1 and the second reference voltage Vr2. The first reference voltage Vr1 and the second reference voltage Vr2 will be described later.

  The signal line BC1 is a signal line for the control circuit unit 1, the bus control unit 4, and the reference voltage supply unit 6 to transmit and receive the control signal of the bus B1. The signal line BC2 is a signal line for the peripheral circuit unit 2 and the bus bridge unit 3 to transmit and receive the control signal of the bus B2. The signal line BC3 is a signal line for the bus bridge unit 3 and the bus control unit 4 to transmit and receive the control signal of the bus B3. Instead of these signal lines BC1 to BC3, buses B1 to B3 may be used. Further, the control circuit unit 1 and the detection unit 5 may be connected via a bus or a signal line.

  FIG. 4 is a diagram showing temporal changes in the frequency of the PLL clock PLLCLK and the frequency of the spread spectrum clock SSCGCLK. The vertical axis represents frequency and the horizontal axis represents time. The symbol PF indicates the frequency of the PLL clock PLLCLK and is constant. Symbol SSF indicates the frequency of the spread spectrum clock SSCGCLK. The frequency SSF of the spread spectrum clock SSCGCLK varies around the frequency PF of the PLL clock PLLCLK, and its shape is a triangular wave shape. That is, the frequency SSF of the spread spectrum clock SSCGCLK is obtained by subjecting the frequency PF of the PLL clock PLLCLK to triangular modulation based on a predetermined modulation frequency. This modulation frequency is, for example, 4 KHz by default.

  At the time indicated by the symbol P0, the frequency SSF and the frequency PF coincide with each other, and the rising timing of the spread spectrum clock SSCGCLK coincides with the rising timing of the PLL clock PLLCLK. The period indicated by the symbol P1 is the reciprocal of the modulation frequency of the spread spectrum clock SSCGCLK and indicates the modulation period. This modulation period is, for example, 250 μsec.

  The detection unit 5 in FIG. 1 detects whether or not the frequency difference DF between the frequency SSF and the frequency PF is within a predetermined range RF. That is, the detection unit 5 detects whether or not the frequency difference DF between the frequency SSF and the frequency PF is within a predetermined range RF with respect to the frequency PF. The minimum value of the predetermined range RF is indicated by a symbol RF1, and the maximum value of the predetermined range RF is indicated by a symbol RF2. The predetermined range RF is a first predetermined range.

  During the period in which the frequency difference DF between the frequency SSF and the frequency PF is within the predetermined range RF, the control circuit unit 1 that operates based on the spread spectrum clock SSCGCLK having the frequency SSF and the peripheral that operates based on the PLL clock PLLCLK having the frequency PF This is regarded as a synchronization period in which the circuit unit 2 operates synchronously. This synchronization period is a period indicated by time T0 to T1 and time T2 to T3.

  The detection unit 5 outputs a signal CD indicating that to the bus control unit 4 during the synchronization period. In response to this signal CD, the bus control unit 4 outputs to the bus bridge unit 3 a bus switching signal BCHG instructing switching to synchronous communication. In response to the bus switching signal BCHG, the bus bridge unit 3 executes synchronous communication as described with reference to FIG.

  On the other hand, the period in which the frequency difference DF between the frequency SSF and the frequency PF is outside the predetermined range RF is regarded as an asynchronous period in which the control circuit unit 1 and the peripheral circuit unit 2 operate asynchronously. This asynchronous period is a period indicated by times T1 to T2 and times T3 to T4.

  The detection unit 5 outputs a signal CD indicating that to the bus control unit 4 during the asynchronous period. In response to this signal CD, the bus control unit 4 outputs to the bus bridge unit 3 a bus switching signal BCHG instructing switching to asynchronous communication. In response to the bus switching signal BCHG, the bus bridge unit 3 executes asynchronous communication as described with reference to FIG.

  According to the present embodiment, the bus bridge unit 3 performs asynchronous communication between the control circuit unit 1 and the peripheral circuit unit 2 during the asynchronous period, and the control circuit unit 1 and the peripheral circuit unit 2 during the synchronous period. Synchronous communication can be executed with

  Assume that communication between the control circuit unit 1 and the peripheral circuit unit 2 is performed by asynchronous communication in the modulation cycle indicated by the symbol P1 in FIG. Here, it is assumed that one command is one clock. In this case, assuming that the frequency of the PLL clock PLCCK is 80 MHz and the modulation frequency is 4 KHz, the number of spread spectrum clock SSCGCLK is about 20,000. When asynchronous communication is performed, the waiting time (number of wait clocks) required for one access to the bus is about 10 clocks. Therefore, in the modulation period P1, the control circuit unit 1 can access the bus B1 about 2000 times.

  On the other hand, in the modulation period P1, the electronic device E according to the present embodiment performs communication between the control circuit unit 1 and the peripheral circuit unit 2, synchronous communication is performed for 1/3 of the modulation period P1, and 2/3 of the modulation period P1. Assume the case of asynchronous communication. In this case, in the above-described example, the control circuit unit 1 receives the 6666 access (20000/3) in the synchronous period for performing synchronous communication and the 1333 access (20000-6666) / 10)) in the asynchronous period for performing asynchronous communication. Is possible. That is, the control circuit unit 1 can access the bus B1 a total of 7,999 times during the modulation period P1. The time for switching between asynchronous communication and synchronous communication is not included.

  Thus, according to the electronic device E of the present embodiment, the control circuit unit 1 and the peripheral circuit unit 2 are about four times per unit time (7999) as compared with the case where the bus communication is performed only by asynchronous communication. / 2000) data communication. As a result, the electronic device E according to the present embodiment can reduce the latency of data communication due to the clock transfer process, and can prevent a decrease in the amount of data communication per unit time.

  Next, an example of a method in which the detection unit 5 detects whether the frequency difference DF between the frequency SSF of the spread spectrum clock SSCGCLK and the frequency PF of the PLL clock PLLCLK is within a predetermined range RF will be described.

  FIG. 5 is a block diagram of the PLL circuit (second clock generation circuit). The PLL circuit 7 controls the phase of the PLL clock PLLCLK so that the phase difference between the reference clock RCLK and the clock NPPCLK (also referred to as a feedback clock) obtained by dividing the PLL clock PLLCLK by N × P is small. Under this control, the PLL circuit 7 outputs a PLL clock PLLCLK obtained by multiplying the frequency of the reference clock RCLK with the same phase as the reference clock RCLK. That is, the PLL circuit 7 outputs the PLL clock PLLCLK locked to a constant frequency.

  The phase comparator (PFD: Phase Frequency Detector) 71 of the PLL circuit 7 compares the phase difference between the reference clock RCLK and the output clock NPPCLK of the 1 / N frequency divider 76, and generates a phase difference signal PHS corresponding to the phase difference. It is generated and output to the charge pump 72.

  The charge pump 72 supplies charges to a capacitor (not shown) of the LPF 73 according to the phase difference signal PHS, or extracts charges from the capacitor of the LPF 73 according to the phase difference signal PHS.

  An LPF (Low Pass Filter) 73 has a capacitor, and outputs a voltage generated by the electric charge accumulated in the capacitor to the voltage controlled oscillator 74 as an oscillator control voltage Vp (second oscillator control voltage). Also, the LPF 73 outputs the oscillator control voltage Vp to the voltage difference detection unit 51 shown in FIG.

  A voltage controlled oscillator (VCO) 74 generates a PLL clock PLLCLK according to the oscillator control voltage Vp. For example, the voltage controlled oscillator 74 generates a PLL clock PLLCLK whose frequency increases in proportion to an increase in the oscillator control voltage Vp.

  The 1 / P divider 75 generates a clock PPCLK obtained by dividing the PLL clock PLLCLK by 1 / P and outputs the clock PPCLK to the 1 / N divider 76.

  The 1 / N divider 76 generates NPPCLK obtained by dividing the clock PPCLK by 1 / N and outputs the generated NPPCLK to the phase comparator 71.

  That is, the PLL circuit 7 is a second phase locked loop circuit having a voltage controlled oscillator 74 that generates a second clock (PLL clock) according to the oscillator control voltage Vp.

  FIG. 6 is a block diagram of the SSCG circuit (first clock generation circuit).

  The phase comparator 81, charge pump 82, LPF 83, voltage controlled oscillator 84, 1 / P frequency divider 85 of the SSCG circuit 8 are the same as the phase comparator 71, charge pump 72, LPF 73, voltage controlled oscillator 74, 1 / P in FIG. It has the same function as the P divider 75. The LPF 83 outputs the oscillator control voltage Vs (first oscillator control voltage) to the voltage controlled oscillator 84. Further, the LPF 83 outputs the oscillator control voltage Vs to the voltage difference detection unit 51 shown in FIG. 9 or the bias voltage generation unit 55 shown in FIG.

  The voltage controlled oscillator 84 generates a spread spectrum clock SSCGCLK according to the oscillator control voltage Vs. The 1 / P divider 85 generates a clock PPCLK obtained by dividing the spread spectrum clock SSCGCLK by 1 / P and outputs the clock PPCLK to the N divider / modulator 86.

  The N-divider_modulator 86 modulates (changes) the frequency of the spread spectrum clock SSCGCLK by, for example, slightly changing this division ratio when generating the clock NPPCLK obtained by dividing the clock PPCLK by 1 / N. . For example, the oscillator control voltage Vs may be slightly changed in order to modulate the frequency of the spread spectrum clock SSCGCLK. Further, when the voltage controlled oscillator 84 generates the spread spectrum clock SSCGCLK, the frequency of the spread spectrum clock SSCGCLK may be modulated.

  That is, the SSCG circuit 8 has a voltage controlled oscillator 84 that generates the first clock (spread spectrum clock) according to the oscillator control voltage Vs, and the frequency of the spread spectrum clock varies with reference to the frequency of the PLL clock PCLK. 1 is a first phase locked loop circuit having a modulator 86 for performing modulation. At this time, the modulator preferably varies the frequency of the spread spectrum clock SSCGCLK around the frequency of the PLL clock PCLK.

  FIG. 7 is a diagram showing the relationship between the oscillator control voltage input to the voltage controlled oscillator and the frequency of the clock output from the voltage controlled oscillator according to the oscillator control voltage. The vertical axis represents the clock frequency, and the horizontal axis represents the oscillator control voltage VCO. As shown in FIG. 7, the oscillator control voltage is proportional to the frequency of the clock output from the voltage controlled oscillator.

  According to FIG. 7, when the frequency of the PLL clock PLLCLK of the PLL circuit 7 is locked at 320 MHz, for example, the oscillator control voltage Vp input to the voltage controlled oscillator 74 of the PLL circuit 7 is 7 mV. Further, it is assumed that the frequency of the spread spectrum clock SSCGCLK of the SSCG circuit 8 varies in the range of 304 MHz to 336 MHz with reference to the frequency 320 MHz of the PLL clock PLLCLK. The oscillator control voltage Vs input to the voltage controlled oscillator 84 of the SSCG circuit 8 corresponding to this range is a voltage in the range indicated by the symbol P2. Further, the range of the oscillator control voltage corresponding to the predetermined range RF shown in FIG. 4 is a voltage in the range indicated by the symbol RV.

  That is, if the oscillator control voltage is uniquely determined, the clock frequency is also uniquely determined. Therefore, the detection unit 5 detects, for example, whether or not the voltage difference between the oscillator control voltage Vs and the oscillator control voltage Vp is within a predetermined range, thereby detecting the frequency SSF of the spread spectrum clock SSCGCLK and the frequency PF of the PLL clock PLLCLK. It is possible to detect whether or not the frequency difference DF is within a predetermined range RF.

  FIG. 8 is a diagram for explaining the operation of the detection unit 5. FIG. 8 (A) is a diagram showing the time change of the oscillator control voltage Vp and the oscillator control voltage Vs, with the vertical axis indicating voltage and the horizontal axis indicating time. Symbol RV indicates a voltage in the second predetermined range RV corresponding to the predetermined range RF described in FIG. The minimum value of the predetermined range RV is (oscillator control voltage Vp−reference voltage Vr1), and the maximum value of the predetermined range RV is (oscillator control voltage Vp + reference voltage Vr2). Symbols Vd and Vd ′ indicate a voltage difference between the oscillator control voltage Vs and the oscillator control voltage Vp. Note that, at the time indicated by the symbol P3, the oscillator control voltage Vp and the oscillator control voltage Vs match, that is, the frequency SSF of the spread spectrum clock SSCGCLK and the frequency PF of the PLL clock PLLCLK match as described with reference to FIG.

  FIG. 8 (B) is a diagram showing a signal CD output from the detection unit 5.

  FIG. 9 is an example of a block diagram of the detection unit 5.

  The voltage difference detector 51 detects the voltage difference between the oscillator control voltage Vp input from the LPF 73 of the PLL circuit 7 shown in FIG. 5 and the oscillator control voltage Vs input from the LPF 83 of the SSCG circuit 8 shown in FIG. To do. Here, the oscillator control voltage Vs−the oscillator control voltage Vp is detected as a voltage difference Vd, and the oscillator control voltage Vp−the oscillator control voltage Vs is detected as a voltage difference Vd ′. The voltage difference detection unit 51 inputs the voltage difference Vd to the non-inverting input terminal (+ terminal) of the comparator 52 and inputs the voltage difference Vd ′ to the non-inverting input terminal of the comparator 53.

  The comparator 52 compares the voltage difference Vd input to the non-inverting input terminal with the reference voltage Vr2 input to the inverting input terminal (− terminal), and inputs the comparison result signal CMP1 to the OR circuit 54. The comparator 53 compares the reference voltage Vr1 input to the inverting input terminal with the voltage difference Vd ′ input to the non-inverting input terminal, and inputs the comparison result signal CMP2 to the OR circuit 54.

  The OR circuit 54 calculates the logical sum of the comparison result signal CMP1 and the comparison result signal CMP2 and outputs the signal CD to the bus control unit 4.

  If the oscillator control voltage Vs is within the predetermined range RV with respect to the oscillator control voltage Vp, that is, if the voltage difference Vd and the voltage difference Vd ′ are within the predetermined range RV, the detection unit 5 outputs the low level signal CD. Output to the bus control unit 4. The period during which the detection unit 5 outputs the low level signal CD is a period indicated by time T0 to T1 and time T2 to T3, and this period is a synchronization period. On the other hand, if the oscillator control voltage Vs is outside the predetermined range RV, that is, if the voltage difference Vd and the voltage difference Vd ′ are outside the predetermined range RV, the detection unit 5 sends the high level signal CD to the bus control unit 4. Output. The period during which the detection unit 5 outputs the high-level signal CD is a period indicated by time T1 to T2 and time T3 to T4, and this period is an asynchronous period.

  The offset voltage of the comparators 52 and 53 is about 1 mv. For example, when the spectrum spread clock SSCGCLK is generated by modulating the frequency of the PLL clock PLLCLK within a range of ± 5%, the fluctuation range of the oscillator control voltage Vs is about 10 mV.

  Therefore, the comparators 52 and 53 can output the comparison result signals CMP1 and CMP2, respectively.

  FIG. 10 is another example of a block diagram of the detection unit 5.

  The bias voltage generation unit 55 includes a capacitor C that cuts the DC component of the oscillator control voltage Vs input from the LPF 83 of the SSCG circuit 8 shown in FIG. 6, and a bias voltage that is applied to the oscillator control voltage Vs from which the DC component has been cut. And a bias voltage generation circuit 55a for generating Vb. This bias voltage Vb is a voltage corresponding to the oscillator control voltage Vp in FIG.

  The bias voltage generation unit 55 inputs the oscillator control voltage Vs ′ to which the bias voltage Vb is applied to the non-inverting input terminal of the comparator 52 and the inverting input terminal of the comparator 53 as described with reference to FIG. .

  FIG. 11 is another diagram for explaining the operation of the detection unit 5. FIG. 11 (A) is a diagram showing the time change of the oscillator control voltage Vs ′, the vertical axis shows the voltage, and the horizontal axis shows the time. Symbol Vb indicates a bias voltage. FIG. 11 (B) is a diagram showing a signal CD output by the detection unit 5.

  If the oscillator control voltage Vs ′ is within a predetermined range RV with respect to the bias voltage Vb (Vr1 ≦ oscillator control voltage Vs ′ ≦ Vr2), that is, the voltage between the oscillator control voltage Vs ′ and the bias voltage Vb is detected. If the difference is within the predetermined range RV, a low level signal CD is output to the bus control unit 4. The period during which the detection unit 5 outputs the low-level signal CD is a period indicated by times T0 to T1 and times T2 to T3.

  On the other hand, if the oscillator control voltage Vs ′ is outside the predetermined range RV with reference to the bias voltage Vb (the oscillator control voltage Vs ′> Vr2, or the oscillator control voltage Vs ′ <Vr1), that is, the oscillator control If the voltage difference between the voltage Vs ′ and the bias voltage Vb is outside the predetermined range RV, a high level signal CD is output to the bus control unit 4. The period during which the detection unit 5 outputs the high-level signal CD is a period indicated by time T1 to T2 and time T3 to T4.

  The bus control unit 4 outputs a bus switching signal BCHG to the bus bridge unit 3 instructing the bus bridge unit 3 to switch between synchronous communication and asynchronous communication according to the level change of the signal CD input from the detection unit 5. To do. That is, when the signal CD falls, the bus control unit 4 outputs a bus switching signal BCHG instructing to switch to synchronous communication to the bus bridge unit 3 in response to the falling of this signal. When the signal CD rises, the bus control unit 4 responds to the rise of this signal and outputs a bus switching signal BCHG to the bus bridge unit 3 instructing switching to asynchronous communication.

  The bus control of the bus control unit 4 will be described with reference to FIGS. In the following description, a case where the signal CD rises, that is, a case where the bus bridge unit 3 switches from synchronous communication to asynchronous communication will be described. When the signal CD falls, the bus bridge unit 3 switches from asynchronous communication to synchronous communication as described in FIG.

  FIG. 12 is a first flowchart for explaining the bus control of the bus control unit 4, and FIG. 13 is a second flowchart for explaining the bus control of the bus control unit 4.

  FIG. 14 is a timing chart for explaining the bus control of the bus control unit 4. FIG. 14A to FIG. 14C show the waveform of the spread spectrum clock SSCGCLK, the bus access data, the switching instruction signal CD, the waveform of the ready signal RDY, and the bus switching timing, respectively, from the top.

  Step S1 in FIG. 12: When the signal CD input from the detection unit 5 rises, the bus control unit 4 determines whether the control circuit unit 1 accesses the bus B1 and executes data transmission. That is, the bus control unit 4 determines whether or not there is bus access to the bus B1.

  When the bus control unit 4 determines that there is no bus access (step S1 / NO), the process proceeds to step S2.

  Step S2: The bus control unit 4 outputs a bus switching signal BCHG instructing the bus bridge unit 3 to switch to asynchronous communication, and starts switching of the bus. In response to the bus switching signal BCHG, the bus bridge unit 3 operates the asynchronous bridge units 31 and 33 to execute asynchronous communication.

  When the bus control unit 4 determines that there is bus access (step S1 / NO), the process proceeds to step S3.

  Step S3: The bus control unit 4 determines whether the bus bridge unit 3 is executing a switching process between asynchronous communication and synchronous communication, that is, whether the bus is being switched.

  When the bus control unit 4 determines that the bus bridge unit 3 is not switching the bus (step S3 / NO), the process proceeds to step S4.

  Step S4: The bus control unit 4 determines whether or not the control circuit unit 1 continuously accesses the bus B1 and executes data communication. That is, the bus control unit 4 determines whether or not there is continuous bus access to the bus B1.

  As shown in FIG. 14A, when the control circuit unit 1 accesses the bus B1 and outputs the write data DATA1 corresponding to the write command CMD1 after the single write command CMD1, the bus control unit 4 determines that there is no continuous bus access to bus B1. On the other hand, as shown in FIG. 14C, the control circuit unit 1 accesses the bus B1, and writes the write command CMD1, the write data DATA1 corresponding to the write command CMD1, the write command CMD2, and the write corresponding to the write command CMD2. When outputting the data DATA2, the bus control unit 4 determines that there is continuous bus access to the bus B1.

  When the bus control unit 4 determines that there is no continuous bus access to the bus B1 (step S4 / NO), the bus control unit 4 determines whether the bus access by the control circuit unit 1 is completed. (Step S5). The bus control unit 4 enters a waiting state until this bus access is completed (step S5 / NO). When this bus access is completed (step S5 / YES), the process proceeds to step S2. In this case, in step S2, at time TA21 shown in FIG. 14A, the bus switching signal BCHG instructing the bus bridge unit 3 to switch to asynchronous communication is output.

  When the bus bridge unit 3 is switching the bus (step S3 / YES), the process proceeds to step S6 in FIG. The case of YES in step S3 will be described with reference to FIG. 14 (B). In the case of YES in step S3, for example, the signal CD rises at time TB21, and the bus control unit 4 outputs the bus switching signal BCHG instructing the bus bridge unit 3 to switch to asynchronous communication at time TB22. However, this is a case where the control circuit unit 1 outputs the control command CD1 and the data DATA1 before the bus bridge unit 3 completes the process of switching to asynchronous communication. In this case, the bus control unit 4 instructs the control circuit unit 1 to suspend the bus access as described below.

  Step S6: The bus control unit 4 latches the access signal from the control circuit unit 1. In FIG. 14B, the write command CMD1, which is an access signal, is latched.

  Step S7: The bus control unit 4 causes the ready signal RDY to fall. In response to the fall of the ready signal RDY, the control circuit unit 1 shifts to a wait state, and temporarily stops the output of the write data DATA1 corresponding to the write command CMD1 (bus access suspension).

  The bus control unit 4 determines whether or not the bus switching by the bus bridge unit 3 has been completed (step S8). The bus control unit 4 enters a wait state until the bus switching is completed (step S8 / NO), and when the bus switching is completed (step S8 / YES), the process proceeds to step S9.

  Step S9: The bus control unit 4 raises the ready signal RDY and accepts an access signal. In response to the rise of the ready signal RDY, the control circuit unit 1 returns from the wait state and resumes outputting the write data DATA1 corresponding to the write command CMD1.

  In step S4 in FIG. 12, when the bus control unit 4 determines that there is continuous bus access to the bus B1 (step S4 / YES), the process proceeds to step S10 in FIG.

  Step S10: The bus control unit 4 latches the access signal from the control circuit unit 1 as in step S6. In FIG. 14C, the write command CMD2, which is an access signal, is latched.

  Step S11: The bus control unit 4 causes the ready signal RDY to fall at time TC21 as in step S7. In response to the fall of the ready signal RDY, the control circuit unit 1 shifts to a wait state and temporarily stops the output of the write data DATA2 corresponding to the write command CMD2 (bus access suspension).

  Step S12: Similarly to step S2, the bus control unit 4 outputs a bus switching signal BCHG instructing the bus bridge unit 3 to switch to asynchronous communication, and starts switching of the bus. In the example of FIG. 14 (C), the bus control unit 4 outputs the bus switching signal BCHG at the same timing as the time TC21 when the ready signal RDY falls.

  The bus control unit 4 determines whether or not the bus switching by the bus bridge unit 3 has been completed (step S13). The bus control unit 4 enters a waiting state until the bus switching is completed (step S13 / NO), and when the bus switching is completed (step S13 / YES), the process proceeds to step S14.

  Step S14: The bus control unit 4 raises the ready signal RDY and accepts an access signal. In response to the rise of the ready signal RDY, the control circuit unit 1 returns from the wait state and resumes outputting the write data DATA1 corresponding to the write command CMD2.

  As described above, the bus control unit 4 monitors the access status of the bus and appropriately controls switching of synchronous communication and asynchronous communication with respect to the bus bridge unit 3.

  FIG. 15 is a block diagram of the reference voltage supply unit 6 described in FIG. The reference voltage supply unit 6 supplies the detection unit 5 with the first reference voltage Vr1 indicating the minimum value of the predetermined range RV and the second reference voltage Vr2 indicating the maximum value of the predetermined range RV. The reference voltage supply unit 6 can supply different values of the reference voltage to the detection unit 5. As a result, the synchronous period and the asynchronous period can be adjusted to an optimal period in bus communication.

  An ASW (Analog Switch) 61 outputs external input voltages Vex1, Vex2, or a high impedance signal Hz input from the outside. The reference voltage supply unit 6 executes a first mode in which the external input voltages Vex1 and Vex2 are supplied to the detection unit 5.

  The voltage generator A621 outputs the voltage V1 or the high impedance signal Hz. Similarly, the voltage generators B622 to N62n output voltages V2 to Vn, respectively. Alternatively, the voltage generators B622 to N62n output a high impedance signal Hz instead of the voltage output.

  FIG. 16 is a block diagram of the voltage generator A621. The voltage dividing resistors Ra1 and Ra2 of the voltage generation unit A621 are provided between the power supply voltage VDD and the ground GND, and output the divided voltage V1 to the ASW621a. The ASW 621a outputs the divided voltage V1 in response to the signal DS1 output from the decoder 636. The ASW 621a outputs a high impedance signal Hz when there is no input of the signal DS1. Similarly to the voltage generation unit A621, the voltage generation units B622 to N62n other than the voltage generation unit A621 also have voltage dividing resistors and ASWs, and output voltages V2 to Vn, respectively.

  Returning to the description of FIG. The selection unit 63 selects one of the voltages V1 to Vn and supplies it to the detection unit 5.

  The voltage selection register 631 is a register in which a first voltage selection signal S1x (x is 1 to n) for selecting a voltage to be supplied to the detection unit 5 from a plurality of voltages V1 to Vn is set. The voltage selection signal S1x can be set by the user from the outside, for example, the control circuit unit 1. The reference voltage supply unit 6 executes a second mode in which any one of the plurality of voltages V1 to Vn is supplied to the detection unit 5 based on the voltage selection signal S1x.

  The PLL frequency setting register 632 is a register in which the frequency of the PLL clock PLLCLK is set. The modulation value setting register 633 is a register in which the modulation value of the N division / modulator 86 is set. The modulation value of the modulation value setting register 633 and the frequency of the PLL clock PLLCLK of the PLL frequency setting register 632 can be set from the outside, for example, the control circuit unit 1.

  The voltage calculation unit 634 has a voltage selection table in which the second voltage selection signal S2x is recorded corresponding to the modulation value of the modulation value setting register 633 and the frequency of the PLL clock PLLCLK of the PLL frequency setting register 632.

  FIG. 17 is a diagram illustrating an example of a voltage selection table. In the voltage selection table shown in FIG. 17, the frequencies of a plurality of PLL clocks PLLCLK that can be generated by the PLL circuit 7 corresponding to the modulation value of the frequency set in the N division / modulator 86 are recorded. Furthermore, voltage selection signals S21 to S2n (S2x) corresponding to the first reference voltage Vr1 and the second reference voltage Vr2 are recorded in the voltage selection table for each frequency of the plurality of PLL clocks PLLCLK.

  The reference voltage supply unit 6 executes a third mode in which any one of the plurality of voltages V1 to Vn is supplied to the detection unit 5 based on the voltage selection signal S2x.

  The selector 635 selects either the voltage selection signal S1x of the voltage selection register 631 or the voltage selection signal S2x of the voltage calculation unit 634 and outputs the selected signal to the decoder 636.

  The decoder 636 decodes the selection signal input from the selector 635, and outputs a signal DSx that instructs the voltage generation unit that generates the reference voltage corresponding to the voltage selection signal to output the reference voltage.

  The mode setting register 64 is a register in which a mode selection signal for selecting execution of the first to third modes is set. The reference voltage supply unit 6 executes any one of the first to third modes based on the mode selection signal. The mode selection signal can be set by the user from the outside, for example, the control circuit unit 1.

  A case where the control circuit unit 1 causes the reference voltage supply unit 6 to execute the first mode will be described. The control circuit unit 1 sets the mode selection signal M1 in the mode setting register 64. The mode setting register 64 outputs the mode selection signal M1 to the ASW 61 and the selector 635 when the mode selection signal M1 is set. When the mode selection signal M1 is input, the ASW 61 outputs the first external input voltage Vex1 input from the outside to the detection unit 5 as the reference voltage Vr1.

  Next, the second external input voltage Vex2 higher than the first external input voltage Vex1 is output to the detection unit 5 as the reference voltage Vr2. The selector 635 does not execute the selection process when the mode selection signal M1 is input. By this voltage output, external input voltages Vex1 and Vex2, that is, reference voltages Vr1 and Vr2 are supplied to the detection unit 5.

  The line L indicated by a bold line has two lines, a supply line for the reference voltage Vr1 and a supply line for the reference voltage Vr2. In the above example, the external input voltage Vex1 is a supply line for the reference voltage Vr1. The external input voltage Vex2 is supplied to the detection unit 5 via a supply line for the reference voltage Vr2.

  A case where the control circuit unit 1 causes the reference voltage supply unit 6 to execute the second mode will be described. Here, the case where the voltages V1 and V2 are supplied to the detection unit 5 as the reference voltages Vr1 and Vr2 is illustrated. For example, the control circuit unit 1 sets the mode selection signal M2 in the mode setting register 64, and further sets the voltage selection signal S1x (x is 1, 2) in the voltage selection register 631.

  The mode setting register 64 outputs the mode selection signal M2 to the ASW 61 and the selector 635 when the mode selection signal M2 is set. When the mode selection signal M2 is input, the ASW 61 outputs a high impedance signal Hz. The voltage selection register 631 outputs a voltage selection signal S1x to the selector 635. When the mode selection signal M2 is input, the selector 635 outputs the voltage selection signal S1x output from the voltage selection register 631 to the decoder 636.

  The decoder 636 outputs a signal DS1 that instructs the voltage generator A621 that generates the voltage V1 corresponding to the voltage selection signal S11 to output the voltage V1. In response to the signal DS1, the ASW 621a of the voltage generation unit A621 outputs the voltage V1 as the reference voltage Vr1 to the detection unit 5 via the supply line for the reference voltage Vr1 of the line L.

  The decoder 636 outputs a signal DS2 that instructs the voltage generator B622 that generates the voltage V2 corresponding to the voltage selection signal S12 to output the voltage V2. In response to the signal DS2, the ASW of the voltage generation unit B622 outputs the voltage V2 as the reference voltage Vr2 to the detection unit 5 through the supply line for the reference voltage Vr2 of the line L.

  A case where the control circuit unit 1 causes the reference voltage supply unit 6 to execute the third mode will be described. For example, the control circuit unit 1 sets the mode selection signal M3 in the mode setting register 64.

  When the mode selection signal M3 is set, the mode setting register 64 outputs the mode selection signal M3 to the ASW 61 and the selector 635. When the mode selection signal M3 is input, the ASW 61 outputs a high impedance signal Hz.

  The voltage calculation unit 634 calculates the PLL clock frequency set in the PLL frequency setting register 632 from the voltage selection signal S2x (x is 1 to n) recorded in FIG. 17 and the modulation set in the modulation value setting register 633. The voltage selection signal S2x corresponding to the value is selected. For example, when the modulation value set in the modulation value setting register 633 is “30 [KHz]” and the PLL clock frequency set in the PLL frequency setting register 632 is “80 [MHz]”, the voltage calculation unit 634 The selection signals S21 and S22 are output to the selector 635.

  When the mode selection signal M3 is input, the selector 635 outputs the voltage selection signals S S21 and S22 output from the voltage selection register 631 to the decoder 636. The decoder 636 outputs a signal DS1 that instructs the voltage generator A621 that generates the voltage V1 corresponding to the voltage selection signal S21 to output the voltage V1. In response to the signal DS1, the ASW 621a of the voltage generation unit A621 outputs the voltage V1 as the reference voltage Vr1 to the detection unit 5 via the supply line for the reference voltage Vr1 of the line L.

  The decoder 636 outputs a signal DS2 that instructs the voltage generator B622 that generates the voltage V2 corresponding to the voltage selection signal S22 to output the voltage V2. In response to the signal DS2, the ASW of the voltage generation unit B622 outputs the voltage V2 as the reference voltage Vr2 to the detection unit 5 through the supply line for the reference voltage Vr2 of the line L.

  The reference voltages Vr1 and Vr2 are voltages with a predetermined margin added in consideration of switching time between synchronous communication and asynchronous communication.

  In this way, reference voltages having different values can be supplied to the detection unit 5. In addition, since the user can cause the reference voltage supply unit 6 to execute a desired mode from the first to third modes, convenience is improved.

  The above embodiment is summarized as follows.

(Appendix 1)
A first clock generation circuit that generates a first clock having a first frequency that varies in frequency with respect to the second frequency;
A second clock generation circuit for generating a second clock having the second frequency;
A first circuit unit that operates based on the first clock;
A second circuit unit that operates based on the second clock;
A bus connecting the first circuit unit and the second circuit unit;
A detection unit for detecting whether a frequency difference between the first frequency and the second frequency is within a first predetermined range;
A synchronization bus that performs synchronous communication between the first circuit unit and the second circuit unit when the frequency difference is within the first predetermined range; and the frequency difference is the first predetermined range. An electronic device comprising: a bus bridge unit having an asynchronous bridge unit that executes asynchronous communication between the first circuit unit and the second circuit unit when out of range.

(Appendix 2)
In Appendix 1,
The first clock generation circuit includes a voltage-controlled oscillator that generates the first clock according to a first oscillator control voltage, and a frequency of the first clock varies with respect to the second frequency. A first phase synchronization circuit having a modulator for performing modulation as described above,
The second clock generation circuit includes a second phase locked loop circuit having a voltage controlled oscillator that generates the second clock according to a second oscillator control voltage,
The detection unit detects whether the voltage difference between the first oscillator control voltage and the second oscillator control voltage is within a second predetermined range, so that the frequency difference is within the first predetermined range. An electronic device that detects whether it is inside or not.

(Appendix 3)
In Appendix 1 or 2,
The electronic device in which the first clock generation circuit varies the first frequency around the second frequency.

(Appendix 4)
In Appendix 2,
Furthermore, an electronic apparatus having a reference voltage supply unit that supplies a reference voltage indicating the second predetermined range to the detection unit.

(Appendix 5)
In Appendix 4,
The reference voltage supply unit is an electronic device that supplies an external input voltage input from the outside to the detection unit.

(Appendix 6)
In Appendix 4 or 5,
The reference voltage supply unit includes a voltage generation unit that generates a plurality of voltages, and a selection register in which a first voltage selection signal that selects a voltage to be supplied to the detection unit from the plurality of voltages is set. An electronic apparatus that supplies any of the plurality of voltages to the detection unit based on the first voltage selection signal, and the first voltage selection signal can be set in the selection register from the outside.

(Appendix 7)
In Appendix 4 or 5,
The reference voltage supply unit includes a voltage generation unit that generates a plurality of voltages, a frequency register in which the second frequency is set, a modulation value register in which a modulation value of the modulator is set, the modulation value, A table in which a second voltage selection signal is recorded corresponding to the second frequency, and supplies one of the plurality of voltages to the detection unit based on the second voltage selection signal, An electronic device in which the modulation value in the modulation value register and the second frequency in the frequency register can be set from the outside.

(Appendix 8)
In Appendix 4,
The reference voltage supply unit includes a voltage generation unit that generates a plurality of voltages, a selection register that is set with a first voltage selection signal that selects a voltage to be supplied to the detection unit from the plurality of voltages, A frequency register in which a second frequency is set, a modulation value register in which a modulation value of the modulator is set, and a second voltage selection signal corresponding to the modulation value and the second frequency are recorded Table,
A first mode in which an external input voltage input from the outside is supplied to the detection unit; a second mode in which any of the plurality of voltages is supplied to the detection unit based on the first voltage selection signal; A mode setting register for setting a mode selection signal for selecting one of the third modes for supplying any of the plurality of voltages to the detection unit based on the voltage selection signal of 2;
Based on the mode selection signal, execute any one of the first to third modes,
The first voltage selection signal of the selection register, the modulation value of the modulation value register, the second frequency of the frequency register, and the mode selection signal of the mode setting register can be set from the outside .

1 ... Control circuit unit (first circuit unit), 2 ... Peripheral circuit unit (second circuit unit), 3 ... Bus bridge unit, 31, 33 ... Asynchronous bridge unit, 311 ... Input unit, 312 ... Output unit, 32, 34 ... selector, 4 ... bus control unit, 5 ... detection unit, 51 ... voltage difference detection unit, 52, 53 ... comparator, 54 ... OR circuit, 55 ... bias voltage generation unit, 55a ... bias voltage generation circuit, C ... Capacitor, 6 ... Reference voltage supply unit, 61 ... ASW, 621 to 62n ... Voltage generation unit A to Voltage generation unit N, 621a ... ASW, Ra1, Ra2 ... Voltage dividing resistor, 63 ... Selection unit, 631 ... Voltage selection Register, 632 ... PLL frequency setting register, 633 ... Modulation value setting register, 634 ... Voltage calculation unit, 635 ... Selector, 636 ... Decoder, 64 ... Mode setting register, 7 ... PLL circuit, 8 ... SSCG circuit, 71,81 ... Phase comparator, 72,82 ... Charge pump, 73,83 ... LPF, 74,84 ... Voltage controlled oscillator, 75,85 ... 1 / P divider, 76 ... 1 / N divider, 86 ... 1 / N Divider_Modulation .

Claims (5)

A first clock generation circuit that generates a first clock having a first frequency that varies in frequency with respect to the second frequency;
A second clock generation circuit for generating a second clock having the second frequency;
A first circuit unit that operates based on the first clock;
A second circuit unit that operates based on the second clock;
A bus connecting the first circuit unit and the second circuit unit;
In a period in which the first circuit unit and the second circuit unit are communicating via the bus, a frequency difference between the first frequency and the second frequency is a first predetermined range. A detection unit for detecting whether or not within,
In the period running the communication, in case indicating that a detection result of the detector is the frequency difference is within the first predetermined range, said first circuit unit and the second circuit unit a synchronous bus for performing synchronous communication with the, in the period running the communication, in case indicating that a detection result of the detector is the frequency difference is outside said first predetermined range, Asynchronous bridge unit that performs asynchronous communication between the first circuit unit and the second circuit unit, and in a period of executing the communication, according to the detection result of the detection unit, An electronic device comprising: a bus bridge unit that performs switching between the synchronous communication and the asynchronous communication . In claim 1,
The first clock generation circuit includes a voltage-controlled oscillator that generates the first clock according to a first oscillator control voltage, and a frequency of the first clock varies with respect to the second frequency. A first phase synchronization circuit having a modulator for performing modulation as described above,
The second clock generation circuit includes a second phase locked loop circuit having a voltage controlled oscillator that generates the second clock according to a second oscillator control voltage,
The detection unit detects whether the voltage difference between the first oscillator control voltage and the second oscillator control voltage is within a second predetermined range, so that the frequency difference is within the first predetermined range. An electronic device that detects whether it is inside or not. In claim 2,
The electronic device in which the first clock generation circuit varies the first frequency around the second frequency. In claim 2,
Furthermore, an electronic apparatus having a reference voltage supply unit that supplies a reference voltage indicating the second predetermined range to the detection unit. In claim 4,
The reference voltage supply unit includes a voltage generation unit that generates a plurality of voltages, a selection register that is set with a first voltage selection signal that selects a voltage to be supplied to the detection unit from the plurality of voltages, A frequency register in which a second frequency is set, a modulation value register in which a modulation value of the modulator is set, and a second voltage selection signal corresponding to the modulation value and the second frequency are recorded Table,
A first mode in which an external input voltage input from the outside is supplied to the detection unit; a second mode in which any of the plurality of voltages is supplied to the detection unit based on the first voltage selection signal; A mode setting register for setting a mode selection signal for selecting one of the third modes for supplying any of the plurality of voltages to the detection unit based on the voltage selection signal of 2;
Based on the mode selection signal, execute any one of the first to third modes,
The first voltage selection signal of the selection register, the modulation value of the modulation value register, the second frequency of the frequency register, and the mode selection signal of the mode setting register can be set from the outside .

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