JPH07264061A - Pll oscillation circuit and semiconductor integrated circuit device using it - Google Patents

Abstract

PURPOSE:To provide a PLL oscillation circuit technique capable of preventing a malfunction and a destruction and making the circuit widely stable in oscillation and low in power consumption by detecting a control voltage to be inputted into a VCO, feedbacking this voltage to the VCO and fixing an output level. CONSTITUTION:This PLL oscillation circuit is incorporated into a semiconductor integrated circuit device such as a single chip microcomputer, and is constituted of a phase comparator 1 comparing the frequencies of an input signal and a feedback signal, a charge pump/low pass filter 2 eliminating high frequency noise components by converting them into the voltage according to the difference of the frequencies and a VCO 3 by which an oscillation frequency changes according to inputs and a voltage detection circuit 4 detecting the voltage level to be inputted in the VCO 3 and controlling the output of the VCO 3. When the error voltage to be detected by this voltage detection circuit 4 deviates from the corresponded voltage within the range of the allowable frequency of an input signal, the output of the VCO 3 is controlled and an output voltage level is fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) oscillator circuit technology for a semiconductor integrated circuit device, and more particularly to a voltage controlled oscillator (VCO).
of a semiconductor integrated circuit device using a PLL oscillation circuit by controlling the output frequency of the ator), prevention of malfunction and destruction of the circuit / system, stabilization of a wide range of oscillation, and low power consumption. And a technique effective when applied to a semiconductor integrated circuit device using the same.

[0002]

2. Description of the Related Art For example, a PLL of a semiconductor integrated circuit device
As a technique related to the oscillation circuit, this PLL oscillation circuit and the basic principle of the PLL are described in April 1, 1992.
It is described in paragraphs 1 and 2 of "PLL Design and Practical Circuits-Learning Through Experiments- (4th Edition)" published by Seatask, Inc., Japan.

As shown in, for example, FIG. 15, the outline thereof is a VCO having a self-excited oscillator, the oscillation frequency of which changes according to an input, a frequency output from the VCO and fed back, and a frequency of an input signal. And a low-pass filter that removes high frequency noise components from the average DC voltage output from the phase comparator and supplies an error voltage.

Then, in the PLL oscillator circuit, the error voltage output from the low-pass filter to form a loop is returned to the VCO, and the error voltage is further fed to the input signal and VCO.
The VCO is operated so as to change the frequency error with the output signal of the CO so as to reduce the frequency error, and a desired frequency that matches the frequency of the input signal is output.

[0005]

However, in the technique described above, the VCO lowers the oscillation frequency of the ring oscillator in the VCO when the voltage level of the input signal decreases.
On the contrary, if it increases, the frequency of the ring oscillator is raised. For example, if the voltage of the input signal becomes the ground level, the oscillation frequency approaches zero, and if it becomes the power supply voltage level, it rises to the maximum oscillation frequency of the ring oscillator.

As a result, abnormal oscillation may occur when the oscillation frequency approaches zero, and the maximum oscillation frequency of the ring oscillator is usually designed with a margin,
When oscillating at the maximum oscillating frequency, the aluminum wiring in the semiconductor integrated circuit device may be blown, and the circuit / system that operates using this oscillating output may malfunction.

Further, the voltage / current converter in the VCO is MO
If it is composed of S transistors, the gate voltage is M
When the threshold voltage Vth of the OS transistor is exceeded, a current suddenly starts to flow, the oscillation frequency changes due to this change in current, and a rapid change in current appears as a rapid change in oscillation frequency, so a stable oscillation frequency can be obtained. Have difficulty.

Further, a PLL oscillator circuit generally has a narrow frequency range, and particularly in a general-purpose microcomputer such as a single-chip microcomputer, it is difficult for the user to limit the frequency of the input signal. Even at the power supply voltage level, it is required that the microcomputer be easy to use without malfunction or destruction depending on the frequency.

Therefore, an object of the present invention is to detect the control voltage input to the VCO in order to control the oscillation frequency of the PLL oscillation circuit and feed it back to the VCO to fix the output level of the ring oscillator. By PL
It is an object of the present invention to provide a semiconductor integrated circuit device configured by using an L oscillating circuit, a PLL oscillating circuit capable of preventing malfunction and destruction in a circuit / system, and a semiconductor integrated circuit device using the same.

Another object of the present invention is to add a resistance element to a voltage / current converter in a VCO and feed it back to a PLL oscillating circuit to improve the voltage / current conversion characteristic and to oscillate the PLL. It is an object of the present invention to provide a semiconductor integrated circuit device configured by using a circuit, a PLL oscillation circuit capable of stable oscillation over a wide range in a circuit / system, and a semiconductor integrated circuit device using the same.

Still another object of the present invention is to control an internal clock signal of a CPU (Central Processing Unit) and a storage device in a semiconductor integrated circuit device and stop the internal clock signal to thereby generate a PLL oscillation circuit. A semiconductor integrated circuit device configured by using
P that can transition the system to a low power consumption state
An object of the present invention is to provide an LL oscillator circuit and a semiconductor integrated circuit device using the same.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the PLL oscillating circuit of the present invention comprises a phase comparator for comparing the frequency of the input signal with the frequency of the feedback signal, a low-pass filter for removing high frequency noise components, and a VCO whose oscillating frequency changes according to the input. And is applied to a PLL oscillation circuit that returns the error voltage output from the low-pass filter to the VCO and changes the frequency of this VCO to output a desired frequency.
The voltage level of the error voltage input to
It has a voltage detecting means for controlling the output of O.

In this case, the voltage detecting means is composed of a logic gate, and the threshold voltage of the logic gate is adjusted to set the upper limit, the lower limit of the allowable frequency of the input signal or the corresponding voltage within the range, or Alternatively, the voltage detecting means has a comparator circuit configuration using MOS transistors, and the comparison voltage of the comparator circuit is adjusted to set the upper limit, the lower limit of the allowable frequency of the input signal, or a voltage corresponding to the range.

In the voltage controlled oscillator, when the voltage / current converter for converting the error voltage input to the voltage controlled oscillator into a current is composed of MOS transistors, the MOS transistors to which the error voltage is directly input are provided. A resistance element is connected in series between the terminal and the ground.

In this case, a resistance or a MOS transistor is connected in series as the resistance element, and feedback is applied to the MOS transistor of the voltage / current converter by using the resistance component of the resistance or the MOS transistor. .

Further, the semiconductor integrated circuit device of the present invention is
The present invention is applied to a semiconductor integrated circuit device using the PLL oscillating circuit, in which the PLL oscillating circuit is built in a signal generating circuit, and in addition to this signal generating circuit, at least a CPU and a memory device are provided on one semiconductor substrate. To form.

In this case, the internal clock signals of the CPU and the storage device are controlled by the output signal from the voltage detecting means of the PLL oscillation circuit.

[0020]

According to the above-described PLL oscillator circuit, the voltage detecting means for detecting the input voltage level to the VCO is provided with the voltage detecting means having the structure of, for example, a logic gate or the comparator circuit of MOS transistors. When the error voltage detected by the voltage detecting means exceeds the voltage corresponding to the upper limit of the allowable frequency of the input signal, is less than the voltage corresponding to the lower limit, or deviates from the voltage corresponding to the range, the VCO The output can be controlled to fix the output voltage level.

Thus, the detection signal of the VCO can be fed back to the VCO to limit the oscillation frequency of the VCO, and at the same time, the output voltage level can be fixed when an unexpected or frequency signal outside the frequency range is input. Therefore, it is possible to prevent malfunction and destruction in the semiconductor integrated circuit device configured by using the PLL oscillation circuit and further in the circuit / system.

In the voltage / current converter in the voltage controlled oscillator, a resistance element such as a resistor or a MOS is provided between the MOS transistor in the input stage and the ground.
By connecting a transistor etc., M of the input stage
Feedback can be applied between the gate and the source of the OS transistor.

As a result, the oscillation frequency can be linearly changed with respect to the feedback to the MOS transistor of the input stage with respect to the change of the flowing current, so that stable oscillation characteristics can be obtained in a wide range.

Further, according to the above-mentioned semiconductor integrated circuit device, the internal clock signal of the device formed on one semiconductor substrate such as the CPU and the memory device is generated by the output signal from the voltage detecting means of the PLL oscillation circuit. By being controlled, the internal clock signal can be stopped when an unexpected or clock signal outside the frequency range is input.

As a result, it is possible to make a transition to a low power consumption state by stopping the internal clock signal, so that it is possible to reduce the power consumption of the semiconductor integrated circuit device and the circuit / system that are configured by using the PLL oscillation circuit. You can

As a result, in a PLL oscillation circuit, a semiconductor integrated circuit device such as a single-chip microcomputer using the same, and a circuit / system such as a microcomputer system,
Even if the input signal exceeds the limit of the frequency range, the oscillation frequency can be limited without causing malfunction or destruction, and stable oscillation can be achieved in a wider range, and the power consumption can be reduced.
An L oscillator circuit can be obtained, and a semiconductor integrated circuit device and a circuit / system that are easy for the user to use can be provided.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a functional block diagram showing a PLL oscillation circuit which is an embodiment of the present invention, FIG. 2 is a circuit diagram showing a VCO in the PLL oscillation circuit of this embodiment, and FIG.
5 is a circuit diagram showing a voltage detection circuit, FIG. 4 is a schematic circuit diagram showing a phase comparator and a charge pump / low-pass filter, FIG.
(A), (b) is a waveform diagram for explaining the transition of the input voltage to the VCO by comparing the frequency of the input signal with the frequency of the output of the VCO, and FIG. 6 is a circuit diagram showing a modified example of the voltage detection circuit. 7 is a circuit diagram showing a modification of the VCO.

First, the configuration of the PLL oscillation circuit of this embodiment will be described with reference to FIG.

The PLL oscillation circuit of this embodiment has, for example, 1
It is a PLL oscillator circuit built in a semiconductor integrated circuit device such as a single-chip microcomputer formed on each semiconductor substrate, and a phase comparator 1 for comparing the frequency of an input signal with the frequency of a feedback signal and a frequency difference Convert it to the appropriate voltage,
A charge pump / low-pass filter 2 that removes high-frequency noise components, and V whose oscillation frequency changes according to the input
It is composed of CO3 and a voltage detection circuit (voltage detection means) 4 that detects the voltage level input to this VCO3 and controls the output of VCO3.

The phase comparator 1 receives an input signal input from the outside and a feedback signal output from the VCO 3 and fed back, and compares the frequency of these input signals with the frequency fed back from the VCO 3. The comparison result is output to the charge pump / low-pass filter 2.

The charge pump / low pass filter 2 is
The output signal from the phase comparator 1 is input and converted into an average DC voltage proportional to the frequency difference and phase difference of this signal,
Further, it is a part that supplies an error voltage from which high-frequency noise components have been removed, and this error voltage is output to the VCO 3 and the voltage detection circuit 4.

The VCO 3 is, for example, as shown in FIG.
A voltage / current converter 5 that converts an input error voltage into a current, a ring oscillator 6 that has a self-excited oscillation function that changes the oscillation frequency according to the current, and a fixed circuit 7 that fixes the output level of the output frequency. The fixed circuit 7 is added with the addition of the voltage detection circuit 4.

In FIG. 2, the voltage / current converter 5 has 2
PMOS transistors TRp and NM connected in series to the stage
An error voltage from the charge pump / low-pass filter 2 is input to the gate of the NMOS transistor TRn in the front stage, which is composed of the OS transistor TRn, and the gates of the PMOS transistor TRp and the NMOS transistor TRn in the rear stage are connected to the ring oscillator 6, respectively.

The ring oscillator 6 includes two PMOS transistors TRp and two NMs connected in series in five stages.
The gate of each PMOS transistor TRp, which is composed of the OS transistor TRn and is connected to the power supply voltage Vcc, has a PMOS transistor TRp of the voltage / current converter 5.
Each of the NMOS connected to the
The gate of the transistor TRn is N of the voltage / current converter 5.
It is connected to the MOS transistor TRn.

Further, each P connected to the central portion
MOS transistor TRp and NMOS transistor TR
The gate and the drain are connected to n, the drains in the previous stage are connected to the gates in the subsequent stage, and the drains in the final stage are connected to the gates in the front stage to be fed back and fixed circuit. Connected to 7.

The fixed circuit 7 is composed of a PMOS transistor TRp, and the drain of the PMOS transistor TRp is connected between the drains between the PMOS transistor TRp and the NMOS transistor TRn at the final stage of the ring oscillator 6, and the ring oscillator 6 Is the output of this PMO
The output level is fixed by the S transistor TRp.

In such a VCO 3, the error voltage signal from the charge pump / low-pass filter 2 and the control signal M from the voltage detection circuit 4 are input, and the error signal from the charge pump / low-pass filter 2 is used. , A part that operates to change the frequency by the ring oscillator 6 in the direction of reducing the frequency difference between the input signal and the output signal of the VCO 3, and this change in frequency is output to the outside and the phase comparator 1 Returned to P
A loop is formed in the LL oscillator circuit.

When the VCO 3 starts changing the frequency, the loop enters the capture range state, and this process is continued until the frequencies of the VCO 3 and the input signal completely match, and when they match, the loop is in the locked or phase locked state. Becomes VCO3 during this phase lock state.
The frequency is output in the same state as the frequency of the input signal of the loop, so that if the phase lock state is entered, it will follow any change in the frequency of the input signal.

When the control signal M from the voltage detection circuit 4 is input to the VCO 3 and the input of the control signal M causes an unexpected or out-of-frequency input signal, that is, the upper limit of the set allowable frequency is exceeded. , VCO3 if the lower limit is not reached or if the lower limit is exceeded
Is controlled, and the output voltage level of the fixed circuit 7 is fixed.

The voltage detection circuit 4 uses the error voltage signal from the charge pump / low-pass filter 2, that is, the VCO.
3 is a part which receives the error voltage input to the input terminal 3 and detects the voltage level of this error voltage to control the output of the VCO 3. For example, as shown in FIG.
It is composed of OT.

In the case of this NOT gate NOT, the threshold voltage Vlt of the NOT gate NOT is adjusted so that either the voltage corresponding to the upper limit or the lower limit of the allowable frequency of the input signal is set and input. The control signal M acting to fix the output voltage level of the VCO 3 is VCO 3 when the error voltage exceeds the set upper limit voltage or less than the lower limit voltage.
Is output to.

As described above, a loop is formed in which the error voltage output from the charge pump / low pass filter 2 through the phase comparator 1 is returned to the VCO 3, and the VCO 3 is formed.
The desired frequency is output by changing the frequency of No. 3, and when the frequency of the input signal is outside the set range, malfunction and destruction of the device in the semiconductor integrated circuit device using this output frequency as the internal clock In order to prevent the above, the output of the VCO 3 is controlled and the output voltage level is fixed.

Next, with respect to the operation of this embodiment, the operation of the PLL oscillation circuit will be described.

First, in the phase comparator 1, the frequency of the input signal input from the outside is compared with the frequency of the feedback signal output from the VCO 3 and fed back, and the comparison result is sent to the charge pump / low-pass filter 2. Output.

Further, in the charge pump / low pass filter 2, the output signal from the phase comparator 1 is converted into an average DC voltage proportional to the frequency difference and the phase difference, the high frequency noise component is removed, and the VCO 3 and the voltage are output as an error voltage. Output to the detection circuit 4.

The VCO 3 operates so that the error voltage from the charge pump / low-pass filter 2 causes the ring oscillator 6 to change the frequency in the direction of reducing the frequency difference between the input signal and the output signal of the VCO 3. , This frequency change is output to the outside and fed back to the phase comparator 1.

Then, the VCO 3 starts changing the frequency, and V
This process is continued until the frequency of CO3 and the frequency of the input signal completely match, and when they match, the loop becomes in the locked or phase locked state, and the output of the PLL oscillation circuit can be output at the frequency equal to the frequency of the input signal. .

At this time, for example, in the configuration of the phase comparator 1 and the charge pump / low-pass filter 2 shown in FIG. 4, when the frequency of the input signal is higher than the frequency of the output of the VCO 3, FIG. As described above, during the period when the control signal UP is Low level, the PMOS transistor TR
Capacitor C is charged via p, which causes VC
The input to O3 is gradually increased to a voltage equal to the frequency of the input signal.

On the contrary, when the frequency of the input signal is lower than the frequency of the output of the VCO 3, the capacitor C is kept in the high level period of the control signal DOWN as shown in FIG. 5 (b).
Through the resistor R and the NMOS transistor TRn, whereby the input to the VCO 3 gradually decreases and drops to a voltage equal to the frequency of the input signal. Thus, if the input signal is within the predetermined frequency range,
The input to VCO3 is controlled to a voltage equal to the frequency of the input signal.

However, when the frequency of the input signal is unexpected or out of the frequency range, that is, when the upper limit of the set allowable frequency is exceeded, when the lower limit is not reached or when the frequency is out of the range, the voltage detection circuit 4 operates. The control signal M controls the output of the VCO 3 to fix the output voltage level of the fixed circuit 7.

For example, when detecting the case where the frequency of the input signal is below the lower limit, the voltage detecting circuit 4 adjusts the threshold voltage of the NOT gate NOT to set the voltage corresponding to the lower limit of the allowable frequency of the input signal. The output voltage level of the VCO 3 is fixed when the voltage level of the error voltage input to the VCO 3 does not reach the set lower limit voltage.

That is, for example, in the case of a PLL oscillation circuit operated within the range of 1V to 4V, when the voltage detected by the voltage detection circuit 4 is less than 1V such as 0.8V, the voltage detection circuit 4 is supplied to the voltage detection circuit 4. The voltage of the error voltage is Low level, and the output of this voltage detection circuit 4 becomes Low level, and this Low level control signal M is input to the fixed circuit 7 of the VCO 3.

Further, by inputting the low-level control signal M to the fixed circuit 7 of the VCO 3, the fixed circuit 7
Of the PMOS transistor TRp of the ring oscillator 6 is turned off,
A high-level feedback signal is applied between the gates of the MOS transistors TRn, and the second-stage low level and 3
High level is applied to the tier, low level is applied to the tier, and high level is applied to the last tier.

Then, the PMOS transistor T at the final stage
L between the drain of Rp and the NMOS transistor TRn
Since the ow level signal is output and the level of the input signal to the VCO 3 can be fixed to the high level by the fixing circuit 7, it is possible to stop the internal clock signal of the circuit connected thereafter.

Similarly, when detecting the case where the frequency of the input signal exceeds the upper limit, the threshold voltage of the NOT gate NOT of the voltage detection circuit 4 is set to a voltage corresponding to the upper limit of the allowable frequency of the input signal, for example, 4V. However, when the voltage level of the error voltage input to the VCO 3 exceeds the set upper limit 4V voltage, the output voltage level of the VCO 3 can be fixed and the internal clock signal of the circuit connected thereafter can be stopped. it can.

Therefore, according to the PLL oscillating circuit of this embodiment, the voltage detecting circuit 4 constituted by the two-stage NOT gate NOT is provided, and the voltage level of the error voltage to the VCO 3 is detected. If the error voltage exceeds the voltage corresponding to the upper limit of the allowable frequency of the input signal or is less than the voltage corresponding to the lower limit, the output of the VCO 3 can be controlled to fix the output voltage level, which is unexpected. Alternatively, when a clock signal outside the frequency range is input, it is possible to prevent a malfunction of the PLL oscillation circuit, and to prevent a malfunction and destruction of a semiconductor integrated circuit device configured by using this PLL oscillation circuit and further a circuit / system. be able to.

Further, this voltage detection circuit (voltage detection means)
4a is, for example, as shown in FIG. 6, NOT gate NO
In the case of T and NOR gate NOR, when the input error voltage deviates from the voltage corresponding to the upper limit and the lower limit of the allowable frequency of the input signal, the output of the VCO 3 is controlled to output the output voltage. Since the level can be fixed, the detection signal of the VCO 3 can be fed back to the VCO 3 to limit the oscillation frequency of the VCO 3 at the same time, and at the same time, prevent malfunction and destruction when a clock signal outside the frequency range is input. be able to.

That is, in FIG. 6, the two Ns in the upper row are
The OT gate NOT adjusts and sets the threshold voltage to a voltage corresponding to the upper limit of the allowable frequency of the input signal, and the lower NOT gate NOT adjusts and sets the threshold voltage to a voltage corresponding to the lower limit of the allowable frequency of the input signal. By doing so, the output voltage level of the VCO 3 can be fixed by the control signal M from the NOR gate NOR when the error voltage input within the set range is deviated, so that malfunctions and damages can be performed as described above. Can be prevented.

Further, in the case where the fixed circuit 7a is constituted by a NAND gate NAND as shown in FIG. 7, for example, the VCO 3a does not pass through the NAND circuit NAND as compared with the PMOS transistor TRp shown in FIG. The effect that the current can be zero can be obtained.

(Embodiment 2) FIG. 8 is a circuit diagram showing a voltage detection circuit in a PLL oscillation circuit which is another embodiment of the present invention, and FIG. 9 is a circuit diagram showing a modification of the voltage detection circuit.

The PLL oscillation circuit of this embodiment is built in a semiconductor integrated circuit device such as a single-chip microcomputer formed on one semiconductor substrate as in the case of the first embodiment, and includes a phase comparator 1, a charge pump / low-pass filter. Filter 2, VCO
3 and a voltage detection circuit 4, which is a PLL oscillation circuit. The difference from the first embodiment is that the first embodiment adjusts the threshold voltage of the gate to detect the level. The embodiment is that a method of detecting a voltage level by a comparator circuit is used.

That is, in this embodiment, the phase comparator 1, charge pump / low-pass filter 2 and VC are used.
The circuit configuration of O3 is the same as that of the first embodiment, and the voltage detection circuit (voltage detection means) 4b is connected in two stages in series as shown in FIG.
It consists of transistor TRn and NOT gate NOT,
It has a comparator circuit configuration of MOS transistors in which the gates of the NMOS transistors TRn at the front and rear stages are connected.

In FIG. 8, the error voltage from the charge pump / low-pass filter 2 is input to the gate of the PMOS transistor TRp in the front stage, and the drain of the PMOS transistor TRp and the NMOS transistor TRn in the front stage is connected to the NOT gate NOT. The control signal M is output from the NOT gate NOT to the VCO 3.

In this case, the comparison voltage of the comparator circuit becomes the comparison voltage because the gate of the PMOS transistor TRp in the subsequent stage is connected to the ground, and the error voltage corresponding to the frequency of the input signal becomes the comparison voltage. If the output voltage level of the VCO 3 is fixed by the control signal M when the comparison voltage is less than the comparison voltage, the internal clock signal of the circuit connected thereafter can be stopped.

Therefore, according to the PLL oscillating circuit of this embodiment, the voltage detecting circuit 4b has the comparator circuit configuration of the PMOS transistor TRp and the NMOS transistor TRn, and the ground level which is the comparison voltage corresponds to the frequency of the input signal. If the error voltage is less than
Since the output voltage level can be fixed by controlling the output of the VCO 3 as in the first embodiment, a malfunction of the PLL oscillation circuit can be prevented, and a semiconductor integrated circuit device configured using this PLL oscillation circuit, Further, malfunctions and damages in the circuit / system can be prevented.

Further, this voltage detection circuit (voltage detection means)
When 4c is composed of, for example, a PMOS transistor TRp and an NMOS transistor TRn connected in series in approximately three stages and a NOT gate NOT as shown in FIG. 9, the threshold voltage Vth of the NMOS transistor TRn in the last stage is 4c. It becomes a comparison voltage, and this comparison voltage can be adjusted and set to a voltage corresponding to the lower limit or the upper limit of the allowable frequency of the input signal.

As a result, when the set voltage is less than or exceeds the set voltage, the NOT gate NOT
Since the output voltage level of the VCO 3 can be fixed by the control signal M from the above, when the input error voltage deviates from the upper limit voltage or the lower limit voltage set corresponding to the allowable frequency of the input signal, Similarly, malfunction and destruction can be prevented.

(Embodiment 3) FIG. 10 is a circuit diagram of a main part showing a voltage detecting circuit in a PLL oscillation circuit which is still another embodiment of the present invention, and FIG. 11 shows an oscillation frequency characteristic in the PLL oscillation circuit of this embodiment. 12 and 13 are characteristic circuit diagrams showing modified examples of the voltage detection circuit.

The PLL oscillation circuit of this embodiment is built in a semiconductor integrated circuit device such as a single-chip microcomputer formed on one semiconductor substrate as in the case of the first embodiment, and includes a phase comparator 1, a charge pump / low-pass filter. Filter 2, VCO
The PLL oscillating circuit is composed of the voltage detector 3 and the voltage detecting circuit 4, and is different from the first and second embodiments in that the first and second embodiments are erroneous when a clock signal outside the frequency range is input or unexpected. In contrast to the purpose of preventing destruction, the present embodiment has the main purpose of enabling stable and wide-range oscillation.

That is, in this embodiment, the phase comparator 1, the charge pump / low-pass filter 2 and the voltage detection circuit 4 have the same circuit configuration as those of the first and second embodiments, and the main part of the VCO 3b, that is, the voltage / current. Converter 5b
As shown in FIG. 10, a resistor (resistive element) R is connected in series between the NMOS transistor TRn to which the error voltage from the charge pump / low-pass filter 2 is input and the ground.

As a result, the voltage drop due to the resistor R becomes
When negative feedback is applied between the gate and the source of the NMOS transistor TRn, that is, when the gate-source voltage Vgs rises and exceeds the threshold voltage Vth of the NMOS transistor TRn, the drain-source current Ids begins to flow and the resistance R causes ΔV. Occurs and Vgs and Ids
Vgs = Vg−ΔV = Vg−Ids × R Ids = (Vg−Vgs) / R, and a rapid increase in Ids due to an increase in the gate voltage Vg can be suppressed.

That is, NM is calculated using the resistance component of the resistance R.
By applying negative feedback to the OS transistor TRn,
As shown in the oscillation frequency characteristic in FIG. 11, the oscillation frequency can be linearly changed in response to the change in the current flowing through the negative feedback, which is conventionally curved. .

Therefore, according to the PLL oscillation circuit of the present embodiment, in the voltage / current converter 5b of the VCO 3b, the resistor R is connected in series between the NMOS transistor TRn to which the error voltage is input and the ground. As a result, the oscillation frequency can be linearly changed with respect to the change in the current flowing by the negative feedback to the NMOS transistor TRn, so that stable oscillation characteristics of the PLL oscillation circuit can be obtained in a wide range, and the PLL can be obtained. It is possible to stably oscillate in a wide range in a semiconductor integrated circuit device configured by using an oscillator circuit and further in a circuit / system.

Further, the voltage / current converter 5c of the VCO 3c has a resistor R of NMO as shown in FIG.
If the gate input is replaced with the power supply voltage Vcc by replacing with the S transistor (resistive element) TRn, this NM
Due to the resistance component of the OS transistor TRn, a negative feedback can be applied to the gate-source voltage Vgs due to the rise of the source potential, and thus stable oscillation over a wide range can be performed as described above.

Further, the voltage of VCO 3d shown in FIG. 13 /
Like the current converter 5d, the NMOS transistor TRn
Even when an error voltage is input to the gate of the same, it is possible to provide an oscillation circuit in which a stable oscillation frequency with a wide operating power supply voltage range can be similarly obtained. Moreover, in the case of the NMOS transistor TRn as shown in FIGS. 12 and 13,
The layout area can be reduced as compared with the case of the resistor R in FIG.

(Fourth Embodiment) FIG. 14 is a schematic block diagram showing a main part of a microcomputer system to which a PLL oscillation circuit according to a fourth embodiment of the present invention is applied.

A microcomputer system to which the PLL oscillation circuit of this embodiment is applied is a semiconductor integrated circuit device such as a single chip microcomputer formed on one semiconductor substrate, and phase comparison similar to that of the first to third embodiments is performed. A PLL oscillation circuit including a charge pump / low-pass filter 2, a VCO 3 and a voltage detection circuit 4 is used.
In the present embodiment, unlike the first to third embodiments, the main purpose is to positively utilize the control signal of the voltage detection circuit 4 to transition to the low power consumption state and stop the internal clock signal in the system. That is the point.

That is, in the microcomputer system of this embodiment, as shown in FIG.
8, ROM (Read Only Memory) 9, RAM
(Random Access Memory) 10, DMAC
In addition to functional modules such as (Direct Memory Access Controller) 11, a CPG (Clock Pulse Generator) 12 is provided, and the CPG 12 has the first embodiment.
The same PLL oscillating circuit as that used in Nos. 3 to 3 is used, and the internal clock signal from the VCO 3 and the control signal M from the voltage detecting circuit 4 are directly output to control the operation of the functional module.

Thus, for example, in the normal case, C
CPU8, R by the internal clock signal from PG12
When the functional modules such as the OM9, the RAM10, and the DMAC11 are normally operated and the input voltage of the VCO3 corresponding to the frequency of the input signal exceeds the voltage corresponding to the upper limit of the set allowable frequency, the voltage corresponding to the lower limit is set. The control signal M from the CPG 12 can be used to stop the internal clock signal if it does not meet, or deviates from the corresponding voltage within its range, to stop the operation of these functional modules.

Therefore, according to the microcomputer system to which the PLL oscillating circuit of this embodiment is applied, the control signal M from the CPG 12 using the PLL oscillating circuit is used to stop the internal clock signal. Since the system can be transited to the low power consumption state by stopping the clock signal, it is possible to reduce the power consumption of the semiconductor integrated circuit device configured by using the PLL oscillation circuit and further the circuit / system.

Although the invention made by the present inventor has been concretely described based on the first to fourth embodiments, the present invention is not limited to the above-mentioned embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the types and configurations of the logic gates of the first embodiment, the types of transistors and the comparator circuit configuration of the second embodiment, the types of resistance elements of the third embodiment, etc., are the same as those of the above-described examples shown in FIGS. However, the present invention is not limited to this configuration, and various modifications are possible.

Further, this PLL oscillation circuit is not only used as an oscillation circuit of its own, but also a semiconductor integrated circuit device such as a single chip microcomputer formed on one semiconductor substrate, and further this semiconductor integrated circuit device. It is also widely applicable to combined circuits and systems.

[0085]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). By having the voltage detection means for detecting the voltage level of the error voltage input to the VCO and controlling the output of the VCO, the error voltage detected by this voltage detection means is If the voltage corresponding to the upper limit of the allowable frequency is exceeded, the voltage corresponding to the lower limit is not reached, or the voltage falls out of the range, the VCO
Since the output voltage level can be fixed by controlling the output of the VCO, the detection signal of the VCO can be fed back to the VCO to limit the oscillation frequency of the VCO, and at the same time, an unexpected or frequency signal outside the frequency range is input. In this case, malfunction and destruction can be prevented.

(2) In the above (1), when a voltage / current converter for converting an error voltage input to the VCO into a current is provided, the error voltage is directly input between the MOS transistor and the ground. By connecting a resistance element in series to the gate, feedback can be applied between the gate and the source of the MOS transistor at the input stage. Therefore, the oscillation frequency is linear with respect to the change in the current flowing due to the feedback to the MOS transistor. It is possible to change it, and thereby it is possible to obtain stable oscillation characteristics in a wide range.

(3) In the above (1), when the PLL oscillation circuit is built in the signal generating circuit and at least the CPU and the memory device are formed on one semiconductor substrate in addition to the signal generating circuit, By controlling the internal clock signals of the CPU and the storage device with the output signals from the voltage detection means of the PLL oscillation circuit, the internal clock signals can be stopped when an unexpected or clock signal outside the frequency range is input. Therefore, it is possible to reduce the power consumption by transitioning to the low power consumption state by stopping the internal clock signal.

(4) Due to the above (1) to (3), particularly in the PLL oscillation circuit, the semiconductor integrated circuit device using the same, and the circuit / system combining these, the input signal limits the frequency range. It is possible to obtain a PLL oscillation circuit in which the oscillation frequency can be restricted without malfunction or destruction even if it exceeds, and stable oscillation and low power consumption can be achieved in a wide range.

(5) Due to the above (4), even if the frequency input to the PLL oscillation circuit is the ground level or the power supply voltage level, the oscillation frequency can be controlled so that the VCO does not abnormally oscillate. Therefore, it is possible to supply a semiconductor integrated circuit device and a circuit / system that are easy for the user to use.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a PLL oscillation circuit that is Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a VCO in the PLL oscillation circuit of the first embodiment.

FIG. 3 is a circuit diagram showing a voltage detection circuit in the PLL oscillation circuit of the first embodiment.

FIG. 4 is a schematic circuit diagram showing a phase comparator and a charge pump / low pass filter in the PLL oscillation circuit of the first embodiment.

5 (a) and 5 (b) are waveform diagrams for explaining the transition of the input voltage to the VCO by comparing the frequency of the input signal with the frequency of the output of the VCO in the PLL oscillation circuit of the first embodiment.

FIG. 6 is a circuit diagram showing a modified example of the voltage detection circuit in the first embodiment.

FIG. 7 is a circuit diagram showing a modification of the VCO in the first embodiment.

FIG. 8 is a circuit diagram showing a voltage detection circuit in a PLL oscillation circuit that is Embodiment 2 of the present invention.

FIG. 9 is a circuit diagram showing a modified example of the voltage detection circuit according to the second embodiment.

FIG. 10 is a main part circuit diagram showing a voltage detection circuit in a PLL oscillation circuit which is Embodiment 3 of the present invention.

FIG. 11 is a characteristic diagram showing an oscillation frequency characteristic in the PLL oscillation circuit of the third embodiment.

FIG. 12 is a main-portion circuit diagram showing a modified example of the voltage detection circuit according to the third embodiment.

FIG. 13 is a main part circuit diagram showing another modified example of the voltage detection circuit in the third embodiment.

FIG. 14 is a schematic block diagram showing a main part of a microcomputer system to which a PLL oscillation circuit according to a fourth embodiment of the present invention is applied.

FIG. 15 is a functional block diagram showing a PLL oscillation circuit which is an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Charge pump / low pass filter 3,3a-3d VCO 4,4a-4c Voltage detection circuit (voltage detection means) 5,5b-5d Voltage / current converter 6 Ring oscillator 7,7a Fixed circuit 8 CPU 9 ROM (storage device) 10 RAM (storage device) 11 DMAC 12 CPG (signal generation circuit) TRp PMOS transistor TRn NMOS transistor NOT NOT gate C capacitor R resistor NOR NOR gate NAND NAND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiro Uchiyama 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Kiyoshi Matsubara 5-chome, Mizumizuhoncho, Kodaira-shi, Tokyo No. 20-1 Incorporated company Hitachi Ltd. Semiconductor Division

Claims (7)

[Claims] 1. A voltage-controlled oscillator having a self-excited oscillator, the oscillation frequency of which changes according to an input, a phase comparison for comparing a frequency output from the voltage-controlled oscillator and fed back, and a frequency of an input signal. And a low-pass filter that removes high-frequency noise components from the average DC voltage output from the phase comparator to supply an error voltage, and returns the error voltage output from the low-pass filter to the voltage controlled oscillator. A PLL oscillation circuit that outputs a desired frequency by changing the frequency of the voltage controlled oscillator, and detects the voltage level of an error voltage input to the voltage controlled oscillator to control the output of the voltage controlled oscillator. A PLL oscillating circuit having a voltage detecting means. 2. The voltage detecting means is composed of a logic gate, and a threshold voltage of the logic gate is adjusted to set a voltage corresponding to an upper limit, a lower limit or a range of an allowable frequency of the input signal, and the detection is performed. If the voltage level of the error voltage that is set exceeds the upper limit voltage that has been set,
2. The PLL oscillating circuit according to claim 1, wherein the output voltage level of the voltage controlled oscillator is fixed when the voltage is below the lower limit voltage or out of a voltage within the range. 3. The voltage detecting means has a comparator circuit configuration using MOS transistors, and the comparison voltage of the comparator circuit is adjusted to set an upper limit, a lower limit of the allowable frequency of the input signal, or a voltage corresponding to the range. The output voltage level of the voltage controlled oscillator is fixed when the voltage level of the detected error voltage exceeds the set upper limit voltage, does not reach the lower limit voltage, or deviates from the voltage within the range. The PLL oscillation circuit according to claim 1, wherein 4. In the voltage controlled oscillator, an error voltage input to the voltage controlled oscillator is converted into a current, and MO
Having a voltage / current converter composed of S-transistors,
4. The PLL oscillation circuit according to claim 1, wherein a resistance element is connected in series between the MOS transistor to which the error voltage is directly input and the ground. 5. A resistance or a MOS transistor is connected in series as the resistance element, and the MO of the voltage / current converter is formed by using the resistance component of the resistance or the MOS transistor.
The PLL oscillation circuit according to claim 4, wherein feedback is applied to the S transistor. 6. The P according to claim 1, 2, 3, 4 or 5.
A semiconductor integrated circuit device using an LL oscillation circuit, wherein the PLL oscillation circuit is built in a signal generation circuit, and at least a CPU and a memory device are formed on one semiconductor substrate in addition to the signal generation circuit. A semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein the internal clock signals of the CPU and the storage device are controlled by an output signal from the voltage detection means of the PLL oscillation circuit.