JP5766095B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP5766095B2
JP5766095B2 JP2011243174A JP2011243174A JP5766095B2 JP 5766095 B2 JP5766095 B2 JP 5766095B2 JP 2011243174 A JP2011243174 A JP 2011243174A JP 2011243174 A JP2011243174 A JP 2011243174A JP 5766095 B2 JP5766095 B2 JP 5766095B2
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electrode
side electrode
type semiconductor
semiconductor layer
led die
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JP2013098515A (en
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嘉将 木下
嘉将 木下
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Citizen Holdings Co Ltd
Citizen Electronics Co Ltd
Citizen Watch Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

本発明はフリップチップ実装用の半導体発光素子に関する。   The present invention relates to a semiconductor light emitting device for flip chip mounting.

ウェハーから切り出された半導体発光素子(以後とくに断らない限りLEDダイと呼ぶ)は、しばしば透明絶縁基板上に発光層を含む半導体層を備えた構成をとる。このようなLEDダイを回路基板に実装した半導体発光装置(以後とくに断らない限りLED装置と呼ぶ)では、LEDダイの透明絶縁基板とは反対側の面(以後電極面と呼ぶ)に突起電極を形成し、突起電極を介してLEDダイと回路基板の電極を導電接続するフリップチップ実装(フェイスダウン実装ともいう)が行われることがある。このフリップチップ実装は、ワイヤボンディングを使う実装方法(フェイスアップ実装ともいう)に較べ熱伝導性や発光効率が良いという特徴がある。   A semiconductor light emitting device cut out from a wafer (hereinafter referred to as an LED die unless otherwise specified) often has a configuration in which a semiconductor layer including a light emitting layer is provided on a transparent insulating substrate. In a semiconductor light emitting device in which such an LED die is mounted on a circuit board (hereinafter referred to as an LED device unless otherwise specified), a protruding electrode is provided on the surface of the LED die opposite to the transparent insulating substrate (hereinafter referred to as an electrode surface). In some cases, flip chip mounting (also referred to as face-down mounting) is performed in which the LED die and the electrode of the circuit board are conductively connected through the protruding electrodes. This flip chip mounting is characterized in that it has better thermal conductivity and light emission efficiency than a mounting method using wire bonding (also referred to as face-up mounting).

電極面にn側電極(カソード)とp側電極(アノード)を備えるLEDダイにおいて、n側電極及びその周囲が発光しないため、LEDダイの平面積が小さい場合、n側電極は電極面の角部若しくは辺部に設けられていた。これに対し最近ではLEDダイの平面積が大きくなり、電流を多く流し発光量を増加させるようになってきた。このような状況に対応するには電流分布を均一化することが有効であり、そのひとつの手段としてn側電極を電極面の中央の配置することがある。   In an LED die having an n-side electrode (cathode) and a p-side electrode (anode) on the electrode surface, the n-side electrode and its surroundings do not emit light. It was provided in the part or side. On the other hand, recently, the area of the LED die has been increased, and a large amount of current is supplied to increase the light emission amount. In order to cope with such a situation, it is effective to make the current distribution uniform, and as one means there is a case where the n-side electrode is arranged at the center of the electrode surface.

例えば特許文献1の図1(a)には、電極面の中央にN側電極15、電極面の四隅にp側電極16を備えたLEDチップ10(半導体発光素子)が示されている。特許文献1には電流分布の改善に関する記載はないが、n側電極を電極面の中央に配置し、さらにp電極を対称的に配置すると、電流分布が均一化し大きな電流を流しても輝度向上が図りやすくなる、ということが知られている。また特許文献1の図2にはリードフレームにLEDチップ10をフリップチップ実装した様子が示されている。   For example, FIG. 1A of Patent Document 1 shows an LED chip 10 (semiconductor light emitting element) including an N-side electrode 15 at the center of an electrode surface and p-side electrodes 16 at four corners of the electrode surface. Although there is no description regarding improvement of current distribution in Patent Document 1, if the n-side electrode is arranged at the center of the electrode surface and the p-electrode is arranged symmetrically, the current distribution becomes uniform and the luminance is improved even when a large current flows. Is known to be easier to plan. FIG. 2 of Patent Document 1 shows a state where the LED chip 10 is flip-chip mounted on a lead frame.

特許第3365787号公報 (図1、図2)Japanese Patent No. 3365787 (FIGS. 1 and 2)

特許文献1の図1に示されたLEDダイ(LEDチップ10)のように電極面の中央にn側電極(N側電極15)があり、電極面の四隅にp側電極(P側電極16)があると、LEDダイを実装する回路基板は電極パターンが複雑になる。つまりp側電極が分離しているので、LEDダイを回路基板に実装したときにフリップチップ実装面側の電極パターンにより全てのp側電極を接続しなければならなかったり、p側電極にとり囲まれているn側電極と接続する電極パターンをp側電極と接続する電極パターンから引き出さなければならなかったりする。このように電極パターンが複雑化すると、回路基板が製造しにくくなるばかりでなく、実装が困難になったり回路基板が大型化したりする。   As in the LED die (LED chip 10) shown in FIG. 1 of Patent Document 1, there is an n-side electrode (N-side electrode 15) at the center of the electrode surface, and p-side electrodes (P-side electrode 16) at the four corners of the electrode surface. ), The circuit board on which the LED die is mounted has a complicated electrode pattern. In other words, since the p-side electrodes are separated, all the p-side electrodes must be connected by the electrode pattern on the flip chip mounting surface side when the LED die is mounted on the circuit board, or surrounded by the p-side electrodes. The electrode pattern connected to the n-side electrode must be extracted from the electrode pattern connected to the p-side electrode. When the electrode pattern becomes complicated in this way, not only the circuit board becomes difficult to manufacture, but also the mounting becomes difficult or the circuit board becomes large.

そこで本発明は、この課題を解決するため、n側電極が電極面の中央部にあっても、電流分布が均一で、回路基板の電極パターンを簡単化できる半導体発光素子を提供することを目的とする。   Therefore, in order to solve this problem, an object of the present invention is to provide a semiconductor light emitting device that can provide a uniform current distribution and simplify an electrode pattern of a circuit board even when the n-side electrode is in the center of the electrode surface. And

上記課題を解決するため本発明の半導体発光素子は、n型半導体層及びp型半導体層、並びに前記n型半導体層及び前記p型半導体層と接続するn側電極及びp側電極を備える半導体発光素子において、
長方形の電極面を有し、
前記n側電極及び前記p側電極が前記電極面にそれぞれ一個ずつ配置され、
前記n側電極が前記電極面の中央部にあり、
前記n側電極に対して前記電極面の一方の辺部に前記p側電極があり、
前記n側電極に対して前記電極面の他方の辺部にフローティング電極があり、
前記p側電極に対して前記p型半導体層全体が低い抵抗で接続している
ことを特徴とする。
In order to solve the above problems, a semiconductor light emitting device of the present invention includes an n-type semiconductor layer and a p-type semiconductor layer, and a semiconductor light emitting device including an n-side electrode and a p-side electrode connected to the n-type semiconductor layer and the p-type semiconductor layer. In the element
Having a rectangular electrode surface;
The n-side electrode and the p-side electrode are arranged one by one on the electrode surface,
The n-side electrode is in the center of the electrode surface;
The p-side electrode is on one short side of the electrode surface with respect to the n-side electrode,
There is a floating electrode on the other short side of the electrode surface with respect to the n-side electrode,
The entire p-type semiconductor layer is connected to the p-side electrode with a low resistance.

上記構成の半導体発光素子をフリップチップ実装する回路基板は、フリップチップ実装面側においてp側電極と接続する回路基板の電極パターンがn側電極に対し一方側にだけあれば良い。同様にn側電極と接続する回路基板の電極パターンは、フリップチップ実装面においてn側電極に対し他方側にだけあれば良い。この電極パターンは中央部でn側電極と接続し、さらにフローティング電極とも接続する。このように回路基板のフリップチップ実装面側の電極パターンは一方側と他方側にそれぞれ設ければ良いだけなので形状や配置が簡単になる。このときp側電極とp型半導体層全体は低抵抗接続しているので電流分布が不均一にならない。   The circuit board on which the semiconductor light emitting element having the above-described structure is flip-chip mounted only needs to have the electrode pattern of the circuit board connected to the p-side electrode on the flip chip mounting surface side on one side with respect to the n-side electrode. Similarly, the electrode pattern of the circuit board connected to the n-side electrode need only be on the other side of the n-side electrode on the flip chip mounting surface. This electrode pattern is connected to the n-side electrode at the center, and is also connected to the floating electrode. Thus, since the electrode patterns on the flip chip mounting surface side of the circuit board need only be provided on one side and the other side, the shape and arrangement are simplified. At this time, since the p-side electrode and the entire p-type semiconductor layer are connected with low resistance, the current distribution does not become non-uniform.

前記n側電極及び前記p側電極並びに前記フローティング電極の前記電極面側に反射性金属層を備えていても良い。
A reflective metal layer may be provided on the electrode surface side of the n-side electrode, the p-side electrode , and the floating electrode .

前記n側電極及び前記p側電極並びに前記フローティング電極を電解メッキ法で形成しても良い。
The n-side electrode, the p-side electrode , and the floating electrode may be formed by electrolytic plating.

前記p側電極を配置した前記一方の辺部に、前記フローティング電極とは分離したフローティング電極を配置しても良い。
A floating electrode separated from the floating electrode may be disposed on the one short side where the p-side electrode is disposed.

以上のように本発明の半導体発光素子は、n側電極が電極面の中央部にあっても、電流分布が均一で、且つ回路基板の電極パターンを簡単化する。   As described above, the semiconductor light emitting device of the present invention has a uniform current distribution and simplifies the electrode pattern of the circuit board even when the n-side electrode is at the center of the electrode surface.

本発明の第1実施形態におけるLEDダイの底面図。The bottom view of the LED die in 1st Embodiment of this invention. 図1に示したLEDダイの断面図。Sectional drawing of the LED die | dye shown in FIG. 図1に示したLEDダイから絶縁膜を剥がした状態の底面図。The bottom view of the state which peeled off the insulating film from the LED die | dye shown in FIG. 図1に示したLEDダイを含むLED装置の断面図。Sectional drawing of the LED apparatus containing the LED die shown in FIG. 図4に示したLED装置に含まれる回路基板の上面図。The top view of the circuit board contained in the LED device shown in FIG. 本発明の第2実施形態におけるLEDダイの底面図。The bottom view of the LED die in 2nd Embodiment of this invention.

以下、添付図1〜6を参照しながら本発明の好適な実施形態について詳細に説明する。なお図面の説明において、同一または相当要素には同一の符号を付し、重複する説明は省略する。また説明のため部材の縮尺は適宜変更している。さらに特許請求の範囲に記載した発明特定事項との関係をカッコ内に記載している。
(第1実施形態)
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted. For the sake of explanation, the scale of the members is changed as appropriate. Furthermore, the relationship with the invention specific matter described in the claims is described in parentheses.
(First embodiment)

図1により本発明の第1実施形態におけるLEDダイ20(半導体発光素子)の電極面を説明する。図1は本実施形態のLEDダイ20の底面図である。LEDダイ20を底面側から眺めると、絶縁膜24が占める領域のなかに2個のフローティング電極25、n側
電極26並びにp側電極27が見える。絶縁膜24はn側電極26とp側電極27の周りが開口している。図中、n側電極26は電極面の中央部にあり、n側電極26の周りにn型半導体層22が見える。p側電極27は電極面の右側(一方の辺部)にあり、p側電極27の周りにp型半導体層23が見える。フローティング電極25は電極面の左側(他方の辺部)にある。なおフローティング電極25の詳細については後述する。
The electrode surface of the LED die 20 (semiconductor light emitting device) in the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a bottom view of the LED die 20 of this embodiment. When the LED die 20 is viewed from the bottom side, two floating electrodes 25, an n-side electrode 26, and a p-side electrode 27 can be seen in the region occupied by the insulating film 24. The insulating film 24 is open around the n-side electrode 26 and the p-side electrode 27. In the figure, the n-side electrode 26 is in the center of the electrode surface, and the n-type semiconductor layer 22 is visible around the n-side electrode 26. The p-side electrode 27 is on the right side (one side) of the electrode surface, and the p-type semiconductor layer 23 can be seen around the p-side electrode 27. The floating electrode 25 is on the left side (the other side) of the electrode surface. Details of the floating electrode 25 will be described later.

本実施形態においては、LEDダイ20は、広く普及しているフェイスアップ実装用LEDダイをフェイスダウン実装(フリップチップ実装)用LEDダイに転用したものとして説明する。フェイスアップ実装では回路基板に電極面とは反対側の面をダイボンディングし、絶縁膜24の二つの開口部にAu電極を形成し、それぞれの電極にn側のワイヤボンディング及びp側のワイヤボンディングを行う。本実施形態のLEDダイ20ではこのワイヤボンディング用の電極部にn側電極26及びp側電極27を形成している。なおフェイスアップ実装用LEDダイが連結して配列したウェハーを入手したとき、絶縁膜24の開口部にはワイヤボンディングのためのAu電極が形成されていることがある。この場合、n側電極26及びp側電極27はこのAu電極上に形成するので、n側電極26及びp側電極27の周りではAu電極の一部が見える。   In the present embodiment, the LED die 20 will be described as a widely used face-up mounting LED die converted to a face-down mounting (flip chip mounting) LED die. In face-up mounting, the surface opposite to the electrode surface is die-bonded on the circuit board, Au electrodes are formed in the two openings of the insulating film 24, and n-side wire bonding and p-side wire bonding are applied to the respective electrodes. I do. In the LED die 20 of the present embodiment, an n-side electrode 26 and a p-side electrode 27 are formed on the electrode portion for wire bonding. When a wafer in which LED dies for face-up mounting are connected and arranged is obtained, an Au electrode for wire bonding may be formed in the opening of the insulating film 24 in some cases. In this case, since the n-side electrode 26 and the p-side electrode 27 are formed on the Au electrode, a part of the Au electrode can be seen around the n-side electrode 26 and the p-side electrode 27.

図2においてLEDダイ20の積層構造を説明する。図2は、図1のAA線に沿って描いたLEDダイ20の断面図である。サファイア基板21の下にはn型半導体層22が形成され、さらにn型半導体層22の下にp型半導体層23が形成されている。なお図ではp型半導体層23が分断されているように描かれているが、分断部はp型半導体層23の開口部であり、左右のp型半導体層23は接続している。絶縁膜24は開口部を除きn型半導体層22及びp型半導体層23を被覆している。フローティング電極25は絶縁膜24の下面に接続して形成されている。n側電極26は絶縁膜24及びp型半導体層23の開口部においてn型半導体層22と接続している。p側電極27は金属層28を介して絶縁膜24の開口部においてp型半導体層23と接続している。また金属層28は図3で後述するようにp型半導体層23の周辺部に敷設されており、図2の左側ではp型半導体層23に下に一部分が現れている。   The stacked structure of the LED die 20 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the LED die 20 drawn along the line AA in FIG. An n-type semiconductor layer 22 is formed under the sapphire substrate 21, and a p-type semiconductor layer 23 is formed under the n-type semiconductor layer 22. In the drawing, the p-type semiconductor layer 23 is illustrated as being divided, but the divided portion is an opening of the p-type semiconductor layer 23 and the left and right p-type semiconductor layers 23 are connected. The insulating film 24 covers the n-type semiconductor layer 22 and the p-type semiconductor layer 23 except for the opening. The floating electrode 25 is formed so as to be connected to the lower surface of the insulating film 24. The n-side electrode 26 is connected to the n-type semiconductor layer 22 in the openings of the insulating film 24 and the p-type semiconductor layer 23. The p-side electrode 27 is connected to the p-type semiconductor layer 23 at the opening of the insulating film 24 through the metal layer 28. As will be described later with reference to FIG. 3, the metal layer 28 is laid on the periphery of the p-type semiconductor layer 23, and a part of the metal layer 28 appears below the p-type semiconductor layer 23 on the left side of FIG. 2.

サファイア基板21は透明絶縁基板であり厚さが80〜120μmである。n型半導体層22はGaNバッファ層とn型GaN層からなり厚さが5μm程度である。p型半導体層23は、透明電極層などを含む金属多層膜とp型GaN層からなり厚みが1μm程度である。図示していないが発光層はp型半導体層23とn型半導体層22の境界部にあり、平面形状はp型半導体層23とほぼ等しい。絶縁膜24はSiO2やポリイミドからなり厚さが数100nm〜1μm程度である。フローティング電極25、n側電極26並びにp側電極27はAu又はCuをコアとするバンプであり、電解メッキ法で形成し厚さが10〜30μm程度である。なお電解メッキ法において高反射アルミ層、TiW層並びにAu層を順に積層した共通電極を使用しているので、フローティング電極25、n側電極26並びにp側電極27は電極面側に反射層を備えている。金属配線28はAuからなり、厚さは数100nmである。   The sapphire substrate 21 is a transparent insulating substrate and has a thickness of 80 to 120 μm. The n-type semiconductor layer 22 is composed of a GaN buffer layer and an n-type GaN layer and has a thickness of about 5 μm. The p-type semiconductor layer 23 includes a metal multilayer film including a transparent electrode layer and the like and a p-type GaN layer, and has a thickness of about 1 μm. Although not shown, the light emitting layer is at the boundary between the p-type semiconductor layer 23 and the n-type semiconductor layer 22, and the planar shape is substantially the same as that of the p-type semiconductor layer 23. The insulating film 24 is made of SiO2 or polyimide and has a thickness of about several hundred nm to 1 [mu] m. The floating electrode 25, the n-side electrode 26 and the p-side electrode 27 are bumps having Au or Cu as a core, and are formed by electrolytic plating and have a thickness of about 10 to 30 μm. In the electrolytic plating method, since a common electrode in which a highly reflective aluminum layer, a TiW layer, and an Au layer are sequentially laminated is used, the floating electrode 25, the n-side electrode 26, and the p-side electrode 27 have a reflective layer on the electrode surface side. ing. The metal wiring 28 is made of Au and has a thickness of several hundred nm.

図3においてLEDダイ20の電極面をさらに詳しく説明する。図3はLEDダイ20の電極面からフローティング電極25、n側電極26、p側電極27並びに絶縁膜24を取り去った状態の底面図である。n型半導体層22の内側にp型半導体層23があり、さらにn型半導体層22は中央部のp型半導体層23の開口部からも見える。図の右側においてp側電極27(図2参照)のあった場所からp型半導体層23の辺に沿って金属配線28が延びている。金属配線28は透明電極(図示せず)を介してp型GaN層とオーミック接続しており、p型半導体層23の端部まで低抵抗で電流が流れるように機能する。すなわち金属によりp型半導体層23の周辺部とp側電極とが接続することで、p側電極27に対してp型半導体層23全体が低い抵抗で接続する。   In FIG. 3, the electrode surface of the LED die 20 will be described in more detail. FIG. 3 is a bottom view of the LED die 20 with the floating electrode 25, the n-side electrode 26, the p-side electrode 27, and the insulating film 24 removed. There is a p-type semiconductor layer 23 inside the n-type semiconductor layer 22, and the n-type semiconductor layer 22 is also visible from the opening of the central p-type semiconductor layer 23. On the right side of the drawing, a metal wiring 28 extends along the side of the p-type semiconductor layer 23 from the place where the p-side electrode 27 (see FIG. 2) is located. The metal wiring 28 is in ohmic contact with the p-type GaN layer via a transparent electrode (not shown), and functions so that a current flows to the end of the p-type semiconductor layer 23 with a low resistance. That is, by connecting the peripheral portion of the p-type semiconductor layer 23 and the p-side electrode with metal, the entire p-type semiconductor layer 23 is connected to the p-side electrode 27 with a low resistance.

前述したようにLEDダイ20はフェイスアップ実装用のLEDダイをフリップチップ実装用に転用したものであった。LED20のもととなったLEDダイをフェイスアップ実装した場合、p型半導体層23側に光が出射する。このためp型半導体層23表面には透明電極が形成され、さらに光の出射の大きな影響を与えないように低抵抗化のため細い金属配線28を設けていた。しかしながら本発明のLEDダイにおける低抵抗化は金属配線だけに限られない。例えば透明電極を低抵抗化してもよい。またLEDダイをフリップチップ専用に設計できれば、p型半導体層に反射層などさまざまな目的で金属層を積層できるので、この金属層によりp型半導体層全体に亘って抵抗を低くできる。   As described above, the LED die 20 is obtained by diverting an LED die for face-up mounting for flip chip mounting. When the LED die that is the basis of the LED 20 is mounted face up, light is emitted to the p-type semiconductor layer 23 side. For this reason, a transparent electrode is formed on the surface of the p-type semiconductor layer 23, and a thin metal wiring 28 is provided in order to reduce resistance so as not to have a large influence on light emission. However, the reduction in resistance in the LED die of the present invention is not limited to metal wiring. For example, the resistance of the transparent electrode may be reduced. Also, if the LED die can be designed exclusively for flip chip, a metal layer can be laminated on the p-type semiconductor layer for various purposes such as a reflective layer, and this metal layer can reduce the resistance over the entire p-type semiconductor layer.

図4においてLEDダイ20を含むLED装置30(半導体発光装置)について説明する。図4はLED装置30の断面図である。LEDダイ20は回路基板38にフリップチップ実装されている。フローティング電極25及びn側電極26は回路基板38の上面に形成された内部接続電極32(他方の電極パターン)と接続し、p側電極27は回路基板38の上面に形成された内部接続電極35(一方の電極パターン)と接続している。内部接続電極32,35はそれぞれスルーホール電極33,36を介して外部接続電極34,37と接続している。回路基板38の上面及びLEDダイ20の周囲は蛍光樹脂31で被覆されている。内部接続電極32,35及び外部接続電極34,37は、表面にNi,Au層を備え厚さが数μm〜数10μmの銅箔である。スルーホール電極33,36は直径が100〜300μm程度のスルーホールに金属ペーストを充填している。なお輝度向上を図る場合、内部接続電極32,35は表面にAg等の反射率の高い金属層を備えると良い。   The LED device 30 (semiconductor light emitting device) including the LED die 20 will be described with reference to FIG. FIG. 4 is a cross-sectional view of the LED device 30. The LED die 20 is flip-chip mounted on the circuit board 38. The floating electrode 25 and the n-side electrode 26 are connected to an internal connection electrode 32 (the other electrode pattern) formed on the upper surface of the circuit board 38, and the p-side electrode 27 is an internal connection electrode 35 formed on the upper surface of the circuit board 38. (One electrode pattern) is connected. The internal connection electrodes 32 and 35 are connected to external connection electrodes 34 and 37 through through-hole electrodes 33 and 36, respectively. The upper surface of the circuit board 38 and the periphery of the LED die 20 are covered with a fluorescent resin 31. The internal connection electrodes 32 and 35 and the external connection electrodes 34 and 37 are copper foils having Ni and Au layers on the surfaces and a thickness of several μm to several tens of μm. The through-hole electrodes 33 and 36 are filled with metal paste in through-holes having a diameter of about 100 to 300 μm. In addition, when aiming at a brightness improvement, it is good for the internal connection electrodes 32 and 35 to provide the metal layer with high reflectances, such as Ag, on the surface.

次に図5により回路基板38の上面(フリップチップ実装面)を説明する。図5はLED装置30に含まれる回路基板38の上面図である。回路基板38の内側には矩形の内部接続電極32,35が形成されている。図4に示したように内部接続電極32にはフローティング電極25とn側電極26が接続し、内部接続電極35にはp側電極27が接続する。   Next, the upper surface (flip chip mounting surface) of the circuit board 38 will be described with reference to FIG. FIG. 5 is a top view of the circuit board 38 included in the LED device 30. Inside the circuit board 38, rectangular internal connection electrodes 32 and 35 are formed. As shown in FIG. 4, the floating electrode 25 and the n-side electrode 26 are connected to the internal connection electrode 32, and the p-side electrode 27 is connected to the internal connection electrode 35.

このフローティング電極25は、フリップチップ実装時にLEDダイ20へ圧力を掛けたとき、LEDダイ20が傾かないように支持する。また発光層の発する熱の一部をp型半導体層23、絶縁膜24及びフローティング電極25からなる経路で回路基板14の内部接続電極32に放出する。さらにフローティング電極25はLEDダイ20と回路基板14の接続を強固なものにする。これらの機能を達成するだけならフローティング電極はp型半導体層23が占める領域に沿って形成すれば良い。しかしながら回路基板14の内部接続電極32を簡単な形状とするためには、例えば図1ならn側電極26より左側に形成しなければならない。   The floating electrode 25 supports the LED die 20 so that it does not tilt when pressure is applied to the LED die 20 during flip-chip mounting. Further, part of heat generated by the light emitting layer is released to the internal connection electrode 32 of the circuit board 14 through a path including the p-type semiconductor layer 23, the insulating film 24, and the floating electrode 25. Further, the floating electrode 25 strengthens the connection between the LED die 20 and the circuit board 14. In order to achieve these functions, the floating electrode may be formed along the region occupied by the p-type semiconductor layer 23. However, in order to make the internal connection electrode 32 of the circuit board 14 in a simple shape, it must be formed on the left side of the n-side electrode 26 in FIG.

また図2等で示しているようにn側電極26は絶縁膜24の角部から離れている。この絶縁膜24の角部はクラックが入っていたりピンホールがあったりする。すなわちLEDダイ20は、n側電極26が絶縁膜24の角部から離れているため、絶縁膜24のクラックやピンホールによるp型半導体層23とn型半導体層22のショートを防止している。
(第2実施形態)
As shown in FIG. 2 and the like, the n-side electrode 26 is separated from the corner of the insulating film 24. The corners of the insulating film 24 are cracked or have pinholes. That is, the LED die 20 prevents the p-type semiconductor layer 23 and the n-type semiconductor layer 22 from being short-circuited due to cracks or pinholes in the insulating film 24 because the n-side electrode 26 is separated from the corner of the insulating film 24. .
(Second Embodiment)

図1に示したLEDダイ20においてフローティング電極25の平面形状は円形であった。しかしながらフローティング電極の平面形状は円形に限られない。また実装時の水平バランスをとるには少なくともp側電極とは反対側の辺部にフローティング電極があれば良いので、追加的なフローティング電極をp側電極の近傍に配置しても良い。そこでフローティング電極の変形例として図6により本発明の第2実施形態におけるLEDダイ60(半導体発光素子)の電極面を説明する。   In the LED die 20 shown in FIG. 1, the floating electrode 25 has a circular planar shape. However, the planar shape of the floating electrode is not limited to a circle. Further, in order to achieve a horizontal balance at the time of mounting, it is sufficient that a floating electrode is provided at least on the side opposite to the p-side electrode. Therefore, an additional floating electrode may be disposed in the vicinity of the p-side electrode. Therefore, as a modification of the floating electrode, an electrode surface of the LED die 60 (semiconductor light emitting element) in the second embodiment of the present invention will be described with reference to FIG.

図6はLEDダイ60の底面図である。LEDダイ60の電極面には、絶縁膜24の内側にn側電極26、p側電極27、フローティング電極61,62,63がある。図1のLEDダイ20の電極面と同様に、LEDダイ60の電極面の中央部にn側電極26、右側(一方の辺部)にp側電極27があり、絶縁膜24の開口部においてn側電極26及びp側電極27の周囲にn型半導体層22及びp型半導体層23が見える。フローティング電極61は電極面の左側(他方の辺部)にあり、コの字型で大きな面積を占めている。さらに電極面の右側にはp側電極27と並ぶようにフローティング電極62,63がある。n側電極26、p側電極27、フローティング電極61,62,63は図1のLEDダイ20と同様にメッキバンプである。すなわちLEDダイ60はLEDダイ20と同じLEDダイ(バンプ形成前)に、同じ形状のn側電極26及びp側電極27を形成するとともに、異なった形状のフローティング電極61,62,63を形成したものである。またこのLEDダイ60は回路基板38(図4,5参照)にフリップチップ実装することができ、このとき内部接続電極32にはn側電極26とともにフローティング電極61が接続し、内部接続電極35にはp側電極27とともにフローティング電極62,63が接続する。   FIG. 6 is a bottom view of the LED die 60. On the electrode surface of the LED die 60, there are an n-side electrode 26, a p-side electrode 27, and floating electrodes 61, 62, 63 inside the insulating film 24. Similar to the electrode surface of the LED die 20 in FIG. 1, there is an n-side electrode 26 at the center of the electrode surface of the LED die 60, a p-side electrode 27 on the right side (one side), and an opening in the insulating film 24. The n-type semiconductor layer 22 and the p-type semiconductor layer 23 can be seen around the n-side electrode 26 and the p-side electrode 27. The floating electrode 61 is on the left side (the other side) of the electrode surface and has a U-shape and occupies a large area. Further, floating electrodes 62 and 63 are arranged on the right side of the electrode surface so as to be aligned with the p-side electrode 27. The n-side electrode 26, the p-side electrode 27, and the floating electrodes 61, 62, and 63 are plated bumps as in the LED die 20 of FIG. That is, in the LED die 60, the n-side electrode 26 and the p-side electrode 27 having the same shape are formed on the same LED die (before bump formation) as the LED die 20, and the floating electrodes 61, 62, 63 having different shapes are formed. Is. The LED die 60 can be flip-chip mounted on the circuit board 38 (see FIGS. 4 and 5). At this time, the floating electrode 61 is connected to the internal connection electrode 32 together with the n-side electrode 26, and the internal connection electrode 35 is connected to the internal connection electrode 35. Are connected to the floating electrodes 62 and 63 together with the p-side electrode 27.

フローティング電極61を大きくし、さらにフローティング電極62,63を追加した主な目的は、LEDダイの放熱特性の改善と輝度の向上である。LEDダイ60は主に発光層で発熱するため、発光層と積層するp型半導体層23(図2,3参照)は回路基板38(図4,5参照)との間に大きな面積で熱伝導性の良い放熱経路を必要とする。フローティング電極61,62,63は、大きな面積を持ち、金属からなるため熱伝導性も良好であるので優れた放電経路となる。またフローティング電極61,62,63は、フローティング電極25と同様に電極面側に反射層を備えており、広い面積を占めていることからLEDダイ60の発光効率を向上させることができる。   The main purpose of enlarging the floating electrode 61 and adding the floating electrodes 62 and 63 is to improve the heat dissipation characteristics and brightness of the LED die. Since the LED die 60 generates heat mainly in the light emitting layer, the p-type semiconductor layer 23 (see FIGS. 2 and 3) laminated with the light emitting layer has a large area between the circuit board 38 (see FIGS. 4 and 5) and conducts heat. A good heat dissipation path is required. Since the floating electrodes 61, 62, and 63 have a large area and are made of metal, they have a good thermal conductivity, and thus become an excellent discharge path. Further, the floating electrodes 61, 62, and 63 have a reflective layer on the electrode surface side like the floating electrode 25, and occupy a wide area, so that the light emission efficiency of the LED die 60 can be improved.

第1実施形態のLED20及び第2実施形態のLED60ではp側電極27が円形であった。p側電極の形状も円形に限定されず、例えば絶縁膜24のp側の開口部が長円形であれば、長円形のp側電極を形成しても良い。

In the LED 20 of the first embodiment and the LED 60 of the second embodiment, the p-side electrode 27 was circular. The shape of the p-side electrode is not limited to a circle. For example, if the opening on the p-side of the insulating film 24 is an oval, an oval p-side electrode may be formed.

20,60…LEDダイ(半導体発光素子)、
21…サファイア基板、
22…n型半導体層、
23…p型半導体層、
24…絶縁膜、
25,61,62,63…フローティング電極、
26…n側電極、
27…p側電極、
28…金属配線、
30…LED装置(半導体発光装置)、
31…蛍光樹脂、
32,35…内部接続電極(電極パターン)、
33,36…スルーホール電極、
34,37…外部接続電極、
38…回路基板。
20, 60 ... LED die (semiconductor light emitting element),
21 ... sapphire substrate,
22 ... n-type semiconductor layer,
23 ... p-type semiconductor layer,
24. Insulating film,
25, 61, 62, 63 ... floating electrodes,
26 ... n-side electrode,
27 ... p-side electrode,
28 ... Metal wiring,
30 ... LED device (semiconductor light emitting device),
31 ... Fluorescent resin,
32, 35 ... internal connection electrodes (electrode patterns),
33, 36 ... through-hole electrodes,
34, 37 ... external connection electrodes,
38. Circuit board.

Claims (4)

n型半導体層及びp型半導体層、並びに前記n型半導体層及び前記p型半導体層と接続するn側電極及びp側電極を備える半導体発光素子において、
長方形の電極面を有し、
前記n側電極及び前記p側電極が前記電極面にそれぞれ一個ずつ配置され、
前記n側電極が前記電極面の中央部にあり、
前記n側電極に対して前記電極面の一方の辺部に前記p側電極があり、
前記n側電極に対して前記電極面の他方の辺部にフローティング電極があり、
前記p側電極に対して前記p型半導体層全体が低い抵抗で接続している
ことを特徴とする半導体発光素子。
In a semiconductor light emitting device comprising an n-type semiconductor layer and a p-type semiconductor layer, and an n-side electrode and a p-side electrode connected to the n-type semiconductor layer and the p-type semiconductor layer,
Having a rectangular electrode surface;
The n-side electrode and the p-side electrode are arranged one by one on the electrode surface,
The n-side electrode is in the center of the electrode surface;
The p-side electrode is on one short side of the electrode surface with respect to the n-side electrode,
There is a floating electrode on the other short side of the electrode surface with respect to the n-side electrode,
The semiconductor light-emitting element, wherein the entire p-type semiconductor layer is connected to the p-side electrode with a low resistance.
前記n側電極及び前記p側電極並びに前記フローティング電極の前記電極面側に反射性金属層を備えていることを特徴とする請求項1に記載の半導体発光素子。 The semiconductor light emitting element according to claim 1, further comprising a reflective metal layer on the electrode surface side of the n-side electrode, the p-side electrode , and the floating electrode . 前記n側電極及び前記p側電極並びに前記フローティング電極を電解メッキ法で形成することを特徴とする請求項に記載の半導体発光素子。 3. The semiconductor light emitting device according to claim 2 , wherein the n-side electrode, the p-side electrode , and the floating electrode are formed by an electrolytic plating method. 前記p側電極を配置した前記一方の辺部に、前記フローティング電極とは分離したフローティング電極を配置したことを特徴とする請求項1からのいずれか一項に記載の半導体発光素子。
Wherein the one short side portion disposed p-side electrode, the semiconductor light-emitting device according to any one of claims 1 to 3, wherein the floating electrode, characterized in that a floating electrode separated.
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