JP5757857B2 - Correction method of wiring board machining position - Google Patents

Description

  The present invention relates to a method for correcting a processing position of a wiring board.

  Conventionally, there has been a method of manufacturing a wiring board in which a positional deviation amount of an alignment mark with respect to an alignment hole is measured and a via hole is formed using positional coordinate data obtained by correcting the expansion and contraction and distortion of the board with a value half the positional deviation amount. It was.

JP 2008-078464 A

  However, since the conventional method of manufacturing a wiring board corrects the expansion and contraction and distortion of the board with a value that is half of the positional displacement amount of the alignment mark with respect to the alignment hole, the half value of the positional displacement amount is an allowable value for via misalignment. If it exceeds, wiring defects will occur.

  Specifically, for example, if the half value of the positional deviation amount exceeds the allowable value of the positional deviation between the via and the pad, there is a possibility that the pad and the via are not connected. When the pad and the via are not connected, there is a problem that the wiring board is defective.

  Accordingly, an object of the present invention is to provide a method for correcting a processing position of a wiring board in which wiring defects are suppressed.

  A method for correcting a processing position of a wiring board according to an embodiment of the present invention includes a first quadrilateral determined by positions of four alignment marks formed at four corners of a surface of a wiring board formed by laminating insulating layers; A first step of obtaining an average angle difference between corresponding sides of the second quadrilateral determined by the position of the alignment mark in the design data; each side of the first quadrilateral and each of the second quadrilateral A second step of rotating the first quadrilateral or the second quadrangle by the average angular difference so that the angular difference with the side becomes small, and the first quadrangle and the second quadrangle correspond to each other. A third step of obtaining an average distance difference between the vertices, and a step of moving the first quadrilateral or the second quadrilateral by the average distance difference so that the first quadrangle and the second quadrangle are close to each other. 4 steps and each top of the first quadrilateral The four lines that pass through the inside of four circles whose radius is the tolerance of a via formed in the wiring board centering on the wiring board, are parallel to the sides of the second quadrilateral, and are closest to the sides of the second quadrilateral. In a fifth step of determining the straight line, a sixth step of determining whether or not four intersections of the four straight lines are within four circles having a radius of the tolerance of the via, and a sixth step A size of the third quadrilateral determined by the four intersections determined to be within four circles having a radius of the tolerance of the via, a shape with respect to a reference position of the third quadrilateral, and the second quadrilateral And a seventh step of correcting the processing position of the circuit pattern included in the design data on the wiring board based on the difference between the size of the second quadrilateral and the shape with respect to the reference position.

  It is possible to provide a method for manufacturing a wiring board that can be manufactured at a low cost, and a structure for a wiring board.

It is a figure which shows the wiring board to which the correction method of the processing position of the wiring board of embodiment is applied. It is a figure which shows the wiring board to which the correction method of the processing position of the wiring board of embodiment is applied. It is process drawing which shows the process of the correction method of the processing position of the wiring board of embodiment. It is a figure which shows the process of calculating | requiring the angle difference of each edge | side of a 1st quadrangle and a 2nd quadrangle in step S1 of the correction method of the process position of the wiring board of embodiment. In the correction method of the processing position of the wiring board of an embodiment, it is a figure showing an example of processing which moves the 2nd quadrangle by average distance difference. It is a figure which shows the process of step S2 in the correction method of the processing position of the wiring board of embodiment. It is a figure which shows the method of calculating | requiring four straight lines in step S2 of the correction method of the processing position of the wiring board of Embodiment 1. FIG.

  Hereinafter, an embodiment to which a method for correcting a processing position of a wiring board according to the present invention is applied will be described.

  1A and 1B are diagrams illustrating a wiring board to which a method for correcting a processing position of a wiring board according to an embodiment is applied, in which FIG. 1A is a cross-sectional view and FIG. 1B is a plan perspective view. FIG. 1A shows a cross section taken along the line AA in FIG.

  As shown in FIG. 1A, the build-up substrate 100 includes a core substrate 110, vias 111A and 111B, wiring layers 120A and 120B, insulating layers 121, vias 122A and 122B, wiring layers 130A, 130B, 130C, and 130D. Alignment marks 131A and 131B and an insulating layer 132 are included.

  The build-up substrate 100 further includes wiring layers 140A and 140B, an insulating layer 141, vias 142A and 142B, wiring layers 150A, 150B, 150C and 150D, and an insulating layer 151 on the lower side of the core substrate 110.

  The build-up substrate 100 is an example of a wiring substrate to which the method for correcting a processing position of the wiring substrate according to the embodiment is applied. Note that here, the term “upper and lower” represents the upper and lower sides in the cross-sectional structure illustrated in FIG. 1A and does not represent a universal vertical positional relationship.

  As the core substrate 110, for example, a glass cloth base material impregnated with an epoxy resin can be used.

  The vias 111A and 111B are formed inside via holes that penetrate the core substrate 110 in the thickness direction. The via hole may be formed by, for example, laser processing or drill processing.

  The vias 111A and 111B may be formed on the inner wall of the via hole penetrating the core substrate 110 in the thickness direction or may be formed so as to fill the inside of the via hole.

  For example, the formation of the vias 111A and 111B by the semi-additive method is as follows, for example. A seed layer is formed on the inner wall of the via hole of the core substrate 110 by electroless copper plating or sputtering, and a plating resist pattern having an opening in the shape of a wiring pattern is formed on the seed layer. Next, copper plating to be vias 111A and 111B is deposited in the via holes by copper electroplating using the seed layer as a power feeding layer. Next, the plating resist is removed, and the seed layer is removed, thereby forming the vias 111A and 111B.

  The wiring layers 120A and 120B are formed on the upper surface of the core substrate 110, and the lower surface side is connected to the vias 111A and 111B. The wiring layers 120 </ b> A and 120 </ b> B are covered with the insulating layer 121 on the upper surface side and connected to the vias 122 </ b> A and 122 </ b> B that penetrate the insulating layer 121.

  The wiring layers 120 </ b> A and 120 </ b> B are first layers on the upper side of the core substrate 110. The wiring layers 120A and 120B are, for example, copper foils and may be formed by a plating process using a resist.

  The insulating layer 121 is formed so as to cover the upper surface of the core substrate 110 and the upper surfaces of the wiring layers 120A and 120B, and the via 122A and the via 122A are formed in part of the upper surfaces of the wiring layers 120A and 120B. 122B is formed.

  The insulating layer 121 is produced, for example, by making a film-like epoxy resin or polyimide resin into a semi-cured resin film, and heating and pressurizing and curing the semi-cured resin film with a vacuum laminator. After that, via holes penetrating to the upper surfaces of the wiring layers 120A and 120B are formed, and vias 122A and 122B are formed inside the via holes.

  The vias 122A and 122B are formed inside via holes that penetrate the insulating layer 121 in the thickness direction, and the lower surfaces thereof are connected to the upper surfaces of the wiring layers 120A and 120B, respectively. The upper surfaces of the vias 122A and 122B are connected to the wiring layers 130A and 130D, respectively.

  The vias 122A and 122B are formed by, for example, copper plating. The vias 122A and 122B may be formed, for example, by a plating process for forming wiring layers 130A, 130B, 130C, and 130D described later.

  The wiring layers 130A, 130B, 130C, and 130D are formed on the upper surface of the insulating layer 121, respectively. Among these, the wiring layers 130A and 130D are connected to the vias 122A and 122B, respectively. The upper surfaces of the wiring layers 130A, 130B, 130C, and 130D are covered with an insulating layer 132.

  The wiring layers 130A, 130B, 130C, and 130D are second layers on the upper side of the core substrate 110.

  The wiring layers 130A, 130B, 130C, and 130D may be formed of, for example, copper foil. The wiring layers 130A, 130B, 130C, 130D may be formed by, for example, via 122A, 122B plating.

  The alignment marks 131 </ b> A and 131 </ b> B are formed at the end of the upper surface of the insulating layer 121 and are covered with the insulating layer 132. The alignment marks 131A and 131B are used for positioning a processing position when a via hole is formed in the insulating layer 132.

  FIG. 1A shows only the alignment marks 131A and 131B included in the second layer on the upper side of the core substrate 110 as in the case of the wiring layers 130A to 130D, but in reality, the via holes for forming the vias 122A and 122B are shown. An alignment mark used for positioning the processing position is formed by the first layer on the upper side of the core substrate 110 in the same manner as the wiring layers 120A and 120B.

  The alignment marks 131A and 131B are formed so as to be positioned at the four corners of the build-up substrate 100 in plan view together with alignment marks 131C and 131D (see FIG. 1B) described later.

  The alignment marks 131A to 131D are formed by patterning the second layer copper foil on the upper side of the core substrate 110 together with the wiring layers 130A, 130B, 130C, and 130D.

  The insulating layer 132 is formed so as to cover the upper surfaces of the insulating layer 121, the wiring layers 130A to 130D, and the alignment marks 131A and 131B.

  The wiring layers 140A and 140B are formed on the lower surface of the core substrate 110, and the upper surface side is connected to the vias 111A and 111B. The wiring layers 140 </ b> A and 140 </ b> B are covered with the insulating layer 141 on the lower surface side and connected to the vias 142 </ b> A and 142 </ b> B that penetrate the insulating layer 141.

  The wiring layers 140 </ b> A and 140 </ b> B are first layers on the lower side of the core substrate 110.

  The wiring layers 140A and 140B are, for example, copper foils and may be formed by a plating process using a resist.

  The insulating layer 141 is formed so as to cover the lower surface of the core substrate 110 and the lower surfaces of the wiring layers 140A and 140B, and the via 142A and the via 142A are formed in a part of the lower surface of the wiring layers 140A and 140B. 142B is formed.

  The insulating layer 141 is produced, for example, by making a film-like epoxy resin or polyimide resin into a semi-cured resin film, and heating and pressurizing and curing the semi-cured resin film with a vacuum laminator. After that, via holes that penetrate to the lower surfaces of the wiring layers 140A and 140B are formed, and vias 142A and 142B are formed inside the via holes.

  The vias 142A and 142B are formed inside via holes that penetrate the insulating layer 141 in the thickness direction, and the upper surfaces thereof are connected to the lower surfaces of the wiring layers 140A and 140B, respectively. The lower surfaces of the vias 142A and 142B are connected to the wiring layers 150B and 150C, respectively.

  The vias 142A and 142B are formed by, for example, copper plating. The vias 142A and 142B may be formed by, for example, a plating process for forming wiring layers 150A, 150B, 150C, and 150D described later.

  The wiring layers 150A, 150B, 150C, and 150D are formed on the lower surface of the insulating layer 141, respectively. Among these, the wiring layers 150B and 150C are connected to the vias 142A and 142B, respectively. The lower surfaces of the wiring layers 150A, 150B, 150C, and 150D are covered with an insulating layer 151.

  The wiring layers 150A, 150B, 150C, and 150D are second layers on the lower side of the core substrate 110.

  The wiring layers 150A, 150B, 150C, and 150D may be formed by a plating process together with the vias 142A and 142B, for example.

  The insulating layer 151 is formed so as to cover the lower surface of the insulating layer 141, the wiring layers 150A to 150D, and the alignment marks 131A and 131B.

  FIG. 1B is a perspective view of wiring layers 120A to 120F, wiring layers 130A to 130L, and alignment marks 131A to 131D that are formed above the core substrate 110 of the build-up substrate 100 according to the embodiment. It is.

  In FIG. 1B, of the components formed above the core substrate 100, the vias 111A and 111B are not shown, and the wiring layers 120A to 120F, the wiring layers 130A to 130L, and the planes of the alignment marks 131A to 131D are omitted. Typical patterns are indicated by broken lines.

  The wiring layers 120A to 120F, the wiring layers 130A to 130L, and the alignment marks 131A to 131D are patterned as shown in FIG.

  Here, the wiring layer 130A is connected to the wiring layer 120A by a via 122A (see FIG. 1A). However, the via 122A is smaller than the wiring layer 130A in a plan view, and therefore the via 122A in FIG. I can't see. Similarly, the wiring layer 130D is connected to the wiring layer 120B by a via 122B (see FIG. 1A). However, the via 122B is smaller than the wiring layer 130B in a plan view, and thus the via 122B in FIG. I can't see. Note that the wiring layers 130A and 130B are not connected (see FIG. 1A), and the wiring layers 130C and 130D are not connected (see FIG. 1A).

  In addition, the wiring layers 120C to 120F and the wiring layers 130E to 130L are connected by vias (not shown) at any point overlapping in plan view, like the wiring layers 120A and 120B and the wiring layers 130A to 130D. Also good.

  Next, a process for forming a via hole for forming a via in the insulating layer 132 of the buildup substrate 100 will be described with reference to FIG.

  2A and 2B are diagrams illustrating a wiring board to which the method for correcting a processing position of the wiring board according to the embodiment is applied, in which FIG. 2A is a cross-sectional view and FIG. 2B is a plan perspective view. FIG. 2A shows a cross section taken along line AA in FIG.

  Via holes 133A to 133F are formed in the build-up substrate 100 shown in FIG.

  As shown in FIGS. 2A and 2B, the via hole 133A penetrates the insulating layer 132 in the thickness direction and reaches the upper surface of the wiring 130B. The via hole 133A is formed to form a via connected to the wiring layer 130B.

  The via hole 133B penetrates the insulating layer 132 in the thickness direction and reaches the upper surface of the wiring 130C. The via hole 133B is formed to form a via connected to the wiring layer 130B.

  The via holes 133A and 133B may be formed by laser processing using a via processing machine, for example. The via holes 133A and 133B have a shape in which the wiring layers 130B and 130C are bottom surfaces and have openings on the surface of the insulating layer 132, for example, a truncated cone having a larger diameter on the opening side than the opening on the bottom surface side. It has a cross section in shape.

  Similarly, the via holes 133C to 133F penetrate the insulating layer 132 in the thickness direction, and reach the upper surfaces of the wirings 130E, 130G, 130I, and 130K. The via holes 133C to 133F are formed to form vias connected to the wiring layers 130E, 130G, 130I, and 130K.

  The via holes 133C to 133F may be formed by, for example, laser processing using a via processing machine. Each of the via holes 133C to 133F has a shape having the wiring layers 130E, 130G, 130I, and 130K as the bottom surface and an opening on the surface of the insulating layer 132. For example, the via hole 133C to 133F has a diameter closer to the opening than the opening on the bottom surface side. It has a large, frustoconical cross section.

  When such via holes 133A to 133F are formed by the via processing machine, the alignment marks 131A are formed in order to form the via holes 133A to 133F on the upper surfaces of the wiring layers 130B, 130C, 130E, 130G, 130I, and 130K, respectively. Alignment is performed using ~ 131D.

  For this reason, the positions of the via holes 133A to 133F in the design data are determined in relation to the positions of the alignment marks 131A to 131D in the design data.

  The positions of the alignment marks 131 </ b> A to 131 </ b> D are detected as coordinate values with respect to a predetermined origin by, for example, photographing the build-up substrate 100 from the upper surface side with a detection device including an infrared camera and performing image processing such as pattern recognition. . The predetermined origin may be an origin in the same coordinate system as the processing stage of the via processing machine that processes the via holes 133A to 133F later, for example.

  However, in the process of manufacturing the build-up substrate 100, after forming the wiring layers 120A to 120F on the core substrate 110, a semi-cured resin film is heated and pressurized with a vacuum laminator and laminated and cured. Thus, the insulating layer 121 is formed.

  Similarly, after the wiring layers 130A to 130L and the alignment marks 131A to 131D are formed on the insulating layer 121, the semi-cured resin film is laminated by heating and pressing with a vacuum laminator and cured. Form.

  The same applies to the wiring layers 140A and 140B, the insulating layer 141, the wiring layers 150A to 150D, the insulating layer 151, and the like formed below the core substrate 110.

  Thus, by performing heating and pressurizing in the process of manufacturing the build-up substrate 100, the build-up substrate 100 is repeatedly expanded and contracted to be deformed. Therefore, the positions of the alignment marks 131A to 131D are determined by design values. It may be out of position.

  If the positions of the alignment marks 131A to 131D are greatly displaced, there is a case where the contact between the via holes 133A to 133F and the wiring layers 130B, 130C, 130E, 130G, 130I, and 130K cannot be obtained.

  For this reason, in the method for correcting the processing position of the wiring board according to the present embodiment, the positions at which the via holes 133A to 133F are processed are corrected as follows.

  FIG. 3 is a process diagram illustrating a process of the correction method of the processing position of the wiring board according to the embodiment.

  The method for correcting the processing position of the wiring board according to the present embodiment roughly includes the following five steps.

  First, the alignment mark is detected by a detection device including an infrared camera, and the position and size of the first quadrangle formed by the four alignment marks and the second quadrangle formed by the corresponding four alignment marks included in the design data. And the second quadrilateral is moved closer to the first quadrilateral (step S1).

  Since the position of the via hole in the design data (processing position) is defined on the same coordinates as the position of the alignment mark in the design data, the position where the via hole is processed by this step S1 is a detection device including an infrared camera. It is moved in accordance with the detected positional deviation of the four alignment marks.

  Next, it passes through the inside of four circles centered on each vertex of the first quadrangle and has a radius of via tolerance, and is parallel to each side of the second quadrangle and closest to each side of the second quadrangle 4 A straight line of the book is obtained (step S2).

  Then, it is determined whether or not the four intersections of the four straight lines are inside the four circles whose radius is the tolerance of the via centered on each vertex of the first quadrilateral (step S3).

  In step S3, when the four intersections of the four straight lines are inside the four circles having the radius of the tolerance of the via centered on each vertex of the first quadrilateral, the size of the third quadrangle determined by the four intersections The processing positions of the via holes 133A to 133F based on the design data are corrected based on the difference between the shape of the third quadrilateral with respect to the reference position and the size of the second quadrilateral and the shape of the second quadrilateral with respect to the reference position. (Step S4).

  In step S3, if any of the four intersections is not within the four circles whose radius is the tolerance of the via centered on each vertex of the first quadrilateral, the intersection that is not in the circle is included in the circle. (Step S5).

  In step S5, the condition that the straight lines in step S2 are parallel is removed, passing through the inside of four circles with a radius of via tolerance centered on each vertex of the first quadrilateral, and on each side of the second quadrilateral The nearest four straight lines are determined. After obtaining four intersections in step S5, the process of step S4 is performed.

  Hereinafter, the details of steps S1 to S4 will be described with reference to FIGS.

  FIG. 4 is a diagram illustrating a process of obtaining an angle difference between each side of the first quadrilateral and the second quadrilateral in step S1 of the method for correcting the processing position of the wiring board according to the embodiment.

  Here, four points Q1 to Q4 obtained by detecting the alignment marks 131A to 131D shown in FIG. The quadrilateral connecting the points Q1 to Q4 is an example of the first quadrilateral.

  The positions of the four points Q1 to Q4 shown in FIG. 4 are represented by coordinates in a coordinate system used by a detection device including an infrared camera. The coordinate system used by the detection device including the infrared camera is the same as the coordinate system in the processing stage of the via processing machine.

  Points P1 to P4 represent the positions of alignment marks 131A to 131D included in the design data. The quadrilateral that connects the points P1 to P4 is an example of a second quadrilateral.

  Here, when the coordinate system used by the detection apparatus including the infrared camera is different from the coordinate system used by the design data, the position coordinates of the points Q1 to Q4 or the points P1 to P4 are converted into position coordinates in any of the coordinate systems. do it.

  In FIG. 4, for convenience of explanation, the coordinate system used by the design data is converted into a coordinate system in a processing stage of a detection device including an infrared camera and a via processing machine. Further, this coordinate system is shown as an XY coordinate system shown in FIG. Further, for each of the four vertices of the first quadrilateral and the second quadrilateral, the subscript number of the point closest to the origin is set to 1, and the subscript numbers 2 to 4 are added counterclockwise.

  In step S1, first, an angular difference between the sides of the first quadrangle Q1Q2Q3Q4 connecting the points Q1 to Q4 and the second quadrangle P1P2P3P4 connecting the points P1 to P4 is obtained.

  Here, in order to obtain the angular difference between the sides of the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4, each side is handled as a vector by defining a direction for each side.

  By giving a counterclockwise direction to each side, vectors VQ1, VQ2, VQ3, and VQ4 of each side of the first quadrangle Q1Q2Q3Q4 are generated. As the suffix numbers of the vectors VQ1 to VQ4, the suffix numbers of the vertices serving as the base points of the vectors are used.

  For example, for the side Q1Q2, a vector VQ1 is obtained by giving a counterclockwise direction (a direction from Q1 to Q2). Similarly, for the side Q2Q3, a vector VQ2 is obtained by giving a counterclockwise direction (a direction from Q2 toward Q3). For the side Q3Q4, a vector VQ3 is obtained by giving a counterclockwise direction (a direction from Q3 toward Q4). For the side Q4Q1, a vector VQ4 is obtained by giving a counterclockwise direction (a direction from Q4 toward Q1).

  Similarly, for the second quadrilateral P1P2P3P4, a vector VP1 is obtained by giving a counterclockwise direction (direction from P1 to P2) for the side P1P2. Similarly, for the side P2P3, a vector VP2 is obtained by giving a counterclockwise direction (a direction from P2 to P3). For the side P3P4, a vector VP3 is obtained by giving a counterclockwise direction (a direction from P3 to P4). For the side P4P1, a vector VP4 is obtained by giving a counterclockwise direction (a direction from P4 to P1).

  For the four vectors obtained for the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 as described above, the angle formed by the vectors with the same suffix numbers is obtained.

  That is, the angle θ1 formed by the vectors VQ1 and VP1, the angle θ2 formed by the vectors VQ2 and VP2, the angle θ3 formed by the vectors VQ3 and VP3, and the angle θ4 formed by the vectors VQ4 and VP4 are obtained.

  Since the coordinates of the base point and the end point of each vector are known, the angle difference between the sides included in the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 can be obtained by obtaining the angle between the vectors. it can.

  For convenience of explanation, FIG. 4 shows the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 in an overlapping manner. However, even if the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 do not overlap, The angle difference between the sides included in the form Q1Q2Q3Q4 and the second quadrilateral P1P2P3P4 can be obtained.

  Next, the average value of the maximum value and the minimum value among the angle θ1 formed by the vectors VQ1 and VP1, the angle θ2 formed by the vectors VQ2 and VP2, the angle θ3 formed by the vectors VQ3 and VP3, and the angle θ4 formed by the vectors VQ4 and VP4 ( Obtain the average angle difference. This step is an example of a first step in the method for correcting the processing position of the wiring board according to the embodiment.

  For example, when θ1 is the maximum of θ1 to θ4 and θ3 is the minimum, the average value (θ1 + θ3) / 2 of the angle θ1 formed by the vectors VQ1 and VP1 and the angle θ3 formed by the vectors VQ3 and VP3 is calculated. Ask.

  In addition, although the form which calculates | requires the average value (average angle difference) of the maximum value and the minimum value of (theta) 1- (theta) 4 is demonstrated here, an average angle difference is not restricted to the value calculated | required by such a method, For example, an average value of θ1 to θ4 may be obtained as an average angle difference.

  Next, the second quadrilateral P1P2P3P4 is rotationally moved by an angle represented by the average angle difference. This step is an example of a second step in the method for correcting the processing position of the wiring board according to the embodiment. Along with this rotational movement, the coordinates of the vertices of the second quadrilateral P1P2P3P4 may be similarly rotationally moved.

  Next, a distance difference between each vertex of the second quadrilateral P1P2P3P4 that has been rotated and each vertex of the first quadrangle Q1Q2Q3Q4 is obtained. This step is an example of a third step in the method for correcting the processing position of the wiring board according to the embodiment.

  The distance difference between vertices is performed for vertices having the same subscript number. Therefore, distance differences D1, D2, D3, and D4 of the vertices Q1 and P1, vertices Q2 and P2, vertices Q3 and P3, and vertices Q4 and P4 are obtained.

The distance differences D1, D2, D3, and D4 may be determined by obtaining the difference (Dx, Dy) between the position coordinates in the X-axis direction and the Y-axis direction. Therefore, the distance differences D1, D2, D3, and D4 are represented as D1 (Dx1, Dy1), D2 (Dx2, Dy2), D3 (Dx3, Dy3), and D4 (Dx4, Dy4), respectively. Each distance is obtained by D = √ (Dx ² + Dy ² ) using a difference between position coordinates in the x direction and the y direction.

  And in this Embodiment, the average value of the maximum value and the minimum value of distance difference D1-D4 of each vertex is calculated | required as an average distance difference.

  Here, among the distance differences D1 to D4, when the distance difference D1 is the largest and the distance difference D4 is the smallest, the average value ((D1 + D4) / 2) of the distance differences D1 and D4 is calculated as the average distance difference Dm ( Dmx, Dmy).

  Next, the second quadrangle P1P2P3P4 is moved by an average distance difference so that the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 approach each other. This step is an example of a fourth step in the method for correcting the processing position of the wiring board according to the embodiment.

  Specifically, the distance differences D1, D2, D3, and D4 are respectively represented by coordinates D1 (Dx1, Dy1), D2 (Dx2, Dy2), and the coordinates of the four vertices P1 to P4 of the second quadrilateral P1P2P3P4. The x coordinate component (Dx) and the y coordinate component (Dy) of D3 (Dx3, Dy3) and D4 (Dx4, Dy4) may be added.

  Accordingly, the second quadrangle P1P2P3P4 is moved by the average distance difference Dm (Dmx, Dmy) so that the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1P2P3P4 are close to each other.

  FIG. 5 is a diagram illustrating an example of a process of moving the second quadrilateral by an average distance difference in the method for correcting the processing position of the wiring board according to the embodiment.

  For example, as shown in FIG. 5, when the second quadrilateral P1P2P3P4 is moved by the average distance difference Dm (Dmx, Dmy), each vertex P1 ′ of the second quadrangle P1′P2′P3′P4 ′ after the movement, P2 ′, P3 ′, and P4 ′ are obtained by translating the vertices P1, P2, P3, and P4 of the second quadrilateral P1P2P3P4 before the movement by Dm in the X-axis direction and Dy in the Y-axis direction.

  As a result, the first quadrangle Q1Q2Q3Q4 and the second quadrangle P1'P2'P3'P4 'are in an overlapped state with substantially the same angle.

  The process of step S1 is completed by the above first to fourth steps.

  Next, the process of step S2 is demonstrated using FIG.

  FIG. 6 is a diagram illustrating the processing in step S2 in the method for correcting the processing position of the wiring board according to the embodiment. FIG. 6A shows the second quadrangle P1P2P3P4 passing through the inside of four circles centered on each vertex of the first quadrangle Q1Q2Q3Q4 and having a radius of via tolerance, parallel to each side of the second quadrangle P1P2P3P4. It is a figure which shows four straight lines nearest to each edge | side.

  Here, let r be the tolerance of vias formed in the via holes 133A, 133B (see FIGS. 2A and 2B). The via tolerance means an allowable maximum error in positional deviation between the via formed in the via holes 133A and 133B and the wiring layers 130B and 130C.

  The maximum allowable error is the maximum misalignment when the vias formed in the via holes 133A and 133B are connected to the wiring layers 130B and 130C, respectively, even when the vias formed in the via holes 133A and 133B are misaligned. Value.

  Using such via tolerances, as shown in FIG. 6A, four circles C1, C2, C3, and C4 having a radius of via tolerance r centered on each vertex of the first quadrangle Q1Q2Q3Q4 are formed. I want.

Then, through the interior of the four circles C1, C2, C3, C4, parallel to the respective sides of the second quadrilateral P1 'P2' P3 'P4', each of the second quadrilateral P1 'P2' P3 'P4' Four straight lines L1, L2, L3, and L4 closest to the side are obtained. This process is the process of step S2 described above, and is an example of a fifth process in the method for correcting the processing position of the wiring board according to the embodiment.

  A specific method for obtaining the straight lines L1, L2, L3, and L4 will be described later.

  Next, four intersections N1, N2, N3, and N4 of the straight lines L1, L2, L3, and L4 are obtained. The coordinates of the intersections N1 to N4 are given by obtaining the coordinates of the intersections between the straight lines. In FIG. 6A, intersection points N1, N2, N3, and N4 are indicated by white circles.

  Next, it is determined whether or not the four intersections N1, N2, N3, and N4 of the four straight lines L1, L2, L3, and L4 are inside the four circles C1, C2, C3, and C4. This processing may be performed based on whether or not the coordinates of the intersection points N1, N2, N3, and N4 are within the same circle with the suffixes of the four circles C1, C2, C3, and C4, respectively. . This step is an example of a sixth step in the method for correcting the processing position of the wiring board according to the embodiment.

  Intersection points N1, N2, N3, and N4 shown in FIG. 6A indicate a case where only the intersection point N2 is inside the circle C2.

  In such a case, the intersections N1, N3, and N4 that are not located inside the circles with the same suffix numbers are moved.

  As shown in FIG. 6 (B), the movement of the intersections N1, N3, and N4 is performed by connecting each intersection N1, N3, and N4 and the vertices Q1, Q3, and Q4 having the same subscript number, and each circle C1, This is done by moving to the intersections N1 ′, N3 ′, N4 ′ with the circumference of C3, N4. In FIG. 6B, the intersections N1 ', N3', N4 'after the movement are indicated by black circles. This process is a process of step S5, and is an example of a moving process in the method for correcting the processing position of the wiring board according to the embodiment.

  Since the intersections N1, N3, and N4 are moved to the intersections N1 ′, N3 ′, and N4 ′ in this step S5, the straight lines L1, L2, L3, and L4 are respectively connected to the second quadrilaterals P1′P2′P3′P4 ′. The straight lines L1 ′, L2 ′, L3 ′, and L4 ′ that are not parallel to the sides are corrected.

  As described above, in step S5, the condition that the straight lines in step S2 are parallel is removed, and four circles C1 having a radius of via tolerance around each vertex Q1, Q2, Q3, Q4 of the first quadrangle Q1Q2Q3Q4. , C2, C3, and C4, and four straight lines L1 ′, L2 ′, L3 ′, and L4 ′ that are closest to each side of the second quadrilateral P1′P2′P3′P4 ′ are obtained.

  As described above, four intersections N1 ', N2, N3', and N4 'are obtained.

  Finally, the size of the third quadrilateral N1′N2N3′N4 ′ defined by the four intersections N1 ′, N2, N3 ′, N4 ′ and the shape of the third quadrilateral N1′N2N3′N4 ′ with respect to the reference position, Based on the difference between the size of the two quadrilaterals P1'P2'P3'P4 'and the shape of the second quadrilateral P1'P2'P3'P4' with respect to the reference position, the via hole machining position based on the design data is corrected ( Step S4). This step S4 is an example of the seventh step.

  For example, the origin of the XY coordinates may be used as the reference position.

  As described above, the first quadrangle Q1Q2Q3Q4 is located inside the four circles C1, C2, C3, C4 centered on the respective vertices Q1, Q2, Q3, Q4 and having the via tolerance as the radius. Four intersections N1 ′, N2, N3 ′, and N4 ′ of four straight lines L1 ′, L2 ′, L3 ′, and L4 ′ closest to each side of P1′P2′P3′P4 ′ are obtained.

  The size and shape of the third quadrilateral N1′N2N3, N4 ′ defined by the four intersections N1 ′, N2, N3 ′, N4 ′ and the corresponding four alignment marks included in the design data are formed. The processing positions of the via holes 133A to 133F based on the design data are corrected based on the difference between the size and shape of the second quadrilateral P1′P2′P3′P4 ′.

  Therefore, the corrected processing positions of the via holes 133A to 133F are corrected according to the distortion of the shape of the buildup substrate 100.

  For this reason, if the via holes 133A to 133F are formed by laser processing or the like at the processing positions of the corrected via holes 133A to 133F and the vias are formed inside the via holes 133A to 133F, the vias and the wiring layers 130B, 130C, 130E, and 130G are formed. , 130I and 130K can be suppressed.

  The build-up substrate 100 expands and contracts due to heating and pressurization each time an insulating layer is stacked, but this expansion and contraction has a certain tendency, and the position of the wiring layer or the like included in the design data May be multiplied by a magnification given by expansion and contraction by heating and pressurization.

  When such a magnification is known in advance, for example, when forming the alignment marks 131A to 131D (see FIGS. 1A and 1B) included in the second layer on the upper side of the core substrate 110, The positions of the alignment marks 131A to 131D included in the design data may be multiplied by the magnification included in the third layer on the upper side of the core substrate 110.

  That is, in step S1, the magnification of the wiring layer (the third layer on the upper side of the core substrate 110) connected to the upper side of the via whose processing position is corrected in step S4 is set at the position of the alignment marks 131A to 131D in the design data. A second quadrilateral determined by the multiplied position may be obtained. And between the corresponding sides of the second quadrilateral determined by the position multiplied by such a magnification and the first quadrangle determined by the positions of the four alignment marks 131A to 131D formed at the four corners of the buildup substrate 100. An angle difference may be obtained.

  In such a case, since the positions of the alignment marks 131A to 131D are corrected by the magnification of the upper layer wiring board, the positional deviation between the wiring layers 130B and 130C and the via holes 133A and 133B is further suppressed. Can do.

  If four straight lines cannot be obtained in step S2, the following steps may be performed.

  FIG. 7 is a diagram illustrating a method of obtaining four straight lines in step S2 of the method for correcting the processing position of the wiring board according to the first embodiment. Here, for convenience of explanation, the positions of two alignment marks included in the design data are represented by Pa and Pb (a and b represent suffix numbers). Further, the positions where the alignment marks at the positions Pa and Pb in the buildup substrate 100 are detected by the infrared camera are indicated by Qa and Qb.

  Qa and Qb are two adjacent vertices of the four vertices of the first quadrilateral, Pa and Pb are two adjacent vertices of the four vertices of the second quadrilateral, The vertices Qa and Qb have the same suffix numbers.

  Further, circles centered on the vertices Qa and Qb and having a radius of via tolerance r are denoted by Ca and Cb, respectively.

  FIG. 7A shows the relationship between the vertices Pa, Pb, Qa, Qb and the circles Ca, Cb when a straight line that passes through the circles Ca, Cb, is parallel to the side PaPb, and is closest to the side PaPb can be drawn. Show.

  FIG. 7B shows the relationship between the vertices Pa, Pb, Qa, Qb and the circles Ca, Cb when a straight line that passes through the circles Ca, Cb, is parallel to the side PaPb, and is not closest to the side PaPb can be drawn. Indicates.

  As shown in FIG. 7A, perpendicular lines are drawn from the side PaPb to the vertices Qa and Qb, and the respective distances between the side PaPb and the vertices Qa and Qb are set to sd1 and ed1.

  In such a case, a range in which a straight line parallel to the side PaPb can be drawn is a section T in which the circles Ca and Cb overlap in a direction perpendicular to the side PaPb. The range of the section T is between (sd1-r) and (ed1 + r) in the direction perpendicular to the side PaPb.

  In this section T, the closest to the side PaPb is the position where the distance from the side PaPb is (sd1-r).

  Here, the distance sd1 is the distance between the side PaPb and the vertex Qa when a perpendicular is drawn from the side PaPb to the vertex Qa, and r is the tolerance of the via.

  Therefore, if the distance (sd1-r) is expressed in the coordinate system that defines the position coordinates of the vertices of the first quadrangle and the second quadrangle, an expression that expresses the straight line La in the coordinate system can be obtained.

  As shown in FIG. 7B, when the straight line that passes through the circles Ca and Cb, is parallel to the side PaPb, and is closest to the side PaPb cannot be drawn, the circles Ca and Cb are perpendicular to the side PaPb. This is a case where there is no overlapping section T (see FIG. 7A) in the direction.

  Here, perpendicular lines are drawn from the side PaPb to the vertices Qa and Qb, and the respective distances between the side PaPb and the vertices Qa and Qb are set to sd2 and ed2.

  In such a case, as shown in FIG. 7B, on the perpendicular drawn from the side PaPb to the vertex Qa, the point α at which the distance from the side PaPb is (sd2 + r) and the side PaPb to the vertex Qb. A straight line passing through the point β where the distance from the side PaPb is (ed2-r) on the vertical line may be used as an alternative straight line to the straight line La shown in FIG.

  The method for correcting the processing position of the wiring board according to the exemplary embodiment of the present invention has been described above, but the present invention is not limited to the specifically disclosed embodiment, and is not limited to the claims. Various modifications and changes can be made without departing from the above.

100 Build-up substrate 110 Core substrate 111A, 111B Via 120A, 120B Wiring layer 121, Via 122A, 122B Insulating layer 130A, 130B, 130C, 130D Wiring layer 120A-120F Wiring layer 130A-130L Wiring layer 131A-131D Alignment mark 132 Insulation Layer 133A to 133F Via hole 140A, 140B Wiring layer 141, Via 142A, 142B Insulating layer 150A, 150B, 150C, 150D Wiring layer 151 Insulating layer

Claims (7)

An average angle difference between corresponding sides of the first quadrilateral determined by the positions of the four alignment marks formed at the four corners of the wiring board and the second quadrangle determined by the positions of the alignment marks in the design data is calculated. A first step to be obtained;
A second step of rotating the first quadrilateral or the second quadrangle by the average angular difference so that an angular difference between each side of the first quadrilateral and each side of the second quadrangle is reduced; ,
A third step of determining an average distance difference between corresponding vertices of the first quadrilateral and the second quadrilateral;
A fourth step of moving the first quadrangle or the second quadrangle by the average distance difference so that the first quadrangle and the second quadrangle approach;
Centering on each vertex of the first quadrilateral, it passes through the inside of four circles whose radius is a tolerance of a via formed in the wiring board, and is parallel to each side of the second quadrilateral, and the second quadrilateral A fifth step for obtaining four straight lines closest to each side of
A sixth step of determining whether or not four intersections of the four straight lines are within four circles having a radius of the tolerance of the via;
A size of the third quadrilateral determined by the four intersections determined to be inside four circles having a radius of the tolerance of the via in the sixth step, and a shape with respect to a reference position of the third quadrilateral; A seventh step of correcting a processing position of the via to the wiring board based on the design data based on a difference between the size of the second quadrilateral and a shape of the second quadrilateral with respect to a reference position. Method for correcting the processing position of the substrate. A moving step of moving an intersection point that has not been determined to be inside the four circles whose radius is the tolerance of the via in the sixth step to the inside of a circle closest to the intersection point among the four circles;
In the moving step, the third four sides defined by four intersection points including the intersection point determined to be inside the circle whose radius is the tolerance of the via in the sixth step and the intersection point moved in the moving step The wiring board based on the design data based on the difference between the shape of the shape relative to the reference position of the third quadrilateral and the shape of the second quadrilateral and the shape relative to the reference position of the second quadrilateral The method for correcting a processing position of a wiring board according to claim 1, wherein the processing position of a via is corrected.   The method for correcting a processing position of a wiring board according to claim 1, wherein the reference position is a center of gravity.   The method for correcting a processing position of a wiring board according to claim 1, wherein the reference position is an average coordinate of coordinates of four vertices.   The average angle difference of the angle differences between the sides obtained in the first step is the maximum angle difference among the angle differences between the four sides of the first quadrilateral and the corresponding four sides of the second quadrilateral. The correction method of the processing position of the wiring board as described in any one of Claims 1 thru | or 4 which is an average angle difference with these and the minimum angle difference.   The average distance difference obtained in the third step is the maximum distance difference and the minimum distance among the distance differences between the four vertices of the first quadrilateral and the corresponding four vertices of the second quadrilateral. The correction method of the processing position of the wiring board as described in any one of Claims 1 thru | or 5 which is an average distance difference with a difference.   In the first step, a second quadrilateral determined by a position obtained by multiplying the position of the alignment mark in the design data by the magnification of the wiring layer connected to the upper side of the via that corrects the processing position in the seventh step; The wiring according to any one of claims 1 to 6, wherein an average angle difference is calculated for an angle difference between corresponding sides of the first quadrilateral determined by positions of four alignment marks formed at four corners of the wiring board. Method for correcting the processing position of the substrate.

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