JP5754419B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5754419B2 JP5754419B2 JP2012152591A JP2012152591A JP5754419B2 JP 5754419 B2 JP5754419 B2 JP 5754419B2 JP 2012152591 A JP2012152591 A JP 2012152591A JP 2012152591 A JP2012152591 A JP 2012152591A JP 5754419 B2 JP5754419 B2 JP 5754419B2
- Authority
- JP
- Japan
- Prior art keywords
- control board
- case
- connector
- semiconductor device
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Coupling Device And Connection With Printed Circuit (AREA)
- Inverter Devices (AREA)
Description
図1は、本発明の実施の形態1に係る半導体装置を示す上面図である。図2は図1のI−IIに沿った断面図である。図3は図1のIII−IVに沿った断面図である。図4は、本発明の実施の形態1に係る半導体装置を示す側面図である。図5は、ハーネスを示す斜視図である。ただし、内部構造を説明するために図1では蓋(後述)を省略している。
図9は、本発明の実施の形態1に係る半導体装置を示す上面図である。図10は、本発明の実施の形態2に係る半導体装置を示す側面図である。図11は、本発明の実施の形態2に係る蓋を示す下面図である。
4 蓋
8 半導体素子
13 制御基板
19 コネクタ
20 ハーネス
21 脱着面
25 押え部
26 位置決め穴
27 突起
Claims (1)
- ケースと、
前記ケース内に配置された半導体素子と、
前記ケース内に配置され、前記半導体素子を制御する制御基板と、
前記制御基板上に設けられ、前記制御基板と外部との電気信号の入出力を仲介するコネクタと、
前記ケースの上部を覆う蓋とを備え、
前記コネクタは、外部のハーネスが脱着される脱着面を有し、
前記コネクタの前記脱着面は前記制御基板の端面と同一面上に配置され、
前記制御基板が前記ケースの側壁上まで延在し、前記制御基板の前記端面は前記ケースの前記側壁の外面と同一面上に配置され、
前記蓋は、前記制御基板の上面を押えて前記制御基板を固定する押え部を有し、
前記制御基板の上面に位置決め穴が設けられ、
前記蓋の前記押え部の先端に、前記位置決め穴に挿入される突起が設けられていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012152591A JP5754419B2 (ja) | 2012-07-06 | 2012-07-06 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012152591A JP5754419B2 (ja) | 2012-07-06 | 2012-07-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014017320A JP2014017320A (ja) | 2014-01-30 |
JP5754419B2 true JP5754419B2 (ja) | 2015-07-29 |
Family
ID=50111780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012152591A Active JP5754419B2 (ja) | 2012-07-06 | 2012-07-06 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5754419B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002315357A (ja) * | 2001-04-16 | 2002-10-25 | Hitachi Ltd | インバータ装置 |
JP3845333B2 (ja) * | 2002-04-30 | 2006-11-15 | 三菱電機株式会社 | 半導体パワーモジュール |
JP5673085B2 (ja) * | 2010-12-27 | 2015-02-18 | 住友電装株式会社 | 電流検出装置 |
-
2012
- 2012-07-06 JP JP2012152591A patent/JP5754419B2/ja active Active
Also Published As
Publication number | Publication date |
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JP2014017320A (ja) | 2014-01-30 |
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